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NUC472/NUC442 BSP
V3.03.001
The Board Support Package for NUC472/NUC442
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NUC472/NUC442 peripheral access layer header file. This file contains all the peripheral register's definitions, bits definitions and memory mapping for NuMicro NUC472/NUC442 MCU. More...
#include "core_cm4.h"#include "system_NUC472_442.h"#include <stdint.h>#include "sys.h"#include "clk.h"#include "acmp.h"#include "adc.h"#include "eadc.h"#include "cap.h"#include "crypto.h"#include "pdma.h"#include "ebi.h"#include "emac.h"#include "fmc.h"#include "gpio.h"#include "i2c.h"#include "pwm.h"#include "epwm.h"#include "rtc.h"#include "sc.h"#include "scuart.h"#include "spi.h"#include "timer.h"#include "uart.h"#include "usbd.h"#include "wdt.h"#include "wwdt.h"#include "i2s.h"#include "can.h"#include "sd.h"#include "ps2.h"#include "crc.h"Go to the source code of this file.
Data Structures | |
| struct | ACMP_T |
| struct | ADC_T |
| struct | CAN_IF_T |
| struct | CAN_T |
| struct | CAP_T |
| struct | ECAP_T |
| struct | CLK_T |
| struct | CRC_T |
| struct | CRPT_T |
| struct | EADC_T |
| struct | EBI_T |
| struct | EMAC_T |
| struct | EPWM_T |
| struct | FMC_T |
| struct | GPIO_T |
| struct | GPIO_DB_T |
| struct | I2C_T |
| struct | I2S_T |
| struct | OPA_T |
| struct | OTG_T |
| struct | DSCT_T |
| struct | PDMA_T |
| struct | PS2_T |
| struct | PWM_T |
| struct | QEI_T |
| struct | RTC_T |
| struct | SC_T |
| struct | SDH_T |
| struct | SPI_T |
| struct | SYS_T |
| struct | TIMER_T |
| struct | UART_T |
| struct | USBH_T |
| struct | USBD_EP_T |
| USBD endpoints register. More... | |
| struct | USBD_T |
| struct | WDT_T |
| struct | WWDT_T |
Macros | |
| #define | __CM4_REV 0x0201 |
| #define | __NVIC_PRIO_BITS 4 |
| #define | __Vendor_SysTickConfig 0 |
| #define | __MPU_PRESENT 1 |
| #define | __FPU_PRESENT 1 |
| #define | FLASH_BASE ((uint32_t)0x00000000) |
| #define | SRAM_BASE ((uint32_t)0x20000000) |
| #define | PERIPH_BASE ((uint32_t)0x40000000) |
| #define | AHBPERIPH_BASE PERIPH_BASE |
| #define | APBPERIPH_BASE (PERIPH_BASE + 0x00040000) |
| #define | SYS_BASE (AHBPERIPH_BASE + 0x00000) |
| #define | CLK_BASE (AHBPERIPH_BASE + 0x00200) |
| #define | GPIOA_BASE (AHBPERIPH_BASE + 0x04000) |
| #define | GPIOB_BASE (AHBPERIPH_BASE + 0x04040) |
| #define | GPIOC_BASE (AHBPERIPH_BASE + 0x04080) |
| #define | GPIOD_BASE (AHBPERIPH_BASE + 0x040C0) |
| #define | GPIOE_BASE (AHBPERIPH_BASE + 0x04100) |
| #define | GPIOF_BASE (AHBPERIPH_BASE + 0x04140) |
| #define | GPIOG_BASE (AHBPERIPH_BASE + 0x04180) |
| #define | GPIOH_BASE (AHBPERIPH_BASE + 0x041C0) |
| #define | GPIOI_BASE (AHBPERIPH_BASE + 0x04200) |
| #define | GPIO_DBCTL_BASE (AHBPERIPH_BASE + 0x04440) |
| #define | GPIO_PIN_DATA_BASE (AHBPERIPH_BASE + 0x04800) |
| #define | PDMA_BASE (AHBPERIPH_BASE + 0x08000) |
| #define | USBH_BASE (AHBPERIPH_BASE + 0x09000) |
| #define | EMAC_BASE (AHBPERIPH_BASE + 0x0B000) |
| #define | FMC_BASE (AHBPERIPH_BASE + 0x0C000) |
| #define | SD_BASE (AHBPERIPH_BASE + 0x0D000) |
| #define | EBI_BASE (AHBPERIPH_BASE + 0x10000) |
| #define | UDC20_BASE (AHBPERIPH_BASE + 0x19000) |
| #define | CAP_BASE (AHBPERIPH_BASE + 0x30000) |
| #define | CRC_BASE (AHBPERIPH_BASE + 0x31000) |
| #define | WDT_BASE (APBPERIPH_BASE + 0x00000) |
| #define | WWDT_BASE (APBPERIPH_BASE + 0x00100) |
| #define | OPA_BASE (APBPERIPH_BASE + 0x06000) |
| #define | I2S0_BASE (APBPERIPH_BASE + 0x08000) |
| #define | TIMER0_BASE (APBPERIPH_BASE + 0x10000) |
| #define | TIMER1_BASE (APBPERIPH_BASE + 0x10020) |
| #define | PWM0_BASE (APBPERIPH_BASE + 0x18000) |
| #define | EPWM0_BASE (APBPERIPH_BASE + 0x1C000) |
| #define | SPI0_BASE (APBPERIPH_BASE + 0x20000) |
| #define | SPI2_BASE (APBPERIPH_BASE + 0x22000) |
| #define | UART0_BASE (APBPERIPH_BASE + 0x30000) |
| #define | UART2_BASE (APBPERIPH_BASE + 0x32000) |
| #define | UART4_BASE (APBPERIPH_BASE + 0x34000) |
| #define | I2C0_BASE (APBPERIPH_BASE + 0x40000) |
| #define | I2C2_BASE (APBPERIPH_BASE + 0x42000) |
| #define | I2C4_BASE (APBPERIPH_BASE + 0x44000) |
| #define | SC0_BASE (APBPERIPH_BASE + 0x50000) |
| #define | SC2_BASE (APBPERIPH_BASE + 0x52000) |
| #define | SC4_BASE (APBPERIPH_BASE + 0x54000) |
| #define | CAN0_BASE (APBPERIPH_BASE + 0x60000) |
| #define | QEI0_BASE (APBPERIPH_BASE + 0x70000) |
| #define | ECAP0_BASE (APBPERIPH_BASE + 0x74000) |
| #define | PS2D_BASE (APBPERIPH_BASE + 0xA0000) |
| #define | RTC_BASE (APBPERIPH_BASE + 0x01000) |
| #define | ADC_BASE (APBPERIPH_BASE + 0x03000) |
| #define | EADC_BASE (APBPERIPH_BASE + 0x04000) |
| #define | ACMP_BASE (APBPERIPH_BASE + 0x05000) |
| #define | I2S1_BASE (APBPERIPH_BASE + 0x09000) |
| #define | OTG_BASE (APBPERIPH_BASE + 0x0D000) |
| #define | TIMER2_BASE (APBPERIPH_BASE + 0x11000) |
| #define | TIMER3_BASE (APBPERIPH_BASE + 0x11020) |
| #define | PWM1_BASE (APBPERIPH_BASE + 0x19000) |
| #define | EPWM1_BASE (APBPERIPH_BASE + 0x1D000) |
| #define | SPI1_BASE (APBPERIPH_BASE + 0x21000) |
| #define | SPI3_BASE (APBPERIPH_BASE + 0x23000) |
| #define | UART1_BASE (APBPERIPH_BASE + 0x31000) |
| #define | UART3_BASE (APBPERIPH_BASE + 0x33000) |
| #define | UART5_BASE (APBPERIPH_BASE + 0x35000) |
| #define | I2C1_BASE (APBPERIPH_BASE + 0x41000) |
| #define | I2C3_BASE (APBPERIPH_BASE + 0x43000) |
| #define | SC1_BASE (APBPERIPH_BASE + 0x51000) |
| #define | SC3_BASE (APBPERIPH_BASE + 0x53000) |
| #define | SC5_BASE (APBPERIPH_BASE + 0x55000) |
| #define | CAN1_BASE (APBPERIPH_BASE + 0x61000) |
| #define | QEI1_BASE (APBPERIPH_BASE + 0x71000) |
| #define | ECAP1_BASE (APBPERIPH_BASE + 0x75000) |
| #define | CRPT_BASE (0x50080000UL) |
| #define | SYS ((SYS_T *) SYS_BASE) |
| #define | CLK ((CLK_T *) CLK_BASE) |
| #define | PA ((GPIO_T *) GPIOA_BASE) |
| #define | PB ((GPIO_T *) GPIOB_BASE) |
| #define | PC ((GPIO_T *) GPIOC_BASE) |
| #define | PD ((GPIO_T *) GPIOD_BASE) |
| #define | PE ((GPIO_T *) GPIOE_BASE) |
| #define | PF ((GPIO_T *) GPIOF_BASE) |
| #define | PG ((GPIO_T *) GPIOG_BASE) |
| #define | PH ((GPIO_T *) GPIOH_BASE) |
| #define | GPA ((GPIO_T *) GPIOA_BASE) |
| #define | GPB ((GPIO_T *) GPIOB_BASE) |
| #define | GPC ((GPIO_T *) GPIOC_BASE) |
| #define | GPD ((GPIO_T *) GPIOD_BASE) |
| #define | GPE ((GPIO_T *) GPIOE_BASE) |
| #define | GPF ((GPIO_T *) GPIOF_BASE) |
| #define | GPG ((GPIO_T *) GPIOG_BASE) |
| #define | GPH ((GPIO_T *) GPIOH_BASE) |
| #define | GPI ((GPIO_T *) GPIOI_BASE) |
| #define | GPIO ((GPIO_DB_T *) GPIO_DBCTL_BASE) |
| #define | PDMA ((PDMA_T *) PDMA_BASE) |
| #define | USBH ((USBH_T *) USBH_BASE) |
| #define | EMAC ((EMAC_T *) EMAC_BASE) |
| #define | FMC ((FMC_T *) FMC_BASE) |
| #define | SD ((SDH_T *) SD_BASE) |
| #define | EBI ((EBI_T *) EBI_BASE) |
| #define | ICAP ((CAP_T *) CAP_BASE) |
| #define | CRC ((CRC_T *) CRC_BASE) |
| #define | WDT ((WDT_T *) WDT_BASE) |
| #define | WWDT ((WWDT_T *) WWDT_BASE) |
| #define | RTC ((RTC_T *) RTC_BASE) |
| #define | ADC ((ADC_T *) ADC_BASE) |
| #define | EADC ((EADC_T *) EADC_BASE) |
| #define | ACMP ((ACMP_T *) ACMP_BASE) |
| #define | I2S0 ((I2S_T *) I2S0_BASE) |
| #define | I2S1 ((I2S_T *) I2S1_BASE) |
| #define | USBD ((USBD_T *) UDC20_BASE) |
| #define | OTG ((OTG_T *) OTG_BASE) |
| #define | TIMER0 ((TIMER_T *) TIMER0_BASE) |
| #define | TIMER1 ((TIMER_T *) TIMER1_BASE) |
| #define | TIMER2 ((TIMER_T *) TIMER2_BASE) |
| #define | TIMER3 ((TIMER_T *) TIMER3_BASE) |
| #define | PWM0 ((PWM_T *) PWM0_BASE) |
| #define | PWM1 ((PWM_T *) PWM1_BASE) |
| #define | EPWM0 ((EPWM_T *) EPWM0_BASE) |
| #define | EPWM1 ((EPWM_T *) EPWM1_BASE) |
| #define | ECAP0 ((ECAP_T *) ECAP0_BASE) |
| #define | ECAP1 ((ECAP_T *) ECAP1_BASE) |
| #define | QEI0 ((QEI_T *) QEI0_BASE) |
| #define | QEI1 ((QEI_T *) QEI1_BASE) |
| #define | SPI0 ((SPI_T *) SPI0_BASE) |
| #define | SPI1 ((SPI_T *) SPI1_BASE) |
| #define | SPI2 ((SPI_T *) SPI2_BASE) |
| #define | SPI3 ((SPI_T *) SPI3_BASE) |
| #define | UART0 ((UART_T *) UART0_BASE) |
| #define | UART1 ((UART_T *) UART1_BASE) |
| #define | UART2 ((UART_T *) UART2_BASE) |
| #define | UART3 ((UART_T *) UART3_BASE) |
| #define | UART4 ((UART_T *) UART4_BASE) |
| #define | UART5 ((UART_T *) UART5_BASE) |
| #define | I2C0 ((I2C_T *) I2C0_BASE) |
| #define | I2C1 ((I2C_T *) I2C1_BASE) |
| #define | I2C2 ((I2C_T *) I2C2_BASE) |
| #define | I2C3 ((I2C_T *) I2C3_BASE) |
| #define | I2C4 ((I2C_T *) I2C4_BASE) |
| #define | SC0 ((SC_T *) SC0_BASE) |
| #define | SC1 ((SC_T *) SC1_BASE) |
| #define | SC2 ((SC_T *) SC2_BASE) |
| #define | SC3 ((SC_T *) SC3_BASE) |
| #define | SC4 ((SC_T *) SC4_BASE) |
| #define | SC5 ((SC_T *) SC5_BASE) |
| #define | CAN0 ((CAN_T *) CAN0_BASE) |
| #define | CAN1 ((CAN_T *) CAN1_BASE) |
| #define | PS2 ((PS2_T *) PS2D_BASE) |
| #define | CRPT ((CRPT_T *) CRPT_BASE) |
| #define | M8(addr) (*((vu8 *) (addr))) |
| Get a 8-bit unsigned value from specified address. More... | |
| #define | M16(addr) (*((vu16 *) (addr))) |
| Get a 16-bit unsigned value from specified address. More... | |
| #define | M32(addr) (*((vu32 *) (addr))) |
| Get a 32-bit unsigned value from specified address. More... | |
| #define | outpw(port, value) *((volatile unsigned int *)(port)) = value |
| Set a 32-bit unsigned value to specified I/O port. More... | |
| #define | inpw(port) (*((volatile unsigned int *)(port))) |
| Get a 32-bit unsigned value from specified I/O port. More... | |
| #define | outps(port, value) *((volatile unsigned short *)(port)) = value |
| Set a 16-bit unsigned value to specified I/O port. More... | |
| #define | inps(port) (*((volatile unsigned short *)(port))) |
| Get a 16-bit unsigned value from specified I/O port. More... | |
| #define | outpb(port, value) *((volatile unsigned char *)(port)) = value |
| Set a 8-bit unsigned value to specified I/O port. More... | |
| #define | inpb(port) (*((volatile unsigned char *)(port))) |
| Get a 8-bit unsigned value from specified I/O port. More... | |
| #define | outp32(port, value) *((volatile unsigned int *)(port)) = value |
| Set a 32-bit unsigned value to specified I/O port. More... | |
| #define | inp32(port) (*((volatile unsigned int *)(port))) |
| Get a 32-bit unsigned value from specified I/O port. More... | |
| #define | outp16(port, value) *((volatile unsigned short *)(port)) = value |
| Set a 16-bit unsigned value to specified I/O port. More... | |
| #define | inp16(port) (*((volatile unsigned short *)(port))) |
| Get a 16-bit unsigned value from specified I/O port. More... | |
| #define | outp8(port, value) *((volatile unsigned char *)(port)) = value |
| Set a 8-bit unsigned value to specified I/O port. More... | |
| #define | inp8(port) (*((volatile unsigned char *)(port))) |
| Get a 8-bit unsigned value from specified I/O port. More... | |
| #define | NULL (0) |
| NULL pointer. More... | |
| #define | TRUE (1) |
| Boolean true, define to use in API parameters or return value. More... | |
| #define | FALSE (0) |
| Boolean false, define to use in API parameters or return value. More... | |
| #define | ENABLE (1) |
| Enable, define to use in API parameters. More... | |
| #define | DISABLE (0) |
| Disable, define to use in API parameters. More... | |
| #define | BIT0 (0x00000001) |
| Bit 0 mask of an 32 bit integer. More... | |
| #define | BIT1 (0x00000002) |
| Bit 1 mask of an 32 bit integer. More... | |
| #define | BIT2 (0x00000004) |
| Bit 2 mask of an 32 bit integer. More... | |
| #define | BIT3 (0x00000008) |
| Bit 3 mask of an 32 bit integer. More... | |
| #define | BIT4 (0x00000010) |
| Bit 4 mask of an 32 bit integer. More... | |
| #define | BIT5 (0x00000020) |
| Bit 5 mask of an 32 bit integer. More... | |
| #define | BIT6 (0x00000040) |
| Bit 6 mask of an 32 bit integer. More... | |
| #define | BIT7 (0x00000080) |
| Bit 7 mask of an 32 bit integer. More... | |
| #define | BIT8 (0x00000100) |
| Bit 8 mask of an 32 bit integer. More... | |
| #define | BIT9 (0x00000200) |
| Bit 9 mask of an 32 bit integer. More... | |
| #define | BIT10 (0x00000400) |
| Bit 10 mask of an 32 bit integer. More... | |
| #define | BIT11 (0x00000800) |
| Bit 11 mask of an 32 bit integer. More... | |
| #define | BIT12 (0x00001000) |
| Bit 12 mask of an 32 bit integer. More... | |
| #define | BIT13 (0x00002000) |
| Bit 13 mask of an 32 bit integer. More... | |
| #define | BIT14 (0x00004000) |
| Bit 14 mask of an 32 bit integer. More... | |
| #define | BIT15 (0x00008000) |
| Bit 15 mask of an 32 bit integer. More... | |
| #define | BIT16 (0x00010000) |
| Bit 16 mask of an 32 bit integer. More... | |
| #define | BIT17 (0x00020000) |
| Bit 17 mask of an 32 bit integer. More... | |
| #define | BIT18 (0x00040000) |
| Bit 18 mask of an 32 bit integer. More... | |
| #define | BIT19 (0x00080000) |
| Bit 19 mask of an 32 bit integer. More... | |
| #define | BIT20 (0x00100000) |
| Bit 20 mask of an 32 bit integer. More... | |
| #define | BIT21 (0x00200000) |
| Bit 21 mask of an 32 bit integer. More... | |
| #define | BIT22 (0x00400000) |
| Bit 22 mask of an 32 bit integer. More... | |
| #define | BIT23 (0x00800000) |
| Bit 23 mask of an 32 bit integer. More... | |
| #define | BIT24 (0x01000000) |
| Bit 24 mask of an 32 bit integer. More... | |
| #define | BIT25 (0x02000000) |
| Bit 25 mask of an 32 bit integer. More... | |
| #define | BIT26 (0x04000000) |
| Bit 26 mask of an 32 bit integer. More... | |
| #define | BIT27 (0x08000000) |
| Bit 27 mask of an 32 bit integer. More... | |
| #define | BIT28 (0x10000000) |
| Bit 28 mask of an 32 bit integer. More... | |
| #define | BIT29 (0x20000000) |
| Bit 29 mask of an 32 bit integer. More... | |
| #define | BIT30 (0x40000000) |
| Bit 30 mask of an 32 bit integer. More... | |
| #define | BIT31 (0x80000000) |
| Bit 31 mask of an 32 bit integer. More... | |
| #define | BYTE0_Msk (0x000000FF) |
| Mask to get bit0~bit7 from a 32 bit integer. More... | |
| #define | BYTE1_Msk (0x0000FF00) |
| Mask to get bit8~bit15 from a 32 bit integer. More... | |
| #define | BYTE2_Msk (0x00FF0000) |
| Mask to get bit16~bit23 from a 32 bit integer. More... | |
| #define | BYTE3_Msk (0xFF000000) |
| Mask to get bit24~bit31 from a 32 bit integer. More... | |
| #define | GET_BYTE0(u32Param) ((u32Param & BYTE0_Msk) ) |
| #define | GET_BYTE1(u32Param) ((u32Param & BYTE1_Msk) >> 8) |
| #define | GET_BYTE2(u32Param) ((u32Param & BYTE2_Msk) >> 16) |
| #define | GET_BYTE3(u32Param) ((u32Param & BYTE3_Msk) >> 24) |
| #define | ACMP_CTL_ACMPEN_Pos (0) |
| #define | ACMP_CTL_ACMPEN_Msk (0x1ul << ACMP_CTL_ACMPEN_Pos) |
| #define | ACMP_CTL_ACMPIE_Pos (1) |
| #define | ACMP_CTL_ACMPIE_Msk (0x1ul << ACMP_CTL_ACMPIE_Pos) |
| #define | ACMP_CTL_HYSEN_Pos (2) |
| #define | ACMP_CTL_HYSEN_Msk (0x1ul << ACMP_CTL_HYSEN_Pos) |
| #define | ACMP_CTL_ACMPOINV_Pos (3) |
| #define | ACMP_CTL_ACMPOINV_Msk (0x1ul << ACMP_CTL_ACMPOINV_Pos) |
| #define | ACMP_CTL_NEGSEL_Pos (4) |
| #define | ACMP_CTL_NEGSEL_Msk (0x1ul << ACMP_CTL_NEGSEL_Pos) |
| #define | ACMP_CTL_POSSEL_Pos (5) |
| #define | ACMP_CTL_POSSEL_Msk (0x7ul << ACMP_CTL_POSSEL_Pos) |
| #define | ACMP_STATUS_ACMPIF0_Pos (0) |
| #define | ACMP_STATUS_ACMPIF0_Msk (0x1ul << ACMP_STATUS_ACMPIF0_Pos) |
| #define | ACMP_STATUS_ACMPIF1_Pos (1) |
| #define | ACMP_STATUS_ACMPIF1_Msk (0x1ul << ACMP_STATUS_ACMPIF1_Pos) |
| #define | ACMP_STATUS_ACMPIF2_Pos (2) |
| #define | ACMP_STATUS_ACMPIF2_Msk (0x1ul << ACMP_STATUS_ACMPIF2_Pos) |
| #define | ACMP_STATUS_ACMPO0_Pos (3) |
| #define | ACMP_STATUS_ACMPO0_Msk (0x1ul << ACMP_STATUS_ACMPO0_Pos) |
| #define | ACMP_STATUS_ACMPO1_Pos (4) |
| #define | ACMP_STATUS_ACMPO1_Msk (0x1ul << ACMP_STATUS_ACMPO1_Pos) |
| #define | ACMP_STATUS_ACMPO2_Pos (5) |
| #define | ACMP_STATUS_ACMPO2_Msk (0x1ul << ACMP_STATUS_ACMPO2_Pos) |
| #define | ACMP_VREF_CRVCTL_Pos (0) |
| #define | ACMP_VREF_CRVCTL_Msk (0xful << ACMP_VREF_CRVCTL_Pos) |
| #define | ACMP_VREF_CRVSSEL_Pos (6) |
| #define | ACMP_VREF_CRVSSEL_Msk (0x1ul << ACMP_VREF_CRVSSEL_Pos) |
| #define | ACMP_VREF_IREFSEL_Pos (7) |
| #define | ACMP_VREF_IREFSEL_Msk (0x1ul << ACMP_VREF_IREFSEL_Pos) |
| #define | ADC_DAT0_RESULT_Pos (0) |
| #define | ADC_DAT0_RESULT_Msk (0xfffful << ADC_DAT0_RESULT_Pos) |
| #define | ADC_DAT0_OV_Pos (16) |
| #define | ADC_DAT0_OV_Msk (0x1ul << ADC_DAT0_OV_Pos) |
| #define | ADC_DAT0_VALID_Pos (17) |
| #define | ADC_DAT0_VALID_Msk (0x1ul << ADC_DAT0_VALID_Pos) |
| #define | ADC_DAT1_RESULT_Pos (0) |
| #define | ADC_DAT1_RESULT_Msk (0xfffful << ADC_DAT1_RESULT_Pos) |
| #define | ADC_DAT1_OV_Pos (16) |
| #define | ADC_DAT1_OV_Msk (0x1ul << ADC_DAT1_OV_Pos) |
| #define | ADC_DAT1_VALID_Pos (17) |
| #define | ADC_DAT1_VALID_Msk (0x1ul << ADC_DAT1_VALID_Pos) |
| #define | ADC_DAT2_RESULT_Pos (0) |
| #define | ADC_DAT2_RESULT_Msk (0xfffful << ADC_DAT2_RESULT_Pos) |
| #define | ADC_DAT2_OV_Pos (16) |
| #define | ADC_DAT2_OV_Msk (0x1ul << ADC_DAT2_OV_Pos) |
| #define | ADC_DAT2_VALID_Pos (17) |
| #define | ADC_DAT2_VALID_Msk (0x1ul << ADC_DAT2_VALID_Pos) |
| #define | ADC_DAT3_RESULT_Pos (0) |
| #define | ADC_DAT3_RESULT_Msk (0xfffful << ADC_DAT3_RESULT_Pos) |
| #define | ADC_DAT3_OV_Pos (16) |
| #define | ADC_DAT3_OV_Msk (0x1ul << ADC_DAT3_OV_Pos) |
| #define | ADC_DAT3_VALID_Pos (17) |
| #define | ADC_DAT3_VALID_Msk (0x1ul << ADC_DAT3_VALID_Pos) |
| #define | ADC_DAT4_RESULT_Pos (0) |
| #define | ADC_DAT4_RESULT_Msk (0xfffful << ADC_DAT4_RESULT_Pos) |
| #define | ADC_DAT4_OV_Pos (16) |
| #define | ADC_DAT4_OV_Msk (0x1ul << ADC_DAT4_OV_Pos) |
| #define | ADC_DAT4_VALID_Pos (17) |
| #define | ADC_DAT4_VALID_Msk (0x1ul << ADC_DAT4_VALID_Pos) |
| #define | ADC_DAT5_RESULT_Pos (0) |
| #define | ADC_DAT5_RESULT_Msk (0xfffful << ADC_DAT5_RESULT_Pos) |
| #define | ADC_DAT5_OV_Pos (16) |
| #define | ADC_DAT5_OV_Msk (0x1ul << ADC_DAT5_OV_Pos) |
| #define | ADC_DAT5_VALID_Pos (17) |
| #define | ADC_DAT5_VALID_Msk (0x1ul << ADC_DAT5_VALID_Pos) |
| #define | ADC_DAT6_RESULT_Pos (0) |
| #define | ADC_DAT6_RESULT_Msk (0xfffful << ADC_DAT6_RESULT_Pos) |
| #define | ADC_DAT6_OV_Pos (16) |
| #define | ADC_DAT6_OV_Msk (0x1ul << ADC_DAT6_OV_Pos) |
| #define | ADC_DAT6_VALID_Pos (17) |
| #define | ADC_DAT6_VALID_Msk (0x1ul << ADC_DAT6_VALID_Pos) |
| #define | ADC_DAT7_RESULT_Pos (0) |
| #define | ADC_DAT7_RESULT_Msk (0xfffful << ADC_DAT7_RESULT_Pos) |
| #define | ADC_DAT7_OV_Pos (16) |
| #define | ADC_DAT7_OV_Msk (0x1ul << ADC_DAT7_OV_Pos) |
| #define | ADC_DAT7_VALID_Pos (17) |
| #define | ADC_DAT7_VALID_Msk (0x1ul << ADC_DAT7_VALID_Pos) |
| #define | ADC_DAT8_RESULT_Pos (0) |
| #define | ADC_DAT8_RESULT_Msk (0xfffful << ADC_DAT8_RESULT_Pos) |
| #define | ADC_DAT8_OV_Pos (16) |
| #define | ADC_DAT8_OV_Msk (0x1ul << ADC_DAT8_OV_Pos) |
| #define | ADC_DAT8_VALID_Pos (17) |
| #define | ADC_DAT8_VALID_Msk (0x1ul << ADC_DAT8_VALID_Pos) |
| #define | ADC_DAT9_RESULT_Pos (0) |
| #define | ADC_DAT9_RESULT_Msk (0xfffful << ADC_DAT9_RESULT_Pos) |
| #define | ADC_DAT9_OV_Pos (16) |
| #define | ADC_DAT9_OV_Msk (0x1ul << ADC_DAT9_OV_Pos) |
| #define | ADC_DAT9_VALID_Pos (17) |
| #define | ADC_DAT9_VALID_Msk (0x1ul << ADC_DAT9_VALID_Pos) |
| #define | ADC_DAT10_RESULT_Pos (0) |
| #define | ADC_DAT10_RESULT_Msk (0xfffful << ADC_DAT10_RESULT_Pos) |
| #define | ADC_DAT10_OV_Pos (16) |
| #define | ADC_DAT10_OV_Msk (0x1ul << ADC_DAT10_OV_Pos) |
| #define | ADC_DAT10_VALID_Pos (17) |
| #define | ADC_DAT10_VALID_Msk (0x1ul << ADC_DAT10_VALID_Pos) |
| #define | ADC_DAT11_RESULT_Pos (0) |
| #define | ADC_DAT11_RESULT_Msk (0xfffful << ADC_DAT11_RESULT_Pos) |
| #define | ADC_DAT11_OV_Pos (16) |
| #define | ADC_DAT11_OV_Msk (0x1ul << ADC_DAT11_OV_Pos) |
| #define | ADC_DAT11_VALID_Pos (17) |
| #define | ADC_DAT11_VALID_Msk (0x1ul << ADC_DAT11_VALID_Pos) |
| #define | ADC_DAT12_RESULT_Pos (0) |
| #define | ADC_DAT12_RESULT_Msk (0xfffful << ADC_DAT12_RESULT_Pos) |
| #define | ADC_DAT12_OV_Pos (16) |
| #define | ADC_DAT12_OV_Msk (0x1ul << ADC_DAT12_OV_Pos) |
| #define | ADC_DAT12_VALID_Pos (17) |
| #define | ADC_DAT12_VALID_Msk (0x1ul << ADC_DAT12_VALID_Pos) |
| #define | ADC_DAT13_RESULT_Pos (0) |
| #define | ADC_DAT13_RESULT_Msk (0xfffful << ADC_DAT13_RESULT_Pos) |
| #define | ADC_DAT13_OV_Pos (16) |
| #define | ADC_DAT13_OV_Msk (0x1ul << ADC_DAT13_OV_Pos) |
| #define | ADC_DAT13_VALID_Pos (17) |
| #define | ADC_DAT13_VALID_Msk (0x1ul << ADC_DAT13_VALID_Pos) |
| #define | ADC_CTL_ADCEN_Pos (0) |
| #define | ADC_CTL_ADCEN_Msk (0x1ul << ADC_CTL_ADCEN_Pos) |
| #define | ADC_CTL_ADCIEN_Pos (1) |
| #define | ADC_CTL_ADCIEN_Msk (0x1ul << ADC_CTL_ADCIEN_Pos) |
| #define | ADC_CTL_OPMODE_Pos (2) |
| #define | ADC_CTL_OPMODE_Msk (0x3ul << ADC_CTL_OPMODE_Pos) |
| #define | ADC_CTL_HWTRGSEL_Pos (4) |
| #define | ADC_CTL_HWTRGSEL_Msk (0x3ul << ADC_CTL_HWTRGSEL_Pos) |
| #define | ADC_CTL_HWTRGCOND_Pos (6) |
| #define | ADC_CTL_HWTRGCOND_Msk (0x3ul << ADC_CTL_HWTRGCOND_Pos) |
| #define | ADC_CTL_HWTRGEN_Pos (8) |
| #define | ADC_CTL_HWTRGEN_Msk (0x1ul << ADC_CTL_HWTRGEN_Pos) |
| #define | ADC_CTL_PDMAEN_Pos (9) |
| #define | ADC_CTL_PDMAEN_Msk (0x1ul << ADC_CTL_PDMAEN_Pos) |
| #define | ADC_CTL_DIFFEN_Pos (10) |
| #define | ADC_CTL_DIFFEN_Msk (0x1ul << ADC_CTL_DIFFEN_Pos) |
| #define | ADC_CTL_SWTRG_Pos (11) |
| #define | ADC_CTL_SWTRG_Msk (0x1ul << ADC_CTL_SWTRG_Pos) |
| #define | ADC_CTL_PWMTRGDLY_Pos (16) |
| #define | ADC_CTL_PWMTRGDLY_Msk (0xfful << ADC_CTL_PWMTRGDLY_Pos) |
| #define | ADC_CTL_DMOF_Pos (31) |
| #define | ADC_CTL_DMOF_Msk (0x1ul << ADC_CTL_DMOF_Pos) |
| #define | ADC_CHEN_CHEN_Pos (0) |
| #define | ADC_CHEN_CHEN_Msk (0xffful << ADC_CHEN_CHEN_Pos) |
| #define | ADC_CHEN_ADTSEN_Pos (16) |
| #define | ADC_CHEN_ADTSEN_Msk (0x1ul << ADC_CHEN_ADTSEN_Pos) |
| #define | ADC_CHEN_ADBGEN_Pos (17) |
| #define | ADC_CHEN_ADBGEN_Msk (0x1ul << ADC_CHEN_ADBGEN_Pos) |
| #define | ADC_CMP0_ADCMPEN_Pos (0) |
| #define | ADC_CMP0_ADCMPEN_Msk (0x1ul << ADC_CMP0_ADCMPEN_Pos) |
| #define | ADC_CMP0_ADCMPIE_Pos (1) |
| #define | ADC_CMP0_ADCMPIE_Msk (0x1ul << ADC_CMP0_ADCMPIE_Pos) |
| #define | ADC_CMP0_CMPCOND_Pos (2) |
| #define | ADC_CMP0_CMPCOND_Msk (0x1ul << ADC_CMP0_CMPCOND_Pos) |
| #define | ADC_CMP0_CMPCH_Pos (3) |
| #define | ADC_CMP0_CMPCH_Msk (0xful << ADC_CMP0_CMPCH_Pos) |
| #define | ADC_CMP0_CMPMCNT_Pos (8) |
| #define | ADC_CMP0_CMPMCNT_Msk (0xful << ADC_CMP0_CMPMCNT_Pos) |
| #define | ADC_CMP0_CMPDAT_Pos (16) |
| #define | ADC_CMP0_CMPDAT_Msk (0xffful << ADC_CMP0_CMPDAT_Pos) |
| #define | ADC_CMP1_ADCMPEN_Pos (0) |
| #define | ADC_CMP1_ADCMPEN_Msk (0x1ul << ADC_CMP1_ADCMPEN_Pos) |
| #define | ADC_CMP1_ADCMPIE_Pos (1) |
| #define | ADC_CMP1_ADCMPIE_Msk (0x1ul << ADC_CMP1_ADCMPIE_Pos) |
| #define | ADC_CMP1_CMPCOND_Pos (2) |
| #define | ADC_CMP1_CMPCOND_Msk (0x1ul << ADC_CMP1_CMPCOND_Pos) |
| #define | ADC_CMP1_CMPCH_Pos (3) |
| #define | ADC_CMP1_CMPCH_Msk (0xful << ADC_CMP1_CMPCH_Pos) |
| #define | ADC_CMP1_CMPMCNT_Pos (8) |
| #define | ADC_CMP1_CMPMCNT_Msk (0xful << ADC_CMP1_CMPMCNT_Pos) |
| #define | ADC_CMP1_CMPDAT_Pos (16) |
| #define | ADC_CMP1_CMPDAT_Msk (0xffful << ADC_CMP1_CMPDAT_Pos) |
| #define | ADC_STATUS0_ADIF_Pos (0) |
| #define | ADC_STATUS0_ADIF_Msk (0x1ul << ADC_STATUS0_ADIF_Pos) |
| #define | ADC_STATUS0_ADCMPF0_Pos (1) |
| #define | ADC_STATUS0_ADCMPF0_Msk (0x1ul << ADC_STATUS0_ADCMPF0_Pos) |
| #define | ADC_STATUS0_ADCMPF1_Pos (2) |
| #define | ADC_STATUS0_ADCMPF1_Msk (0x1ul << ADC_STATUS0_ADCMPF1_Pos) |
| #define | ADC_STATUS0_BUSY_Pos (3) |
| #define | ADC_STATUS0_BUSY_Msk (0x1ul << ADC_STATUS0_BUSY_Pos) |
| #define | ADC_STATUS0_CHANNEL_Pos (4) |
| #define | ADC_STATUS0_CHANNEL_Msk (0xful << ADC_STATUS0_CHANNEL_Pos) |
| #define | ADC_STATUS1_VALID_Pos (0) |
| #define | ADC_STATUS1_VALID_Msk (0x3ffful << ADC_STATUS1_VALID_Pos) |
| #define | ADC_STATUS1_OV_Pos (16) |
| #define | ADC_STATUS1_OV_Msk (0x3ffful << ADC_STATUS1_OV_Pos) |
| #define | ADC_CURDAT_CURDAT_Pos (0) |
| #define | ADC_CURDAT_CURDAT_Msk (0x3fffful << ADC_CURDAT_CURDAT_Pos) |
| #define | CAN_CON_TEST_Pos 7 |
| #define | CAN_CON_TEST_Msk (1ul << CAN_CON_TEST_Pos) |
| #define | CAN_CON_CCE_Pos 6 |
| #define | CAN_CON_CCE_Msk (1ul << CAN_CON_CCE_Pos) |
| #define | CAN_CON_DAR_Pos 5 |
| #define | CAN_CON_DAR_Msk (1ul << CAN_CON_DAR_Pos) |
| #define | CAN_CON_EIE_Pos 3 |
| #define | CAN_CON_EIE_Msk (1ul << CAN_CON_EIE_Pos) |
| #define | CAN_CON_SIE_Pos 2 |
| #define | CAN_CON_SIE_Msk (1ul << CAN_CON_SIE_Pos) |
| #define | CAN_CON_IE_Pos 1 |
| #define | CAN_CON_IE_Msk (1ul << CAN_CON_IE_Pos) |
| #define | CAN_CON_INIT_Pos 0 |
| #define | CAN_CON_INIT_Msk (1ul << CAN_CON_INIT_Pos) |
| #define | CAN_STATUS_BOFF_Pos 7 |
| #define | CAN_STATUS_BOFF_Msk (1ul << CAN_STATUS_BOFF_Pos) |
| #define | CAN_STATUS_EWARN_Pos 6 |
| #define | CAN_STATUS_EWARN_Msk (1ul << CAN_STATUS_EWARN_Pos) |
| #define | CAN_STATUS_EPASS_Pos 5 |
| #define | CAN_STATUS_EPASS_Msk (1ul << CAN_STATUS_EPASS_Pos) |
| #define | CAN_STATUS_RXOK_Pos 4 |
| #define | CAN_STATUS_RXOK_Msk (1ul << CAN_STATUS_RXOK_Pos) |
| #define | CAN_STATUS_TXOK_Pos 3 |
| #define | CAN_STATUS_TXOK_Msk (1ul << CAN_STATUS_TXOK_Pos) |
| #define | CAN_STATUS_LEC_Pos 0 |
| #define | CAN_STATUS_LEC_Msk (0x7ul << CAN_STATUS_LEC_Pos) |
| #define | CAN_ERR_RP_Pos 15 |
| #define | CAN_ERR_RP_Msk (1ul << CAN_ERR_RP_Pos) |
| #define | CAN_ERR_REC_Pos 8 |
| #define | CAN_ERR_REC_Msk (0x7Ful << CAN_ERR_REC_Pos) |
| #define | CAN_ERR_TEC_Pos 0 |
| #define | CAN_ERR_TEC_Msk (0xFFul << CAN_ERR_TEC_Pos) |
| #define | CAN_BTIME_TSEG2_Pos 12 |
| #define | CAN_BTIME_TSEG2_Msk (0x7ul << CAN_BTIME_TSEG2_Pos) |
| #define | CAN_BTIME_TSEG1_Pos 8 |
| #define | CAN_BTIME_TSEG1_Msk (0xFul << CAN_BTIME_TSEG1_Pos) |
| #define | CAN_BTIME_SJW_Pos 6 |
| #define | CAN_BTIME_SJW_Msk (0x3ul << CAN_BTIME_SJW_Pos) |
| #define | CAN_BTIME_BRP_Pos 0 |
| #define | CAN_BTIME_BRP_Msk (0x3Ful << CAN_BTIME_BRP_Pos) |
| #define | CAN_IIDR_INTID_Pos 0 |
| #define | CAN_IIDR_INTID_Msk (0xFFFFul << CAN_IIDR_INTID_Pos) |
| #define | CAN_TEST_RX_Pos 7 |
| #define | CAN_TEST_RX_Msk (1ul << CAN_TEST_RX_Pos) |
| #define | CAN_TEST_TX_Pos 5 |
| #define | CAN_TEST_TX_Msk (0x3ul << CAN_TEST_TX_Pos) |
| #define | CAN_TEST_LBACK_Pos 4 |
| #define | CAN_TEST_LBACK_Msk (1ul << CAN_TEST_LBACK_Pos) |
| #define | CAN_TEST_SILENT_Pos 3 |
| #define | CAN_TEST_SILENT_Msk (1ul << CAN_TEST_SILENT_Pos) |
| #define | CAN_TEST_BASIC_Pos 2 |
| #define | CAN_TEST_BASIC_Msk (1ul << CAN_TEST_BASIC_Pos) |
| #define | CAN_BRPE_BRPE_Pos 0 |
| #define | CAN_BRPE_BRPE_Msk (0xFul << CAN_BRPE_BRPE_Pos) |
| #define | CAN_IF_CREQ_BUSY_Pos 15 |
| #define | CAN_IF_CREQ_BUSY_Msk (1ul << CAN_IF_CREQ_BUSY_Pos) |
| #define | CAN_IF_CREQ_MSGNUM_Pos 0 |
| #define | CAN_IF_CREQ_MSGNUM_Msk (0x3Ful << CAN_IF_CREQ_MSGNUM_Pos) |
| #define | CAN_IF_CMASK_WRRD_Pos 7 |
| #define | CAN_IF_CMASK_WRRD_Msk (1ul << CAN_IF_CMASK_WRRD_Pos) |
| #define | CAN_IF_CMASK_MASK_Pos 6 |
| #define | CAN_IF_CMASK_MASK_Msk (1ul << CAN_IF_CMASK_MASK_Pos) |
| #define | CAN_IF_CMASK_ARB_Pos 5 |
| #define | CAN_IF_CMASK_ARB_Msk (1ul << CAN_IF_CMASK_ARB_Pos) |
| #define | CAN_IF_CMASK_CONTROL_Pos 4 |
| #define | CAN_IF_CMASK_CONTROL_Msk (1ul << CAN_IF_CMASK_CONTROL_Pos) |
| #define | CAN_IF_CMASK_CLRINTPND_Pos 3 |
| #define | CAN_IF_CMASK_CLRINTPND_Msk (1ul << CAN_IF_CMASK_CLRINTPND_Pos) |
| #define | CAN_IF_CMASK_TXRQSTNEWDAT_Pos 2 |
| #define | CAN_IF_CMASK_TXRQSTNEWDAT_Msk (1ul << CAN_IF_CMASK_TXRQSTNEWDAT_Pos) |
| #define | CAN_IF_CMASK_DATAA_Pos 1 |
| #define | CAN_IF_CMASK_DATAA_Msk (1ul << CAN_IF_CMASK_DATAA_Pos) |
| #define | CAN_IF_CMASK_DATAB_Pos 0 |
| #define | CAN_IF_CMASK_DATAB_Msk (1ul << CAN_IF_CMASK_DATAB_Pos) |
| #define | CAN_IF_MASK1_MSK_Pos 0 |
| #define | CAN_IF_MASK1_MSK_Msk (0xFFul << CAN_IF_MASK1_MSK_Pos) |
| #define | CAN_IF_MASK2_MXTD_Pos 15 |
| #define | CAN_IF_MASK2_MXTD_Msk (1ul << CAN_IF_MASK2_MXTD_Pos) |
| #define | CAN_IF_MASK2_MDIR_Pos 14 |
| #define | CAN_IF_MASK2_MDIR_Msk (1ul << CAN_IF_MASK2_MDIR_Pos) |
| #define | CAN_IF_MASK2_MSK_Pos 0 |
| #define | CAN_IF_MASK2_MSK_Msk (0x1FFul << CAN_IF_MASK2_MSK_Pos) |
| #define | CAN_IF_ARB1_ID_Pos 0 |
| #define | CAN_IF_ARB1_ID_Msk (0xFFFFul << CAN_IF_ARB1_ID_Pos) |
| #define | CAN_IF_ARB2_MSGVAL_Pos 15 |
| #define | CAN_IF_ARB2_MSGVAL_Msk (1ul << CAN_IF_ARB2_MSGVAL_Pos) |
| #define | CAN_IF_ARB2_XTD_Pos 14 |
| #define | CAN_IF_ARB2_XTD_Msk (1ul << CAN_IF_ARB2_XTD_Pos) |
| #define | CAN_IF_ARB2_DIR_Pos 13 |
| #define | CAN_IF_ARB2_DIR_Msk (1ul << CAN_IF_ARB2_DIR_Pos) |
| #define | CAN_IF_ARB2_ID_Pos 0 |
| #define | CAN_IF_ARB2_ID_Msk (0x1FFFul << CAN_IF_ARB2_ID_Pos) |
| #define | CAN_IF_MCON_NEWDAT_Pos 15 |
| #define | CAN_IF_MCON_NEWDAT_Msk (1ul << CAN_IF_MCON_NEWDAT_Pos) |
| #define | CAN_IF_MCON_MSGLST_Pos 14 |
| #define | CAN_IF_MCON_MSGLST_Msk (1ul << CAN_IF_MCON_MSGLST_Pos) |
| #define | CAN_IF_MCON_INTPND_Pos 13 |
| #define | CAN_IF_MCON_INTPND_Msk (1ul << CAN_IF_MCON_INTPND_Pos) |
| #define | CAN_IF_MCON_UMASK_Pos 12 |
| #define | CAN_IF_MCON_UMASK_Msk (1ul << CAN_IF_MCON_UMASK_Pos) |
| #define | CAN_IF_MCON_TXIE_Pos 11 |
| #define | CAN_IF_MCON_TXIE_Msk (1ul << CAN_IF_MCON_TXIE_Pos) |
| #define | CAN_IF_MCON_RXIE_Pos 10 |
| #define | CAN_IF_MCON_RXIE_Msk (1ul << CAN_IF_MCON_RXIE_Pos) |
| #define | CAN_IF_MCON_RMTEN_Pos 9 |
| #define | CAN_IF_MCON_RMTEN_Msk (1ul << CAN_IF_MCON_RMTEN_Pos) |
| #define | CAN_IF_MCON_TXRQST_Pos 8 |
| #define | CAN_IF_MCON_TXRQST_Msk (1ul << CAN_IF_MCON_TXRQST_Pos) |
| #define | CAN_IF_MCON_EOB_Pos 7 |
| #define | CAN_IF_MCON_EOB_Msk (1ul << CAN_IF_MCON_EOB_Pos) |
| #define | CAN_IF_MCON_DLC_Pos 0 |
| #define | CAN_IF_MCON_DLC_Msk (0xFul << CAN_IF_MCON_DLC_Pos) |
| #define | CAN_IF_DAT_A1_DATA1_Pos 8 |
| #define | CAN_IF_DAT_A1_DATA1_Msk (0xFFul << CAN_IF_DAT_A1_DATA1_Pos) |
| #define | CAN_IF_DAT_A1_DATA0_Pos 0 |
| #define | CAN_IF_DAT_A1_DATA0_Msk (0xFFul << CAN_IF_DAT_A1_DATA0_Pos) |
| #define | CAN_IF_DAT_A2_DATA3_Pos 8 |
| #define | CAN_IF_DAT_A2_DATA3_Msk (0xFFul << CAN_IF_DAT_A2_DATA3_Pos) |
| #define | CAN_IF_DAT_A2_DATA2_Pos 0 |
| #define | CAN_IF_DAT_A2_DATA2_Msk (0xFFul << CAN_IF_DAT_A2_DATA2_Pos) |
| #define | CAN_IF_DAT_B1_DATA5_Pos 8 |
| #define | CAN_IF_DAT_B1_DATA5_Msk (0xFFul << CAN_IF_DAT_B1_DATA5_Pos) |
| #define | CAN_IF_DAT_B1_DATA4_Pos 0 |
| #define | CAN_IF_DAT_B1_DATA4_Msk (0xFFul << CAN_IF_DAT_B1_DATA4_Pos) |
| #define | CAN_IF_DAT_B2_DATA7_Pos 8 |
| #define | CAN_IF_DAT_B2_DATA7_Msk (0xFFul << CAN_IF_DAT_B2_DATA7_Pos) |
| #define | CAN_IF_DAT_B2_DATA6_Pos 0 |
| #define | CAN_IF_DAT_B2_DATA6_Msk (0xFFul << CAN_IF_DAT_B2_DATA6_Pos) |
| #define | CAN_IF_TXRQST1_TXRQST_Pos 0 |
| #define | CAN_IF_TXRQST1_TXRQST_Msk (0xFFFFul << CAN_IF_TXRQST1_TXRQST_Pos) |
| #define | CAN_IF_TXRQST2_TXRQST_Pos 0 |
| #define | CAN_IF_TXRQST2_TXRQST_Msk (0xFFFFul << CAN_IF_TXRQST2_TXRQST_Pos) |
| #define | CAN_IF_NDAT1_NEWDATA_Pos 0 |
| #define | CAN_IF_NDAT1_NEWDATA_Msk (0xFFFFul << CAN_IF_NDAT1_NEWDATA_Pos) |
| #define | CAN_IF_NDAT2_NEWDATA_Pos 0 |
| #define | CAN_IF_NDAT2_NEWDATA_Msk (0xFFFFul << CAN_IF_NDAT2_NEWDATA_Pos) |
| #define | CAN_IF_IPND1_INTPND_Pos 0 |
| #define | CAN_IF_IPND1_INTPND_Msk (0xFFFFul << CAN_IF_IPND1_INTPND_Pos) |
| #define | CAN_IF_IPND2_INTPND_Pos 0 |
| #define | CAN_IF_IPND2_INTPND_Msk (0xFFFFul << CAN_IF_IPND2_INTPND_Pos) |
| #define | CAN_IF_MVLD1_MSGVAL_Pos 0 |
| #define | CAN_IF_MVLD1_MSGVAL_Msk (0xFFFFul << CAN_IF_MVLD1_MSGVAL_Pos) |
| #define | CAN_IF_MVLD2_MSGVAL_Pos 0 |
| #define | CAN_IF_MVLD2_MSGVAL_Msk (0xFFFFul << CAN_IF_MVLD2_MSGVAL_Pos) |
| #define | CAN_WUEN_WAKUP_EN_Pos 0 |
| #define | CAN_WUEN_WAKUP_EN_Msk (1ul << CAN_WUEN_WAKUP_EN_Pos) |
| #define | CAN_WUSTATUS_WAKUP_STS_Pos 0 |
| #define | CAN_WUSTATUS_WAKUP_STS_Msk (1ul << CAN_WUSTATUS_WAKUP_STS_Pos) |
| #define | CAP_CTL_CAPEN_Pos (0) |
| #define | CAP_CTL_CAPEN_Msk (0x1ul << CAP_CTL_CAPEN_Pos) |
| #define | CAP_CTL_ADDRSW_Pos (3) |
| #define | CAP_CTL_ADDRSW_Msk (0x1ul << CAP_CTL_ADDRSW_Pos) |
| #define | CAP_CTL_PLNEN_Pos (5) |
| #define | CAP_CTL_PLNEN_Msk (0x1ul << CAP_CTL_PLNEN_Pos) |
| #define | CAP_CTL_PKTEN_Pos (6) |
| #define | CAP_CTL_PKTEN_Msk (0x1ul << CAP_CTL_PKTEN_Pos) |
| #define | CAP_CTL_SHUTTER_Pos (16) |
| #define | CAP_CTL_SHUTTER_Msk (0x1ul << CAP_CTL_SHUTTER_Pos) |
| #define | CAP_CTL_UPDATE_Pos (20) |
| #define | CAP_CTL_UPDATE_Msk (0x1ul << CAP_CTL_UPDATE_Pos) |
| #define | CAP_CTL_VPRST_Pos (24) |
| #define | CAP_CTL_VPRST_Msk (0x1ul << CAP_CTL_VPRST_Pos) |
| #define | CAP_PAR_INFMT_Pos (0) |
| #define | CAP_PAR_INFMT_Msk (0x1ul << CAP_PAR_INFMT_Pos) |
| #define | CAP_PAR_SENTYPE_Pos (1) |
| #define | CAP_PAR_SENTYPE_Msk (0x1ul << CAP_PAR_SENTYPE_Pos) |
| #define | CAP_PAR_INDATORD_Pos (2) |
| #define | CAP_PAR_INDATORD_Msk (0x3ul << CAP_PAR_INDATORD_Pos) |
| #define | CAP_PAR_OUTFMT_Pos (4) |
| #define | CAP_PAR_OUTFMT_Msk (0x3ul << CAP_PAR_OUTFMT_Pos) |
| #define | CAP_PAR_RANGE_Pos (6) |
| #define | CAP_PAR_RANGE_Msk (0x1ul << CAP_PAR_RANGE_Pos) |
| #define | CAP_PAR_PLNFMT_Pos (7) |
| #define | CAP_PAR_PLNFMT_Msk (0x1ul << CAP_PAR_PLNFMT_Pos) |
| #define | CAP_PAR_PCLKP_Pos (8) |
| #define | CAP_PAR_PCLKP_Msk (0x1ul << CAP_PAR_PCLKP_Pos) |
| #define | CAP_PAR_HSP_Pos (9) |
| #define | CAP_PAR_HSP_Msk (0x1ul << CAP_PAR_HSP_Pos) |
| #define | CAP_PAR_VSP_Pos (10) |
| #define | CAP_PAR_VSP_Msk (0x1ul << CAP_PAR_VSP_Pos) |
| #define | CAP_PAR_COLORCTL_Pos (11) |
| #define | CAP_PAR_COLORCTL_Msk (0x3ul << CAP_PAR_COLORCTL_Pos) |
| #define | CAP_PAR_FBB_Pos (18) |
| #define | CAP_PAR_FBB_Msk (0x1ul << CAP_PAR_FBB_Pos) |
| #define | CAP_INT_VINTF_Pos (0) |
| #define | CAP_INT_VINTF_Msk (0x1ul << CAP_INT_VINTF_Pos) |
| #define | CAP_INT_MEINTF_Pos (1) |
| #define | CAP_INT_MEINTF_Msk (0x1ul << CAP_INT_MEINTF_Pos) |
| #define | CAP_INT_ADDRMINTF_Pos (3) |
| #define | CAP_INT_ADDRMINTF_Msk (0x1ul << CAP_INT_ADDRMINTF_Pos) |
| #define | CAP_INT_MDINTF_Pos (4) |
| #define | CAP_INT_MDINTF_Msk (0x1ul << CAP_INT_MDINTF_Pos) |
| #define | CAP_INT_VIEN_Pos (16) |
| #define | CAP_INT_VIEN_Msk (0x1ul << CAP_INT_VIEN_Pos) |
| #define | CAP_INT_MEIEN_Pos (17) |
| #define | CAP_INT_MEIEN_Msk (0x1ul << CAP_INT_MEIEN_Pos) |
| #define | CAP_INT_ADDRMIEN_Pos (19) |
| #define | CAP_INT_ADDRMIEN_Msk (0x1ul << CAP_INT_ADDRMIEN_Pos) |
| #define | CAP_INT_MDIEN_Pos (20) |
| #define | CAP_INT_MDIEN_Msk (0x1ul << CAP_INT_MDIEN_Pos) |
| #define | CAP_POSTERIZE_VCOMP_Pos (0) |
| #define | CAP_POSTERIZE_VCOMP_Msk (0xfful << CAP_POSTERIZE_VCOMP_Pos) |
| #define | CAP_POSTERIZE_UCOMP_Pos (8) |
| #define | CAP_POSTERIZE_UCOMP_Msk (0xfful << CAP_POSTERIZE_UCOMP_Pos) |
| #define | CAP_POSTERIZE_YCOMP_Pos (16) |
| #define | CAP_POSTERIZE_YCOMP_Msk (0xfful << CAP_POSTERIZE_YCOMP_Pos) |
| #define | CAP_MD_MDEN_Pos (0) |
| #define | CAP_MD_MDEN_Msk (0x1ul << CAP_MD_MDEN_Pos) |
| #define | CAP_MD_MDBS_Pos (8) |
| #define | CAP_MD_MDBS_Msk (0x1ul << CAP_MD_MDBS_Pos) |
| #define | CAP_MD_MDSM_Pos (9) |
| #define | CAP_MD_MDSM_Msk (0x1ul << CAP_MD_MDSM_Pos) |
| #define | CAP_MD_MDDF_Pos (10) |
| #define | CAP_MD_MDDF_Msk (0x3ul << CAP_MD_MDDF_Pos) |
| #define | CAP_MD_MDTHR_Pos (16) |
| #define | CAP_MD_MDTHR_Msk (0x1ful << CAP_MD_MDTHR_Pos) |
| #define | CAP_MDADDR_MDADDR_Pos (0) |
| #define | CAP_MDADDR_MDADDR_Msk (0xfffffffful << CAP_MDADDR_MDADDR_Pos) |
| #define | CAP_MDYADDR_MDYADDR_Pos (0) |
| #define | CAP_MDYADDR_MDYADDR_Msk (0xfffffffful << CAP_MDYADDR_MDYADDR_Pos) |
| #define | CAP_SEPIA_VCOMP_Pos (0) |
| #define | CAP_SEPIA_VCOMP_Msk (0xfful << CAP_SEPIA_VCOMP_Pos) |
| #define | CAP_SEPIA_UCOMP_Pos (8) |
| #define | CAP_SEPIA_UCOMP_Msk (0xfful << CAP_SEPIA_UCOMP_Pos) |
| #define | CAP_CWSP_CWSADDRH_Pos (0) |
| #define | CAP_CWSP_CWSADDRH_Msk (0xffful << CAP_CWSP_CWSADDRH_Pos) |
| #define | CAP_CWSP_CWSADDRV_Pos (16) |
| #define | CAP_CWSP_CWSADDRV_Msk (0x7fful << CAP_CWSP_CWSADDRV_Pos) |
| #define | CAP_CWS_CWW_Pos (0) |
| #define | CAP_CWS_CWW_Msk (0xffful << CAP_CWS_CWW_Pos) |
| #define | CAP_CWS_CWH_Pos (16) |
| #define | CAP_CWS_CWH_Msk (0x7fful << CAP_CWS_CWH_Pos) |
| #define | CAP_PKTSL_PKTSHML_Pos (0) |
| #define | CAP_PKTSL_PKTSHML_Msk (0xfful << CAP_PKTSL_PKTSHML_Pos) |
| #define | CAP_PKTSL_PKTSHNL_Pos (8) |
| #define | CAP_PKTSL_PKTSHNL_Msk (0xfful << CAP_PKTSL_PKTSHNL_Pos) |
| #define | CAP_PKTSL_PKTSVML_Pos (16) |
| #define | CAP_PKTSL_PKTSVML_Msk (0xfful << CAP_PKTSL_PKTSVML_Pos) |
| #define | CAP_PKTSL_PKTSVNL_Pos (24) |
| #define | CAP_PKTSL_PKTSVNL_Msk (0xfful << CAP_PKTSL_PKTSVNL_Pos) |
| #define | CAP_PLNSL_PLNSHML_Pos (0) |
| #define | CAP_PLNSL_PLNSHML_Msk (0xfful << CAP_PLNSL_PLNSHML_Pos) |
| #define | CAP_PLNSL_PLNSHNL_Pos (8) |
| #define | CAP_PLNSL_PLNSHNL_Msk (0xfful << CAP_PLNSL_PLNSHNL_Pos) |
| #define | CAP_PLNSL_PLNSVML_Pos (16) |
| #define | CAP_PLNSL_PLNSVML_Msk (0xfful << CAP_PLNSL_PLNSVML_Pos) |
| #define | CAP_PLNSL_PLNSVNL_Pos (24) |
| #define | CAP_PLNSL_PLNSVNL_Msk (0xfful << CAP_PLNSL_PLNSVNL_Pos) |
| #define | CAP_FRCTL_FRM_Pos (0) |
| #define | CAP_FRCTL_FRM_Msk (0x3ful << CAP_FRCTL_FRM_Pos) |
| #define | CAP_FRCTL_FRN_Pos (8) |
| #define | CAP_FRCTL_FRN_Msk (0x3ful << CAP_FRCTL_FRN_Pos) |
| #define | CAP_STRIDE_PKTSTRIDE_Pos (0) |
| #define | CAP_STRIDE_PKTSTRIDE_Msk (0x3ffful << CAP_STRIDE_PKTSTRIDE_Pos) |
| #define | CAP_STRIDE_PLNSTRIDE_Pos (16) |
| #define | CAP_STRIDE_PLNSTRIDE_Msk (0x3ffful << CAP_STRIDE_PLNSTRIDE_Pos) |
| #define | CAP_FIFOTH_PLNVFTH_Pos (0) |
| #define | CAP_FIFOTH_PLNVFTH_Msk (0xful << CAP_FIFOTH_PLNVFTH_Pos) |
| #define | CAP_FIFOTH_PLNUFTH_Pos (8) |
| #define | CAP_FIFOTH_PLNUFTH_Msk (0xful << CAP_FIFOTH_PLNUFTH_Pos) |
| #define | CAP_FIFOTH_PLNYFTH_Pos (16) |
| #define | CAP_FIFOTH_PLNYFTH_Msk (0x1ful << CAP_FIFOTH_PLNYFTH_Pos) |
| #define | CAP_FIFOTH_PKTFTH_Pos (24) |
| #define | CAP_FIFOTH_PKTFTH_Msk (0x1ful << CAP_FIFOTH_PKTFTH_Pos) |
| #define | CAP_FIFOTH_OVF_Pos (31) |
| #define | CAP_FIFOTH_OVF_Msk (0x1ul << CAP_FIFOTH_OVF_Pos) |
| #define | CAP_CMPADDR_CMPADDR_Pos (0) |
| #define | CAP_CMPADDR_CMPADDR_Msk (0xfffffffful << CAP_CMPADDR_CMPADDR_Pos) |
| #define | CAP_PKTSM_PKTSHMH_Pos (0) |
| #define | CAP_PKTSM_PKTSHMH_Msk (0xfful << CAP_PKTSM_PKTSHMH_Pos) |
| #define | CAP_PKTSM_PKTSHNH_Pos (8) |
| #define | CAP_PKTSM_PKTSHNH_Msk (0xfful << CAP_PKTSM_PKTSHNH_Pos) |
| #define | CAP_PKTSM_PKTSVMH_Pos (16) |
| #define | CAP_PKTSM_PKTSVMH_Msk (0xfful << CAP_PKTSM_PKTSVMH_Pos) |
| #define | CAP_PKTSM_PKTSVNH_Pos (24) |
| #define | CAP_PKTSM_PKTSVNH_Msk (0xfful << CAP_PKTSM_PKTSVNH_Pos) |
| #define | CAP_PLNSM_PLNSHMH_Pos (0) |
| #define | CAP_PLNSM_PLNSHMH_Msk (0xfful << CAP_PLNSM_PLNSHMH_Pos) |
| #define | CAP_PLNSM_PLNSHNH_Pos (8) |
| #define | CAP_PLNSM_PLNSHNH_Msk (0xfful << CAP_PLNSM_PLNSHNH_Pos) |
| #define | CAP_PLNSM_PLNSVMH_Pos (16) |
| #define | CAP_PLNSM_PLNSVMH_Msk (0xfful << CAP_PLNSM_PLNSVMH_Pos) |
| #define | CAP_PLNSM_PLNSVNH_Pos (24) |
| #define | CAP_PLNSM_PLNSVNH_Msk (0xfful << CAP_PLNSM_PLNSVNH_Pos) |
| #define | CAP_CURADDRP_CURADDR_Pos (0) |
| #define | CAP_CURADDRP_CURADDR_Msk (0xfffffffful << CAP_CURADDRP_CURADDR_Pos) |
| #define | CAP_CURADDRY_CURADDR_Pos (0) |
| #define | CAP_CURADDRY_CURADDR_Msk (0xfffffffful << CAP_CURADDRY_CURADDR_Pos) |
| #define | CAP_CURADDRU_CURADDR_Pos (0) |
| #define | CAP_CURADDRU_CURADDR_Msk (0xfffffffful << CAP_CURADDRU_CURADDR_Pos) |
| #define | CAP_CURVADDR_CURADDR_Pos (0) |
| #define | CAP_CURVADDR_CURADDR_Msk (0xfffffffful << CAP_CURVADDR_CURADDR_Pos) |
| #define | CAP_PKTBA0_BASEADDR_Pos (0) |
| #define | CAP_PKTBA0_BASEADDR_Msk (0xfffffffful << CAP_PKTBA0_BASEADDR_Pos) |
| #define | CAP_PKTBA1_BASEADDR_Pos (0) |
| #define | CAP_PKTBA1_BASEADDR_Msk (0xfffffffful << CAP_PKTBA1_BASEADDR_Pos) |
| #define | CAP_YBA_BASEADDR_Pos (0) |
| #define | CAP_YBA_BASEADDR_Msk (0xfffffffful << CAP_YBA_BASEADDR_Pos) |
| #define | CAP_UBA_BASEADDR_Pos (0) |
| #define | CAP_UBA_BASEADDR_Msk (0xfffffffful << CAP_UBA_BASEADDR_Pos) |
| #define | CAP_VBA_BASEADDR_Pos (0) |
| #define | CAP_VBA_BASEADDR_Msk (0xfffffffful << CAP_VBA_BASEADDR_Pos) |
| #define | ECAP_CNT_VAL_Pos (0) |
| #define | ECAP_CNT_VAL_Msk (0xfffffful << ECAP_CNT_VAL_Pos) |
| #define | ECAP_HOLD0_VAL_Pos (0) |
| #define | ECAP_HOLD0_VAL_Msk (0xfffffful << ECAP_HOLD0_VAL_Pos) |
| #define | ECAP_HOLD1_VAL_Pos (0) |
| #define | ECAP_HOLD1_VAL_Msk (0xfffffful << ECAP_HOLD1_VAL_Pos) |
| #define | ECAP_HOLD2_VAL_Pos (0) |
| #define | ECAP_HOLD2_VAL_Msk (0xfffffful << ECAP_HOLD2_VAL_Pos) |
| #define | ECAP_CNTCMP_VAL_Pos (0) |
| #define | ECAP_CNTCMP_VAL_Msk (0xfffffful << ECAP_CNTCMP_VAL_Pos) |
| #define | ECAP_CTL0_NFDIS_Pos (0) |
| #define | ECAP_CTL0_NFDIS_Msk (0x3ul << ECAP_CTL0_NFDIS_Pos) |
| #define | ECAP_CTL0_CAPNF_DIS_Pos (3) |
| #define | ECAP_CTL0_CAPNF_DIS_Msk (0x1ul << ECAP_CTL0_CAPNF_DIS_Pos) |
| #define | ECAP_CTL0_CAPEN0_Pos (4) |
| #define | ECAP_CTL0_CAPEN0_Msk (0x1ul << ECAP_CTL0_CAPEN0_Pos) |
| #define | ECAP_CTL0_CAPEN1_Pos (5) |
| #define | ECAP_CTL0_CAPEN1_Msk (0x1ul << ECAP_CTL0_CAPEN1_Pos) |
| #define | ECAP_CTL0_CAPEN2_Pos (6) |
| #define | ECAP_CTL0_CAPEN2_Msk (0x1ul << ECAP_CTL0_CAPEN2_Pos) |
| #define | ECAP_CTL0_CAPSEL0_Pos (8) |
| #define | ECAP_CTL0_CAPSEL0_Msk (0x3ul << ECAP_CTL0_CAPSEL0_Pos) |
| #define | ECAP_CTL0_CAPSEL1_Pos (10) |
| #define | ECAP_CTL0_CAPSEL1_Msk (0x3ul << ECAP_CTL0_CAPSEL1_Pos) |
| #define | ECAP_CTL0_CAPSEL2_Pos (12) |
| #define | ECAP_CTL0_CAPSEL2_Msk (0x3ul << ECAP_CTL0_CAPSEL2_Pos) |
| #define | ECAP_CTL0_CAPIEN0_Pos (16) |
| #define | ECAP_CTL0_CAPIEN0_Msk (0x1ul << ECAP_CTL0_CAPIEN0_Pos) |
| #define | ECAP_CTL0_CAPIEN1_Pos (17) |
| #define | ECAP_CTL0_CAPIEN1_Msk (0x1ul << ECAP_CTL0_CAPIEN1_Pos) |
| #define | ECAP_CTL0_CAPIEN2_Pos (18) |
| #define | ECAP_CTL0_CAPIEN2_Msk (0x1ul << ECAP_CTL0_CAPIEN2_Pos) |
| #define | ECAP_CTL0_OVIEN_Pos (20) |
| #define | ECAP_CTL0_OVIEN_Msk (0x1ul << ECAP_CTL0_OVIEN_Pos) |
| #define | ECAP_CTL0_CMPIEN_Pos (21) |
| #define | ECAP_CTL0_CMPIEN_Msk (0x1ul << ECAP_CTL0_CMPIEN_Pos) |
| #define | ECAP_CTL0_CNTEN_Pos (24) |
| #define | ECAP_CTL0_CNTEN_Msk (0x1ul << ECAP_CTL0_CNTEN_Pos) |
| #define | ECAP_CTL0_CMPCLR_Pos (25) |
| #define | ECAP_CTL0_CMPCLR_Msk (0x1ul << ECAP_CTL0_CMPCLR_Pos) |
| #define | ECAP_CTL0_CPTCLR_Pos (26) |
| #define | ECAP_CTL0_CPTCLR_Msk (0x1ul << ECAP_CTL0_CPTCLR_Pos) |
| #define | ECAP_CTL0_RLDEN_Pos (27) |
| #define | ECAP_CTL0_RLDEN_Msk (0x1ul << ECAP_CTL0_RLDEN_Pos) |
| #define | ECAP_CTL0_CMPEN_Pos (28) |
| #define | ECAP_CTL0_CMPEN_Msk (0x1ul << ECAP_CTL0_CMPEN_Pos) |
| #define | ECAP_CTL0_CAPEN_Pos (29) |
| #define | ECAP_CTL0_CAPEN_Msk (0x1ul << ECAP_CTL0_CAPEN_Pos) |
| #define | ECAP_CTL1_EDGESEL0_Pos (0) |
| #define | ECAP_CTL1_EDGESEL0_Msk (0x3ul << ECAP_CTL1_EDGESEL0_Pos) |
| #define | ECAP_CTL1_EDGESEL1_Pos (2) |
| #define | ECAP_CTL1_EDGESEL1_Msk (0x3ul << ECAP_CTL1_EDGESEL1_Pos) |
| #define | ECAP_CTL1_EDGESEL2_Pos (4) |
| #define | ECAP_CTL1_EDGESEL2_Msk (0x3ul << ECAP_CTL1_EDGESEL2_Pos) |
| #define | ECAP_CTL1_RLDSEL_Pos (8) |
| #define | ECAP_CTL1_RLDSEL_Msk (0x7ul << ECAP_CTL1_RLDSEL_Pos) |
| #define | ECAP_CTL1_CLKSEL_Pos (12) |
| #define | ECAP_CTL1_CLKSEL_Msk (0x7ul << ECAP_CTL1_CLKSEL_Pos) |
| #define | ECAP_CTL1_SRCSEL_Pos (16) |
| #define | ECAP_CTL1_SRCSEL_Msk (0x3ul << ECAP_CTL1_SRCSEL_Pos) |
| #define | ECAP_STATUS_CAPF0_Pos (0) |
| #define | ECAP_STATUS_CAPF0_Msk (0x1ul << ECAP_STATUS_CAPF0_Pos) |
| #define | ECAP_STATUS_CAPF1_Pos (1) |
| #define | ECAP_STATUS_CAPF1_Msk (0x1ul << ECAP_STATUS_CAPF1_Pos) |
| #define | ECAP_STATUS_CAPF2_Pos (2) |
| #define | ECAP_STATUS_CAPF2_Msk (0x1ul << ECAP_STATUS_CAPF2_Pos) |
| #define | ECAP_STATUS_CMPF_Pos (4) |
| #define | ECAP_STATUS_CMPF_Msk (0x1ul << ECAP_STATUS_CMPF_Pos) |
| #define | ECAP_STATUS_OVF_Pos (5) |
| #define | ECAP_STATUS_OVF_Msk (0x1ul << ECAP_STATUS_OVF_Pos) |
| #define | CLK_PWRCTL_HXTEN_Pos (0) |
| #define | CLK_PWRCTL_HXTEN_Msk (0x1ul << CLK_PWRCTL_HXTEN_Pos) |
| #define | CLK_PWRCTL_LXTEN_Pos (1) |
| #define | CLK_PWRCTL_LXTEN_Msk (0x1ul << CLK_PWRCTL_LXTEN_Pos) |
| #define | CLK_PWRCTL_HIRCEN_Pos (2) |
| #define | CLK_PWRCTL_HIRCEN_Msk (0x1ul << CLK_PWRCTL_HIRCEN_Pos) |
| #define | CLK_PWRCTL_LIRCEN_Pos (3) |
| #define | CLK_PWRCTL_LIRCEN_Msk (0x1ul << CLK_PWRCTL_LIRCEN_Pos) |
| #define | CLK_PWRCTL_PDWKDLY_Pos (4) |
| #define | CLK_PWRCTL_PDWKDLY_Msk (0x1ul << CLK_PWRCTL_PDWKDLY_Pos) |
| #define | CLK_PWRCTL_PDWKIEN_Pos (5) |
| #define | CLK_PWRCTL_PDWKIEN_Msk (0x1ul << CLK_PWRCTL_PDWKIEN_Pos) |
| #define | CLK_PWRCTL_PDWKIF_Pos (6) |
| #define | CLK_PWRCTL_PDWKIF_Msk (0x1ul << CLK_PWRCTL_PDWKIF_Pos) |
| #define | CLK_PWRCTL_PDEN_Pos (7) |
| #define | CLK_PWRCTL_PDEN_Msk (0x1ul << CLK_PWRCTL_PDEN_Pos) |
| #define | CLK_PWRCTL_PDWTCPU_Pos (8) |
| #define | CLK_PWRCTL_PDWTCPU_Msk (0x1ul << CLK_PWRCTL_PDWTCPU_Pos) |
| #define | CLK_PWRCTL_DBPDEN_Pos (9) |
| #define | CLK_PWRCTL_DBPDEN_Msk (0x1ul << CLK_PWRCTL_DBPDEN_Pos) |
| #define | CLK_AHBCLK_PDMACKEN_Pos (1) |
| #define | CLK_AHBCLK_PDMACKEN_Msk (0x1ul << CLK_AHBCLK_PDMACKEN_Pos) |
| #define | CLK_AHBCLK_ISPCKEN_Pos (2) |
| #define | CLK_AHBCLK_ISPCKEN_Msk (0x1ul << CLK_AHBCLK_ISPCKEN_Pos) |
| #define | CLK_AHBCLK_EBICKEN_Pos (3) |
| #define | CLK_AHBCLK_EBICKEN_Msk (0x1ul << CLK_AHBCLK_EBICKEN_Pos) |
| #define | CLK_AHBCLK_USBHCKEN_Pos (4) |
| #define | CLK_AHBCLK_USBHCKEN_Msk (0x1ul << CLK_AHBCLK_USBHCKEN_Pos) |
| #define | CLK_AHBCLK_EMACCKEN_Pos (5) |
| #define | CLK_AHBCLK_EMACCKEN_Msk (0x1ul << CLK_AHBCLK_EMACCKEN_Pos) |
| #define | CLK_AHBCLK_SDHCKEN_Pos (6) |
| #define | CLK_AHBCLK_SDHCKEN_Msk (0x1ul << CLK_AHBCLK_SDHCKEN_Pos) |
| #define | CLK_AHBCLK_CRCCKEN_Pos (7) |
| #define | CLK_AHBCLK_CRCCKEN_Msk (0x1ul << CLK_AHBCLK_CRCCKEN_Pos) |
| #define | CLK_AHBCLK_CAPCKEN_Pos (8) |
| #define | CLK_AHBCLK_CAPCKEN_Msk (0x1ul << CLK_AHBCLK_CAPCKEN_Pos) |
| #define | CLK_AHBCLK_SENCKEN_Pos (9) |
| #define | CLK_AHBCLK_SENCKEN_Msk (0x1ul << CLK_AHBCLK_SENCKEN_Pos) |
| #define | CLK_AHBCLK_USBDCKEN_Pos (10) |
| #define | CLK_AHBCLK_USBDCKEN_Msk (0x1ul << CLK_AHBCLK_USBDCKEN_Pos) |
| #define | CLK_AHBCLK_CRPTCKEN_Pos (12) |
| #define | CLK_AHBCLK_CRPTCKEN_Msk (0x1ul << CLK_AHBCLK_CRPTCKEN_Pos) |
| #define | CLK_APBCLK0_WDTCKEN_Pos (0) |
| #define | CLK_APBCLK0_WDTCKEN_Msk (0x1ul << CLK_APBCLK0_WDTCKEN_Pos) |
| #define | CLK_APBCLK0_RTCCKEN_Pos (1) |
| #define | CLK_APBCLK0_RTCCKEN_Msk (0x1ul << CLK_APBCLK0_RTCCKEN_Pos) |
| #define | CLK_APBCLK0_TMR0CKEN_Pos (2) |
| #define | CLK_APBCLK0_TMR0CKEN_Msk (0x1ul << CLK_APBCLK0_TMR0CKEN_Pos) |
| #define | CLK_APBCLK0_TMR1CKEN_Pos (3) |
| #define | CLK_APBCLK0_TMR1CKEN_Msk (0x1ul << CLK_APBCLK0_TMR1CKEN_Pos) |
| #define | CLK_APBCLK0_TMR2CKEN_Pos (4) |
| #define | CLK_APBCLK0_TMR2CKEN_Msk (0x1ul << CLK_APBCLK0_TMR2CKEN_Pos) |
| #define | CLK_APBCLK0_TMR3CKEN_Pos (5) |
| #define | CLK_APBCLK0_TMR3CKEN_Msk (0x1ul << CLK_APBCLK0_TMR3CKEN_Pos) |
| #define | CLK_APBCLK0_CLKOCKEN_Pos (6) |
| #define | CLK_APBCLK0_CLKOCKEN_Msk (0x1ul << CLK_APBCLK0_CLKOCKEN_Pos) |
| #define | CLK_APBCLK0_ACMPCKEN_Pos (7) |
| #define | CLK_APBCLK0_ACMPCKEN_Msk (0x1ul << CLK_APBCLK0_ACMPCKEN_Pos) |
| #define | CLK_APBCLK0_I2C0CKEN_Pos (8) |
| #define | CLK_APBCLK0_I2C0CKEN_Msk (0x1ul << CLK_APBCLK0_I2C0CKEN_Pos) |
| #define | CLK_APBCLK0_I2C1CKEN_Pos (9) |
| #define | CLK_APBCLK0_I2C1CKEN_Msk (0x1ul << CLK_APBCLK0_I2C1CKEN_Pos) |
| #define | CLK_APBCLK0_I2C2CKEN_Pos (10) |
| #define | CLK_APBCLK0_I2C2CKEN_Msk (0x1ul << CLK_APBCLK0_I2C2CKEN_Pos) |
| #define | CLK_APBCLK0_I2C3CKEN_Pos (11) |
| #define | CLK_APBCLK0_I2C3CKEN_Msk (0x1ul << CLK_APBCLK0_I2C3CKEN_Pos) |
| #define | CLK_APBCLK0_SPI0CKEN_Pos (12) |
| #define | CLK_APBCLK0_SPI0CKEN_Msk (0x1ul << CLK_APBCLK0_SPI0CKEN_Pos) |
| #define | CLK_APBCLK0_SPI1CKEN_Pos (13) |
| #define | CLK_APBCLK0_SPI1CKEN_Msk (0x1ul << CLK_APBCLK0_SPI1CKEN_Pos) |
| #define | CLK_APBCLK0_SPI2CKEN_Pos (14) |
| #define | CLK_APBCLK0_SPI2CKEN_Msk (0x1ul << CLK_APBCLK0_SPI2CKEN_Pos) |
| #define | CLK_APBCLK0_SPI3CKEN_Pos (15) |
| #define | CLK_APBCLK0_SPI3CKEN_Msk (0x1ul << CLK_APBCLK0_SPI3CKEN_Pos) |
| #define | CLK_APBCLK0_UART0CKEN_Pos (16) |
| #define | CLK_APBCLK0_UART0CKEN_Msk (0x1ul << CLK_APBCLK0_UART0CKEN_Pos) |
| #define | CLK_APBCLK0_UART1CKEN_Pos (17) |
| #define | CLK_APBCLK0_UART1CKEN_Msk (0x1ul << CLK_APBCLK0_UART1CKEN_Pos) |
| #define | CLK_APBCLK0_UART2CKEN_Pos (18) |
| #define | CLK_APBCLK0_UART2CKEN_Msk (0x1ul << CLK_APBCLK0_UART2CKEN_Pos) |
| #define | CLK_APBCLK0_UART3CKEN_Pos (19) |
| #define | CLK_APBCLK0_UART3CKEN_Msk (0x1ul << CLK_APBCLK0_UART3CKEN_Pos) |
| #define | CLK_APBCLK0_UART4CKEN_Pos (20) |
| #define | CLK_APBCLK0_UART4CKEN_Msk (0x1ul << CLK_APBCLK0_UART4CKEN_Pos) |
| #define | CLK_APBCLK0_UART5CKEN_Pos (21) |
| #define | CLK_APBCLK0_UART5CKEN_Msk (0x1ul << CLK_APBCLK0_UART5CKEN_Pos) |
| #define | CLK_APBCLK0_CAN0CKEN_Pos (24) |
| #define | CLK_APBCLK0_CAN0CKEN_Msk (0x1ul << CLK_APBCLK0_CAN0CKEN_Pos) |
| #define | CLK_APBCLK0_CAN1CKEN_Pos (25) |
| #define | CLK_APBCLK0_CAN1CKEN_Msk (0x1ul << CLK_APBCLK0_CAN1CKEN_Pos) |
| #define | CLK_APBCLK0_OTGCKEN_Pos (26) |
| #define | CLK_APBCLK0_OTGCKEN_Msk (0x1ul << CLK_APBCLK0_OTGCKEN_Pos) |
| #define | CLK_APBCLK0_ADCCKEN_Pos (28) |
| #define | CLK_APBCLK0_ADCCKEN_Msk (0x1ul << CLK_APBCLK0_ADCCKEN_Pos) |
| #define | CLK_APBCLK0_I2S0CKEN_Pos (29) |
| #define | CLK_APBCLK0_I2S0CKEN_Msk (0x1ul << CLK_APBCLK0_I2S0CKEN_Pos) |
| #define | CLK_APBCLK0_I2S1CKEN_Pos (30) |
| #define | CLK_APBCLK0_I2S1CKEN_Msk (0x1ul << CLK_APBCLK0_I2S1CKEN_Pos) |
| #define | CLK_APBCLK0_PS2CKEN_Pos (31) |
| #define | CLK_APBCLK0_PS2CKEN_Msk (0x1ul << CLK_APBCLK0_PS2CKEN_Pos) |
| #define | CLK_APBCLK1_SC0CKEN_Pos (0) |
| #define | CLK_APBCLK1_SC0CKEN_Msk (0x1ul << CLK_APBCLK1_SC0CKEN_Pos) |
| #define | CLK_APBCLK1_SC1CKEN_Pos (1) |
| #define | CLK_APBCLK1_SC1CKEN_Msk (0x1ul << CLK_APBCLK1_SC1CKEN_Pos) |
| #define | CLK_APBCLK1_SC2CKEN_Pos (2) |
| #define | CLK_APBCLK1_SC2CKEN_Msk (0x1ul << CLK_APBCLK1_SC2CKEN_Pos) |
| #define | CLK_APBCLK1_SC3CKEN_Pos (3) |
| #define | CLK_APBCLK1_SC3CKEN_Msk (0x1ul << CLK_APBCLK1_SC3CKEN_Pos) |
| #define | CLK_APBCLK1_SC4CKEN_Pos (4) |
| #define | CLK_APBCLK1_SC4CKEN_Msk (0x1ul << CLK_APBCLK1_SC4CKEN_Pos) |
| #define | CLK_APBCLK1_SC5CKEN_Pos (5) |
| #define | CLK_APBCLK1_SC5CKEN_Msk (0x1ul << CLK_APBCLK1_SC5CKEN_Pos) |
| #define | CLK_APBCLK1_I2C4CKEN_Pos (8) |
| #define | CLK_APBCLK1_I2C4CKEN_Msk (0x1ul << CLK_APBCLK1_I2C4CKEN_Pos) |
| #define | CLK_APBCLK1_PWM0CH01CKEN_Pos (16) |
| #define | CLK_APBCLK1_PWM0CH01CKEN_Msk (0x1ul << CLK_APBCLK1_PWM0CH01CKEN_Pos) |
| #define | CLK_APBCLK1_PWM0CH23CKEN_Pos (17) |
| #define | CLK_APBCLK1_PWM0CH23CKEN_Msk (0x1ul << CLK_APBCLK1_PWM0CH23CKEN_Pos) |
| #define | CLK_APBCLK1_PWM0CH45CKEN_Pos (18) |
| #define | CLK_APBCLK1_PWM0CH45CKEN_Msk (0x1ul << CLK_APBCLK1_PWM0CH45CKEN_Pos) |
| #define | CLK_APBCLK1_PWM1CH01CKEN_Pos (19) |
| #define | CLK_APBCLK1_PWM1CH01CKEN_Msk (0x1ul << CLK_APBCLK1_PWM1CH01CKEN_Pos) |
| #define | CLK_APBCLK1_PWM1CH23CKEN_Pos (20) |
| #define | CLK_APBCLK1_PWM1CH23CKEN_Msk (0x3ul << CLK_APBCLK1_PWM1CH23CKEN_Pos) |
| #define | CLK_APBCLK1_PWM1CH45CKEN_Pos (21) |
| #define | CLK_APBCLK1_PWM1CH45CKEN_Msk (0x1ul << CLK_APBCLK1_PWM1CH45CKEN_Pos) |
| #define | CLK_APBCLK1_QEI0CKEN_Pos (22) |
| #define | CLK_APBCLK1_QEI0CKEN_Msk (0x1ul << CLK_APBCLK1_QEI0CKEN_Pos) |
| #define | CLK_APBCLK1_QEI1CKEN_Pos (23) |
| #define | CLK_APBCLK1_QEI1CKEN_Msk (0x1ul << CLK_APBCLK1_QEI1CKEN_Pos) |
| #define | CLK_APBCLK1_ECAP0CKEN_Pos (26) |
| #define | CLK_APBCLK1_ECAP0CKEN_Msk (0x1ul << CLK_APBCLK1_ECAP0CKEN_Pos) |
| #define | CLK_APBCLK1_ECAP1CKEN_Pos (27) |
| #define | CLK_APBCLK1_ECAP1CKEN_Msk (0x1ul << CLK_APBCLK1_ECAP1CKEN_Pos) |
| #define | CLK_APBCLK1_EPWM0CKEN_Pos (28) |
| #define | CLK_APBCLK1_EPWM0CKEN_Msk (0x1ul << CLK_APBCLK1_EPWM0CKEN_Pos) |
| #define | CLK_APBCLK1_EPWM1CKEN_Pos (29) |
| #define | CLK_APBCLK1_EPWM1CKEN_Msk (0x1ul << CLK_APBCLK1_EPWM1CKEN_Pos) |
| #define | CLK_APBCLK1_OPACKEN_Pos (30) |
| #define | CLK_APBCLK1_OPACKEN_Msk (0x1ul << CLK_APBCLK1_OPACKEN_Pos) |
| #define | CLK_APBCLK1_EADCCKEN_Pos (31) |
| #define | CLK_APBCLK1_EADCCKEN_Msk (0x1ul << CLK_APBCLK1_EADCCKEN_Pos) |
| #define | CLK_CLKSEL0_HCLKSEL_Pos (0) |
| #define | CLK_CLKSEL0_HCLKSEL_Msk (0x7ul << CLK_CLKSEL0_HCLKSEL_Pos) |
| #define | CLK_CLKSEL0_STCLKSEL_Pos (3) |
| #define | CLK_CLKSEL0_STCLKSEL_Msk (0x7ul << CLK_CLKSEL0_STCLKSEL_Pos) |
| #define | CLK_CLKSEL0_PCLKSEL_Pos (6) |
| #define | CLK_CLKSEL0_PCLKSEL_Msk (0x1ul << CLK_CLKSEL0_PCLKSEL_Pos) |
| #define | CLK_CLKSEL0_USBHSEL_Pos (8) |
| #define | CLK_CLKSEL0_USBHSEL_Msk (0x1ul << CLK_CLKSEL0_USBHSEL_Pos) |
| #define | CLK_CLKSEL0_CAPSEL_Pos (16) |
| #define | CLK_CLKSEL0_CAPSEL_Msk (0x3ul << CLK_CLKSEL0_CAPSEL_Pos) |
| #define | CLK_CLKSEL0_SDHSEL_Pos (20) |
| #define | CLK_CLKSEL0_SDHSEL_Msk (0x3ul << CLK_CLKSEL0_SDHSEL_Pos) |
| #define | CLK_CLKSEL1_WDTSEL_Pos (0) |
| #define | CLK_CLKSEL1_WDTSEL_Msk (0x3ul << CLK_CLKSEL1_WDTSEL_Pos) |
| #define | CLK_CLKSEL1_ADCSEL_Pos (2) |
| #define | CLK_CLKSEL1_ADCSEL_Msk (0x3ul << CLK_CLKSEL1_ADCSEL_Pos) |
| #define | CLK_CLKSEL1_SPI0SEL_Pos (4) |
| #define | CLK_CLKSEL1_SPI0SEL_Msk (0x1ul << CLK_CLKSEL1_SPI0SEL_Pos) |
| #define | CLK_CLKSEL1_SPI1SEL_Pos (5) |
| #define | CLK_CLKSEL1_SPI1SEL_Msk (0x1ul << CLK_CLKSEL1_SPI1SEL_Pos) |
| #define | CLK_CLKSEL1_SPI2SEL_Pos (6) |
| #define | CLK_CLKSEL1_SPI2SEL_Msk (0x1ul << CLK_CLKSEL1_SPI2SEL_Pos) |
| #define | CLK_CLKSEL1_SPI3SEL_Pos (7) |
| #define | CLK_CLKSEL1_SPI3SEL_Msk (0x1ul << CLK_CLKSEL1_SPI3SEL_Pos) |
| #define | CLK_CLKSEL1_TMR0SEL_Pos (8) |
| #define | CLK_CLKSEL1_TMR0SEL_Msk (0x7ul << CLK_CLKSEL1_TMR0SEL_Pos) |
| #define | CLK_CLKSEL1_TMR1SEL_Pos (12) |
| #define | CLK_CLKSEL1_TMR1SEL_Msk (0x7ul << CLK_CLKSEL1_TMR1SEL_Pos) |
| #define | CLK_CLKSEL1_TMR2SEL_Pos (16) |
| #define | CLK_CLKSEL1_TMR2SEL_Msk (0x7ul << CLK_CLKSEL1_TMR2SEL_Pos) |
| #define | CLK_CLKSEL1_TMR3SEL_Pos (20) |
| #define | CLK_CLKSEL1_TMR3SEL_Msk (0x7ul << CLK_CLKSEL1_TMR3SEL_Pos) |
| #define | CLK_CLKSEL1_UARTSEL_Pos (24) |
| #define | CLK_CLKSEL1_UARTSEL_Msk (0x3ul << CLK_CLKSEL1_UARTSEL_Pos) |
| #define | CLK_CLKSEL1_CLKOSEL_Pos (28) |
| #define | CLK_CLKSEL1_CLKOSEL_Msk (0x3ul << CLK_CLKSEL1_CLKOSEL_Pos) |
| #define | CLK_CLKSEL1_WWDTSEL_Pos (30) |
| #define | CLK_CLKSEL1_WWDTSEL_Msk (0x3ul << CLK_CLKSEL1_WWDTSEL_Pos) |
| #define | CLK_CLKSEL2_PWM0CH01SEL_Pos (0) |
| #define | CLK_CLKSEL2_PWM0CH01SEL_Msk (0x7ul << CLK_CLKSEL2_PWM0CH01SEL_Pos) |
| #define | CLK_CLKSEL2_PWM0CH23SEL_Pos (4) |
| #define | CLK_CLKSEL2_PWM0CH23SEL_Msk (0x7ul << CLK_CLKSEL2_PWM0CH23SEL_Pos) |
| #define | CLK_CLKSEL2_PWM0CH45SEL_Pos (8) |
| #define | CLK_CLKSEL2_PWM0CH45SEL_Msk (0x7ul << CLK_CLKSEL2_PWM0CH45SEL_Pos) |
| #define | CLK_CLKSEL2_PWM1CH01SEL_Pos (12) |
| #define | CLK_CLKSEL2_PWM1CH01SEL_Msk (0x7ul << CLK_CLKSEL2_PWM1CH01SEL_Pos) |
| #define | CLK_CLKSEL2_PWM1CH23SEL_Pos (16) |
| #define | CLK_CLKSEL2_PWM1CH23SEL_Msk (0x7ul << CLK_CLKSEL2_PWM1CH23SEL_Pos) |
| #define | CLK_CLKSEL2_PWM1CH45SEL_Pos (20) |
| #define | CLK_CLKSEL2_PWM1CH45SEL_Msk (0x7ul << CLK_CLKSEL2_PWM1CH45SEL_Pos) |
| #define | CLK_CLKSEL3_SC0SEL_Pos (0) |
| #define | CLK_CLKSEL3_SC0SEL_Msk (0x3ul << CLK_CLKSEL3_SC0SEL_Pos) |
| #define | CLK_CLKSEL3_SC1SEL_Pos (2) |
| #define | CLK_CLKSEL3_SC1SEL_Msk (0x3ul << CLK_CLKSEL3_SC1SEL_Pos) |
| #define | CLK_CLKSEL3_SC2SEL_Pos (4) |
| #define | CLK_CLKSEL3_SC2SEL_Msk (0x3ul << CLK_CLKSEL3_SC2SEL_Pos) |
| #define | CLK_CLKSEL3_SC3SEL_Pos (6) |
| #define | CLK_CLKSEL3_SC3SEL_Msk (0x3ul << CLK_CLKSEL3_SC3SEL_Pos) |
| #define | CLK_CLKSEL3_SC4SEL_Pos (8) |
| #define | CLK_CLKSEL3_SC4SEL_Msk (0x3ul << CLK_CLKSEL3_SC4SEL_Pos) |
| #define | CLK_CLKSEL3_SC5SEL_Pos (10) |
| #define | CLK_CLKSEL3_SC5SEL_Msk (0x3ul << CLK_CLKSEL3_SC5SEL_Pos) |
| #define | CLK_CLKSEL3_I2S0SEL_Pos (16) |
| #define | CLK_CLKSEL3_I2S0SEL_Msk (0x3ul << CLK_CLKSEL3_I2S0SEL_Pos) |
| #define | CLK_CLKSEL3_I2S1SEL_Pos (18) |
| #define | CLK_CLKSEL3_I2S1SEL_Msk (0x3ul << CLK_CLKSEL3_I2S1SEL_Pos) |
| #define | CLK_CLKDIV0_HCLKDIV_Pos (0) |
| #define | CLK_CLKDIV0_HCLKDIV_Msk (0xful << CLK_CLKDIV0_HCLKDIV_Pos) |
| #define | CLK_CLKDIV0_USBHDIV_Pos (4) |
| #define | CLK_CLKDIV0_USBHDIV_Msk (0xful << CLK_CLKDIV0_USBHDIV_Pos) |
| #define | CLK_CLKDIV0_UARTDIV_Pos (8) |
| #define | CLK_CLKDIV0_UARTDIV_Msk (0xful << CLK_CLKDIV0_UARTDIV_Pos) |
| #define | CLK_CLKDIV0_ADCDIV_Pos (16) |
| #define | CLK_CLKDIV0_ADCDIV_Msk (0xfful << CLK_CLKDIV0_ADCDIV_Pos) |
| #define | CLK_CLKDIV0_SDHDIV_Pos (24) |
| #define | CLK_CLKDIV0_SDHDIV_Msk (0xfful << CLK_CLKDIV0_SDHDIV_Pos) |
| #define | CLK_CLKDIV1_SC0DIV_Pos (0) |
| #define | CLK_CLKDIV1_SC0DIV_Msk (0xfful << CLK_CLKDIV1_SC0DIV_Pos) |
| #define | CLK_CLKDIV1_SC1DIV_Pos (8) |
| #define | CLK_CLKDIV1_SC1DIV_Msk (0xfful << CLK_CLKDIV1_SC1DIV_Pos) |
| #define | CLK_CLKDIV1_SC2DIV_Pos (16) |
| #define | CLK_CLKDIV1_SC2DIV_Msk (0xfful << CLK_CLKDIV1_SC2DIV_Pos) |
| #define | CLK_CLKDIV1_SC3DIV_Pos (24) |
| #define | CLK_CLKDIV1_SC3DIV_Msk (0xfful << CLK_CLKDIV1_SC3DIV_Pos) |
| #define | CLK_CLKDIV2_SC4DIV_Pos (0) |
| #define | CLK_CLKDIV2_SC4DIV_Msk (0xfful << CLK_CLKDIV2_SC4DIV_Pos) |
| #define | CLK_CLKDIV2_SC5DIV_Pos (8) |
| #define | CLK_CLKDIV2_SC5DIV_Msk (0xfful << CLK_CLKDIV2_SC5DIV_Pos) |
| #define | CLK_CLKDIV3_CAPDIV_Pos (0) |
| #define | CLK_CLKDIV3_CAPDIV_Msk (0xfful << CLK_CLKDIV3_CAPDIV_Pos) |
| #define | CLK_CLKDIV3_VSENSEDIV_Pos (8) |
| #define | CLK_CLKDIV3_VSENSEDIV_Msk (0xfful << CLK_CLKDIV3_VSENSEDIV_Pos) |
| #define | CLK_CLKDIV3_EMACDIV_Pos (16) |
| #define | CLK_CLKDIV3_EMACDIV_Msk (0xfful << CLK_CLKDIV3_EMACDIV_Pos) |
| #define | CLK_PLLCTL_FBDIV_Pos (0) |
| #define | CLK_PLLCTL_FBDIV_Msk (0x1fful << CLK_PLLCTL_FBDIV_Pos) |
| #define | CLK_PLLCTL_INDIV_Pos (9) |
| #define | CLK_PLLCTL_INDIV_Msk (0x1ful << CLK_PLLCTL_INDIV_Pos) |
| #define | CLK_PLLCTL_OUTDV_Pos (14) |
| #define | CLK_PLLCTL_OUTDV_Msk (0x3ul << CLK_PLLCTL_OUTDV_Pos) |
| #define | CLK_PLLCTL_PD_Pos (16) |
| #define | CLK_PLLCTL_PD_Msk (0x1ul << CLK_PLLCTL_PD_Pos) |
| #define | CLK_PLLCTL_BP_Pos (17) |
| #define | CLK_PLLCTL_BP_Msk (0x1ul << CLK_PLLCTL_BP_Pos) |
| #define | CLK_PLLCTL_OE_Pos (18) |
| #define | CLK_PLLCTL_OE_Msk (0x1ul << CLK_PLLCTL_OE_Pos) |
| #define | CLK_PLLCTL_PLLSRC_Pos (19) |
| #define | CLK_PLLCTL_PLLSRC_Msk (0x1ul << CLK_PLLCTL_PLLSRC_Pos) |
| #define | CLK_PLLCTL_PLLREMAP_Pos (20) |
| #define | CLK_PLLCTL_PLLREMAP_Msk (0x1ul << CLK_PLLCTL_PLLREMAP_Pos) |
| #define | CLK_PLL2CTL_PLL2DIV_Pos (0) |
| #define | CLK_PLL2CTL_PLL2DIV_Msk (0xfful << CLK_PLL2CTL_PLL2DIV_Pos) |
| #define | CLK_PLL2CTL_PLL2CKEN_Pos (8) |
| #define | CLK_PLL2CTL_PLL2CKEN_Msk (0x1ul << CLK_PLL2CTL_PLL2CKEN_Pos) |
| #define | CLK_STATUS_HXTSTB_Pos (0) |
| #define | CLK_STATUS_HXTSTB_Msk (0x1ul << CLK_STATUS_HXTSTB_Pos) |
| #define | CLK_STATUS_LXTSTB_Pos (1) |
| #define | CLK_STATUS_LXTSTB_Msk (0x1ul << CLK_STATUS_LXTSTB_Pos) |
| #define | CLK_STATUS_PLLSTB_Pos (2) |
| #define | CLK_STATUS_PLLSTB_Msk (0x1ul << CLK_STATUS_PLLSTB_Pos) |
| #define | CLK_STATUS_LIRCSTB_Pos (3) |
| #define | CLK_STATUS_LIRCSTB_Msk (0x1ul << CLK_STATUS_LIRCSTB_Pos) |
| #define | CLK_STATUS_HIRCSTB_Pos (4) |
| #define | CLK_STATUS_HIRCSTB_Msk (0x1ul << CLK_STATUS_HIRCSTB_Pos) |
| #define | CLK_STATUS_PLL2STB_Pos (5) |
| #define | CLK_STATUS_PLL2STB_Msk (0x1ul << CLK_STATUS_PLL2STB_Pos) |
| #define | CLK_STATUS_CLKSFAIL_Pos (7) |
| #define | CLK_STATUS_CLKSFAIL_Msk (0x1ul << CLK_STATUS_CLKSFAIL_Pos) |
| #define | CLK_CLKOCTL_FSEL_Pos (0) |
| #define | CLK_CLKOCTL_FSEL_Msk (0xful << CLK_CLKOCTL_FSEL_Pos) |
| #define | CLK_CLKOCTL_CLKOEN_Pos (4) |
| #define | CLK_CLKOCTL_CLKOEN_Msk (0x1ul << CLK_CLKOCTL_CLKOEN_Pos) |
| #define | CLK_CLKOCTL_DIV1EN_Pos (5) |
| #define | CLK_CLKOCTL_DIV1EN_Msk (0x1ul << CLK_CLKOCTL_DIV1EN_Pos) |
| #define | CLK_CLKDCTL_SYSFDEN_Pos (0) |
| #define | CLK_CLKDCTL_SYSFDEN_Msk (0x1ul << CLK_CLKDCTL_SYSFDEN_Pos) |
| #define | CLK_CLKDCTL_SYSFIEN_Pos (1) |
| #define | CLK_CLKDCTL_SYSFIEN_Msk (0x1ul << CLK_CLKDCTL_SYSFIEN_Pos) |
| #define | CLK_CLKDCTL_SYSFIF_Pos (2) |
| #define | CLK_CLKDCTL_SYSFIF_Msk (0x1ul << CLK_CLKDCTL_SYSFIF_Pos) |
| #define | CLK_CLKDCTL_IRCDEN_Pos (8) |
| #define | CLK_CLKDCTL_IRCDEN_Msk (0x1ul << CLK_CLKDCTL_IRCDEN_Pos) |
| #define | CLK_CLKDCTL_IRCFIEN_Pos (9) |
| #define | CLK_CLKDCTL_IRCFIEN_Msk (0x1ul << CLK_CLKDCTL_IRCFIEN_Pos) |
| #define | CLK_CLKDCTL_IRCFIF_Pos (10) |
| #define | CLK_CLKDCTL_IRCFIF_Msk (0x1ul << CLK_CLKDCTL_IRCFIF_Pos) |
| #define | CRC_CTL_CRCEN_Pos (0) |
| #define | CRC_CTL_CRCEN_Msk (0x1ul << CRC_CTL_CRCEN_Pos) |
| #define | CRC_CTL_CRCRST_Pos (1) |
| #define | CRC_CTL_CRCRST_Msk (0x1ul << CRC_CTL_CRCRST_Pos) |
| #define | CRC_CTL_DATREV_Pos (24) |
| #define | CRC_CTL_DATREV_Msk (0x1ul << CRC_CTL_DATREV_Pos) |
| #define | CRC_CTL_CHKSREV_Pos (25) |
| #define | CRC_CTL_CHKSREV_Msk (0x1ul << CRC_CTL_CHKSREV_Pos) |
| #define | CRC_CTL_DATFMT_Pos (26) |
| #define | CRC_CTL_DATFMT_Msk (0x1ul << CRC_CTL_DATFMT_Pos) |
| #define | CRC_CTL_CHKSFMT_Pos (27) |
| #define | CRC_CTL_CHKSFMT_Msk (0x1ul << CRC_CTL_CHKSFMT_Pos) |
| #define | CRC_CTL_DATLEN_Pos (28) |
| #define | CRC_CTL_DATLEN_Msk (0x3ul << CRC_CTL_DATLEN_Pos) |
| #define | CRC_CTL_CRCMODE_Pos (30) |
| #define | CRC_CTL_CRCMODE_Msk (0x3ul << CRC_CTL_CRCMODE_Pos) |
| #define | CRC_DAT_DATA_Pos (0) |
| #define | CRC_DAT_DATA_Msk (0xfffffffful << CRC_DAT_DATA_Pos) |
| #define | CRC_SEED_SEED_Pos (0) |
| #define | CRC_SEED_SEED_Msk (0xfffffffful << CRC_SEED_SEED_Pos) |
| #define | CRC_CHECKSUM_CHECKSUM_Pos (0) |
| #define | CRC_CHECKSUM_CHECKSUM_Msk (0xfffffffful << CRC_CHECKSUM_CHECKSUM_Pos) |
| #define | CRPT_INTEN_AESIEN_Pos (0) |
| #define | CRPT_INTEN_AESIEN_Msk (0x1ul << CRPT_INTEN_AESIEN_Pos) |
| #define | CRPT_INTEN_AESERRIEN_Pos (1) |
| #define | CRPT_INTEN_AESERRIEN_Msk (0x1ul << CRPT_INTEN_AESERRIEN_Pos) |
| #define | CRPT_INTEN_TDESIEN_Pos (8) |
| #define | CRPT_INTEN_TDESIEN_Msk (0x1ul << CRPT_INTEN_TDESIEN_Pos) |
| #define | CRPT_INTEN_TDESERRIEN_Pos (9) |
| #define | CRPT_INTEN_TDESERRIEN_Msk (0x1ul << CRPT_INTEN_TDESERRIEN_Pos) |
| #define | CRPT_INTEN_PRNGIEN_Pos (16) |
| #define | CRPT_INTEN_PRNGIEN_Msk (0x1ul << CRPT_INTEN_PRNGIEN_Pos) |
| #define | CRPT_INTEN_SHAIEN_Pos (24) |
| #define | CRPT_INTEN_SHAIEN_Msk (0x1ul << CRPT_INTEN_SHAIEN_Pos) |
| #define | CRPT_INTEN_SHAERRIEN_Pos (25) |
| #define | CRPT_INTEN_SHAERRIEN_Msk (0x1ul << CRPT_INTEN_SHAERRIEN_Pos) |
| #define | CRPT_INTSTS_AESIF_Pos (0) |
| #define | CRPT_INTSTS_AESIF_Msk (0x1ul << CRPT_INTSTS_AESIF_Pos) |
| #define | CRPT_INTSTS_AESERRIF_Pos (1) |
| #define | CRPT_INTSTS_AESERRIF_Msk (0x1ul << CRPT_INTSTS_AESERRIF_Pos) |
| #define | CRPT_INTSTS_TDESIF_Pos (8) |
| #define | CRPT_INTSTS_TDESIF_Msk (0x1ul << CRPT_INTSTS_TDESIF_Pos) |
| #define | CRPT_INTSTS_TDESERRIF_Pos (9) |
| #define | CRPT_INTSTS_TDESERRIF_Msk (0x1ul << CRPT_INTSTS_TDESERRIF_Pos) |
| #define | CRPT_INTSTS_PRNGIF_Pos (16) |
| #define | CRPT_INTSTS_PRNGIF_Msk (0x1ul << CRPT_INTSTS_PRNGIF_Pos) |
| #define | CRPT_INTSTS_SHAIF_Pos (24) |
| #define | CRPT_INTSTS_SHAIF_Msk (0x1ul << CRPT_INTSTS_SHAIF_Pos) |
| #define | CRPT_INTSTS_SHAERRIF_Pos (25) |
| #define | CRPT_INTSTS_SHAERRIF_Msk (0x1ul << CRPT_INTSTS_SHAERRIF_Pos) |
| #define | CRPT_PRNG_CTL_START_Pos (0) |
| #define | CRPT_PRNG_CTL_START_Msk (0x1ul << CRPT_PRNG_CTL_START_Pos) |
| #define | CRPT_PRNG_CTL_SEEDRLD_Pos (1) |
| #define | CRPT_PRNG_CTL_SEEDRLD_Msk (0x1ul << CRPT_PRNG_CTL_SEEDRLD_Pos) |
| #define | CRPT_PRNG_CTL_KEYSZ_Pos (2) |
| #define | CRPT_PRNG_CTL_KEYSZ_Msk (0x3ul << CRPT_PRNG_CTL_KEYSZ_Pos) |
| #define | CRPT_PRNG_CTL_BUSY_Pos (8) |
| #define | CRPT_PRNG_CTL_BUSY_Msk (0x1ul << CRPT_PRNG_CTL_BUSY_Pos) |
| #define | CRPT_PRNG_SEED_SEED_Pos (0) |
| #define | CRPT_PRNG_SEED_SEED_Msk (0xfffffffful << CRPT_PRNG_SEED_SEED_Pos) |
| #define | CRPT_PRNG_KEY0_KEY_Pos (0) |
| #define | CRPT_PRNG_KEY0_KEY_Msk (0xfffffffful << CRPT_PRNG_KEY0_KEY_Pos) |
| #define | CRPT_PRNG_KEY1_KEY_Pos (0) |
| #define | CRPT_PRNG_KEY1_KEY_Msk (0xfffffffful << CRPT_PRNG_KEY1_KEY_Pos) |
| #define | CRPT_PRNG_KEY2_KEY_Pos (0) |
| #define | CRPT_PRNG_KEY2_KEY_Msk (0xfffffffful << CRPT_PRNG_KEY2_KEY_Pos) |
| #define | CRPT_PRNG_KEY3_KEY_Pos (0) |
| #define | CRPT_PRNG_KEY3_KEY_Msk (0xfffffffful << CRPT_PRNG_KEY3_KEY_Pos) |
| #define | CRPT_PRNG_KEY4_KEY_Pos (0) |
| #define | CRPT_PRNG_KEY4_KEY_Msk (0xfffffffful << CRPT_PRNG_KEY4_KEY_Pos) |
| #define | CRPT_PRNG_KEY5_KEY_Pos (0) |
| #define | CRPT_PRNG_KEY5_KEY_Msk (0xfffffffful << CRPT_PRNG_KEY5_KEY_Pos) |
| #define | CRPT_PRNG_KEY6_KEY_Pos (0) |
| #define | CRPT_PRNG_KEY6_KEY_Msk (0xfffffffful << CRPT_PRNG_KEY6_KEY_Pos) |
| #define | CRPT_PRNG_KEY7_KEY_Pos (0) |
| #define | CRPT_PRNG_KEY7_KEY_Msk (0xfffffffful << CRPT_PRNG_KEY7_KEY_Pos) |
| #define | CRPT_AES_FDBCK0_FDBCK_Pos (0) |
| #define | CRPT_AES_FDBCK0_FDBCK_Msk (0xfffffffful << CRPT_AES_FDBCK0_FDBCK_Pos) |
| #define | CRPT_AES_FDBCK1_FDBCK_Pos (0) |
| #define | CRPT_AES_FDBCK1_FDBCK_Msk (0xfffffffful << CRPT_AES_FDBCK1_FDBCK_Pos) |
| #define | CRPT_AES_FDBCK2_FDBCK_Pos (0) |
| #define | CRPT_AES_FDBCK2_FDBCK_Msk (0xfffffffful << CRPT_AES_FDBCK2_FDBCK_Pos) |
| #define | CRPT_AES_FDBCK3_FDBCK_Pos (0) |
| #define | CRPT_AES_FDBCK3_FDBCK_Msk (0xfffffffful << CRPT_AES_FDBCK3_FDBCK_Pos) |
| #define | CRPT_TDES_FDBCKH_FDBCK_Pos (0) |
| #define | CRPT_TDES_FDBCKH_FDBCK_Msk (0xfffffffful << CRPT_TDES_FDBCKH_FDBCK_Pos) |
| #define | CRPT_TDES_FDBCKL_FDBCK_Pos (0) |
| #define | CRPT_TDES_FDBCKL_FDBCK_Msk (0xfffffffful << CRPT_TDES_FDBCKL_FDBCK_Pos) |
| #define | CRPT_AES_CTL_START_Pos (0) |
| #define | CRPT_AES_CTL_START_Msk (0x1ul << CRPT_AES_CTL_START_Pos) |
| #define | CRPT_AES_CTL_STOP_Pos (1) |
| #define | CRPT_AES_CTL_STOP_Msk (0x1ul << CRPT_AES_CTL_STOP_Pos) |
| #define | CRPT_AES_CTL_KEYSZ_Pos (2) |
| #define | CRPT_AES_CTL_KEYSZ_Msk (0x3ul << CRPT_AES_CTL_KEYSZ_Pos) |
| #define | CRPT_AES_CTL_DMALAST_Pos (5) |
| #define | CRPT_AES_CTL_DMALAST_Msk (0x1ul << CRPT_AES_CTL_DMALAST_Pos) |
| #define | CRPT_AES_CTL_DMACSCAD_Pos (6) |
| #define | CRPT_AES_CTL_DMACSCAD_Msk (0x1ul << CRPT_AES_CTL_DMACSCAD_Pos) |
| #define | CRPT_AES_CTL_DMAEN_Pos (7) |
| #define | CRPT_AES_CTL_DMAEN_Msk (0x1ul << CRPT_AES_CTL_DMAEN_Pos) |
| #define | CRPT_AES_CTL_OPMODE_Pos (8) |
| #define | CRPT_AES_CTL_OPMODE_Msk (0xfful << CRPT_AES_CTL_OPMODE_Pos) |
| #define | CRPT_AES_CTL_ENCRPT_Pos (16) |
| #define | CRPT_AES_CTL_ENCRPT_Msk (0x1ul << CRPT_AES_CTL_ENCRPT_Pos) |
| #define | CRPT_AES_CTL_OUTSWAP_Pos (22) |
| #define | CRPT_AES_CTL_OUTSWAP_Msk (0x1ul << CRPT_AES_CTL_OUTSWAP_Pos) |
| #define | CRPT_AES_CTL_INSWAP_Pos (23) |
| #define | CRPT_AES_CTL_INSWAP_Msk (0x1ul << CRPT_AES_CTL_INSWAP_Pos) |
| #define | CRPT_AES_CTL_CHANNEL_Pos (24) |
| #define | CRPT_AES_CTL_CHANNEL_Msk (0x3ul << CRPT_AES_CTL_CHANNEL_Pos) |
| #define | CRPT_AES_CTL_KEYUNPRT_Pos (26) |
| #define | CRPT_AES_CTL_KEYUNPRT_Msk (0x1ful << CRPT_AES_CTL_KEYUNPRT_Pos) |
| #define | CRPT_AES_CTL_KEYPRT_Pos (31) |
| #define | CRPT_AES_CTL_KEYPRT_Msk (0x1ul << CRPT_AES_CTL_KEYPRT_Pos) |
| #define | CRPT_AES_STS_BUSY_Pos (0) |
| #define | CRPT_AES_STS_BUSY_Msk (0x1ul << CRPT_AES_STS_BUSY_Pos) |
| #define | CRPT_AES_STS_INBUFEMPTY_Pos (8) |
| #define | CRPT_AES_STS_INBUFEMPTY_Msk (0x1ul << CRPT_AES_STS_INBUFEMPTY_Pos) |
| #define | CRPT_AES_STS_INBUFFULL_Pos (9) |
| #define | CRPT_AES_STS_INBUFFULL_Msk (0x1ul << CRPT_AES_STS_INBUFFULL_Pos) |
| #define | CRPT_AES_STS_INBUFERR_Pos (10) |
| #define | CRPT_AES_STS_INBUFERR_Msk (0x1ul << CRPT_AES_STS_INBUFERR_Pos) |
| #define | CRPT_AES_STS_CNTERR_Pos (12) |
| #define | CRPT_AES_STS_CNTERR_Msk (0x1ul << CRPT_AES_STS_CNTERR_Pos) |
| #define | CRPT_AES_STS_OUTBUFEMPTY_Pos (16) |
| #define | CRPT_AES_STS_OUTBUFEMPTY_Msk (0x1ul << CRPT_AES_STS_OUTBUFEMPTY_Pos) |
| #define | CRPT_AES_STS_OUTBUFFULL_Pos (17) |
| #define | CRPT_AES_STS_OUTBUFFULL_Msk (0x1ul << CRPT_AES_STS_OUTBUFFULL_Pos) |
| #define | CRPT_AES_STS_OUTBUFERR_Pos (18) |
| #define | CRPT_AES_STS_OUTBUFERR_Msk (0x1ul << CRPT_AES_STS_OUTBUFERR_Pos) |
| #define | CRPT_AES_STS_BUSERR_Pos (20) |
| #define | CRPT_AES_STS_BUSERR_Msk (0x1ul << CRPT_AES_STS_BUSERR_Pos) |
| #define | CRPT_AES_DATIN_DATIN_Pos (0) |
| #define | CRPT_AES_DATIN_DATIN_Msk (0xfffffffful << CRPT_AES_DATIN_DATIN_Pos) |
| #define | CRPT_AES_DATOUT_DATOUT_Pos (0) |
| #define | CRPT_AES_DATOUT_DATOUT_Msk (0xfffffffful << CRPT_AES_DATOUT_DATOUT_Pos) |
| #define | CRPT_AES0_KEY0_KEY_Pos (0) |
| #define | CRPT_AES0_KEY0_KEY_Msk (0xfffffffful << CRPT_AES0_KEY0_KEY_Pos) |
| #define | CRPT_AES0_KEY1_KEY_Pos (0) |
| #define | CRPT_AES0_KEY1_KEY_Msk (0xfffffffful << CRPT_AES0_KEY1_KEY_Pos) |
| #define | CRPT_AES0_KEY2_KEY_Pos (0) |
| #define | CRPT_AES0_KEY2_KEY_Msk (0xfffffffful << CRPT_AES0_KEY2_KEY_Pos) |
| #define | CRPT_AES0_KEY3_KEY_Pos (0) |
| #define | CRPT_AES0_KEY3_KEY_Msk (0xfffffffful << CRPT_AES0_KEY3_KEY_Pos) |
| #define | CRPT_AES0_KEY4_KEY_Pos (0) |
| #define | CRPT_AES0_KEY4_KEY_Msk (0xfffffffful << CRPT_AES0_KEY4_KEY_Pos) |
| #define | CRPT_AES0_KEY5_KEY_Pos (0) |
| #define | CRPT_AES0_KEY5_KEY_Msk (0xfffffffful << CRPT_AES0_KEY5_KEY_Pos) |
| #define | CRPT_AES0_KEY6_KEY_Pos (0) |
| #define | CRPT_AES0_KEY6_KEY_Msk (0xfffffffful << CRPT_AES0_KEY6_KEY_Pos) |
| #define | CRPT_AES0_KEY7_KEY_Pos (0) |
| #define | CRPT_AES0_KEY7_KEY_Msk (0xfffffffful << CRPT_AES0_KEY7_KEY_Pos) |
| #define | CRPT_AES0_IV0_IV_Pos (0) |
| #define | CRPT_AES0_IV0_IV_Msk (0xfffffffful << CRPT_AES0_IV0_IV_Pos) |
| #define | CRPT_AES0_IV1_IV_Pos (0) |
| #define | CRPT_AES0_IV1_IV_Msk (0xfffffffful << CRPT_AES0_IV1_IV_Pos) |
| #define | CRPT_AES0_IV2_IV_Pos (0) |
| #define | CRPT_AES0_IV2_IV_Msk (0xfffffffful << CRPT_AES0_IV2_IV_Pos) |
| #define | CRPT_AES0_IV3_IV_Pos (0) |
| #define | CRPT_AES0_IV3_IV_Msk (0xfffffffful << CRPT_AES0_IV3_IV_Pos) |
| #define | CRPT_AES0_SADDR_SADDR_Pos (0) |
| #define | CRPT_AES0_SADDR_SADDR_Msk (0xfffffffful << CRPT_AES0_SADDR_SADDR_Pos) |
| #define | CRPT_AES0_DADDR_DADDR_Pos (0) |
| #define | CRPT_AES0_DADDR_DADDR_Msk (0xfffffffful << CRPT_AES0_DADDR_DADDR_Pos) |
| #define | CRPT_AES0_CNT_CNT_Pos (0) |
| #define | CRPT_AES0_CNT_CNT_Msk (0xfffffffful << CRPT_AES0_CNT_CNT_Pos) |
| #define | CRPT_AES1_KEY0_KEY_Pos (0) |
| #define | CRPT_AES1_KEY0_KEY_Msk (0xfffffffful << CRPT_AES1_KEY0_KEY_Pos) |
| #define | CRPT_AES1_KEY1_KEY_Pos (0) |
| #define | CRPT_AES1_KEY1_KEY_Msk (0xfffffffful << CRPT_AES1_KEY1_KEY_Pos) |
| #define | CRPT_AES1_KEY2_KEY_Pos (0) |
| #define | CRPT_AES1_KEY2_KEY_Msk (0xfffffffful << CRPT_AES1_KEY2_KEY_Pos) |
| #define | CRPT_AES1_KEY3_KEY_Pos (0) |
| #define | CRPT_AES1_KEY3_KEY_Msk (0xfffffffful << CRPT_AES1_KEY3_KEY_Pos) |
| #define | CRPT_AES1_KEY4_KEY_Pos (0) |
| #define | CRPT_AES1_KEY4_KEY_Msk (0xfffffffful << CRPT_AES1_KEY4_KEY_Pos) |
| #define | CRPT_AES1_KEY5_KEY_Pos (0) |
| #define | CRPT_AES1_KEY5_KEY_Msk (0xfffffffful << CRPT_AES1_KEY5_KEY_Pos) |
| #define | CRPT_AES1_KEY6_KEY_Pos (0) |
| #define | CRPT_AES1_KEY6_KEY_Msk (0xfffffffful << CRPT_AES1_KEY6_KEY_Pos) |
| #define | CRPT_AES1_KEY7_KEY_Pos (0) |
| #define | CRPT_AES1_KEY7_KEY_Msk (0xfffffffful << CRPT_AES1_KEY7_KEY_Pos) |
| #define | CRPT_AES1_IV0_IV_Pos (0) |
| #define | CRPT_AES1_IV0_IV_Msk (0xfffffffful << CRPT_AES1_IV0_IV_Pos) |
| #define | CRPT_AES1_IV1_IV_Pos (0) |
| #define | CRPT_AES1_IV1_IV_Msk (0xfffffffful << CRPT_AES1_IV1_IV_Pos) |
| #define | CRPT_AES1_IV2_IV_Pos (0) |
| #define | CRPT_AES1_IV2_IV_Msk (0xfffffffful << CRPT_AES1_IV2_IV_Pos) |
| #define | CRPT_AES1_IV3_IV_Pos (0) |
| #define | CRPT_AES1_IV3_IV_Msk (0xfffffffful << CRPT_AES1_IV3_IV_Pos) |
| #define | CRPT_AES1_SADDR_SADDR_Pos (0) |
| #define | CRPT_AES1_SADDR_SADDR_Msk (0xfffffffful << CRPT_AES1_SADDR_SADDR_Pos) |
| #define | CRPT_AES1_DADDR_DADDR_Pos (0) |
| #define | CRPT_AES1_DADDR_DADDR_Msk (0xfffffffful << CRPT_AES1_DADDR_DADDR_Pos) |
| #define | CRPT_AES1_CNT_CNT_Pos (0) |
| #define | CRPT_AES1_CNT_CNT_Msk (0xfffffffful << CRPT_AES1_CNT_CNT_Pos) |
| #define | CRPT_AES2_KEY0_KEY_Pos (0) |
| #define | CRPT_AES2_KEY0_KEY_Msk (0xfffffffful << CRPT_AES2_KEY0_KEY_Pos) |
| #define | CRPT_AES2_KEY1_KEY_Pos (0) |
| #define | CRPT_AES2_KEY1_KEY_Msk (0xfffffffful << CRPT_AES2_KEY1_KEY_Pos) |
| #define | CRPT_AES2_KEY2_KEY_Pos (0) |
| #define | CRPT_AES2_KEY2_KEY_Msk (0xfffffffful << CRPT_AES2_KEY2_KEY_Pos) |
| #define | CRPT_AES2_KEY3_KEY_Pos (0) |
| #define | CRPT_AES2_KEY3_KEY_Msk (0xfffffffful << CRPT_AES2_KEY3_KEY_Pos) |
| #define | CRPT_AES2_KEY4_KEY_Pos (0) |
| #define | CRPT_AES2_KEY4_KEY_Msk (0xfffffffful << CRPT_AES2_KEY4_KEY_Pos) |
| #define | CRPT_AES2_KEY5_KEY_Pos (0) |
| #define | CRPT_AES2_KEY5_KEY_Msk (0xfffffffful << CRPT_AES2_KEY5_KEY_Pos) |
| #define | CRPT_AES2_KEY6_KEY_Pos (0) |
| #define | CRPT_AES2_KEY6_KEY_Msk (0xfffffffful << CRPT_AES2_KEY6_KEY_Pos) |
| #define | CRPT_AES2_KEY7_KEY_Pos (0) |
| #define | CRPT_AES2_KEY7_KEY_Msk (0xfffffffful << CRPT_AES2_KEY7_KEY_Pos) |
| #define | CRPT_AES2_IV0_IV_Pos (0) |
| #define | CRPT_AES2_IV0_IV_Msk (0xfffffffful << CRPT_AES2_IV0_IV_Pos) |
| #define | CRPT_AES2_IV1_IV_Pos (0) |
| #define | CRPT_AES2_IV1_IV_Msk (0xfffffffful << CRPT_AES2_IV1_IV_Pos) |
| #define | CRPT_AES2_IV2_IV_Pos (0) |
| #define | CRPT_AES2_IV2_IV_Msk (0xfffffffful << CRPT_AES2_IV2_IV_Pos) |
| #define | CRPT_AES2_IV3_IV_Pos (0) |
| #define | CRPT_AES2_IV3_IV_Msk (0xfffffffful << CRPT_AES2_IV3_IV_Pos) |
| #define | CRPT_AES2_SADDR_SADDR_Pos (0) |
| #define | CRPT_AES2_SADDR_SADDR_Msk (0xfffffffful << CRPT_AES2_SADDR_SADDR_Pos) |
| #define | CRPT_AES2_DADDR_DADDR_Pos (0) |
| #define | CRPT_AES2_DADDR_DADDR_Msk (0xfffffffful << CRPT_AES2_DADDR_DADDR_Pos) |
| #define | CRPT_AES2_CNT_CNT_Pos (0) |
| #define | CRPT_AES2_CNT_CNT_Msk (0xfffffffful << CRPT_AES2_CNT_CNT_Pos) |
| #define | CRPT_AES3_KEY0_KEY_Pos (0) |
| #define | CRPT_AES3_KEY0_KEY_Msk (0xfffffffful << CRPT_AES3_KEY0_KEY_Pos) |
| #define | CRPT_AES3_KEY1_KEY_Pos (0) |
| #define | CRPT_AES3_KEY1_KEY_Msk (0xfffffffful << CRPT_AES3_KEY1_KEY_Pos) |
| #define | CRPT_AES3_KEY2_KEY_Pos (0) |
| #define | CRPT_AES3_KEY2_KEY_Msk (0xfffffffful << CRPT_AES3_KEY2_KEY_Pos) |
| #define | CRPT_AES3_KEY3_KEY_Pos (0) |
| #define | CRPT_AES3_KEY3_KEY_Msk (0xfffffffful << CRPT_AES3_KEY3_KEY_Pos) |
| #define | CRPT_AES3_KEY4_KEY_Pos (0) |
| #define | CRPT_AES3_KEY4_KEY_Msk (0xfffffffful << CRPT_AES3_KEY4_KEY_Pos) |
| #define | CRPT_AES3_KEY5_KEY_Pos (0) |
| #define | CRPT_AES3_KEY5_KEY_Msk (0xfffffffful << CRPT_AES3_KEY5_KEY_Pos) |
| #define | CRPT_AES3_KEY6_KEY_Pos (0) |
| #define | CRPT_AES3_KEY6_KEY_Msk (0xfffffffful << CRPT_AES3_KEY6_KEY_Pos) |
| #define | CRPT_AES3_KEY7_KEY_Pos (0) |
| #define | CRPT_AES3_KEY7_KEY_Msk (0xfffffffful << CRPT_AES3_KEY7_KEY_Pos) |
| #define | CRPT_AES3_IV0_IV_Pos (0) |
| #define | CRPT_AES3_IV0_IV_Msk (0xfffffffful << CRPT_AES3_IV0_IV_Pos) |
| #define | CRPT_AES3_IV1_IV_Pos (0) |
| #define | CRPT_AES3_IV1_IV_Msk (0xfffffffful << CRPT_AES3_IV1_IV_Pos) |
| #define | CRPT_AES3_IV2_IV_Pos (0) |
| #define | CRPT_AES3_IV2_IV_Msk (0xfffffffful << CRPT_AES3_IV2_IV_Pos) |
| #define | CRPT_AES3_IV3_IV_Pos (0) |
| #define | CRPT_AES3_IV3_IV_Msk (0xfffffffful << CRPT_AES3_IV3_IV_Pos) |
| #define | CRPT_AES3_SADDR_SADDR_Pos (0) |
| #define | CRPT_AES3_SADDR_SADDR_Msk (0xfffffffful << CRPT_AES3_SADDR_SADDR_Pos) |
| #define | CRPT_AES3_DADDR_DADDR_Pos (0) |
| #define | CRPT_AES3_DADDR_DADDR_Msk (0xfffffffful << CRPT_AES3_DADDR_DADDR_Pos) |
| #define | CRPT_AES3_CNT_CNT_Pos (0) |
| #define | CRPT_AES3_CNT_CNT_Msk (0xfffffffful << CRPT_AES3_CNT_CNT_Pos) |
| #define | CRPT_TDES_CTL_START_Pos (0) |
| #define | CRPT_TDES_CTL_START_Msk (0x1ul << CRPT_TDES_CTL_START_Pos) |
| #define | CRPT_TDES_CTL_STOP_Pos (1) |
| #define | CRPT_TDES_CTL_STOP_Msk (0x1ul << CRPT_TDES_CTL_STOP_Pos) |
| #define | CRPT_TDES_CTL_TMODE_Pos (2) |
| #define | CRPT_TDES_CTL_TMODE_Msk (0x1ul << CRPT_TDES_CTL_TMODE_Pos) |
| #define | CRPT_TDES_CTL_3KEYS_Pos (3) |
| #define | CRPT_TDES_CTL_3KEYS_Msk (0x1ul << CRPT_TDES_CTL_3KEYS_Pos) |
| #define | CRPT_TDES_CTL_DMALAST_Pos (5) |
| #define | CRPT_TDES_CTL_DMALAST_Msk (0x1ul << CRPT_TDES_CTL_DMALAST_Pos) |
| #define | CRPT_TDES_CTL_DMACSCAD_Pos (6) |
| #define | CRPT_TDES_CTL_DMACSCAD_Msk (0x1ul << CRPT_TDES_CTL_DMACSCAD_Pos) |
| #define | CRPT_TDES_CTL_DMAEN_Pos (7) |
| #define | CRPT_TDES_CTL_DMAEN_Msk (0x1ul << CRPT_TDES_CTL_DMAEN_Pos) |
| #define | CRPT_TDES_CTL_OPMODE_Pos (8) |
| #define | CRPT_TDES_CTL_OPMODE_Msk (0x7ul << CRPT_TDES_CTL_OPMODE_Pos) |
| #define | CRPT_TDES_CTL_ENCRPT_Pos (16) |
| #define | CRPT_TDES_CTL_ENCRPT_Msk (0x1ul << CRPT_TDES_CTL_ENCRPT_Pos) |
| #define | CRPT_TDES_CTL_BLKSWAP_Pos (21) |
| #define | CRPT_TDES_CTL_BLKSWAP_Msk (0x1ul << CRPT_TDES_CTL_BLKSWAP_Pos) |
| #define | CRPT_TDES_CTL_OUTSWAP_Pos (22) |
| #define | CRPT_TDES_CTL_OUTSWAP_Msk (0x1ul << CRPT_TDES_CTL_OUTSWAP_Pos) |
| #define | CRPT_TDES_CTL_INSWAP_Pos (23) |
| #define | CRPT_TDES_CTL_INSWAP_Msk (0x1ul << CRPT_TDES_CTL_INSWAP_Pos) |
| #define | CRPT_TDES_CTL_CHANNEL_Pos (24) |
| #define | CRPT_TDES_CTL_CHANNEL_Msk (0x3ul << CRPT_TDES_CTL_CHANNEL_Pos) |
| #define | CRPT_TDES_CTL_KEYUNPRT_Pos (26) |
| #define | CRPT_TDES_CTL_KEYUNPRT_Msk (0x1ful << CRPT_TDES_CTL_KEYUNPRT_Pos) |
| #define | CRPT_TDES_CTL_KEYPRT_Pos (31) |
| #define | CRPT_TDES_CTL_KEYPRT_Msk (0x1ul << CRPT_TDES_CTL_KEYPRT_Pos) |
| #define | CRPT_TDES_STS_BUSY_Pos (0) |
| #define | CRPT_TDES_STS_BUSY_Msk (0x1ul << CRPT_TDES_STS_BUSY_Pos) |
| #define | CRPT_TDES_STS_INBUFEMPTY_Pos (8) |
| #define | CRPT_TDES_STS_INBUFEMPTY_Msk (0x1ul << CRPT_TDES_STS_INBUFEMPTY_Pos) |
| #define | CRPT_TDES_STS_INBUFFULL_Pos (9) |
| #define | CRPT_TDES_STS_INBUFFULL_Msk (0x1ul << CRPT_TDES_STS_INBUFFULL_Pos) |
| #define | CRPT_TDES_STS_INBUFERR_Pos (10) |
| #define | CRPT_TDES_STS_INBUFERR_Msk (0x1ul << CRPT_TDES_STS_INBUFERR_Pos) |
| #define | CRPT_TDES_STS_OUTBUFEMPTY_Pos (16) |
| #define | CRPT_TDES_STS_OUTBUFEMPTY_Msk (0x1ul << CRPT_TDES_STS_OUTBUFEMPTY_Pos) |
| #define | CRPT_TDES_STS_OUTBUFFULL_Pos (17) |
| #define | CRPT_TDES_STS_OUTBUFFULL_Msk (0x1ul << CRPT_TDES_STS_OUTBUFFULL_Pos) |
| #define | CRPT_TDES_STS_OUTBUFERR_Pos (18) |
| #define | CRPT_TDES_STS_OUTBUFERR_Msk (0x1ul << CRPT_TDES_STS_OUTBUFERR_Pos) |
| #define | CRPT_TDES_STS_BUSERR_Pos (20) |
| #define | CRPT_TDES_STS_BUSERR_Msk (0x1ul << CRPT_TDES_STS_BUSERR_Pos) |
| #define | CRPT_TDES0_KEY1H_KEY_Pos (0) |
| #define | CRPT_TDES0_KEY1H_KEY_Msk (0xfffffffful << CRPT_TDES0_KEY1H_KEY_Pos) |
| #define | CRPT_TDES0_KEY1L_KEY_Pos (0) |
| #define | CRPT_TDES0_KEY1L_KEY_Msk (0xfffffffful << CRPT_TDES0_KEY1L_KEY_Pos) |
| #define | CRPT_TDES0_KEY2H_KEY_Pos (0) |
| #define | CRPT_TDES0_KEY2H_KEY_Msk (0xfffffffful << CRPT_TDES0_KEY2H_KEY_Pos) |
| #define | CRPT_TDES0_KEY2L_KEY_Pos (0) |
| #define | CRPT_TDES0_KEY2L_KEY_Msk (0xfffffffful << CRPT_TDES0_KEY2L_KEY_Pos) |
| #define | CRPT_TDES0_KEY3H_KEY_Pos (0) |
| #define | CRPT_TDES0_KEY3H_KEY_Msk (0xfffffffful << CRPT_TDES0_KEY3H_KEY_Pos) |
| #define | CRPT_TDES0_KEY3L_KEY_Pos (0) |
| #define | CRPT_TDES0_KEY3L_KEY_Msk (0xfffffffful << CRPT_TDES0_KEY3L_KEY_Pos) |
| #define | CRPT_TDES0_IVH_IV_Pos (0) |
| #define | CRPT_TDES0_IVH_IV_Msk (0xfffffffful << CRPT_TDES0_IVH_IV_Pos) |
| #define | CRPT_TDES0_IVL_IV_Pos (0) |
| #define | CRPT_TDES0_IVL_IV_Msk (0xfffffffful << CRPT_TDES0_IVL_IV_Pos) |
| #define | CRPT_TDES0_SADDR_SADDR_Pos (0) |
| #define | CRPT_TDES0_SADDR_SADDR_Msk (0xfffffffful << CRPT_TDES0_SADDR_SADDR_Pos) |
| #define | CRPT_TDES0_DADDR_DADDR_Pos (0) |
| #define | CRPT_TDES0_DADDR_DADDR_Msk (0xfffffffful << CRPT_TDES0_DADDR_DADDR_Pos) |
| #define | CRPT_TDES0_CNT_CNT_Pos (0) |
| #define | CRPT_TDES0_CNT_CNT_Msk (0xfffffffful << CRPT_TDES0_CNT_CNT_Pos) |
| #define | CRPT_TDES_DATIN_DATIN_Pos (0) |
| #define | CRPT_TDES_DATIN_DATIN_Msk (0xfffffffful << CRPT_TDES_DATIN_DATIN_Pos) |
| #define | CRPT_TDES_DATOUT_DATOUT_Pos (0) |
| #define | CRPT_TDES_DATOUT_DATOUT_Msk (0xfffffffful << CRPT_TDES_DATOUT_DATOUT_Pos) |
| #define | CRPT_TDES1_KEY1H_KEY_Pos (0) |
| #define | CRPT_TDES1_KEY1H_KEY_Msk (0xfffffffful << CRPT_TDES1_KEY1H_KEY_Pos) |
| #define | CRPT_TDES1_KEY1L_KEYL_Pos (0) |
| #define | CRPT_TDES1_KEY1L_KEY_Msk (0xfffffffful << CRPT_TDES1_KEY1L_KEY_Pos) |
| #define | CRPT_TDES1_KEY2H_KEY_Pos (0) |
| #define | CRPT_TDES1_KEY2H_KEY_Msk (0xfffffffful << CRPT_TDES1_KEY2H_KEY_Pos) |
| #define | CRPT_TDES1_KEY2L_KEY_Pos (0) |
| #define | CRPT_TDES1_KEY2L_KEY_Msk (0xfffffffful << CRPT_TDES1_KEY2L_KEY_Pos) |
| #define | CRPT_TDES1_KEY3H_KEY_Pos (0) |
| #define | CRPT_TDES1_KEY3H_KEY_Msk (0xfffffffful << CRPT_TDES1_KEY3H_KEY_Pos) |
| #define | CRPT_TDES1_KEY3L_KEY_Pos (0) |
| #define | CRPT_TDES1_KEY3L_KEY_Msk (0xfffffffful << CRPT_TDES1_KEY3L_KEY_Pos) |
| #define | CRPT_TDES1_IVH_IV_Pos (0) |
| #define | CRPT_TDES1_IVH_IV_Msk (0xfffffffful << CRPT_TDES1_IVH_IV_Pos) |
| #define | CRPT_TDES1_IVL_IV_Pos (0) |
| #define | CRPT_TDES1_IVL_IV_Msk (0xfffffffful << CRPT_TDES1_IVL_IV_Pos) |
| #define | CRPT_TDES1_SADDR_SADDR_Pos (0) |
| #define | CRPT_TDES1_SADDR_SADDR_Msk (0xfffffffful << CRPT_TDES1_SADDR_SADDR_Pos) |
| #define | CRPT_TDES1_DADDR_DADDR_Pos (0) |
| #define | CRPT_TDES1_DADDR_DADDR_Msk (0xfffffffful << CRPT_TDES1_DADDR_DADDR_Pos) |
| #define | CRPT_TDES1_CNT_CNT_Pos (0) |
| #define | CRPT_TDES1_CNT_CNT_Msk (0xfffffffful << CRPT_TDES1_CNT_CNT_Pos) |
| #define | CRPT_TDES2_KEY1H_KEY_Pos (0) |
| #define | CRPT_TDES2_KEY1H_KEY_Msk (0xfffffffful << CRPT_TDES2_KEY1H_KEY_Pos) |
| #define | CRPT_TDES2_KEY1L_KEY_Pos (0) |
| #define | CRPT_TDES2_KEY1L_KEY_Msk (0xfffffffful << CRPT_TDES2_KEY1L_KEY_Pos) |
| #define | CRPT_TDES2_KEY2H_KEY_Pos (0) |
| #define | CRPT_TDES2_KEY2H_KEY_Msk (0xfffffffful << CRPT_TDES2_KEY2H_KEY_Pos) |
| #define | CRPT_TDES2_KEY2L_KEY_Pos (0) |
| #define | CRPT_TDES2_KEY2L_KEY_Msk (0xfffffffful << CRPT_TDES2_KEY2L_KEY_Pos) |
| #define | CRPT_TDES2_KEY3H_KEY_Pos (0) |
| #define | CRPT_TDES2_KEY3H_KEY_Msk (0xfffffffful << CRPT_TDES2_KEY3H_KEY_Pos) |
| #define | CRPT_TDES2_KEY3L_KEY_Pos (0) |
| #define | CRPT_TDES2_KEY3L_KEY_Msk (0xfffffffful << CRPT_TDES2_KEY3L_KEY_Pos) |
| #define | CRPT_TDES2_IVH_IV_Pos (0) |
| #define | CRPT_TDES2_IVH_IV_Msk (0xfffffffful << CRPT_TDES2_IVH_IV_Pos) |
| #define | CRPT_TDES2_IVL_IV_Pos (0) |
| #define | CRPT_TDES2_IVL_IV_Msk (0xfffffffful << CRPT_TDES2_IVL_IV_Pos) |
| #define | CRPT_TDES2_SADDR_SADDR_Pos (0) |
| #define | CRPT_TDES2_SADDR_SADDR_Msk (0xfffffffful << CRPT_TDES2_SADDR_SADDR_Pos) |
| #define | CRPT_TDES2_DADDR_DADDR_Pos (0) |
| #define | CRPT_TDES2_DADDR_DADDR_Msk (0xfffffffful << CRPT_TDES2_DADDR_DADDR_Pos) |
| #define | CRPT_TDES2_CNT_CNT_Pos (0) |
| #define | CRPT_TDES2_CNT_CNT_Msk (0xfffffffful << CRPT_TDES2_CNT_CNT_Pos) |
| #define | CRPT_TDES3_KEY1H_KEY_Pos (0) |
| #define | CRPT_TDES3_KEY1H_KEY_Msk (0xfffffffful << CRPT_TDES3_KEY1H_KEY_Pos) |
| #define | CRPT_TDES3_KEY1L_KEY_Pos (0) |
| #define | CRPT_TDES3_KEY1L_KEY_Msk (0xfffffffful << CRPT_TDES3_KEY1L_KEY_Pos) |
| #define | CRPT_TDES3_KEY2H_KEY_Pos (0) |
| #define | CRPT_TDES3_KEY2H_KEY_Msk (0xfffffffful << CRPT_TDES3_KEY2H_KEY_Pos) |
| #define | CRPT_TDES3_KEY2L_KEY_Pos (0) |
| #define | CRPT_TDES3_KEY2L_KEY_Msk (0xfffffffful << CRPT_TDES3_KEY2L_KEY_Pos) |
| #define | CRPT_TDES3_KEY3H_KEY_Pos (0) |
| #define | CRPT_TDES3_KEY3H_KEY_Msk (0xfffffffful << CRPT_TDES3_KEY3H_KEY_Pos) |
| #define | CRPT_TDES3_KEY3L_KEY_Pos (0) |
| #define | CRPT_TDES3_KEY3L_KEY_Msk (0xfffffffful << CRPT_TDES3_KEY3L_KEY_Pos) |
| #define | CRPT_TDES3_IVH_IV_Pos (0) |
| #define | CRPT_TDES3_IVH_IV_Msk (0xfffffffful << CRPT_TDES3_IVH_IV_Pos) |
| #define | CRPT_TDES3_IVL_IV_Pos (0) |
| #define | CRPT_TDES3_IVL_IV_Msk (0xfffffffful << CRPT_TDES3_IVL_IV_Pos) |
| #define | CRPT_TDES3_SADDR_SADDR_Pos (0) |
| #define | CRPT_TDES3_SADDR_SADDR_Msk (0xfffffffful << CRPT_TDES3_SADDR_SADDR_Pos) |
| #define | CRPT_TDES3_DADDR_DADDR_Pos (0) |
| #define | CRPT_TDES3_DADDR_DADDR_Msk (0xfffffffful << CRPT_TDES3_DADDR_DADDR_Pos) |
| #define | CRPT_TDES3_CNT_CNT_Pos (0) |
| #define | CRPT_TDES3_CNT_CNT_Msk (0xfffffffful << CRPT_TDES3_CNT_CNT_Pos) |
| #define | CRPT_SHA_CTL_START_Pos (0) |
| #define | CRPT_SHA_CTL_START_Msk (0x1ul << CRPT_SHA_CTL_START_Pos) |
| #define | CRPT_SHA_CTL_STOP_Pos (1) |
| #define | CRPT_SHA_CTL_STOP_Msk (0x1ul << CRPT_SHA_CTL_STOP_Pos) |
| #define | CRPT_SHA_CTL_DMALAST_Pos (5) |
| #define | CRPT_SHA_CTL_DMALAST_Msk (0x1ul << CRPT_SHA_CTL_DMALAST_Pos) |
| #define | CRPT_SHA_CTL_DMAEN_Pos (7) |
| #define | CRPT_SHA_CTL_DMAEN_Msk (0x1ul << CRPT_SHA_CTL_DMAEN_Pos) |
| #define | CRPT_SHA_CTL_OPMODE_Pos (8) |
| #define | CRPT_SHA_CTL_OPMODE_Msk (0x7ul << CRPT_SHA_CTL_OPMODE_Pos) |
| #define | CRPT_SHA_CTL_OUTSWAP_Pos (22) |
| #define | CRPT_SHA_CTL_OUTSWAP_Msk (0x1ul << CRPT_SHA_CTL_OUTSWAP_Pos) |
| #define | CRPT_SHA_CTL_INSWAP_Pos (23) |
| #define | CRPT_SHA_CTL_INSWAP_Msk (0x1ul << CRPT_SHA_CTL_INSWAP_Pos) |
| #define | CRPT_SHA_STS_BUSY_Pos (0) |
| #define | CRPT_SHA_STS_BUSY_Msk (0x1ul << CRPT_SHA_STS_BUSY_Pos) |
| #define | CRPT_SHA_STS_DMABUSY_Pos (1) |
| #define | CRPT_SHA_STS_DMABUSY_Msk (0x1ul << CRPT_SHA_STS_DMABUSY_Pos) |
| #define | CRPT_SHA_STS_DMAERR_Pos (8) |
| #define | CRPT_SHA_STS_DMAERR_Msk (0x1ul << CRPT_SHA_STS_DMAERR_Pos) |
| #define | CRPT_SHA_STS_DATINREQ_Pos (16) |
| #define | CRPT_SHA_STS_DATINREQ_Msk (0x1ul << CRPT_SHA_STS_DATINREQ_Pos) |
| #define | CRPT_SHA_DGST0_DGST_Pos (0) |
| #define | CRPT_SHA_DGST0_DGST_Msk (0xfffffffful << CRPT_SHA_DGST0_DGST_Pos) |
| #define | CRPT_SHA_DGST1_DGST_Pos (0) |
| #define | CRPT_SHA_DGST1_DGST_Msk (0xfffffffful << CRPT_SHA_DGST1_DGST_Pos) |
| #define | CRPT_SHA_DGST2_DGST_Pos (0) |
| #define | CRPT_SHA_DGST2_DGST_Msk (0xfffffffful << CRPT_SHA_DGST2_DGST_Pos) |
| #define | CRPT_SHA_DGST3_DGST_Pos (0) |
| #define | CRPT_SHA_DGST3_DGST_Msk (0xfffffffful << CRPT_SHA_DGST3_DGST_Pos) |
| #define | CRPT_SHA_DGST4_DGST_Pos (0) |
| #define | CRPT_SHA_DGST4_DGST_Msk (0xfffffffful << CRPT_SHA_DGST4_DGST_Pos) |
| #define | CRPT_SHA_DGST5_DGST_Pos (0) |
| #define | CRPT_SHA_DGST5_DGST_Msk (0xfffffffful << CRPT_SHA_DGST5_DGST_Pos) |
| #define | CRPT_SHA_DGST6_DGST_Pos (0) |
| #define | CRPT_SHA_DGST6_DGST_Msk (0xfffffffful << CRPT_SHA_DGST6_DGST_Pos) |
| #define | CRPT_SHA_DGST7_DGST_Pos (0) |
| #define | CRPT_SHA_DGST7_DGST_Msk (0xfffffffful << CRPT_SHA_DGST7_DGST_Pos) |
| #define | CRPT_SHA_KEYCNT_KEYCNT_Pos (0) |
| #define | CRPT_SHA_KEYCNT_KEYCNT_Msk (0xfffffffful << CRPT_SHA_KEYCNT_KEYCNT_Pos) |
| #define | CRPT_SHA_SADDR_SADDR_Pos (0) |
| #define | CRPT_SHA_SADDR_SADDR_Msk (0xfffffffful << CRPT_SHA_SADDR_SADDR_Pos) |
| #define | CRPT_SHA_DMACNT_DMACNT_Pos (0) |
| #define | CRPT_SHA_DMACNT_DMACNT_Msk (0xfffffffful << CRPT_SHA_DMACNT_DMACNT_Pos) |
| #define | CRPT_SHA_DATIN_DATIN_Pos (0) |
| #define | CRPT_SHA_DATIN_DATIN_Msk (0xfffffffful << CRPT_SHA_DATIN_DATIN_Pos) |
| #define | EADC_AD0DAT0_RESULT_Pos (0) |
| #define | EADC_AD0DAT0_RESULT_Msk (0xffful << EADC_AD0DAT0_RESULT_Pos) |
| #define | EADC_AD0DAT0_OV_Pos (16) |
| #define | EADC_AD0DAT0_OV_Msk (0x1ul << EADC_AD0DAT0_OV_Pos) |
| #define | EADC_AD0DAT0_VALID_Pos (17) |
| #define | EADC_AD0DAT0_VALID_Msk (0x1ul << EADC_AD0DAT0_VALID_Pos) |
| #define | EADC_AD0DAT1_RESULT_Pos (0) |
| #define | EADC_AD0DAT1_RESULT_Msk (0xffful << EADC_AD0DAT1_RESULT_Pos) |
| #define | EADC_AD0DAT1_OV_Pos (16) |
| #define | EADC_AD0DAT1_OV_Msk (0x1ul << EADC_AD0DAT1_OV_Pos) |
| #define | EADC_AD0DAT1_VALID_Pos (17) |
| #define | EADC_AD0DAT1_VALID_Msk (0x1ul << EADC_AD0DAT1_VALID_Pos) |
| #define | EADC_AD0DAT2_RESULT_Pos (0) |
| #define | EADC_AD0DAT2_RESULT_Msk (0xffful << EADC_AD0DAT2_RESULT_Pos) |
| #define | EADC_AD0DAT2_OV_Pos (16) |
| #define | EADC_AD0DAT2_OV_Msk (0x1ul << EADC_AD0DAT2_OV_Pos) |
| #define | EADC_AD0DAT2_VALID_Pos (17) |
| #define | EADC_AD0DAT2_VALID_Msk (0x1ul << EADC_AD0DAT2_VALID_Pos) |
| #define | EADC_AD0DAT3_RESULT_Pos (0) |
| #define | EADC_AD0DAT3_RESULT_Msk (0xffful << EADC_AD0DAT3_RESULT_Pos) |
| #define | EADC_AD0DAT3_OV_Pos (16) |
| #define | EADC_AD0DAT3_OV_Msk (0x1ul << EADC_AD0DAT3_OV_Pos) |
| #define | EADC_AD0DAT3_VALID_Pos (17) |
| #define | EADC_AD0DAT3_VALID_Msk (0x1ul << EADC_AD0DAT3_VALID_Pos) |
| #define | EADC_AD0DAT4_RESULT_Pos (0) |
| #define | EADC_AD0DAT4_RESULT_Msk (0xffful << EADC_AD0DAT4_RESULT_Pos) |
| #define | EADC_AD0DAT4_OV_Pos (16) |
| #define | EADC_AD0DAT4_OV_Msk (0x1ul << EADC_AD0DAT4_OV_Pos) |
| #define | EADC_AD0DAT4_VALID_Pos (17) |
| #define | EADC_AD0DAT4_VALID_Msk (0x1ul << EADC_AD0DAT4_VALID_Pos) |
| #define | EADC_AD0DAT5_RESULT_Pos (0) |
| #define | EADC_AD0DAT5_RESULT_Msk (0xffful << EADC_AD0DAT5_RESULT_Pos) |
| #define | EADC_AD0DAT5_OV_Pos (16) |
| #define | EADC_AD0DAT5_OV_Msk (0x1ul << EADC_AD0DAT5_OV_Pos) |
| #define | EADC_AD0DAT5_VALID_Pos (17) |
| #define | EADC_AD0DAT5_VALID_Msk (0x1ul << EADC_AD0DAT5_VALID_Pos) |
| #define | EADC_AD0DAT6_RESULT_Pos (0) |
| #define | EADC_AD0DAT6_RESULT_Msk (0xffful << EADC_AD0DAT6_RESULT_Pos) |
| #define | EADC_AD0DAT6_OV_Pos (16) |
| #define | EADC_AD0DAT6_OV_Msk (0x1ul << EADC_AD0DAT6_OV_Pos) |
| #define | EADC_AD0DAT6_VALID_Pos (17) |
| #define | EADC_AD0DAT6_VALID_Msk (0x1ul << EADC_AD0DAT6_VALID_Pos) |
| #define | EADC_AD0DAT7_RESULT_Pos (0) |
| #define | EADC_AD0DAT7_RESULT_Msk (0xffful << EADC_AD0DAT7_RESULT_Pos) |
| #define | EADC_AD0DAT7_OV_Pos (16) |
| #define | EADC_AD0DAT7_OV_Msk (0x1ul << EADC_AD0DAT7_OV_Pos) |
| #define | EADC_AD0DAT7_VALID_Pos (17) |
| #define | EADC_AD0DAT7_VALID_Msk (0x1ul << EADC_AD0DAT7_VALID_Pos) |
| #define | EADC_AD1DAT0_RESULT_Pos (0) |
| #define | EADC_AD1DAT0_RESULT_Msk (0xffful << EADC_AD1DAT0_RESULT_Pos) |
| #define | EADC_AD1DAT0_OV_Pos (16) |
| #define | EADC_AD1DAT0_OV_Msk (0x1ul << EADC_AD1DAT0_OV_Pos) |
| #define | EADC_AD1DAT0_VALID_Pos (17) |
| #define | EADC_AD1DAT0_VALID_Msk (0x1ul << EADC_AD1DAT0_VALID_Pos) |
| #define | EADC_AD1DAT1_RESULT_Pos (0) |
| #define | EADC_AD1DAT1_RESULT_Msk (0xffful << EADC_AD1DAT1_RESULT_Pos) |
| #define | EADC_AD1DAT1_OV_Pos (16) |
| #define | EADC_AD1DAT1_OV_Msk (0x1ul << EADC_AD1DAT1_OV_Pos) |
| #define | EADC_AD1DAT1_VALID_Pos (17) |
| #define | EADC_AD1DAT1_VALID_Msk (0x1ul << EADC_AD1DAT1_VALID_Pos) |
| #define | EADC_AD1DAT2_RESULT_Pos (0) |
| #define | EADC_AD1DAT2_RESULT_Msk (0xffful << EADC_AD1DAT2_RESULT_Pos) |
| #define | EADC_AD1DAT2_OV_Pos (16) |
| #define | EADC_AD1DAT2_OV_Msk (0x1ul << EADC_AD1DAT2_OV_Pos) |
| #define | EADC_AD1DAT2_VALID_Pos (17) |
| #define | EADC_AD1DAT2_VALID_Msk (0x1ul << EADC_AD1DAT2_VALID_Pos) |
| #define | EADC_AD1DAT3_RESULT_Pos (0) |
| #define | EADC_AD1DAT3_RESULT_Msk (0xffful << EADC_AD1DAT3_RESULT_Pos) |
| #define | EADC_AD1DAT3_OV_Pos (16) |
| #define | EADC_AD1DAT3_OV_Msk (0x1ul << EADC_AD1DAT3_OV_Pos) |
| #define | EADC_AD1DAT3_VALID_Pos (17) |
| #define | EADC_AD1DAT3_VALID_Msk (0x1ul << EADC_AD1DAT3_VALID_Pos) |
| #define | EADC_AD1DAT4_RESULT_Pos (0) |
| #define | EADC_AD1DAT4_RESULT_Msk (0xffful << EADC_AD1DAT4_RESULT_Pos) |
| #define | EADC_AD1DAT4_OV_Pos (16) |
| #define | EADC_AD1DAT4_OV_Msk (0x1ul << EADC_AD1DAT4_OV_Pos) |
| #define | EADC_AD1DAT4_VALID_Pos (17) |
| #define | EADC_AD1DAT4_VALID_Msk (0x1ul << EADC_AD1DAT4_VALID_Pos) |
| #define | EADC_AD1DAT5_RESULT_Pos (0) |
| #define | EADC_AD1DAT5_RESULT_Msk (0xffful << EADC_AD1DAT5_RESULT_Pos) |
| #define | EADC_AD1DAT5_OV_Pos (16) |
| #define | EADC_AD1DAT5_OV_Msk (0x1ul << EADC_AD1DAT5_OV_Pos) |
| #define | EADC_AD1DAT5_VALID_Pos (17) |
| #define | EADC_AD1DAT5_VALID_Msk (0x1ul << EADC_AD1DAT5_VALID_Pos) |
| #define | EADC_AD1DAT6_RESULT_Pos (0) |
| #define | EADC_AD1DAT6_RESULT_Msk (0xffful << EADC_AD1DAT6_RESULT_Pos) |
| #define | EADC_AD1DAT6_OV_Pos (16) |
| #define | EADC_AD1DAT6_OV_Msk (0x1ul << EADC_AD1DAT6_OV_Pos) |
| #define | EADC_AD1DAT6_VALID_Pos (17) |
| #define | EADC_AD1DAT6_VALID_Msk (0x1ul << EADC_AD1DAT6_VALID_Pos) |
| #define | EADC_AD1DAT7_RESULT_Pos (0) |
| #define | EADC_AD1DAT7_RESULT_Msk (0xffful << EADC_AD1DAT7_RESULT_Pos) |
| #define | EADC_AD1DAT7_OV_Pos (16) |
| #define | EADC_AD1DAT7_OV_Msk (0x1ul << EADC_AD1DAT7_OV_Pos) |
| #define | EADC_AD1DAT7_VALID_Pos (17) |
| #define | EADC_AD1DAT7_VALID_Msk (0x1ul << EADC_AD1DAT7_VALID_Pos) |
| #define | EADC_CTL_ADCEN_Pos (0) |
| #define | EADC_CTL_ADCEN_Msk (0x1ul << EADC_CTL_ADCEN_Pos) |
| #define | EADC_CTL_ADCRST_Pos (1) |
| #define | EADC_CTL_ADCRST_Msk (0x1ul << EADC_CTL_ADCRST_Pos) |
| #define | EADC_CTL_ADCIEN0_Pos (2) |
| #define | EADC_CTL_ADCIEN0_Msk (0x1ul << EADC_CTL_ADCIEN0_Pos) |
| #define | EADC_CTL_ADCIEN1_Pos (3) |
| #define | EADC_CTL_ADCIEN1_Msk (0x1ul << EADC_CTL_ADCIEN1_Pos) |
| #define | EADC_CTL_ADCIEN2_Pos (4) |
| #define | EADC_CTL_ADCIEN2_Msk (0x1ul << EADC_CTL_ADCIEN2_Pos) |
| #define | EADC_CTL_ADCIEN3_Pos (5) |
| #define | EADC_CTL_ADCIEN3_Msk (0x1ul << EADC_CTL_ADCIEN3_Pos) |
| #define | EADC_SWTRG_SWTRG7_0_Pos (0) |
| #define | EADC_SWTRG_SWTRG7_0_Msk (0xfful << EADC_SWTRG_SWTRG7_0_Pos) |
| #define | EADC_SWTRG_SWTRG15_8_Pos (8) |
| #define | EADC_SWTRG_SWTRG15_8_Msk (0xfful << EADC_SWTRG_SWTRG15_8_Pos) |
| #define | EADC_PENDSTS_STPF7_0_Pos (0) |
| #define | EADC_PENDSTS_STPF7_0_Msk (0xfful << EADC_PENDSTS_STPF7_0_Pos) |
| #define | EADC_PENDSTS_STPF15_8_Pos (8) |
| #define | EADC_PENDSTS_STPF15_8_Msk (0xfful << EADC_PENDSTS_STPF15_8_Pos) |
| #define | EADC_ADIFOV_ADFOV0_Pos (0) |
| #define | EADC_ADIFOV_ADFOV0_Msk (0x1ul << EADC_ADIFOV_ADFOV0_Pos) |
| #define | EADC_ADIFOV_ADFOV1_Pos (1) |
| #define | EADC_ADIFOV_ADFOV1_Msk (0x1ul << EADC_ADIFOV_ADFOV1_Pos) |
| #define | EADC_ADIFOV_ADFOV2_Pos (2) |
| #define | EADC_ADIFOV_ADFOV2_Msk (0x1ul << EADC_ADIFOV_ADFOV2_Pos) |
| #define | EADC_ADIFOV_ADFOV3_Pos (3) |
| #define | EADC_ADIFOV_ADFOV3_Msk (0x1ul << EADC_ADIFOV_ADFOV3_Pos) |
| #define | EADC_OVSTS_SPOVF7_0_Pos (0) |
| #define | EADC_OVSTS_SPOVF7_0_Msk (0xfful << EADC_OVSTS_SPOVF7_0_Pos) |
| #define | EADC_OVSTS_SPOVF15_8_Pos (8) |
| #define | EADC_OVSTS_SPOVF15_8_Msk (0xfful << EADC_OVSTS_SPOVF15_8_Pos) |
| #define | EADC_AD0SPCTL0_CHSEL_Pos (0) |
| #define | EADC_AD0SPCTL0_CHSEL_Msk (0xful << EADC_AD0SPCTL0_CHSEL_Pos) |
| #define | EADC_AD0SPCTL0_TRGSEL_Pos (4) |
| #define | EADC_AD0SPCTL0_TRGSEL_Msk (0xful << EADC_AD0SPCTL0_TRGSEL_Pos) |
| #define | EADC_AD0SPCTL0_TRGDLYCNT_Pos (8) |
| #define | EADC_AD0SPCTL0_TRGDLYCNT_Msk (0xfful << EADC_AD0SPCTL0_TRGDLYCNT_Pos) |
| #define | EADC_AD0SPCTL0_TRGDLYDIV_Pos (16) |
| #define | EADC_AD0SPCTL0_TRGDLYDIV_Msk (0x3ul << EADC_AD0SPCTL0_TRGDLYDIV_Pos) |
| #define | EADC_AD0SPCTL0_EXTREN_Pos (20) |
| #define | EADC_AD0SPCTL0_EXTREN_Msk (0x1ul << EADC_AD0SPCTL0_EXTREN_Pos) |
| #define | EADC_AD0SPCTL0_EXTFEN_Pos (21) |
| #define | EADC_AD0SPCTL0_EXTFEN_Msk (0x1ul << EADC_AD0SPCTL0_EXTFEN_Pos) |
| #define | EADC_AD0SPCTL1_CHSEL_Pos (0) |
| #define | EADC_AD0SPCTL1_CHSEL_Msk (0xful << EADC_AD0SPCTL1_CHSEL_Pos) |
| #define | EADC_AD0SPCTL1_TRGSEL_Pos (4) |
| #define | EADC_AD0SPCTL1_TRGSEL_Msk (0xful << EADC_AD0SPCTL1_TRGSEL_Pos) |
| #define | EADC_AD0SPCTL1_TRGDLYCNT_Pos (8) |
| #define | EADC_AD0SPCTL1_TRGDLYCNT_Msk (0xfful << EADC_AD0SPCTL1_TRGDLYCNT_Pos) |
| #define | EADC_AD0SPCTL1_TRGDLYDIV_Pos (16) |
| #define | EADC_AD0SPCTL1_TRGDLYDIV_Msk (0x3ul << EADC_AD0SPCTL1_TRGDLYDIV_Pos) |
| #define | EADC_AD0SPCTL1_EXTREN_Pos (20) |
| #define | EADC_AD0SPCTL1_EXTREN_Msk (0x1ul << EADC_AD0SPCTL1_EXTREN_Pos) |
| #define | EADC_AD0SPCTL1_EXTFEN_Pos (21) |
| #define | EADC_AD0SPCTL1_EXTFEN_Msk (0x1ul << EADC_AD0SPCTL1_EXTFEN_Pos) |
| #define | EADC_AD0SPCTL2_CHSEL_Pos (0) |
| #define | EADC_AD0SPCTL2_CHSEL_Msk (0xful << EADC_AD0SPCTL2_CHSEL_Pos) |
| #define | EADC_AD0SPCTL2_TRGSEL_Pos (4) |
| #define | EADC_AD0SPCTL2_TRGSEL_Msk (0xful << EADC_AD0SPCTL2_TRGSEL_Pos) |
| #define | EADC_AD0SPCTL2_TRGDLYCNT_Pos (8) |
| #define | EADC_AD0SPCTL2_TRGDLYCNT_Msk (0xfful << EADC_AD0SPCTL2_TRGDLYCNT_Pos) |
| #define | EADC_AD0SPCTL2_TRGDLYDIV_Pos (16) |
| #define | EADC_AD0SPCTL2_TRGDLYDIV_Msk (0x3ul << EADC_AD0SPCTL2_TRGDLYDIV_Pos) |
| #define | EADC_AD0SPCTL2_EXTREN_Pos (20) |
| #define | EADC_AD0SPCTL2_EXTREN_Msk (0x1ul << EADC_AD0SPCTL2_EXTREN_Pos) |
| #define | EADC_AD0SPCTL2_EXTFEN_Pos (21) |
| #define | EADC_AD0SPCTL2_EXTFEN_Msk (0x1ul << EADC_AD0SPCTL2_EXTFEN_Pos) |
| #define | EADC_AD0SPCTL3_CHSEL_Pos (0) |
| #define | EADC_AD0SPCTL3_CHSEL_Msk (0xful << EADC_AD0SPCTL3_CHSEL_Pos) |
| #define | EADC_AD0SPCTL3_TRGSEL_Pos (4) |
| #define | EADC_AD0SPCTL3_TRGSEL_Msk (0xful << EADC_AD0SPCTL3_TRGSEL_Pos) |
| #define | EADC_AD0SPCTL3_TRGDLYCNT_Pos (8) |
| #define | EADC_AD0SPCTL3_TRGDLYCNT_Msk (0xfful << EADC_AD0SPCTL3_TRGDLYCNT_Pos) |
| #define | EADC_AD0SPCTL3_TRGDLYDIV_Pos (16) |
| #define | EADC_AD0SPCTL3_TRGDLYDIV_Msk (0x3ul << EADC_AD0SPCTL3_TRGDLYDIV_Pos) |
| #define | EADC_AD0SPCTL3_EXTREN_Pos (20) |
| #define | EADC_AD0SPCTL3_EXTREN_Msk (0x1ul << EADC_AD0SPCTL3_EXTREN_Pos) |
| #define | EADC_AD0SPCTL3_EXTFEN_Pos (21) |
| #define | EADC_AD0SPCTL3_EXTFEN_Msk (0x1ul << EADC_AD0SPCTL3_EXTFEN_Pos) |
| #define | EADC_AD0SPCTL4_CHSEL_Pos (0) |
| #define | EADC_AD0SPCTL4_CHSEL_Msk (0xful << EADC_AD0SPCTL4_CHSEL_Pos) |
| #define | EADC_AD0SPCTL4_TRGSEL_Pos (4) |
| #define | EADC_AD0SPCTL4_TRGSEL_Msk (0x7ul << EADC_AD0SPCTL4_TRGSEL_Pos) |
| #define | EADC_AD0SPCTL4_EXTREN_Pos (20) |
| #define | EADC_AD0SPCTL4_EXTREN_Msk (0x1ul << EADC_AD0SPCTL4_EXTREN_Pos) |
| #define | EADC_AD0SPCTL4_EXTFEN_Pos (21) |
| #define | EADC_AD0SPCTL4_EXTFEN_Msk (0x1ul << EADC_AD0SPCTL4_EXTFEN_Pos) |
| #define | EADC_AD0SPCTL5_CHSEL_Pos (0) |
| #define | EADC_AD0SPCTL5_CHSEL_Msk (0xful << EADC_AD0SPCTL5_CHSEL_Pos) |
| #define | EADC_AD0SPCTL5_TRGSEL_Pos (4) |
| #define | EADC_AD0SPCTL5_TRGSEL_Msk (0x7ul << EADC_AD0SPCTL5_TRGSEL_Pos) |
| #define | EADC_AD0SPCTL5_EXTREN_Pos (20) |
| #define | EADC_AD0SPCTL5_EXTREN_Msk (0x1ul << EADC_AD0SPCTL5_EXTREN_Pos) |
| #define | EADC_AD0SPCTL5_EXTFEN_Pos (21) |
| #define | EADC_AD0SPCTL5_EXTFEN_Msk (0x1ul << EADC_AD0SPCTL5_EXTFEN_Pos) |
| #define | EADC_AD0SPCTL6_CHSEL_Pos (0) |
| #define | EADC_AD0SPCTL6_CHSEL_Msk (0xful << EADC_AD0SPCTL6_CHSEL_Pos) |
| #define | EADC_AD0SPCTL6_TRGSEL_Pos (4) |
| #define | EADC_AD0SPCTL6_TRGSEL_Msk (0x7ul << EADC_AD0SPCTL6_TRGSEL_Pos) |
| #define | EADC_AD0SPCTL6_EXTREN_Pos (20) |
| #define | EADC_AD0SPCTL6_EXTREN_Msk (0x1ul << EADC_AD0SPCTL6_EXTREN_Pos) |
| #define | EADC_AD0SPCTL6_EXTFEN_Pos (21) |
| #define | EADC_AD0SPCTL6_EXTFEN_Msk (0x1ul << EADC_AD0SPCTL6_EXTFEN_Pos) |
| #define | EADC_AD0SPCTL7_CHSEL_Pos (0) |
| #define | EADC_AD0SPCTL7_CHSEL_Msk (0xful << EADC_AD0SPCTL7_CHSEL_Pos) |
| #define | EADC_AD0SPCTL7_TRGSEL_Pos (4) |
| #define | EADC_AD0SPCTL7_TRGSEL_Msk (0x7ul << EADC_AD0SPCTL7_TRGSEL_Pos) |
| #define | EADC_AD0SPCTL7_EXTREN_Pos (20) |
| #define | EADC_AD0SPCTL7_EXTREN_Msk (0x1ul << EADC_AD0SPCTL7_EXTREN_Pos) |
| #define | EADC_AD0SPCTL7_EXTFEN_Pos (21) |
| #define | EADC_AD0SPCTL7_EXTFEN_Msk (0x1ul << EADC_AD0SPCTL7_EXTFEN_Pos) |
| #define | EADC_AD1SPCTL0_CHSEL_Pos (0) |
| #define | EADC_AD1SPCTL0_CHSEL_Msk (0xful << EADC_AD1SPCTL0_CHSEL_Pos) |
| #define | EADC_AD1SPCTL0_TRGSEL_Pos (4) |
| #define | EADC_AD1SPCTL0_TRGSEL_Msk (0xful << EADC_AD1SPCTL0_TRGSEL_Pos) |
| #define | EADC_AD1SPCTL0_TRGDLYCNT_Pos (8) |
| #define | EADC_AD1SPCTL0_TRGDLYCNT_Msk (0xfful << EADC_AD1SPCTL0_TRGDLYCNT_Pos) |
| #define | EADC_AD1SPCTL0_TRGDLYDIV_Pos (16) |
| #define | EADC_AD1SPCTL0_TRGDLYDIV_Msk (0x3ul << EADC_AD1SPCTL0_TRGDLYDIV_Pos) |
| #define | EADC_AD1SPCTL0_EXTREN_Pos (20) |
| #define | EADC_AD1SPCTL0_EXTREN_Msk (0x1ul << EADC_AD1SPCTL0_EXTREN_Pos) |
| #define | EADC_AD1SPCTL0_EXTFEN_Pos (21) |
| #define | EADC_AD1SPCTL0_EXTFEN_Msk (0x1ul << EADC_AD1SPCTL0_EXTFEN_Pos) |
| #define | EADC_AD1SPCTL1_CHSEL_Pos (0) |
| #define | EADC_AD1SPCTL1_CHSEL_Msk (0xful << EADC_AD1SPCTL1_CHSEL_Pos) |
| #define | EADC_AD1SPCTL1_TRGSEL_Pos (4) |
| #define | EADC_AD1SPCTL1_TRGSEL_Msk (0xful << EADC_AD1SPCTL1_TRGSEL_Pos) |
| #define | EADC_AD1SPCTL1_TRGDLYCNT_Pos (8) |
| #define | EADC_AD1SPCTL1_TRGDLYCNT_Msk (0xfful << EADC_AD1SPCTL1_TRGDLYCNT_Pos) |
| #define | EADC_AD1SPCTL1_TRGDLYDIV_Pos (16) |
| #define | EADC_AD1SPCTL1_TRGDLYDIV_Msk (0x3ul << EADC_AD1SPCTL1_TRGDLYDIV_Pos) |
| #define | EADC_AD1SPCTL1_EXTREN_Pos (20) |
| #define | EADC_AD1SPCTL1_EXTREN_Msk (0x1ul << EADC_AD1SPCTL1_EXTREN_Pos) |
| #define | EADC_AD1SPCTL1_EXTFEN_Pos (21) |
| #define | EADC_AD1SPCTL1_EXTFEN_Msk (0x1ul << EADC_AD1SPCTL1_EXTFEN_Pos) |
| #define | EADC_AD1SPCTL2_CHSEL_Pos (0) |
| #define | EADC_AD1SPCTL2_CHSEL_Msk (0xful << EADC_AD1SPCTL2_CHSEL_Pos) |
| #define | EADC_AD1SPCTL2_TRGSEL_Pos (4) |
| #define | EADC_AD1SPCTL2_TRGSEL_Msk (0xful << EADC_AD1SPCTL2_TRGSEL_Pos) |
| #define | EADC_AD1SPCTL2_TRGDLYCNT_Pos (8) |
| #define | EADC_AD1SPCTL2_TRGDLYCNT_Msk (0xfful << EADC_AD1SPCTL2_TRGDLYCNT_Pos) |
| #define | EADC_AD1SPCTL2_TRGDLYDIV_Pos (16) |
| #define | EADC_AD1SPCTL2_TRGDLYDIV_Msk (0x3ul << EADC_AD1SPCTL2_TRGDLYDIV_Pos) |
| #define | EADC_AD1SPCTL2_EXTREN_Pos (20) |
| #define | EADC_AD1SPCTL2_EXTREN_Msk (0x1ul << EADC_AD1SPCTL2_EXTREN_Pos) |
| #define | EADC_AD1SPCTL2_EXTFEN_Pos (21) |
| #define | EADC_AD1SPCTL2_EXTFEN_Msk (0x1ul << EADC_AD1SPCTL2_EXTFEN_Pos) |
| #define | EADC_AD1SPCTL3_CHSEL_Pos (0) |
| #define | EADC_AD1SPCTL3_CHSEL_Msk (0xful << EADC_AD1SPCTL3_CHSEL_Pos) |
| #define | EADC_AD1SPCTL3_TRGSEL_Pos (4) |
| #define | EADC_AD1SPCTL3_TRGSEL_Msk (0xful << EADC_AD1SPCTL3_TRGSEL_Pos) |
| #define | EADC_AD1SPCTL3_TRGDLYCNT_Pos (8) |
| #define | EADC_AD1SPCTL3_TRGDLYCNT_Msk (0xfful << EADC_AD1SPCTL3_TRGDLYCNT_Pos) |
| #define | EADC_AD1SPCTL3_TRGDLYDIV_Pos (16) |
| #define | EADC_AD1SPCTL3_TRGDLYDIV_Msk (0x3ul << EADC_AD1SPCTL3_TRGDLYDIV_Pos) |
| #define | EADC_AD1SPCTL3_EXTREN_Pos (20) |
| #define | EADC_AD1SPCTL3_EXTREN_Msk (0x1ul << EADC_AD1SPCTL3_EXTREN_Pos) |
| #define | EADC_AD1SPCTL3_EXTFEN_Pos (21) |
| #define | EADC_AD1SPCTL3_EXTFEN_Msk (0x1ul << EADC_AD1SPCTL3_EXTFEN_Pos) |
| #define | EADC_AD1SPCTL4_CHSEL_Pos (0) |
| #define | EADC_AD1SPCTL4_CHSEL_Msk (0xful << EADC_AD1SPCTL4_CHSEL_Pos) |
| #define | EADC_AD1SPCTL4_TRGSEL_Pos (4) |
| #define | EADC_AD1SPCTL4_TRGSEL_Msk (0x7ul << EADC_AD1SPCTL4_TRGSEL_Pos) |
| #define | EADC_AD1SPCTL4_EXTREN_Pos (20) |
| #define | EADC_AD1SPCTL4_EXTREN_Msk (0x1ul << EADC_AD1SPCTL4_EXTREN_Pos) |
| #define | EADC_AD1SPCTL4_EXTFEN_Pos (21) |
| #define | EADC_AD1SPCTL4_EXTFEN_Msk (0x1ul << EADC_AD1SPCTL4_EXTFEN_Pos) |
| #define | EADC_AD1SPCTL5_CHSEL_Pos (0) |
| #define | EADC_AD1SPCTL5_CHSEL_Msk (0xful << EADC_AD1SPCTL5_CHSEL_Pos) |
| #define | EADC_AD1SPCTL5_TRGSEL_Pos (4) |
| #define | EADC_AD1SPCTL5_TRGSEL_Msk (0x7ul << EADC_AD1SPCTL5_TRGSEL_Pos) |
| #define | EADC_AD1SPCTL5_EXTREN_Pos (20) |
| #define | EADC_AD1SPCTL5_EXTREN_Msk (0x1ul << EADC_AD1SPCTL5_EXTREN_Pos) |
| #define | EADC_AD1SPCTL5_EXTFEN_Pos (21) |
| #define | EADC_AD1SPCTL5_EXTFEN_Msk (0x1ul << EADC_AD1SPCTL5_EXTFEN_Pos) |
| #define | EADC_AD1SPCTL6_CHSEL_Pos (0) |
| #define | EADC_AD1SPCTL6_CHSEL_Msk (0xful << EADC_AD1SPCTL6_CHSEL_Pos) |
| #define | EADC_AD1SPCTL6_TRGSEL_Pos (4) |
| #define | EADC_AD1SPCTL6_TRGSEL_Msk (0x7ul << EADC_AD1SPCTL6_TRGSEL_Pos) |
| #define | EADC_AD1SPCTL6_EXTREN_Pos (20) |
| #define | EADC_AD1SPCTL6_EXTREN_Msk (0x1ul << EADC_AD1SPCTL6_EXTREN_Pos) |
| #define | EADC_AD1SPCTL6_EXTFEN_Pos (21) |
| #define | EADC_AD1SPCTL6_EXTFEN_Msk (0x1ul << EADC_AD1SPCTL6_EXTFEN_Pos) |
| #define | EADC_AD1SPCTL7_CHSEL_Pos (0) |
| #define | EADC_AD1SPCTL7_CHSEL_Msk (0xful << EADC_AD1SPCTL7_CHSEL_Pos) |
| #define | EADC_AD1SPCTL7_TRGSEL_Pos (4) |
| #define | EADC_AD1SPCTL7_TRGSEL_Msk (0x7ul << EADC_AD1SPCTL7_TRGSEL_Pos) |
| #define | EADC_AD1SPCTL7_EXTREN_Pos (20) |
| #define | EADC_AD1SPCTL7_EXTREN_Msk (0x1ul << EADC_AD1SPCTL7_EXTREN_Pos) |
| #define | EADC_AD1SPCTL7_EXTFEN_Pos (21) |
| #define | EADC_AD1SPCTL7_EXTFEN_Msk (0x1ul << EADC_AD1SPCTL7_EXTFEN_Pos) |
| #define | EADC_SIMUSEL_SIMUSEL0_Pos (0) |
| #define | EADC_SIMUSEL_SIMUSEL0_Msk (0x1ul << EADC_SIMUSEL_SIMUSEL0_Pos) |
| #define | EADC_SIMUSEL_SIMUSEL1_Pos (1) |
| #define | EADC_SIMUSEL_SIMUSEL1_Msk (0x1ul << EADC_SIMUSEL_SIMUSEL1_Pos) |
| #define | EADC_SIMUSEL_SIMUSEL2_Pos (2) |
| #define | EADC_SIMUSEL_SIMUSEL2_Msk (0x1ul << EADC_SIMUSEL_SIMUSEL2_Pos) |
| #define | EADC_SIMUSEL_SIMUSEL3_Pos (3) |
| #define | EADC_SIMUSEL_SIMUSEL3_Msk (0x1ul << EADC_SIMUSEL_SIMUSEL3_Pos) |
| #define | EADC_SIMUSEL_SIMUSEL4_Pos (4) |
| #define | EADC_SIMUSEL_SIMUSEL4_Msk (0x1ul << EADC_SIMUSEL_SIMUSEL4_Pos) |
| #define | EADC_SIMUSEL_SIMUSEL5_Pos (5) |
| #define | EADC_SIMUSEL_SIMUSEL5_Msk (0x1ul << EADC_SIMUSEL_SIMUSEL5_Pos) |
| #define | EADC_SIMUSEL_SIMUSEL6_Pos (6) |
| #define | EADC_SIMUSEL_SIMUSEL6_Msk (0x1ul << EADC_SIMUSEL_SIMUSEL6_Pos) |
| #define | EADC_SIMUSEL_SIMUSEL7_Pos (7) |
| #define | EADC_SIMUSEL_SIMUSEL7_Msk (0x1ul << EADC_SIMUSEL_SIMUSEL7_Pos) |
| #define | EADC_CMP0_ADCMPEN_Pos (0) |
| #define | EADC_CMP0_ADCMPEN_Msk (0x1ul << EADC_CMP0_ADCMPEN_Pos) |
| #define | EADC_CMP0_ADCMPIE_Pos (1) |
| #define | EADC_CMP0_ADCMPIE_Msk (0x1ul << EADC_CMP0_ADCMPIE_Pos) |
| #define | EADC_CMP0_CMPCOND_Pos (2) |
| #define | EADC_CMP0_CMPCOND_Msk (0x1ul << EADC_CMP0_CMPCOND_Pos) |
| #define | EADC_CMP0_CMPSPL_Pos (3) |
| #define | EADC_CMP0_CMPSPL_Msk (0x7ul << EADC_CMP0_CMPSPL_Pos) |
| #define | EADC_CMP0_CMPMCNT_Pos (8) |
| #define | EADC_CMP0_CMPMCNT_Msk (0xful << EADC_CMP0_CMPMCNT_Pos) |
| #define | EADC_CMP0_CMPDAT_Pos (16) |
| #define | EADC_CMP0_CMPDAT_Msk (0xffful << EADC_CMP0_CMPDAT_Pos) |
| #define | EADC_CMP1_ADCMPEN_Pos (0) |
| #define | EADC_CMP1_ADCMPEN_Msk (0x1ul << EADC_CMP1_ADCMPEN_Pos) |
| #define | EADC_CMP1_ADCMPIE_Pos (1) |
| #define | EADC_CMP1_ADCMPIE_Msk (0x1ul << EADC_CMP1_ADCMPIE_Pos) |
| #define | EADC_CMP1_CMPCOND_Pos (2) |
| #define | EADC_CMP1_CMPCOND_Msk (0x1ul << EADC_CMP1_CMPCOND_Pos) |
| #define | EADC_CMP1_CMPSPL_Pos (3) |
| #define | EADC_CMP1_CMPSPL_Msk (0x7ul << EADC_CMP1_CMPSPL_Pos) |
| #define | EADC_CMP1_CMPMCNT_Pos (8) |
| #define | EADC_CMP1_CMPMCNT_Msk (0xful << EADC_CMP1_CMPMCNT_Pos) |
| #define | EADC_CMP1_CMPDAT_Pos (16) |
| #define | EADC_CMP1_CMPDAT_Msk (0xffful << EADC_CMP1_CMPDAT_Pos) |
| #define | EADC_STATUS0_VALID_Pos (0) |
| #define | EADC_STATUS0_VALID_Msk (0xfffful << EADC_STATUS0_VALID_Pos) |
| #define | EADC_STATUS0_OV_Pos (16) |
| #define | EADC_STATUS0_OV_Msk (0xfffful << EADC_STATUS0_OV_Pos) |
| #define | EADC_STATUS1_ADIF0_Pos (0) |
| #define | EADC_STATUS1_ADIF0_Msk (0x1ul << EADC_STATUS1_ADIF0_Pos) |
| #define | EADC_STATUS1_ADIF1_Pos (1) |
| #define | EADC_STATUS1_ADIF1_Msk (0x1ul << EADC_STATUS1_ADIF1_Pos) |
| #define | EADC_STATUS1_ADIF2_Pos (2) |
| #define | EADC_STATUS1_ADIF2_Msk (0x1ul << EADC_STATUS1_ADIF2_Pos) |
| #define | EADC_STATUS1_ADIF3_Pos (3) |
| #define | EADC_STATUS1_ADIF3_Msk (0x1ul << EADC_STATUS1_ADIF3_Pos) |
| #define | EADC_STATUS1_ADCMPO0_Pos (4) |
| #define | EADC_STATUS1_ADCMPO0_Msk (0x1ul << EADC_STATUS1_ADCMPO0_Pos) |
| #define | EADC_STATUS1_ADCMPO1_Pos (5) |
| #define | EADC_STATUS1_ADCMPO1_Msk (0x1ul << EADC_STATUS1_ADCMPO1_Pos) |
| #define | EADC_STATUS1_ADCMPF0_Pos (6) |
| #define | EADC_STATUS1_ADCMPF0_Msk (0x1ul << EADC_STATUS1_ADCMPF0_Pos) |
| #define | EADC_STATUS1_ADCMPF1_Pos (7) |
| #define | EADC_STATUS1_ADCMPF1_Msk (0x1ul << EADC_STATUS1_ADCMPF1_Pos) |
| #define | EADC_STATUS1_BUSY0_Pos (8) |
| #define | EADC_STATUS1_BUSY0_Msk (0x1ul << EADC_STATUS1_BUSY0_Pos) |
| #define | EADC_STATUS1_CHANNEL0_Pos (12) |
| #define | EADC_STATUS1_CHANNEL0_Msk (0xful << EADC_STATUS1_CHANNEL0_Pos) |
| #define | EADC_STATUS1_BUSY1_Pos (16) |
| #define | EADC_STATUS1_BUSY1_Msk (0x1ul << EADC_STATUS1_BUSY1_Pos) |
| #define | EADC_STATUS1_CHANNEL1_Pos (20) |
| #define | EADC_STATUS1_CHANNEL1_Msk (0xful << EADC_STATUS1_CHANNEL1_Pos) |
| #define | EADC_STATUS1_ADOVIF_Pos (24) |
| #define | EADC_STATUS1_ADOVIF_Msk (0x1ul << EADC_STATUS1_ADOVIF_Pos) |
| #define | EADC_STATUS1_STOVF_Pos (25) |
| #define | EADC_STATUS1_STOVF_Msk (0x1ul << EADC_STATUS1_STOVF_Pos) |
| #define | EADC_STATUS1_AVALID_Pos (26) |
| #define | EADC_STATUS1_AVALID_Msk (0x1ul << EADC_STATUS1_AVALID_Pos) |
| #define | EADC_STATUS1_AOV_Pos (27) |
| #define | EADC_STATUS1_AOV_Msk (0x1ul << EADC_STATUS1_AOV_Pos) |
| #define | EADC_EXTSMPT_EXTSMPT0_Pos (0) |
| #define | EADC_EXTSMPT_EXTSMPT0_Msk (0xfful << EADC_EXTSMPT_EXTSMPT0_Pos) |
| #define | EADC_EXTSMPT_EXTSMPT1_Pos (16) |
| #define | EADC_EXTSMPT_EXTSMPT1_Msk (0xfful << EADC_EXTSMPT_EXTSMPT1_Pos) |
| #define | EADC_AD0DDAT0_RESULT_Pos (0) |
| #define | EADC_AD0DDAT0_RESULT_Msk (0xffful << EADC_AD0DDAT0_RESULT_Pos) |
| #define | EADC_AD0DDAT0_VALID_Pos (16) |
| #define | EADC_AD0DDAT0_VALID_Msk (0x1ul << EADC_AD0DDAT0_VALID_Pos) |
| #define | EADC_AD0DDAT1_RESULT_Pos (0) |
| #define | EADC_AD0DDAT1_RESULT_Msk (0xffful << EADC_AD0DDAT1_RESULT_Pos) |
| #define | EADC_AD0DDAT1_VALID_Pos (16) |
| #define | EADC_AD0DDAT1_VALID_Msk (0x1ul << EADC_AD0DDAT1_VALID_Pos) |
| #define | EADC_AD0DDAT2_RESULT_Pos (0) |
| #define | EADC_AD0DDAT2_RESULT_Msk (0xffful << EADC_AD0DDAT2_RESULT_Pos) |
| #define | EADC_AD0DDAT2_VALID_Pos (16) |
| #define | EADC_AD0DDAT2_VALID_Msk (0x1ul << EADC_AD0DDAT2_VALID_Pos) |
| #define | EADC_AD0DDAT3_RESULT_Pos (0) |
| #define | EADC_AD0DDAT3_RESULT_Msk (0xffful << EADC_AD0DDAT3_RESULT_Pos) |
| #define | EADC_AD0DDAT3_VALID_Pos (16) |
| #define | EADC_AD0DDAT3_VALID_Msk (0x1ul << EADC_AD0DDAT3_VALID_Pos) |
| #define | EADC_AD1DDAT0_RESULT_Pos (0) |
| #define | EADC_AD1DDAT0_RESULT_Msk (0xffful << EADC_AD1DDAT0_RESULT_Pos) |
| #define | EADC_AD1DDAT0_VALID_Pos (16) |
| #define | EADC_AD1DDAT0_VALID_Msk (0x1ul << EADC_AD1DDAT0_VALID_Pos) |
| #define | EADC_AD1DDAT1_RESULT_Pos (0) |
| #define | EADC_AD1DDAT1_RESULT_Msk (0xffful << EADC_AD1DDAT1_RESULT_Pos) |
| #define | EADC_AD1DDAT1_VALID_Pos (16) |
| #define | EADC_AD1DDAT1_VALID_Msk (0x1ul << EADC_AD1DDAT1_VALID_Pos) |
| #define | EADC_AD1DDAT2_RESULT_Pos (0) |
| #define | EADC_AD1DDAT2_RESULT_Msk (0xffful << EADC_AD1DDAT2_RESULT_Pos) |
| #define | EADC_AD1DDAT2_VALID_Pos (16) |
| #define | EADC_AD1DDAT2_VALID_Msk (0x1ul << EADC_AD1DDAT2_VALID_Pos) |
| #define | EADC_AD1DDAT3_RESULT_Pos (0) |
| #define | EADC_AD1DDAT3_RESULT_Msk (0xffful << EADC_AD1DDAT3_RESULT_Pos) |
| #define | EADC_AD1DDAT3_VALID_Pos (16) |
| #define | EADC_AD1DDAT3_VALID_Msk (0x1ul << EADC_AD1DDAT3_VALID_Pos) |
| #define | EADC_DBMEN_AD0DBM0_Pos (0) |
| #define | EADC_DBMEN_AD0DBM0_Msk (0x1ul << EADC_DBMEN_AD0DBM0_Pos) |
| #define | EADC_DBMEN_AD0DBM1_Pos (1) |
| #define | EADC_DBMEN_AD0DBM1_Msk (0x1ul << EADC_DBMEN_AD0DBM1_Pos) |
| #define | EADC_DBMEN_AD0DBM2_Pos (2) |
| #define | EADC_DBMEN_AD0DBM2_Msk (0x1ul << EADC_DBMEN_AD0DBM2_Pos) |
| #define | EADC_DBMEN_AD0DBM3_Pos (3) |
| #define | EADC_DBMEN_AD0DBM3_Msk (0x1ul << EADC_DBMEN_AD0DBM3_Pos) |
| #define | EADC_DBMEN_AD1DBM0_Pos (8) |
| #define | EADC_DBMEN_AD1DBM0_Msk (0x1ul << EADC_DBMEN_AD1DBM0_Pos) |
| #define | EADC_DBMEN_AD1DBM1_Pos (9) |
| #define | EADC_DBMEN_AD1DBM1_Msk (0x1ul << EADC_DBMEN_AD1DBM1_Pos) |
| #define | EADC_DBMEN_AD1DBM2_Pos (10) |
| #define | EADC_DBMEN_AD1DBM2_Msk (0x1ul << EADC_DBMEN_AD1DBM2_Pos) |
| #define | EADC_DBMEN_AD1DBM3_Pos (11) |
| #define | EADC_DBMEN_AD1DBM3_Msk (0x1ul << EADC_DBMEN_AD1DBM3_Pos) |
| #define | EADC_INTSRC0_AD0SPIE0_Pos (0) |
| #define | EADC_INTSRC0_AD0SPIE0_Msk (0x1ul << EADC_INTSRC0_AD0SPIE0_Pos) |
| #define | EADC_INTSRC0_AD0SPIE1_Pos (1) |
| #define | EADC_INTSRC0_AD0SPIE1_Msk (0x1ul << EADC_INTSRC0_AD0SPIE1_Pos) |
| #define | EADC_INTSRC0_AD0SPIE2_Pos (2) |
| #define | EADC_INTSRC0_AD0SPIE2_Msk (0x1ul << EADC_INTSRC0_AD0SPIE2_Pos) |
| #define | EADC_INTSRC0_AD0SPIE3_Pos (3) |
| #define | EADC_INTSRC0_AD0SPIE3_Msk (0x1ul << EADC_INTSRC0_AD0SPIE3_Pos) |
| #define | EADC_INTSRC0_AD0SPIE4_Pos (4) |
| #define | EADC_INTSRC0_AD0SPIE4_Msk (0x1ul << EADC_INTSRC0_AD0SPIE4_Pos) |
| #define | EADC_INTSRC0_AD0SPIE5_Pos (5) |
| #define | EADC_INTSRC0_AD0SPIE5_Msk (0x1ul << EADC_INTSRC0_AD0SPIE5_Pos) |
| #define | EADC_INTSRC0_AD0SPIE6_Pos (6) |
| #define | EADC_INTSRC0_AD0SPIE6_Msk (0x1ul << EADC_INTSRC0_AD0SPIE6_Pos) |
| #define | EADC_INTSRC0_AD0SPIE7_Pos (7) |
| #define | EADC_INTSRC0_AD0SPIE7_Msk (0x1ul << EADC_INTSRC0_AD0SPIE7_Pos) |
| #define | EADC_INTSRC0_AD1SPIE0_Pos (8) |
| #define | EADC_INTSRC0_AD1SPIE0_Msk (0x1ul << EADC_INTSRC0_AD1SPIE0_Pos) |
| #define | EADC_INTSRC0_AD1SPIE1_Pos (9) |
| #define | EADC_INTSRC0_AD1SPIE1_Msk (0x1ul << EADC_INTSRC0_AD1SPIE1_Pos) |
| #define | EADC_INTSRC0_AD1SPIE2_Pos (10) |
| #define | EADC_INTSRC0_AD1SPIE2_Msk (0x1ul << EADC_INTSRC0_AD1SPIE2_Pos) |
| #define | EADC_INTSRC0_AD1SPIE3_Pos (11) |
| #define | EADC_INTSRC0_AD1SPIE3_Msk (0x1ul << EADC_INTSRC0_AD1SPIE3_Pos) |
| #define | EADC_INTSRC0_AD1SPIE4_Pos (12) |
| #define | EADC_INTSRC0_AD1SPIE4_Msk (0x1ul << EADC_INTSRC0_AD1SPIE4_Pos) |
| #define | EADC_INTSRC0_AD1SPIE5_Pos (13) |
| #define | EADC_INTSRC0_AD1SPIE5_Msk (0x1ul << EADC_INTSRC0_AD1SPIE5_Pos) |
| #define | EADC_INTSRC0_AD1SPIE6_Pos (14) |
| #define | EADC_INTSRC0_AD1SPIE6_Msk (0x1ul << EADC_INTSRC0_AD1SPIE6_Pos) |
| #define | EADC_INTSRC0_AD1SPIE7_Pos (15) |
| #define | EADC_INTSRC0_AD1SPIE7_Msk (0x1ul << EADC_INTSRC0_AD1SPIE7_Pos) |
| #define | EADC_INTSRC1_AD0SPIE0_Pos (0) |
| #define | EADC_INTSRC1_AD0SPIE0_Msk (0x1ul << EADC_INTSRC1_AD0SPIE0_Pos) |
| #define | EADC_INTSRC1_AD0SPIE1_Pos (1) |
| #define | EADC_INTSRC1_AD0SPIE1_Msk (0x1ul << EADC_INTSRC1_AD0SPIE1_Pos) |
| #define | EADC_INTSRC1_AD0SPIE2_Pos (2) |
| #define | EADC_INTSRC1_AD0SPIE2_Msk (0x1ul << EADC_INTSRC1_AD0SPIE2_Pos) |
| #define | EADC_INTSRC1_AD0SPIE3_Pos (3) |
| #define | EADC_INTSRC1_AD0SPIE3_Msk (0x1ul << EADC_INTSRC1_AD0SPIE3_Pos) |
| #define | EADC_INTSRC1_AD0SPIE4_Pos (4) |
| #define | EADC_INTSRC1_AD0SPIE4_Msk (0x1ul << EADC_INTSRC1_AD0SPIE4_Pos) |
| #define | EADC_INTSRC1_AD0SPIE5_Pos (5) |
| #define | EADC_INTSRC1_AD0SPIE5_Msk (0x1ul << EADC_INTSRC1_AD0SPIE5_Pos) |
| #define | EADC_INTSRC1_AD0SPIE6_Pos (6) |
| #define | EADC_INTSRC1_AD0SPIE6_Msk (0x1ul << EADC_INTSRC1_AD0SPIE6_Pos) |
| #define | EADC_INTSRC1_AD0SPIE7_Pos (7) |
| #define | EADC_INTSRC1_AD0SPIE7_Msk (0x1ul << EADC_INTSRC1_AD0SPIE7_Pos) |
| #define | EADC_INTSRC1_AD1SPIE0_Pos (8) |
| #define | EADC_INTSRC1_AD1SPIE0_Msk (0x1ul << EADC_INTSRC1_AD1SPIE0_Pos) |
| #define | EADC_INTSRC1_AD1SPIE1_Pos (9) |
| #define | EADC_INTSRC1_AD1SPIE1_Msk (0x1ul << EADC_INTSRC1_AD1SPIE1_Pos) |
| #define | EADC_INTSRC1_AD1SPIE2_Pos (10) |
| #define | EADC_INTSRC1_AD1SPIE2_Msk (0x1ul << EADC_INTSRC1_AD1SPIE2_Pos) |
| #define | EADC_INTSRC1_AD1SPIE3_Pos (11) |
| #define | EADC_INTSRC1_AD1SPIE3_Msk (0x1ul << EADC_INTSRC1_AD1SPIE3_Pos) |
| #define | EADC_INTSRC1_AD1SPIE4_Pos (12) |
| #define | EADC_INTSRC1_AD1SPIE4_Msk (0x1ul << EADC_INTSRC1_AD1SPIE4_Pos) |
| #define | EADC_INTSRC1_AD1SPIE5_Pos (13) |
| #define | EADC_INTSRC1_AD1SPIE5_Msk (0x1ul << EADC_INTSRC1_AD1SPIE5_Pos) |
| #define | EADC_INTSRC1_AD1SPIE6_Pos (14) |
| #define | EADC_INTSRC1_AD1SPIE6_Msk (0x1ul << EADC_INTSRC1_AD1SPIE6_Pos) |
| #define | EADC_INTSRC1_AD1SPIE7_Pos (15) |
| #define | EADC_INTSRC1_AD1SPIE7_Msk (0x1ul << EADC_INTSRC1_AD1SPIE7_Pos) |
| #define | EADC_INTSRC2_AD0SPIE0_Pos (0) |
| #define | EADC_INTSRC2_AD0SPIE0_Msk (0x1ul << EADC_INTSRC2_AD0SPIE0_Pos) |
| #define | EADC_INTSRC2_AD0SPIE1_Pos (1) |
| #define | EADC_INTSRC2_AD0SPIE1_Msk (0x1ul << EADC_INTSRC2_AD0SPIE1_Pos) |
| #define | EADC_INTSRC2_AD0SPIE2_Pos (2) |
| #define | EADC_INTSRC2_AD0SPIE2_Msk (0x1ul << EADC_INTSRC2_AD0SPIE2_Pos) |
| #define | EADC_INTSRC2_AD0SPIE3_Pos (3) |
| #define | EADC_INTSRC2_AD0SPIE3_Msk (0x1ul << EADC_INTSRC2_AD0SPIE3_Pos) |
| #define | EADC_INTSRC2_AD0SPIE4_Pos (4) |
| #define | EADC_INTSRC2_AD0SPIE4_Msk (0x1ul << EADC_INTSRC2_AD0SPIE4_Pos) |
| #define | EADC_INTSRC2_AD0SPIE5_Pos (5) |
| #define | EADC_INTSRC2_AD0SPIE5_Msk (0x1ul << EADC_INTSRC2_AD0SPIE5_Pos) |
| #define | EADC_INTSRC2_AD0SPIE6_Pos (6) |
| #define | EADC_INTSRC2_AD0SPIE6_Msk (0x1ul << EADC_INTSRC2_AD0SPIE6_Pos) |
| #define | EADC_INTSRC2_AD0SPIE7_Pos (7) |
| #define | EADC_INTSRC2_AD0SPIE7_Msk (0x1ul << EADC_INTSRC2_AD0SPIE7_Pos) |
| #define | EADC_INTSRC2_AD1SPIE0_Pos (8) |
| #define | EADC_INTSRC2_AD1SPIE0_Msk (0x1ul << EADC_INTSRC2_AD1SPIE0_Pos) |
| #define | EADC_INTSRC2_AD1SPIE1_Pos (9) |
| #define | EADC_INTSRC2_AD1SPIE1_Msk (0x1ul << EADC_INTSRC2_AD1SPIE1_Pos) |
| #define | EADC_INTSRC2_AD1SPIE2_Pos (10) |
| #define | EADC_INTSRC2_AD1SPIE2_Msk (0x1ul << EADC_INTSRC2_AD1SPIE2_Pos) |
| #define | EADC_INTSRC2_AD1SPIE3_Pos (11) |
| #define | EADC_INTSRC2_AD1SPIE3_Msk (0x1ul << EADC_INTSRC2_AD1SPIE3_Pos) |
| #define | EADC_INTSRC2_AD1SPIE4_Pos (12) |
| #define | EADC_INTSRC2_AD1SPIE4_Msk (0x1ul << EADC_INTSRC2_AD1SPIE4_Pos) |
| #define | EADC_INTSRC2_AD1SPIE5_Pos (13) |
| #define | EADC_INTSRC2_AD1SPIE5_Msk (0x1ul << EADC_INTSRC2_AD1SPIE5_Pos) |
| #define | EADC_INTSRC2_AD1SPIE6_Pos (14) |
| #define | EADC_INTSRC2_AD1SPIE6_Msk (0x1ul << EADC_INTSRC2_AD1SPIE6_Pos) |
| #define | EADC_INTSRC2_AD1SPIE7_Pos (15) |
| #define | EADC_INTSRC2_AD1SPIE7_Msk (0x1ul << EADC_INTSRC2_AD1SPIE7_Pos) |
| #define | EADC_INTSRC3_AD0SPIE0_Pos (0) |
| #define | EADC_INTSRC3_AD0SPIE0_Msk (0x1ul << EADC_INTSRC3_AD0SPIE0_Pos) |
| #define | EADC_INTSRC3_AD0SPIE1_Pos (1) |
| #define | EADC_INTSRC3_AD0SPIE1_Msk (0x1ul << EADC_INTSRC3_AD0SPIE1_Pos) |
| #define | EADC_INTSRC3_AD0SPIE2_Pos (2) |
| #define | EADC_INTSRC3_AD0SPIE2_Msk (0x1ul << EADC_INTSRC3_AD0SPIE2_Pos) |
| #define | EADC_INTSRC3_AD0SPIE3_Pos (3) |
| #define | EADC_INTSRC3_AD0SPIE3_Msk (0x1ul << EADC_INTSRC3_AD0SPIE3_Pos) |
| #define | EADC_INTSRC3_AD0SPIE4_Pos (4) |
| #define | EADC_INTSRC3_AD0SPIE4_Msk (0x1ul << EADC_INTSRC3_AD0SPIE4_Pos) |
| #define | EADC_INTSRC3_AD0SPIE5_Pos (5) |
| #define | EADC_INTSRC3_AD0SPIE5_Msk (0x1ul << EADC_INTSRC3_AD0SPIE5_Pos) |
| #define | EADC_INTSRC3_AD0SPIE6_Pos (6) |
| #define | EADC_INTSRC3_AD0SPIE6_Msk (0x1ul << EADC_INTSRC3_AD0SPIE6_Pos) |
| #define | EADC_INTSRC3_AD0SPIE7_Pos (7) |
| #define | EADC_INTSRC3_AD0SPIE7_Msk (0x1ul << EADC_INTSRC3_AD0SPIE7_Pos) |
| #define | EADC_INTSRC3_AD1SPIE0_Pos (8) |
| #define | EADC_INTSRC3_AD1SPIE0_Msk (0x1ul << EADC_INTSRC3_AD1SPIE0_Pos) |
| #define | EADC_INTSRC3_AD1SPIE1_Pos (9) |
| #define | EADC_INTSRC3_AD1SPIE1_Msk (0x1ul << EADC_INTSRC3_AD1SPIE1_Pos) |
| #define | EADC_INTSRC3_AD1SPIE2_Pos (10) |
| #define | EADC_INTSRC3_AD1SPIE2_Msk (0x1ul << EADC_INTSRC3_AD1SPIE2_Pos) |
| #define | EADC_INTSRC3_AD1SPIE3_Pos (11) |
| #define | EADC_INTSRC3_AD1SPIE3_Msk (0x1ul << EADC_INTSRC3_AD1SPIE3_Pos) |
| #define | EADC_INTSRC3_AD1SPIE4_Pos (12) |
| #define | EADC_INTSRC3_AD1SPIE4_Msk (0x1ul << EADC_INTSRC3_AD1SPIE4_Pos) |
| #define | EADC_INTSRC3_AD1SPIE5_Pos (13) |
| #define | EADC_INTSRC3_AD1SPIE5_Msk (0x1ul << EADC_INTSRC3_AD1SPIE5_Pos) |
| #define | EADC_INTSRC3_AD1SPIE6_Pos (14) |
| #define | EADC_INTSRC3_AD1SPIE6_Msk (0x1ul << EADC_INTSRC3_AD1SPIE6_Pos) |
| #define | EADC_INTSRC3_AD1SPIE7_Pos (15) |
| #define | EADC_INTSRC3_AD1SPIE7_Msk (0x1ul << EADC_INTSRC3_AD1SPIE7_Pos) |
| #define | EADC_AD0TRGEN0_EPWM00REN_Pos (0) |
| #define | EADC_AD0TRGEN0_EPWM00REN_Msk (0x1ul << EADC_AD0TRGEN0_EPWM00REN_Pos) |
| #define | EADC_AD0TRGEN0_EPWM00FEN_Pos (1) |
| #define | EADC_AD0TRGEN0_EPWM00FEN_Msk (0x1ul << EADC_AD0TRGEN0_EPWM00FEN_Pos) |
| #define | EADC_AD0TRGEN0_EPWM00PEN_Pos (2) |
| #define | EADC_AD0TRGEN0_EPWM00PEN_Msk (0x1ul << EADC_AD0TRGEN0_EPWM00PEN_Pos) |
| #define | EADC_AD0TRGEN0_EPWM00CEN_Pos (3) |
| #define | EADC_AD0TRGEN0_EPWM00CEN_Msk (0x1ul << EADC_AD0TRGEN0_EPWM00CEN_Pos) |
| #define | EADC_AD0TRGEN0_EPWM02REN_Pos (4) |
| #define | EADC_AD0TRGEN0_EPWM02REN_Msk (0x1ul << EADC_AD0TRGEN0_EPWM02REN_Pos) |
| #define | EADC_AD0TRGEN0_EPWM02FEN_Pos (5) |
| #define | EADC_AD0TRGEN0_EPWM02FEN_Msk (0x1ul << EADC_AD0TRGEN0_EPWM02FEN_Pos) |
| #define | EADC_AD0TRGEN0_EPWM02PEN_Pos (6) |
| #define | EADC_AD0TRGEN0_EPWM02PEN_Msk (0x1ul << EADC_AD0TRGEN0_EPWM02PEN_Pos) |
| #define | EADC_AD0TRGEN0_EPWM02CEN_Pos (7) |
| #define | EADC_AD0TRGEN0_EPWM02CEN_Msk (0x1ul << EADC_AD0TRGEN0_EPWM02CEN_Pos) |
| #define | EADC_AD0TRGEN0_EPWM04REN_Pos (8) |
| #define | EADC_AD0TRGEN0_EPWM04REN_Msk (0x1ul << EADC_AD0TRGEN0_EPWM04REN_Pos) |
| #define | EADC_AD0TRGEN0_EPWM04FEN_Pos (9) |
| #define | EADC_AD0TRGEN0_EPWM04FEN_Msk (0x1ul << EADC_AD0TRGEN0_EPWM04FEN_Pos) |
| #define | EADC_AD0TRGEN0_EPWM04PEN_Pos (10) |
| #define | EADC_AD0TRGEN0_EPWM04PEN_Msk (0x1ul << EADC_AD0TRGEN0_EPWM04PEN_Pos) |
| #define | EADC_AD0TRGEN0_EPWM04CEN_Pos (11) |
| #define | EADC_AD0TRGEN0_EPWM04CEN_Msk (0x1ul << EADC_AD0TRGEN0_EPWM04CEN_Pos) |
| #define | EADC_AD0TRGEN0_EPWM10REN_Pos (12) |
| #define | EADC_AD0TRGEN0_EPWM10REN_Msk (0x1ul << EADC_AD0TRGEN0_EPWM10REN_Pos) |
| #define | EADC_AD0TRGEN0_EPWM10FEN_Pos (13) |
| #define | EADC_AD0TRGEN0_EPWM10FEN_Msk (0x1ul << EADC_AD0TRGEN0_EPWM10FEN_Pos) |
| #define | EADC_AD0TRGEN0_EPWM10PEN_Pos (14) |
| #define | EADC_AD0TRGEN0_EPWM10PEN_Msk (0x1ul << EADC_AD0TRGEN0_EPWM10PEN_Pos) |
| #define | EADC_AD0TRGEN0_EPWM10CEN_Pos (15) |
| #define | EADC_AD0TRGEN0_EPWM10CEN_Msk (0x1ul << EADC_AD0TRGEN0_EPWM10CEN_Pos) |
| #define | EADC_AD0TRGEN0_EPWM12REN_Pos (16) |
| #define | EADC_AD0TRGEN0_EPWM12REN_Msk (0x1ul << EADC_AD0TRGEN0_EPWM12REN_Pos) |
| #define | EADC_AD0TRGEN0_EPWM120FEN_Pos (17) |
| #define | EADC_AD0TRGEN0_EPWM120FEN_Msk (0x1ul << EADC_AD0TRGEN0_EPWM120FEN_Pos) |
| #define | EADC_AD0TRGEN0_EPWM12PEN_Pos (18) |
| #define | EADC_AD0TRGEN0_EPWM12PEN_Msk (0x1ul << EADC_AD0TRGEN0_EPWM12PEN_Pos) |
| #define | EADC_AD0TRGEN0_EPWM12CEN_Pos (19) |
| #define | EADC_AD0TRGEN0_EPWM12CEN_Msk (0x1ul << EADC_AD0TRGEN0_EPWM12CEN_Pos) |
| #define | EADC_AD0TRGEN0_EPWM14REN_Pos (20) |
| #define | EADC_AD0TRGEN0_EPWM14REN_Msk (0x1ul << EADC_AD0TRGEN0_EPWM14REN_Pos) |
| #define | EADC_AD0TRGEN0_EPWM14FEN_Pos (21) |
| #define | EADC_AD0TRGEN0_EPWM14FEN_Msk (0x1ul << EADC_AD0TRGEN0_EPWM14FEN_Pos) |
| #define | EADC_AD0TRGEN0_EPWM14PEN_Pos (22) |
| #define | EADC_AD0TRGEN0_EPWM14PEN_Msk (0x1ul << EADC_AD0TRGEN0_EPWM14PEN_Pos) |
| #define | EADC_AD0TRGEN0_EPWM14CEN_Pos (23) |
| #define | EADC_AD0TRGEN0_EPWM14CEN_Msk (0x1ul << EADC_AD0TRGEN0_EPWM14CEN_Pos) |
| #define | EADC_AD0TRGEN0_PWM00REN_Pos (24) |
| #define | EADC_AD0TRGEN0_PWM00REN_Msk (0x1ul << EADC_AD0TRGEN0_PWM00REN_Pos) |
| #define | EADC_AD0TRGEN0_PWM00FEN_Pos (25) |
| #define | EADC_AD0TRGEN0_PWM00FEN_Msk (0x1ul << EADC_AD0TRGEN0_PWM00FEN_Pos) |
| #define | EADC_AD0TRGEN0_PWM00PEN_Pos (26) |
| #define | EADC_AD0TRGEN0_PWM00PEN_Msk (0x1ul << EADC_AD0TRGEN0_PWM00PEN_Pos) |
| #define | EADC_AD0TRGEN0_PWM00CEN_Pos (27) |
| #define | EADC_AD0TRGEN0_PWM00CEN_Msk (0x1ul << EADC_AD0TRGEN0_PWM00CEN_Pos) |
| #define | EADC_AD0TRGEN0_PWM01REN_Pos (28) |
| #define | EADC_AD0TRGEN0_PWM01REN_Msk (0x1ul << EADC_AD0TRGEN0_PWM01REN_Pos) |
| #define | EADC_AD0TRGEN0_PWM01FEN_Pos (29) |
| #define | EADC_AD0TRGEN0_PWM01FEN_Msk (0x1ul << EADC_AD0TRGEN0_PWM01FEN_Pos) |
| #define | EADC_AD0TRGEN0_PWM01PEN_Pos (30) |
| #define | EADC_AD0TRGEN0_PWM01PEN_Msk (0x1ul << EADC_AD0TRGEN0_PWM01PEN_Pos) |
| #define | EADC_AD0TRGEN0_PWM01CEN_Pos (31) |
| #define | EADC_AD0TRGEN0_PWM01CEN_Msk (0x1ul << EADC_AD0TRGEN0_PWM01CEN_Pos) |
| #define | EADC_AD0TRGEN1_EPWM00REN_Pos (0) |
| #define | EADC_AD0TRGEN1_EPWM00REN_Msk (0x1ul << EADC_AD0TRGEN1_EPWM00REN_Pos) |
| #define | EADC_AD0TRGEN1_EPWM00FEN_Pos (1) |
| #define | EADC_AD0TRGEN1_EPWM00FEN_Msk (0x1ul << EADC_AD0TRGEN1_EPWM00FEN_Pos) |
| #define | EADC_AD0TRGEN1_EPWM00PEN_Pos (2) |
| #define | EADC_AD0TRGEN1_EPWM00PEN_Msk (0x1ul << EADC_AD0TRGEN1_EPWM00PEN_Pos) |
| #define | EADC_AD0TRGEN1_EPWM00CEN_Pos (3) |
| #define | EADC_AD0TRGEN1_EPWM00CEN_Msk (0x1ul << EADC_AD0TRGEN1_EPWM00CEN_Pos) |
| #define | EADC_AD0TRGEN1_EPWM02REN_Pos (4) |
| #define | EADC_AD0TRGEN1_EPWM02REN_Msk (0x1ul << EADC_AD0TRGEN1_EPWM02REN_Pos) |
| #define | EADC_AD0TRGEN1_EPWM02FEN_Pos (5) |
| #define | EADC_AD0TRGEN1_EPWM02FEN_Msk (0x1ul << EADC_AD0TRGEN1_EPWM02FEN_Pos) |
| #define | EADC_AD0TRGEN1_EPWM02PEN_Pos (6) |
| #define | EADC_AD0TRGEN1_EPWM02PEN_Msk (0x1ul << EADC_AD0TRGEN1_EPWM02PEN_Pos) |
| #define | EADC_AD0TRGEN1_EPWM02CEN_Pos (7) |
| #define | EADC_AD0TRGEN1_EPWM02CEN_Msk (0x1ul << EADC_AD0TRGEN1_EPWM02CEN_Pos) |
| #define | EADC_AD0TRGEN1_EPWM04REN_Pos (8) |
| #define | EADC_AD0TRGEN1_EPWM04REN_Msk (0x1ul << EADC_AD0TRGEN1_EPWM04REN_Pos) |
| #define | EADC_AD0TRGEN1_EPWM04FEN_Pos (9) |
| #define | EADC_AD0TRGEN1_EPWM04FEN_Msk (0x1ul << EADC_AD0TRGEN1_EPWM04FEN_Pos) |
| #define | EADC_AD0TRGEN1_EPWM04PEN_Pos (10) |
| #define | EADC_AD0TRGEN1_EPWM04PEN_Msk (0x1ul << EADC_AD0TRGEN1_EPWM04PEN_Pos) |
| #define | EADC_AD0TRGEN1_EPWM04CEN_Pos (11) |
| #define | EADC_AD0TRGEN1_EPWM04CEN_Msk (0x1ul << EADC_AD0TRGEN1_EPWM04CEN_Pos) |
| #define | EADC_AD0TRGEN1_EPWM10REN_Pos (12) |
| #define | EADC_AD0TRGEN1_EPWM10REN_Msk (0x1ul << EADC_AD0TRGEN1_EPWM10REN_Pos) |
| #define | EADC_AD0TRGEN1_EPWM10FEN_Pos (13) |
| #define | EADC_AD0TRGEN1_EPWM10FEN_Msk (0x1ul << EADC_AD0TRGEN1_EPWM10FEN_Pos) |
| #define | EADC_AD0TRGEN1_EPWM10PEN_Pos (14) |
| #define | EADC_AD0TRGEN1_EPWM10PEN_Msk (0x1ul << EADC_AD0TRGEN1_EPWM10PEN_Pos) |
| #define | EADC_AD0TRGEN1_EPWM10CEN_Pos (15) |
| #define | EADC_AD0TRGEN1_EPWM10CEN_Msk (0x1ul << EADC_AD0TRGEN1_EPWM10CEN_Pos) |
| #define | EADC_AD0TRGEN1_EPWM12REN_Pos (16) |
| #define | EADC_AD0TRGEN1_EPWM12REN_Msk (0x1ul << EADC_AD0TRGEN1_EPWM12REN_Pos) |
| #define | EADC_AD0TRGEN1_EPWM120FEN_Pos (17) |
| #define | EADC_AD0TRGEN1_EPWM120FEN_Msk (0x1ul << EADC_AD0TRGEN1_EPWM120FEN_Pos) |
| #define | EADC_AD0TRGEN1_EPWM12PEN_Pos (18) |
| #define | EADC_AD0TRGEN1_EPWM12PEN_Msk (0x1ul << EADC_AD0TRGEN1_EPWM12PEN_Pos) |
| #define | EADC_AD0TRGEN1_EPWM12CEN_Pos (19) |
| #define | EADC_AD0TRGEN1_EPWM12CEN_Msk (0x1ul << EADC_AD0TRGEN1_EPWM12CEN_Pos) |
| #define | EADC_AD0TRGEN1_EPWM14REN_Pos (20) |
| #define | EADC_AD0TRGEN1_EPWM14REN_Msk (0x1ul << EADC_AD0TRGEN1_EPWM14REN_Pos) |
| #define | EADC_AD0TRGEN1_EPWM14FEN_Pos (21) |
| #define | EADC_AD0TRGEN1_EPWM14FEN_Msk (0x1ul << EADC_AD0TRGEN1_EPWM14FEN_Pos) |
| #define | EADC_AD0TRGEN1_EPWM14PEN_Pos (22) |
| #define | EADC_AD0TRGEN1_EPWM14PEN_Msk (0x1ul << EADC_AD0TRGEN1_EPWM14PEN_Pos) |
| #define | EADC_AD0TRGEN1_EPWM14CEN_Pos (23) |
| #define | EADC_AD0TRGEN1_EPWM14CEN_Msk (0x1ul << EADC_AD0TRGEN1_EPWM14CEN_Pos) |
| #define | EADC_AD0TRGEN1_PWM00REN_Pos (24) |
| #define | EADC_AD0TRGEN1_PWM00REN_Msk (0x1ul << EADC_AD0TRGEN1_PWM00REN_Pos) |
| #define | EADC_AD0TRGEN1_PWM00FEN_Pos (25) |
| #define | EADC_AD0TRGEN1_PWM00FEN_Msk (0x1ul << EADC_AD0TRGEN1_PWM00FEN_Pos) |
| #define | EADC_AD0TRGEN1_PWM00PEN_Pos (26) |
| #define | EADC_AD0TRGEN1_PWM00PEN_Msk (0x1ul << EADC_AD0TRGEN1_PWM00PEN_Pos) |
| #define | EADC_AD0TRGEN1_PWM00CEN_Pos (27) |
| #define | EADC_AD0TRGEN1_PWM00CEN_Msk (0x1ul << EADC_AD0TRGEN1_PWM00CEN_Pos) |
| #define | EADC_AD0TRGEN1_PWM01REN_Pos (28) |
| #define | EADC_AD0TRGEN1_PWM01REN_Msk (0x1ul << EADC_AD0TRGEN1_PWM01REN_Pos) |
| #define | EADC_AD0TRGEN1_PWM01FEN_Pos (29) |
| #define | EADC_AD0TRGEN1_PWM01FEN_Msk (0x1ul << EADC_AD0TRGEN1_PWM01FEN_Pos) |
| #define | EADC_AD0TRGEN1_PWM01PEN_Pos (30) |
| #define | EADC_AD0TRGEN1_PWM01PEN_Msk (0x1ul << EADC_AD0TRGEN1_PWM01PEN_Pos) |
| #define | EADC_AD0TRGEN1_PWM01CEN_Pos (31) |
| #define | EADC_AD0TRGEN1_PWM01CEN_Msk (0x1ul << EADC_AD0TRGEN1_PWM01CEN_Pos) |
| #define | EADC_AD0TRGEN2_EPWM00REN_Pos (0) |
| #define | EADC_AD0TRGEN2_EPWM00REN_Msk (0x1ul << EADC_AD0TRGEN2_EPWM00REN_Pos) |
| #define | EADC_AD0TRGEN2_EPWM00FEN_Pos (1) |
| #define | EADC_AD0TRGEN2_EPWM00FEN_Msk (0x1ul << EADC_AD0TRGEN2_EPWM00FEN_Pos) |
| #define | EADC_AD0TRGEN2_EPWM00PEN_Pos (2) |
| #define | EADC_AD0TRGEN2_EPWM00PEN_Msk (0x1ul << EADC_AD0TRGEN2_EPWM00PEN_Pos) |
| #define | EADC_AD0TRGEN2_EPWM00CEN_Pos (3) |
| #define | EADC_AD0TRGEN2_EPWM00CEN_Msk (0x1ul << EADC_AD0TRGEN2_EPWM00CEN_Pos) |
| #define | EADC_AD0TRGEN2_EPWM02REN_Pos (4) |
| #define | EADC_AD0TRGEN2_EPWM02REN_Msk (0x1ul << EADC_AD0TRGEN2_EPWM02REN_Pos) |
| #define | EADC_AD0TRGEN2_EPWM02FEN_Pos (5) |
| #define | EADC_AD0TRGEN2_EPWM02FEN_Msk (0x1ul << EADC_AD0TRGEN2_EPWM02FEN_Pos) |
| #define | EADC_AD0TRGEN2_EPWM02PEN_Pos (6) |
| #define | EADC_AD0TRGEN2_EPWM02PEN_Msk (0x1ul << EADC_AD0TRGEN2_EPWM02PEN_Pos) |
| #define | EADC_AD0TRGEN2_EPWM02CEN_Pos (7) |
| #define | EADC_AD0TRGEN2_EPWM02CEN_Msk (0x1ul << EADC_AD0TRGEN2_EPWM02CEN_Pos) |
| #define | EADC_AD0TRGEN2_EPWM04REN_Pos (8) |
| #define | EADC_AD0TRGEN2_EPWM04REN_Msk (0x1ul << EADC_AD0TRGEN2_EPWM04REN_Pos) |
| #define | EADC_AD0TRGEN2_EPWM04FEN_Pos (9) |
| #define | EADC_AD0TRGEN2_EPWM04FEN_Msk (0x1ul << EADC_AD0TRGEN2_EPWM04FEN_Pos) |
| #define | EADC_AD0TRGEN2_EPWM04PEN_Pos (10) |
| #define | EADC_AD0TRGEN2_EPWM04PEN_Msk (0x1ul << EADC_AD0TRGEN2_EPWM04PEN_Pos) |
| #define | EADC_AD0TRGEN2_EPWM04CEN_Pos (11) |
| #define | EADC_AD0TRGEN2_EPWM04CEN_Msk (0x1ul << EADC_AD0TRGEN2_EPWM04CEN_Pos) |
| #define | EADC_AD0TRGEN2_EPWM10REN_Pos (12) |
| #define | EADC_AD0TRGEN2_EPWM10REN_Msk (0x1ul << EADC_AD0TRGEN2_EPWM10REN_Pos) |
| #define | EADC_AD0TRGEN2_EPWM10FEN_Pos (13) |
| #define | EADC_AD0TRGEN2_EPWM10FEN_Msk (0x1ul << EADC_AD0TRGEN2_EPWM10FEN_Pos) |
| #define | EADC_AD0TRGEN2_EPWM10PEN_Pos (14) |
| #define | EADC_AD0TRGEN2_EPWM10PEN_Msk (0x1ul << EADC_AD0TRGEN2_EPWM10PEN_Pos) |
| #define | EADC_AD0TRGEN2_EPWM10CEN_Pos (15) |
| #define | EADC_AD0TRGEN2_EPWM10CEN_Msk (0x1ul << EADC_AD0TRGEN2_EPWM10CEN_Pos) |
| #define | EADC_AD0TRGEN2_EPWM12REN_Pos (16) |
| #define | EADC_AD0TRGEN2_EPWM12REN_Msk (0x1ul << EADC_AD0TRGEN2_EPWM12REN_Pos) |
| #define | EADC_AD0TRGEN2_EPWM120FEN_Pos (17) |
| #define | EADC_AD0TRGEN2_EPWM120FEN_Msk (0x1ul << EADC_AD0TRGEN2_EPWM120FEN_Pos) |
| #define | EADC_AD0TRGEN2_EPWM12PEN_Pos (18) |
| #define | EADC_AD0TRGEN2_EPWM12PEN_Msk (0x1ul << EADC_AD0TRGEN2_EPWM12PEN_Pos) |
| #define | EADC_AD0TRGEN2_EPWM12CEN_Pos (19) |
| #define | EADC_AD0TRGEN2_EPWM12CEN_Msk (0x1ul << EADC_AD0TRGEN2_EPWM12CEN_Pos) |
| #define | EADC_AD0TRGEN2_EPWM14REN_Pos (20) |
| #define | EADC_AD0TRGEN2_EPWM14REN_Msk (0x1ul << EADC_AD0TRGEN2_EPWM14REN_Pos) |
| #define | EADC_AD0TRGEN2_EPWM14FEN_Pos (21) |
| #define | EADC_AD0TRGEN2_EPWM14FEN_Msk (0x1ul << EADC_AD0TRGEN2_EPWM14FEN_Pos) |
| #define | EADC_AD0TRGEN2_EPWM14PEN_Pos (22) |
| #define | EADC_AD0TRGEN2_EPWM14PEN_Msk (0x1ul << EADC_AD0TRGEN2_EPWM14PEN_Pos) |
| #define | EADC_AD0TRGEN2_EPWM14CEN_Pos (23) |
| #define | EADC_AD0TRGEN2_EPWM14CEN_Msk (0x1ul << EADC_AD0TRGEN2_EPWM14CEN_Pos) |
| #define | EADC_AD0TRGEN2_PWM00REN_Pos (24) |
| #define | EADC_AD0TRGEN2_PWM00REN_Msk (0x1ul << EADC_AD0TRGEN2_PWM00REN_Pos) |
| #define | EADC_AD0TRGEN2_PWM00FEN_Pos (25) |
| #define | EADC_AD0TRGEN2_PWM00FEN_Msk (0x1ul << EADC_AD0TRGEN2_PWM00FEN_Pos) |
| #define | EADC_AD0TRGEN2_PWM00PEN_Pos (26) |
| #define | EADC_AD0TRGEN2_PWM00PEN_Msk (0x1ul << EADC_AD0TRGEN2_PWM00PEN_Pos) |
| #define | EADC_AD0TRGEN2_PWM00CEN_Pos (27) |
| #define | EADC_AD0TRGEN2_PWM00CEN_Msk (0x1ul << EADC_AD0TRGEN2_PWM00CEN_Pos) |
| #define | EADC_AD0TRGEN2_PWM01REN_Pos (28) |
| #define | EADC_AD0TRGEN2_PWM01REN_Msk (0x1ul << EADC_AD0TRGEN2_PWM01REN_Pos) |
| #define | EADC_AD0TRGEN2_PWM01FEN_Pos (29) |
| #define | EADC_AD0TRGEN2_PWM01FEN_Msk (0x1ul << EADC_AD0TRGEN2_PWM01FEN_Pos) |
| #define | EADC_AD0TRGEN2_PWM01PEN_Pos (30) |
| #define | EADC_AD0TRGEN2_PWM01PEN_Msk (0x1ul << EADC_AD0TRGEN2_PWM01PEN_Pos) |
| #define | EADC_AD0TRGEN2_PWM01CEN_Pos (31) |
| #define | EADC_AD0TRGEN2_PWM01CEN_Msk (0x1ul << EADC_AD0TRGEN2_PWM01CEN_Pos) |
| #define | EADC_AD0TRGEN3_EPWM00REN_Pos (0) |
| #define | EADC_AD0TRGEN3_EPWM00REN_Msk (0x1ul << EADC_AD0TRGEN3_EPWM00REN_Pos) |
| #define | EADC_AD0TRGEN3_EPWM00FEN_Pos (1) |
| #define | EADC_AD0TRGEN3_EPWM00FEN_Msk (0x1ul << EADC_AD0TRGEN3_EPWM00FEN_Pos) |
| #define | EADC_AD0TRGEN3_EPWM00PEN_Pos (2) |
| #define | EADC_AD0TRGEN3_EPWM00PEN_Msk (0x1ul << EADC_AD0TRGEN3_EPWM00PEN_Pos) |
| #define | EADC_AD0TRGEN3_EPWM00CEN_Pos (3) |
| #define | EADC_AD0TRGEN3_EPWM00CEN_Msk (0x1ul << EADC_AD0TRGEN3_EPWM00CEN_Pos) |
| #define | EADC_AD0TRGEN3_EPWM02REN_Pos (4) |
| #define | EADC_AD0TRGEN3_EPWM02REN_Msk (0x1ul << EADC_AD0TRGEN3_EPWM02REN_Pos) |
| #define | EADC_AD0TRGEN3_EPWM02FEN_Pos (5) |
| #define | EADC_AD0TRGEN3_EPWM02FEN_Msk (0x1ul << EADC_AD0TRGEN3_EPWM02FEN_Pos) |
| #define | EADC_AD0TRGEN3_EPWM02PEN_Pos (6) |
| #define | EADC_AD0TRGEN3_EPWM02PEN_Msk (0x1ul << EADC_AD0TRGEN3_EPWM02PEN_Pos) |
| #define | EADC_AD0TRGEN3_EPWM02CEN_Pos (7) |
| #define | EADC_AD0TRGEN3_EPWM02CEN_Msk (0x1ul << EADC_AD0TRGEN3_EPWM02CEN_Pos) |
| #define | EADC_AD0TRGEN3_EPWM04REN_Pos (8) |
| #define | EADC_AD0TRGEN3_EPWM04REN_Msk (0x1ul << EADC_AD0TRGEN3_EPWM04REN_Pos) |
| #define | EADC_AD0TRGEN3_EPWM04FEN_Pos (9) |
| #define | EADC_AD0TRGEN3_EPWM04FEN_Msk (0x1ul << EADC_AD0TRGEN3_EPWM04FEN_Pos) |
| #define | EADC_AD0TRGEN3_EPWM04PEN_Pos (10) |
| #define | EADC_AD0TRGEN3_EPWM04PEN_Msk (0x1ul << EADC_AD0TRGEN3_EPWM04PEN_Pos) |
| #define | EADC_AD0TRGEN3_EPWM04CEN_Pos (11) |
| #define | EADC_AD0TRGEN3_EPWM04CEN_Msk (0x1ul << EADC_AD0TRGEN3_EPWM04CEN_Pos) |
| #define | EADC_AD0TRGEN3_EPWM10REN_Pos (12) |
| #define | EADC_AD0TRGEN3_EPWM10REN_Msk (0x1ul << EADC_AD0TRGEN3_EPWM10REN_Pos) |
| #define | EADC_AD0TRGEN3_EPWM10FEN_Pos (13) |
| #define | EADC_AD0TRGEN3_EPWM10FEN_Msk (0x1ul << EADC_AD0TRGEN3_EPWM10FEN_Pos) |
| #define | EADC_AD0TRGEN3_EPWM10PEN_Pos (14) |
| #define | EADC_AD0TRGEN3_EPWM10PEN_Msk (0x1ul << EADC_AD0TRGEN3_EPWM10PEN_Pos) |
| #define | EADC_AD0TRGEN3_EPWM10CEN_Pos (15) |
| #define | EADC_AD0TRGEN3_EPWM10CEN_Msk (0x1ul << EADC_AD0TRGEN3_EPWM10CEN_Pos) |
| #define | EADC_AD0TRGEN3_EPWM12REN_Pos (16) |
| #define | EADC_AD0TRGEN3_EPWM12REN_Msk (0x1ul << EADC_AD0TRGEN3_EPWM12REN_Pos) |
| #define | EADC_AD0TRGEN3_EPWM120FEN_Pos (17) |
| #define | EADC_AD0TRGEN3_EPWM120FEN_Msk (0x1ul << EADC_AD0TRGEN3_EPWM120FEN_Pos) |
| #define | EADC_AD0TRGEN3_EPWM12PEN_Pos (18) |
| #define | EADC_AD0TRGEN3_EPWM12PEN_Msk (0x1ul << EADC_AD0TRGEN3_EPWM12PEN_Pos) |
| #define | EADC_AD0TRGEN3_EPWM12CEN_Pos (19) |
| #define | EADC_AD0TRGEN3_EPWM12CEN_Msk (0x1ul << EADC_AD0TRGEN3_EPWM12CEN_Pos) |
| #define | EADC_AD0TRGEN3_EPWM14REN_Pos (20) |
| #define | EADC_AD0TRGEN3_EPWM14REN_Msk (0x1ul << EADC_AD0TRGEN3_EPWM14REN_Pos) |
| #define | EADC_AD0TRGEN3_EPWM14FEN_Pos (21) |
| #define | EADC_AD0TRGEN3_EPWM14FEN_Msk (0x1ul << EADC_AD0TRGEN3_EPWM14FEN_Pos) |
| #define | EADC_AD0TRGEN3_EPWM14PEN_Pos (22) |
| #define | EADC_AD0TRGEN3_EPWM14PEN_Msk (0x1ul << EADC_AD0TRGEN3_EPWM14PEN_Pos) |
| #define | EADC_AD0TRGEN3_EPWM14CEN_Pos (23) |
| #define | EADC_AD0TRGEN3_EPWM14CEN_Msk (0x1ul << EADC_AD0TRGEN3_EPWM14CEN_Pos) |
| #define | EADC_AD0TRGEN3_PWM00REN_Pos (24) |
| #define | EADC_AD0TRGEN3_PWM00REN_Msk (0x1ul << EADC_AD0TRGEN3_PWM00REN_Pos) |
| #define | EADC_AD0TRGEN3_PWM00FEN_Pos (25) |
| #define | EADC_AD0TRGEN3_PWM00FEN_Msk (0x1ul << EADC_AD0TRGEN3_PWM00FEN_Pos) |
| #define | EADC_AD0TRGEN3_PWM00PEN_Pos (26) |
| #define | EADC_AD0TRGEN3_PWM00PEN_Msk (0x1ul << EADC_AD0TRGEN3_PWM00PEN_Pos) |
| #define | EADC_AD0TRGEN3_PWM00CEN_Pos (27) |
| #define | EADC_AD0TRGEN3_PWM00CEN_Msk (0x1ul << EADC_AD0TRGEN3_PWM00CEN_Pos) |
| #define | EADC_AD0TRGEN3_PWM01REN_Pos (28) |
| #define | EADC_AD0TRGEN3_PWM01REN_Msk (0x1ul << EADC_AD0TRGEN3_PWM01REN_Pos) |
| #define | EADC_AD0TRGEN3_PWM01FEN_Pos (29) |
| #define | EADC_AD0TRGEN3_PWM01FEN_Msk (0x1ul << EADC_AD0TRGEN3_PWM01FEN_Pos) |
| #define | EADC_AD0TRGEN3_PWM01PEN_Pos (30) |
| #define | EADC_AD0TRGEN3_PWM01PEN_Msk (0x1ul << EADC_AD0TRGEN3_PWM01PEN_Pos) |
| #define | EADC_AD0TRGEN3_PWM01CEN_Pos (31) |
| #define | EADC_AD0TRGEN3_PWM01CEN_Msk (0x1ul << EADC_AD0TRGEN3_PWM01CEN_Pos) |
| #define | EADC_AD1TRGEN0_EPWM00REN_Pos (0) |
| #define | EADC_AD1TRGEN0_EPWM00REN_Msk (0x1ul << EADC_AD1TRGEN0_EPWM00REN_Pos) |
| #define | EADC_AD1TRGEN0_EPWM00FEN_Pos (1) |
| #define | EADC_AD1TRGEN0_EPWM00FEN_Msk (0x1ul << EADC_AD1TRGEN0_EPWM00FEN_Pos) |
| #define | EADC_AD1TRGEN0_EPWM00PEN_Pos (2) |
| #define | EADC_AD1TRGEN0_EPWM00PEN_Msk (0x1ul << EADC_AD1TRGEN0_EPWM00PEN_Pos) |
| #define | EADC_AD1TRGEN0_EPWM00CEN_Pos (3) |
| #define | EADC_AD1TRGEN0_EPWM00CEN_Msk (0x1ul << EADC_AD1TRGEN0_EPWM00CEN_Pos) |
| #define | EADC_AD1TRGEN0_EPWM02REN_Pos (4) |
| #define | EADC_AD1TRGEN0_EPWM02REN_Msk (0x1ul << EADC_AD1TRGEN0_EPWM02REN_Pos) |
| #define | EADC_AD1TRGEN0_EPWM02FEN_Pos (5) |
| #define | EADC_AD1TRGEN0_EPWM02FEN_Msk (0x1ul << EADC_AD1TRGEN0_EPWM02FEN_Pos) |
| #define | EADC_AD1TRGEN0_EPWM02PEN_Pos (6) |
| #define | EADC_AD1TRGEN0_EPWM02PEN_Msk (0x1ul << EADC_AD1TRGEN0_EPWM02PEN_Pos) |
| #define | EADC_AD1TRGEN0_EPWM02CEN_Pos (7) |
| #define | EADC_AD1TRGEN0_EPWM02CEN_Msk (0x1ul << EADC_AD1TRGEN0_EPWM02CEN_Pos) |
| #define | EADC_AD1TRGEN0_EPWM04REN_Pos (8) |
| #define | EADC_AD1TRGEN0_EPWM04REN_Msk (0x1ul << EADC_AD1TRGEN0_EPWM04REN_Pos) |
| #define | EADC_AD1TRGEN0_EPWM04FEN_Pos (9) |
| #define | EADC_AD1TRGEN0_EPWM04FEN_Msk (0x1ul << EADC_AD1TRGEN0_EPWM04FEN_Pos) |
| #define | EADC_AD1TRGEN0_EPWM04PEN_Pos (10) |
| #define | EADC_AD1TRGEN0_EPWM04PEN_Msk (0x1ul << EADC_AD1TRGEN0_EPWM04PEN_Pos) |
| #define | EADC_AD1TRGEN0_EPWM04CEN_Pos (11) |
| #define | EADC_AD1TRGEN0_EPWM04CEN_Msk (0x1ul << EADC_AD1TRGEN0_EPWM04CEN_Pos) |
| #define | EADC_AD1TRGEN0_EPWM10REN_Pos (12) |
| #define | EADC_AD1TRGEN0_EPWM10REN_Msk (0x1ul << EADC_AD1TRGEN0_EPWM10REN_Pos) |
| #define | EADC_AD1TRGEN0_EPWM10FEN_Pos (13) |
| #define | EADC_AD1TRGEN0_EPWM10FEN_Msk (0x1ul << EADC_AD1TRGEN0_EPWM10FEN_Pos) |
| #define | EADC_AD1TRGEN0_EPWM10PEN_Pos (14) |
| #define | EADC_AD1TRGEN0_EPWM10PEN_Msk (0x1ul << EADC_AD1TRGEN0_EPWM10PEN_Pos) |
| #define | EADC_AD1TRGEN0_EPWM10CEN_Pos (15) |
| #define | EADC_AD1TRGEN0_EPWM10CEN_Msk (0x1ul << EADC_AD1TRGEN0_EPWM10CEN_Pos) |
| #define | EADC_AD1TRGEN0_EPWM12REN_Pos (16) |
| #define | EADC_AD1TRGEN0_EPWM12REN_Msk (0x1ul << EADC_AD1TRGEN0_EPWM12REN_Pos) |
| #define | EADC_AD1TRGEN0_EPWM120FEN_Pos (17) |
| #define | EADC_AD1TRGEN0_EPWM120FEN_Msk (0x1ul << EADC_AD1TRGEN0_EPWM120FEN_Pos) |
| #define | EADC_AD1TRGEN0_EPWM12PEN_Pos (18) |
| #define | EADC_AD1TRGEN0_EPWM12PEN_Msk (0x1ul << EADC_AD1TRGEN0_EPWM12PEN_Pos) |
| #define | EADC_AD1TRGEN0_EPWM12CEN_Pos (19) |
| #define | EADC_AD1TRGEN0_EPWM12CEN_Msk (0x1ul << EADC_AD1TRGEN0_EPWM12CEN_Pos) |
| #define | EADC_AD1TRGEN0_EPWM14REN_Pos (20) |
| #define | EADC_AD1TRGEN0_EPWM14REN_Msk (0x1ul << EADC_AD1TRGEN0_EPWM14REN_Pos) |
| #define | EADC_AD1TRGEN0_EPWM14FEN_Pos (21) |
| #define | EADC_AD1TRGEN0_EPWM14FEN_Msk (0x1ul << EADC_AD1TRGEN0_EPWM14FEN_Pos) |
| #define | EADC_AD1TRGEN0_EPWM14PEN_Pos (22) |
| #define | EADC_AD1TRGEN0_EPWM14PEN_Msk (0x1ul << EADC_AD1TRGEN0_EPWM14PEN_Pos) |
| #define | EADC_AD1TRGEN0_EPWM14CEN_Pos (23) |
| #define | EADC_AD1TRGEN0_EPWM14CEN_Msk (0x1ul << EADC_AD1TRGEN0_EPWM14CEN_Pos) |
| #define | EADC_AD1TRGEN0_PWM00REN_Pos (24) |
| #define | EADC_AD1TRGEN0_PWM00REN_Msk (0x1ul << EADC_AD1TRGEN0_PWM00REN_Pos) |
| #define | EADC_AD1TRGEN0_PWM00FEN_Pos (25) |
| #define | EADC_AD1TRGEN0_PWM00FEN_Msk (0x1ul << EADC_AD1TRGEN0_PWM00FEN_Pos) |
| #define | EADC_AD1TRGEN0_PWM00PEN_Pos (26) |
| #define | EADC_AD1TRGEN0_PWM00PEN_Msk (0x1ul << EADC_AD1TRGEN0_PWM00PEN_Pos) |
| #define | EADC_AD1TRGEN0_PWM00CEN_Pos (27) |
| #define | EADC_AD1TRGEN0_PWM00CEN_Msk (0x1ul << EADC_AD1TRGEN0_PWM00CEN_Pos) |
| #define | EADC_AD1TRGEN0_PWM01REN_Pos (28) |
| #define | EADC_AD1TRGEN0_PWM01REN_Msk (0x1ul << EADC_AD1TRGEN0_PWM01REN_Pos) |
| #define | EADC_AD1TRGEN0_PWM01FEN_Pos (29) |
| #define | EADC_AD1TRGEN0_PWM01FEN_Msk (0x1ul << EADC_AD1TRGEN0_PWM01FEN_Pos) |
| #define | EADC_AD1TRGEN0_PWM01PEN_Pos (30) |
| #define | EADC_AD1TRGEN0_PWM01PEN_Msk (0x1ul << EADC_AD1TRGEN0_PWM01PEN_Pos) |
| #define | EADC_AD1TRGEN0_PWM01CEN_Pos (31) |
| #define | EADC_AD1TRGEN0_PWM01CEN_Msk (0x1ul << EADC_AD1TRGEN0_PWM01CEN_Pos) |
| #define | EADC_AD1TRGEN1_EPWM00REN_Pos (0) |
| #define | EADC_AD1TRGEN1_EPWM00REN_Msk (0x1ul << EADC_AD1TRGEN1_EPWM00REN_Pos) |
| #define | EADC_AD1TRGEN1_EPWM00FEN_Pos (1) |
| #define | EADC_AD1TRGEN1_EPWM00FEN_Msk (0x1ul << EADC_AD1TRGEN1_EPWM00FEN_Pos) |
| #define | EADC_AD1TRGEN1_EPWM00PEN_Pos (2) |
| #define | EADC_AD1TRGEN1_EPWM00PEN_Msk (0x1ul << EADC_AD1TRGEN1_EPWM00PEN_Pos) |
| #define | EADC_AD1TRGEN1_EPWM00CEN_Pos (3) |
| #define | EADC_AD1TRGEN1_EPWM00CEN_Msk (0x1ul << EADC_AD1TRGEN1_EPWM00CEN_Pos) |
| #define | EADC_AD1TRGEN1_EPWM02REN_Pos (4) |
| #define | EADC_AD1TRGEN1_EPWM02REN_Msk (0x1ul << EADC_AD1TRGEN1_EPWM02REN_Pos) |
| #define | EADC_AD1TRGEN1_EPWM02FEN_Pos (5) |
| #define | EADC_AD1TRGEN1_EPWM02FEN_Msk (0x1ul << EADC_AD1TRGEN1_EPWM02FEN_Pos) |
| #define | EADC_AD1TRGEN1_EPWM02PEN_Pos (6) |
| #define | EADC_AD1TRGEN1_EPWM02PEN_Msk (0x1ul << EADC_AD1TRGEN1_EPWM02PEN_Pos) |
| #define | EADC_AD1TRGEN1_EPWM02CEN_Pos (7) |
| #define | EADC_AD1TRGEN1_EPWM02CEN_Msk (0x1ul << EADC_AD1TRGEN1_EPWM02CEN_Pos) |
| #define | EADC_AD1TRGEN1_EPWM04REN_Pos (8) |
| #define | EADC_AD1TRGEN1_EPWM04REN_Msk (0x1ul << EADC_AD1TRGEN1_EPWM04REN_Pos) |
| #define | EADC_AD1TRGEN1_EPWM04FEN_Pos (9) |
| #define | EADC_AD1TRGEN1_EPWM04FEN_Msk (0x1ul << EADC_AD1TRGEN1_EPWM04FEN_Pos) |
| #define | EADC_AD1TRGEN1_EPWM04PEN_Pos (10) |
| #define | EADC_AD1TRGEN1_EPWM04PEN_Msk (0x1ul << EADC_AD1TRGEN1_EPWM04PEN_Pos) |
| #define | EADC_AD1TRGEN1_EPWM04CEN_Pos (11) |
| #define | EADC_AD1TRGEN1_EPWM04CEN_Msk (0x1ul << EADC_AD1TRGEN1_EPWM04CEN_Pos) |
| #define | EADC_AD1TRGEN1_EPWM10REN_Pos (12) |
| #define | EADC_AD1TRGEN1_EPWM10REN_Msk (0x1ul << EADC_AD1TRGEN1_EPWM10REN_Pos) |
| #define | EADC_AD1TRGEN1_EPWM10FEN_Pos (13) |
| #define | EADC_AD1TRGEN1_EPWM10FEN_Msk (0x1ul << EADC_AD1TRGEN1_EPWM10FEN_Pos) |
| #define | EADC_AD1TRGEN1_EPWM10PEN_Pos (14) |
| #define | EADC_AD1TRGEN1_EPWM10PEN_Msk (0x1ul << EADC_AD1TRGEN1_EPWM10PEN_Pos) |
| #define | EADC_AD1TRGEN1_EPWM10CEN_Pos (15) |
| #define | EADC_AD1TRGEN1_EPWM10CEN_Msk (0x1ul << EADC_AD1TRGEN1_EPWM10CEN_Pos) |
| #define | EADC_AD1TRGEN1_EPWM12REN_Pos (16) |
| #define | EADC_AD1TRGEN1_EPWM12REN_Msk (0x1ul << EADC_AD1TRGEN1_EPWM12REN_Pos) |
| #define | EADC_AD1TRGEN1_EPWM120FEN_Pos (17) |
| #define | EADC_AD1TRGEN1_EPWM120FEN_Msk (0x1ul << EADC_AD1TRGEN1_EPWM120FEN_Pos) |
| #define | EADC_AD1TRGEN1_EPWM12PEN_Pos (18) |
| #define | EADC_AD1TRGEN1_EPWM12PEN_Msk (0x1ul << EADC_AD1TRGEN1_EPWM12PEN_Pos) |
| #define | EADC_AD1TRGEN1_EPWM12CEN_Pos (19) |
| #define | EADC_AD1TRGEN1_EPWM12CEN_Msk (0x1ul << EADC_AD1TRGEN1_EPWM12CEN_Pos) |
| #define | EADC_AD1TRGEN1_EPWM14REN_Pos (20) |
| #define | EADC_AD1TRGEN1_EPWM14REN_Msk (0x1ul << EADC_AD1TRGEN1_EPWM14REN_Pos) |
| #define | EADC_AD1TRGEN1_EPWM14FEN_Pos (21) |
| #define | EADC_AD1TRGEN1_EPWM14FEN_Msk (0x1ul << EADC_AD1TRGEN1_EPWM14FEN_Pos) |
| #define | EADC_AD1TRGEN1_EPWM14PEN_Pos (22) |
| #define | EADC_AD1TRGEN1_EPWM14PEN_Msk (0x1ul << EADC_AD1TRGEN1_EPWM14PEN_Pos) |
| #define | EADC_AD1TRGEN1_EPWM14CEN_Pos (23) |
| #define | EADC_AD1TRGEN1_EPWM14CEN_Msk (0x1ul << EADC_AD1TRGEN1_EPWM14CEN_Pos) |
| #define | EADC_AD1TRGEN1_PWM00REN_Pos (24) |
| #define | EADC_AD1TRGEN1_PWM00REN_Msk (0x1ul << EADC_AD1TRGEN1_PWM00REN_Pos) |
| #define | EADC_AD1TRGEN1_PWM00FEN_Pos (25) |
| #define | EADC_AD1TRGEN1_PWM00FEN_Msk (0x1ul << EADC_AD1TRGEN1_PWM00FEN_Pos) |
| #define | EADC_AD1TRGEN1_PWM00PEN_Pos (26) |
| #define | EADC_AD1TRGEN1_PWM00PEN_Msk (0x1ul << EADC_AD1TRGEN1_PWM00PEN_Pos) |
| #define | EADC_AD1TRGEN1_PWM00CEN_Pos (27) |
| #define | EADC_AD1TRGEN1_PWM00CEN_Msk (0x1ul << EADC_AD1TRGEN1_PWM00CEN_Pos) |
| #define | EADC_AD1TRGEN1_PWM01REN_Pos (28) |
| #define | EADC_AD1TRGEN1_PWM01REN_Msk (0x1ul << EADC_AD1TRGEN1_PWM01REN_Pos) |
| #define | EADC_AD1TRGEN1_PWM01FEN_Pos (29) |
| #define | EADC_AD1TRGEN1_PWM01FEN_Msk (0x1ul << EADC_AD1TRGEN1_PWM01FEN_Pos) |
| #define | EADC_AD1TRGEN1_PWM01PEN_Pos (30) |
| #define | EADC_AD1TRGEN1_PWM01PEN_Msk (0x1ul << EADC_AD1TRGEN1_PWM01PEN_Pos) |
| #define | EADC_AD1TRGEN1_PWM01CEN_Pos (31) |
| #define | EADC_AD1TRGEN1_PWM01CEN_Msk (0x1ul << EADC_AD1TRGEN1_PWM01CEN_Pos) |
| #define | EADC_AD1TRGEN2_EPWM00REN_Pos (0) |
| #define | EADC_AD1TRGEN2_EPWM00REN_Msk (0x1ul << EADC_AD1TRGEN2_EPWM00REN_Pos) |
| #define | EADC_AD1TRGEN2_EPWM00FEN_Pos (1) |
| #define | EADC_AD1TRGEN2_EPWM00FEN_Msk (0x1ul << EADC_AD1TRGEN2_EPWM00FEN_Pos) |
| #define | EADC_AD1TRGEN2_EPWM00PEN_Pos (2) |
| #define | EADC_AD1TRGEN2_EPWM00PEN_Msk (0x1ul << EADC_AD1TRGEN2_EPWM00PEN_Pos) |
| #define | EADC_AD1TRGEN2_EPWM00CEN_Pos (3) |
| #define | EADC_AD1TRGEN2_EPWM00CEN_Msk (0x1ul << EADC_AD1TRGEN2_EPWM00CEN_Pos) |
| #define | EADC_AD1TRGEN2_EPWM02REN_Pos (4) |
| #define | EADC_AD1TRGEN2_EPWM02REN_Msk (0x1ul << EADC_AD1TRGEN2_EPWM02REN_Pos) |
| #define | EADC_AD1TRGEN2_EPWM02FEN_Pos (5) |
| #define | EADC_AD1TRGEN2_EPWM02FEN_Msk (0x1ul << EADC_AD1TRGEN2_EPWM02FEN_Pos) |
| #define | EADC_AD1TRGEN2_EPWM02PEN_Pos (6) |
| #define | EADC_AD1TRGEN2_EPWM02PEN_Msk (0x1ul << EADC_AD1TRGEN2_EPWM02PEN_Pos) |
| #define | EADC_AD1TRGEN2_EPWM02CEN_Pos (7) |
| #define | EADC_AD1TRGEN2_EPWM02CEN_Msk (0x1ul << EADC_AD1TRGEN2_EPWM02CEN_Pos) |
| #define | EADC_AD1TRGEN2_EPWM04REN_Pos (8) |
| #define | EADC_AD1TRGEN2_EPWM04REN_Msk (0x1ul << EADC_AD1TRGEN2_EPWM04REN_Pos) |
| #define | EADC_AD1TRGEN2_EPWM04FEN_Pos (9) |
| #define | EADC_AD1TRGEN2_EPWM04FEN_Msk (0x1ul << EADC_AD1TRGEN2_EPWM04FEN_Pos) |
| #define | EADC_AD1TRGEN2_EPWM04PEN_Pos (10) |
| #define | EADC_AD1TRGEN2_EPWM04PEN_Msk (0x1ul << EADC_AD1TRGEN2_EPWM04PEN_Pos) |
| #define | EADC_AD1TRGEN2_EPWM04CEN_Pos (11) |
| #define | EADC_AD1TRGEN2_EPWM04CEN_Msk (0x1ul << EADC_AD1TRGEN2_EPWM04CEN_Pos) |
| #define | EADC_AD1TRGEN2_EPWM10REN_Pos (12) |
| #define | EADC_AD1TRGEN2_EPWM10REN_Msk (0x1ul << EADC_AD1TRGEN2_EPWM10REN_Pos) |
| #define | EADC_AD1TRGEN2_EPWM10FEN_Pos (13) |
| #define | EADC_AD1TRGEN2_EPWM10FEN_Msk (0x1ul << EADC_AD1TRGEN2_EPWM10FEN_Pos) |
| #define | EADC_AD1TRGEN2_EPWM10PEN_Pos (14) |
| #define | EADC_AD1TRGEN2_EPWM10PEN_Msk (0x1ul << EADC_AD1TRGEN2_EPWM10PEN_Pos) |
| #define | EADC_AD1TRGEN2_EPWM10CEN_Pos (15) |
| #define | EADC_AD1TRGEN2_EPWM10CEN_Msk (0x1ul << EADC_AD1TRGEN2_EPWM10CEN_Pos) |
| #define | EADC_AD1TRGEN2_EPWM12REN_Pos (16) |
| #define | EADC_AD1TRGEN2_EPWM12REN_Msk (0x1ul << EADC_AD1TRGEN2_EPWM12REN_Pos) |
| #define | EADC_AD1TRGEN2_EPWM120FEN_Pos (17) |
| #define | EADC_AD1TRGEN2_EPWM120FEN_Msk (0x1ul << EADC_AD1TRGEN2_EPWM120FEN_Pos) |
| #define | EADC_AD1TRGEN2_EPWM12PEN_Pos (18) |
| #define | EADC_AD1TRGEN2_EPWM12PEN_Msk (0x1ul << EADC_AD1TRGEN2_EPWM12PEN_Pos) |
| #define | EADC_AD1TRGEN2_EPWM12CEN_Pos (19) |
| #define | EADC_AD1TRGEN2_EPWM12CEN_Msk (0x1ul << EADC_AD1TRGEN2_EPWM12CEN_Pos) |
| #define | EADC_AD1TRGEN2_EPWM14REN_Pos (20) |
| #define | EADC_AD1TRGEN2_EPWM14REN_Msk (0x1ul << EADC_AD1TRGEN2_EPWM14REN_Pos) |
| #define | EADC_AD1TRGEN2_EPWM14FEN_Pos (21) |
| #define | EADC_AD1TRGEN2_EPWM14FEN_Msk (0x1ul << EADC_AD1TRGEN2_EPWM14FEN_Pos) |
| #define | EADC_AD1TRGEN2_EPWM14PEN_Pos (22) |
| #define | EADC_AD1TRGEN2_EPWM14PEN_Msk (0x1ul << EADC_AD1TRGEN2_EPWM14PEN_Pos) |
| #define | EADC_AD1TRGEN2_EPWM14CEN_Pos (23) |
| #define | EADC_AD1TRGEN2_EPWM14CEN_Msk (0x1ul << EADC_AD1TRGEN2_EPWM14CEN_Pos) |
| #define | EADC_AD1TRGEN2_PWM00REN_Pos (24) |
| #define | EADC_AD1TRGEN2_PWM00REN_Msk (0x1ul << EADC_AD1TRGEN2_PWM00REN_Pos) |
| #define | EADC_AD1TRGEN2_PWM00FEN_Pos (25) |
| #define | EADC_AD1TRGEN2_PWM00FEN_Msk (0x1ul << EADC_AD1TRGEN2_PWM00FEN_Pos) |
| #define | EADC_AD1TRGEN2_PWM00PEN_Pos (26) |
| #define | EADC_AD1TRGEN2_PWM00PEN_Msk (0x1ul << EADC_AD1TRGEN2_PWM00PEN_Pos) |
| #define | EADC_AD1TRGEN2_PWM00CEN_Pos (27) |
| #define | EADC_AD1TRGEN2_PWM00CEN_Msk (0x1ul << EADC_AD1TRGEN2_PWM00CEN_Pos) |
| #define | EADC_AD1TRGEN2_PWM01REN_Pos (28) |
| #define | EADC_AD1TRGEN2_PWM01REN_Msk (0x1ul << EADC_AD1TRGEN2_PWM01REN_Pos) |
| #define | EADC_AD1TRGEN2_PWM01FEN_Pos (29) |
| #define | EADC_AD1TRGEN2_PWM01FEN_Msk (0x1ul << EADC_AD1TRGEN2_PWM01FEN_Pos) |
| #define | EADC_AD1TRGEN2_PWM01PEN_Pos (30) |
| #define | EADC_AD1TRGEN2_PWM01PEN_Msk (0x1ul << EADC_AD1TRGEN2_PWM01PEN_Pos) |
| #define | EADC_AD1TRGEN2_PWM01CEN_Pos (31) |
| #define | EADC_AD1TRGEN2_PWM01CEN_Msk (0x1ul << EADC_AD1TRGEN2_PWM01CEN_Pos) |
| #define | EADC_AD1TRGEN3_EPWM00REN_Pos (0) |
| #define | EADC_AD1TRGEN3_EPWM00REN_Msk (0x1ul << EADC_AD1TRGEN3_EPWM00REN_Pos) |
| #define | EADC_AD1TRGEN3_EPWM00FEN_Pos (1) |
| #define | EADC_AD1TRGEN3_EPWM00FEN_Msk (0x1ul << EADC_AD1TRGEN3_EPWM00FEN_Pos) |
| #define | EADC_AD1TRGEN3_EPWM00PEN_Pos (2) |
| #define | EADC_AD1TRGEN3_EPWM00PEN_Msk (0x1ul << EADC_AD1TRGEN3_EPWM00PEN_Pos) |
| #define | EADC_AD1TRGEN3_EPWM00CEN_Pos (3) |
| #define | EADC_AD1TRGEN3_EPWM00CEN_Msk (0x1ul << EADC_AD1TRGEN3_EPWM00CEN_Pos) |
| #define | EADC_AD1TRGEN3_EPWM02REN_Pos (4) |
| #define | EADC_AD1TRGEN3_EPWM02REN_Msk (0x1ul << EADC_AD1TRGEN3_EPWM02REN_Pos) |
| #define | EADC_AD1TRGEN3_EPWM02FEN_Pos (5) |
| #define | EADC_AD1TRGEN3_EPWM02FEN_Msk (0x1ul << EADC_AD1TRGEN3_EPWM02FEN_Pos) |
| #define | EADC_AD1TRGEN3_EPWM02PEN_Pos (6) |
| #define | EADC_AD1TRGEN3_EPWM02PEN_Msk (0x1ul << EADC_AD1TRGEN3_EPWM02PEN_Pos) |
| #define | EADC_AD1TRGEN3_EPWM02CEN_Pos (7) |
| #define | EADC_AD1TRGEN3_EPWM02CEN_Msk (0x1ul << EADC_AD1TRGEN3_EPWM02CEN_Pos) |
| #define | EADC_AD1TRGEN3_EPWM04REN_Pos (8) |
| #define | EADC_AD1TRGEN3_EPWM04REN_Msk (0x1ul << EADC_AD1TRGEN3_EPWM04REN_Pos) |
| #define | EADC_AD1TRGEN3_EPWM04FEN_Pos (9) |
| #define | EADC_AD1TRGEN3_EPWM04FEN_Msk (0x1ul << EADC_AD1TRGEN3_EPWM04FEN_Pos) |
| #define | EADC_AD1TRGEN3_EPWM04PEN_Pos (10) |
| #define | EADC_AD1TRGEN3_EPWM04PEN_Msk (0x1ul << EADC_AD1TRGEN3_EPWM04PEN_Pos) |
| #define | EADC_AD1TRGEN3_EPWM04CEN_Pos (11) |
| #define | EADC_AD1TRGEN3_EPWM04CEN_Msk (0x1ul << EADC_AD1TRGEN3_EPWM04CEN_Pos) |
| #define | EADC_AD1TRGEN3_EPWM10REN_Pos (12) |
| #define | EADC_AD1TRGEN3_EPWM10REN_Msk (0x1ul << EADC_AD1TRGEN3_EPWM10REN_Pos) |
| #define | EADC_AD1TRGEN3_EPWM10FEN_Pos (13) |
| #define | EADC_AD1TRGEN3_EPWM10FEN_Msk (0x1ul << EADC_AD1TRGEN3_EPWM10FEN_Pos) |
| #define | EADC_AD1TRGEN3_EPWM10PEN_Pos (14) |
| #define | EADC_AD1TRGEN3_EPWM10PEN_Msk (0x1ul << EADC_AD1TRGEN3_EPWM10PEN_Pos) |
| #define | EADC_AD1TRGEN3_EPWM10CEN_Pos (15) |
| #define | EADC_AD1TRGEN3_EPWM10CEN_Msk (0x1ul << EADC_AD1TRGEN3_EPWM10CEN_Pos) |
| #define | EADC_AD1TRGEN3_EPWM12REN_Pos (16) |
| #define | EADC_AD1TRGEN3_EPWM12REN_Msk (0x1ul << EADC_AD1TRGEN3_EPWM12REN_Pos) |
| #define | EADC_AD1TRGEN3_EPWM120FEN_Pos (17) |
| #define | EADC_AD1TRGEN3_EPWM120FEN_Msk (0x1ul << EADC_AD1TRGEN3_EPWM120FEN_Pos) |
| #define | EADC_AD1TRGEN3_EPWM12PEN_Pos (18) |
| #define | EADC_AD1TRGEN3_EPWM12PEN_Msk (0x1ul << EADC_AD1TRGEN3_EPWM12PEN_Pos) |
| #define | EADC_AD1TRGEN3_EPWM12CEN_Pos (19) |
| #define | EADC_AD1TRGEN3_EPWM12CEN_Msk (0x1ul << EADC_AD1TRGEN3_EPWM12CEN_Pos) |
| #define | EADC_AD1TRGEN3_EPWM14REN_Pos (20) |
| #define | EADC_AD1TRGEN3_EPWM14REN_Msk (0x1ul << EADC_AD1TRGEN3_EPWM14REN_Pos) |
| #define | EADC_AD1TRGEN3_EPWM14FEN_Pos (21) |
| #define | EADC_AD1TRGEN3_EPWM14FEN_Msk (0x1ul << EADC_AD1TRGEN3_EPWM14FEN_Pos) |
| #define | EADC_AD1TRGEN3_EPWM14PEN_Pos (22) |
| #define | EADC_AD1TRGEN3_EPWM14PEN_Msk (0x1ul << EADC_AD1TRGEN3_EPWM14PEN_Pos) |
| #define | EADC_AD1TRGEN3_EPWM14CEN_Pos (23) |
| #define | EADC_AD1TRGEN3_EPWM14CEN_Msk (0x1ul << EADC_AD1TRGEN3_EPWM14CEN_Pos) |
| #define | EADC_AD1TRGEN3_PWM00REN_Pos (24) |
| #define | EADC_AD1TRGEN3_PWM00REN_Msk (0x1ul << EADC_AD1TRGEN3_PWM00REN_Pos) |
| #define | EADC_AD1TRGEN3_PWM00FEN_Pos (25) |
| #define | EADC_AD1TRGEN3_PWM00FEN_Msk (0x1ul << EADC_AD1TRGEN3_PWM00FEN_Pos) |
| #define | EADC_AD1TRGEN3_PWM00PEN_Pos (26) |
| #define | EADC_AD1TRGEN3_PWM00PEN_Msk (0x1ul << EADC_AD1TRGEN3_PWM00PEN_Pos) |
| #define | EADC_AD1TRGEN3_PWM00CEN_Pos (27) |
| #define | EADC_AD1TRGEN3_PWM00CEN_Msk (0x1ul << EADC_AD1TRGEN3_PWM00CEN_Pos) |
| #define | EADC_AD1TRGEN3_PWM01REN_Pos (28) |
| #define | EADC_AD1TRGEN3_PWM01REN_Msk (0x1ul << EADC_AD1TRGEN3_PWM01REN_Pos) |
| #define | EADC_AD1TRGEN3_PWM01FEN_Pos (29) |
| #define | EADC_AD1TRGEN3_PWM01FEN_Msk (0x1ul << EADC_AD1TRGEN3_PWM01FEN_Pos) |
| #define | EADC_AD1TRGEN3_PWM01PEN_Pos (30) |
| #define | EADC_AD1TRGEN3_PWM01PEN_Msk (0x1ul << EADC_AD1TRGEN3_PWM01PEN_Pos) |
| #define | EADC_AD1TRGEN3_PWM01CEN_Pos (31) |
| #define | EADC_AD1TRGEN3_PWM01CEN_Msk (0x1ul << EADC_AD1TRGEN3_PWM01CEN_Pos) |
| #define | EBI_CTL_MCLKDIV_Pos (8) |
| #define | EBI_CTL_MCLKDIV_Msk (0x7ul << EBI_CTL_MCLKDIV_Pos) |
| #define | EBI_CTL_CRYPTOEN_Pos (24) |
| #define | EBI_CTL_CRYPTOEN_Msk (0xful << EBI_CTL_CRYPTOEN_Pos) |
| #define | EBI_CTL_CSPOLINV_Pos (28) |
| #define | EBI_CTL_CSPOLINV_Msk (0xful << EBI_CTL_CSPOLINV_Pos) |
| #define | EBI_TCTL_TALE_Pos (0) |
| #define | EBI_TCTL_TALE_Msk (0x7ul << EBI_TCTL_TALE_Pos) |
| #define | EBI_TCTL_TACC_Pos (3) |
| #define | EBI_TCTL_TACC_Msk (0x1ful << EBI_TCTL_TACC_Pos) |
| #define | EBI_TCTL_TAHD_Pos (8) |
| #define | EBI_TCTL_TAHD_Msk (0x7ul << EBI_TCTL_TAHD_Pos) |
| #define | EBI_TCTL_W2X_Pos (12) |
| #define | EBI_TCTL_W2X_Msk (0xful << EBI_TCTL_W2X_Pos) |
| #define | EBI_TCTL_R2W_Pos (16) |
| #define | EBI_TCTL_R2W_Msk (0xful << EBI_TCTL_R2W_Pos) |
| #define | EBI_TCTL_R2R_Pos (24) |
| #define | EBI_TCTL_R2R_Msk (0xful << EBI_TCTL_R2R_Pos) |
| #define | EBI_TCTL_CSEN_Pos (28) |
| #define | EBI_TCTL_CSEN_Msk (0x1ul << EBI_TCTL_CSEN_Pos) |
| #define | EBI_TCTL_DW16_Pos (29) |
| #define | EBI_TCTL_DW16_Msk (0x1ul << EBI_TCTL_DW16_Pos) |
| #define | EBI_TCTL_SEPEN_Pos (30) |
| #define | EBI_TCTL_SEPEN_Msk (0x1ul << EBI_TCTL_SEPEN_Pos) |
| #define | EBI_KEY0_KEY_Pos (0) |
| #define | EBI_KEY0_KEY_Msk (0xfffffffful << EBI_KEY0_KEY_Pos) |
| #define | EBI_KEY1_KEY_Pos (0) |
| #define | EBI_KEY1_KEY_Msk (0xfffffffful << EBI_KEY1_KEY_Pos) |
| #define | EBI_KEY2_KEY_Pos (0) |
| #define | EBI_KEY2_KEY_Msk (0xfffffffful << EBI_KEY2_KEY_Pos) |
| #define | EBI_KEY3_KEY_Pos (0) |
| #define | EBI_KEY3_KEY_Msk (0xfffffffful << EBI_KEY3_KEY_Pos) |
| #define | EMAC_CAMCTL_AUP_Pos (0) |
| #define | EMAC_CAMCTL_AUP_Msk (0x1ul << EMAC_CAMCTL_AUP_Pos) |
| #define | EMAC_CAMCTL_AMP_Pos (1) |
| #define | EMAC_CAMCTL_AMP_Msk (0x1ul << EMAC_CAMCTL_AMP_Pos) |
| #define | EMAC_CAMCTL_ABP_Pos (2) |
| #define | EMAC_CAMCTL_ABP_Msk (0x1ul << EMAC_CAMCTL_ABP_Pos) |
| #define | EMAC_CAMCTL_COMPEN_Pos (3) |
| #define | EMAC_CAMCTL_COMPEN_Msk (0x1ul << EMAC_CAMCTL_COMPEN_Pos) |
| #define | EMAC_CAMCTL_CMPEN_Pos (4) |
| #define | EMAC_CAMCTL_CMPEN_Msk (0x1ul << EMAC_CAMCTL_CMPEN_Pos) |
| #define | EMAC_CAMEN_CAMxEN_Pos (0) |
| #define | EMAC_CAMEN_CAMxEN_Msk (0x1ul << EMAC_CAMEN_CAMxEN_Pos) |
| #define | EMAC_CAM0M_MACADDR2_Pos (0) |
| #define | EMAC_CAM0M_MACADDR2_Msk (0xfful << EMAC_CAM0M_MACADDR2_Pos) |
| #define | EMAC_CAM0M_MACADDR3_Pos (8) |
| #define | EMAC_CAM0M_MACADDR3_Msk (0xfful << EMAC_CAM0M_MACADDR3_Pos) |
| #define | EMAC_CAM0M_MACADDR4_Pos (16) |
| #define | EMAC_CAM0M_MACADDR4_Msk (0xfful << EMAC_CAM0M_MACADDR4_Pos) |
| #define | EMAC_CAM0M_MACADDR5_Pos (24) |
| #define | EMAC_CAM0M_MACADDR5_Msk (0xfful << EMAC_CAM0M_MACADDR5_Pos) |
| #define | EMAC_CAM0L_Rserved_Pos (0) |
| #define | EMAC_CAM0L_Rserved_Msk (0xfffful << EMAC_CAM0L_Rserved_Pos) |
| #define | EMAC_CAM0L_MACADDR0_Pos (16) |
| #define | EMAC_CAM0L_MACADDR0_Msk (0xfful << EMAC_CAM0L_MACADDR0_Pos) |
| #define | EMAC_CAM0L_MACADDR1_Pos (24) |
| #define | EMAC_CAM0L_MACADDR1_Msk (0xfful << EMAC_CAM0L_MACADDR1_Pos) |
| #define | EMAC_CAM1M_MACADDR2_Pos (0) |
| #define | EMAC_CAM1M_MACADDR2_Msk (0xfful << EMAC_CAM1M_MACADDR2_Pos) |
| #define | EMAC_CAM1M_MACADDR3_Pos (8) |
| #define | EMAC_CAM1M_MACADDR3_Msk (0xfful << EMAC_CAM1M_MACADDR3_Pos) |
| #define | EMAC_CAM1M_MACADDR4_Pos (16) |
| #define | EMAC_CAM1M_MACADDR4_Msk (0xfful << EMAC_CAM1M_MACADDR4_Pos) |
| #define | EMAC_CAM1M_MACADDR5_Pos (24) |
| #define | EMAC_CAM1M_MACADDR5_Msk (0xfful << EMAC_CAM1M_MACADDR5_Pos) |
| #define | EMAC_CAM1L_Rserved_Pos (0) |
| #define | EMAC_CAM1L_Rserved_Msk (0xfffful << EMAC_CAM1L_Rserved_Pos) |
| #define | EMAC_CAM1L_MACADDR0_Pos (16) |
| #define | EMAC_CAM1L_MACADDR0_Msk (0xfful << EMAC_CAM1L_MACADDR0_Pos) |
| #define | EMAC_CAM1L_MACADDR1_Pos (24) |
| #define | EMAC_CAM1L_MACADDR1_Msk (0xfful << EMAC_CAM1L_MACADDR1_Pos) |
| #define | EMAC_CAM2M_MACADDR2_Pos (0) |
| #define | EMAC_CAM2M_MACADDR2_Msk (0xfful << EMAC_CAM2M_MACADDR2_Pos) |
| #define | EMAC_CAM2M_MACADDR3_Pos (8) |
| #define | EMAC_CAM2M_MACADDR3_Msk (0xfful << EMAC_CAM2M_MACADDR3_Pos) |
| #define | EMAC_CAM2M_MACADDR4_Pos (16) |
| #define | EMAC_CAM2M_MACADDR4_Msk (0xfful << EMAC_CAM2M_MACADDR4_Pos) |
| #define | EMAC_CAM2M_MACADDR5_Pos (24) |
| #define | EMAC_CAM2M_MACADDR5_Msk (0xfful << EMAC_CAM2M_MACADDR5_Pos) |
| #define | EMAC_CAM2L_Rserved_Pos (0) |
| #define | EMAC_CAM2L_Rserved_Msk (0xfffful << EMAC_CAM2L_Rserved_Pos) |
| #define | EMAC_CAM2L_MACADDR0_Pos (16) |
| #define | EMAC_CAM2L_MACADDR0_Msk (0xfful << EMAC_CAM2L_MACADDR0_Pos) |
| #define | EMAC_CAM2L_MACADDR1_Pos (24) |
| #define | EMAC_CAM2L_MACADDR1_Msk (0xfful << EMAC_CAM2L_MACADDR1_Pos) |
| #define | EMAC_CAM3M_MACADDR2_Pos (0) |
| #define | EMAC_CAM3M_MACADDR2_Msk (0xfful << EMAC_CAM3M_MACADDR2_Pos) |
| #define | EMAC_CAM3M_MACADDR3_Pos (8) |
| #define | EMAC_CAM3M_MACADDR3_Msk (0xfful << EMAC_CAM3M_MACADDR3_Pos) |
| #define | EMAC_CAM3M_MACADDR4_Pos (16) |
| #define | EMAC_CAM3M_MACADDR4_Msk (0xfful << EMAC_CAM3M_MACADDR4_Pos) |
| #define | EMAC_CAM3M_MACADDR5_Pos (24) |
| #define | EMAC_CAM3M_MACADDR5_Msk (0xfful << EMAC_CAM3M_MACADDR5_Pos) |
| #define | EMAC_CAM3L_Rserved_Pos (0) |
| #define | EMAC_CAM3L_Rserved_Msk (0xfffful << EMAC_CAM3L_Rserved_Pos) |
| #define | EMAC_CAM3L_MACADDR0_Pos (16) |
| #define | EMAC_CAM3L_MACADDR0_Msk (0xfful << EMAC_CAM3L_MACADDR0_Pos) |
| #define | EMAC_CAM3L_MACADDR1_Pos (24) |
| #define | EMAC_CAM3L_MACADDR1_Msk (0xfful << EMAC_CAM3L_MACADDR1_Pos) |
| #define | EMAC_CAM4M_MACADDR2_Pos (0) |
| #define | EMAC_CAM4M_MACADDR2_Msk (0xfful << EMAC_CAM4M_MACADDR2_Pos) |
| #define | EMAC_CAM4M_MACADDR3_Pos (8) |
| #define | EMAC_CAM4M_MACADDR3_Msk (0xfful << EMAC_CAM4M_MACADDR3_Pos) |
| #define | EMAC_CAM4M_MACADDR4_Pos (16) |
| #define | EMAC_CAM4M_MACADDR4_Msk (0xfful << EMAC_CAM4M_MACADDR4_Pos) |
| #define | EMAC_CAM4M_MACADDR5_Pos (24) |
| #define | EMAC_CAM4M_MACADDR5_Msk (0xfful << EMAC_CAM4M_MACADDR5_Pos) |
| #define | EMAC_CAM4L_Rserved_Pos (0) |
| #define | EMAC_CAM4L_Rserved_Msk (0xfffful << EMAC_CAM4L_Rserved_Pos) |
| #define | EMAC_CAM4L_MACADDR0_Pos (16) |
| #define | EMAC_CAM4L_MACADDR0_Msk (0xfful << EMAC_CAM4L_MACADDR0_Pos) |
| #define | EMAC_CAM4L_MACADDR1_Pos (24) |
| #define | EMAC_CAM4L_MACADDR1_Msk (0xfful << EMAC_CAM4L_MACADDR1_Pos) |
| #define | EMAC_CAM5M_MACADDR2_Pos (0) |
| #define | EMAC_CAM5M_MACADDR2_Msk (0xfful << EMAC_CAM5M_MACADDR2_Pos) |
| #define | EMAC_CAM5M_MACADDR3_Pos (8) |
| #define | EMAC_CAM5M_MACADDR3_Msk (0xfful << EMAC_CAM5M_MACADDR3_Pos) |
| #define | EMAC_CAM5M_MACADDR4_Pos (16) |
| #define | EMAC_CAM5M_MACADDR4_Msk (0xfful << EMAC_CAM5M_MACADDR4_Pos) |
| #define | EMAC_CAM5M_MACADDR5_Pos (24) |
| #define | EMAC_CAM5M_MACADDR5_Msk (0xfful << EMAC_CAM5M_MACADDR5_Pos) |
| #define | EMAC_CAM5L_Rserved_Pos (0) |
| #define | EMAC_CAM5L_Rserved_Msk (0xfffful << EMAC_CAM5L_Rserved_Pos) |
| #define | EMAC_CAM5L_MACADDR0_Pos (16) |
| #define | EMAC_CAM5L_MACADDR0_Msk (0xfful << EMAC_CAM5L_MACADDR0_Pos) |
| #define | EMAC_CAM5L_MACADDR1_Pos (24) |
| #define | EMAC_CAM5L_MACADDR1_Msk (0xfful << EMAC_CAM5L_MACADDR1_Pos) |
| #define | EMAC_CAM6M_MACADDR2_Pos (0) |
| #define | EMAC_CAM6M_MACADDR2_Msk (0xfful << EMAC_CAM6M_MACADDR2_Pos) |
| #define | EMAC_CAM6M_MACADDR3_Pos (8) |
| #define | EMAC_CAM6M_MACADDR3_Msk (0xfful << EMAC_CAM6M_MACADDR3_Pos) |
| #define | EMAC_CAM6M_MACADDR4_Pos (16) |
| #define | EMAC_CAM6M_MACADDR4_Msk (0xfful << EMAC_CAM6M_MACADDR4_Pos) |
| #define | EMAC_CAM6M_MACADDR5_Pos (24) |
| #define | EMAC_CAM6M_MACADDR5_Msk (0xfful << EMAC_CAM6M_MACADDR5_Pos) |
| #define | EMAC_CAM6L_Rserved_Pos (0) |
| #define | EMAC_CAM6L_Rserved_Msk (0xfffful << EMAC_CAM6L_Rserved_Pos) |
| #define | EMAC_CAM6L_MACADDR0_Pos (16) |
| #define | EMAC_CAM6L_MACADDR0_Msk (0xfful << EMAC_CAM6L_MACADDR0_Pos) |
| #define | EMAC_CAM6L_MACADDR1_Pos (24) |
| #define | EMAC_CAM6L_MACADDR1_Msk (0xfful << EMAC_CAM6L_MACADDR1_Pos) |
| #define | EMAC_CAM7M_MACADDR2_Pos (0) |
| #define | EMAC_CAM7M_MACADDR2_Msk (0xfful << EMAC_CAM7M_MACADDR2_Pos) |
| #define | EMAC_CAM7M_MACADDR3_Pos (8) |
| #define | EMAC_CAM7M_MACADDR3_Msk (0xfful << EMAC_CAM7M_MACADDR3_Pos) |
| #define | EMAC_CAM7M_MACADDR4_Pos (16) |
| #define | EMAC_CAM7M_MACADDR4_Msk (0xfful << EMAC_CAM7M_MACADDR4_Pos) |
| #define | EMAC_CAM7M_MACADDR5_Pos (24) |
| #define | EMAC_CAM7M_MACADDR5_Msk (0xfful << EMAC_CAM7M_MACADDR5_Pos) |
| #define | EMAC_CAM7L_Rserved_Pos (0) |
| #define | EMAC_CAM7L_Rserved_Msk (0xfffful << EMAC_CAM7L_Rserved_Pos) |
| #define | EMAC_CAM7L_MACADDR0_Pos (16) |
| #define | EMAC_CAM7L_MACADDR0_Msk (0xfful << EMAC_CAM7L_MACADDR0_Pos) |
| #define | EMAC_CAM7L_MACADDR1_Pos (24) |
| #define | EMAC_CAM7L_MACADDR1_Msk (0xfful << EMAC_CAM7L_MACADDR1_Pos) |
| #define | EMAC_CAM8M_MACADDR2_Pos (0) |
| #define | EMAC_CAM8M_MACADDR2_Msk (0xfful << EMAC_CAM8M_MACADDR2_Pos) |
| #define | EMAC_CAM8M_MACADDR3_Pos (8) |
| #define | EMAC_CAM8M_MACADDR3_Msk (0xfful << EMAC_CAM8M_MACADDR3_Pos) |
| #define | EMAC_CAM8M_MACADDR4_Pos (16) |
| #define | EMAC_CAM8M_MACADDR4_Msk (0xfful << EMAC_CAM8M_MACADDR4_Pos) |
| #define | EMAC_CAM8M_MACADDR5_Pos (24) |
| #define | EMAC_CAM8M_MACADDR5_Msk (0xfful << EMAC_CAM8M_MACADDR5_Pos) |
| #define | EMAC_CAM8L_Rserved_Pos (0) |
| #define | EMAC_CAM8L_Rserved_Msk (0xfffful << EMAC_CAM8L_Rserved_Pos) |
| #define | EMAC_CAM8L_MACADDR0_Pos (16) |
| #define | EMAC_CAM8L_MACADDR0_Msk (0xfful << EMAC_CAM8L_MACADDR0_Pos) |
| #define | EMAC_CAM8L_MACADDR1_Pos (24) |
| #define | EMAC_CAM8L_MACADDR1_Msk (0xfful << EMAC_CAM8L_MACADDR1_Pos) |
| #define | EMAC_CAM9M_MACADDR2_Pos (0) |
| #define | EMAC_CAM9M_MACADDR2_Msk (0xfful << EMAC_CAM9M_MACADDR2_Pos) |
| #define | EMAC_CAM9M_MACADDR3_Pos (8) |
| #define | EMAC_CAM9M_MACADDR3_Msk (0xfful << EMAC_CAM9M_MACADDR3_Pos) |
| #define | EMAC_CAM9M_MACADDR4_Pos (16) |
| #define | EMAC_CAM9M_MACADDR4_Msk (0xfful << EMAC_CAM9M_MACADDR4_Pos) |
| #define | EMAC_CAM9M_MACADDR5_Pos (24) |
| #define | EMAC_CAM9M_MACADDR5_Msk (0xfful << EMAC_CAM9M_MACADDR5_Pos) |
| #define | EMAC_CAM9L_Rserved_Pos (0) |
| #define | EMAC_CAM9L_Rserved_Msk (0xfffful << EMAC_CAM9L_Rserved_Pos) |
| #define | EMAC_CAM9L_MACADDR0_Pos (16) |
| #define | EMAC_CAM9L_MACADDR0_Msk (0xfful << EMAC_CAM9L_MACADDR0_Pos) |
| #define | EMAC_CAM9L_MACADDR1_Pos (24) |
| #define | EMAC_CAM9L_MACADDR1_Msk (0xfful << EMAC_CAM9L_MACADDR1_Pos) |
| #define | EMAC_CAM10M_MACADDR2_Pos (0) |
| #define | EMAC_CAM10M_MACADDR2_Msk (0xfful << EMAC_CAM10M_MACADDR2_Pos) |
| #define | EMAC_CAM10M_MACADDR3_Pos (8) |
| #define | EMAC_CAM10M_MACADDR3_Msk (0xfful << EMAC_CAM10M_MACADDR3_Pos) |
| #define | EMAC_CAM10M_MACADDR4_Pos (16) |
| #define | EMAC_CAM10M_MACADDR4_Msk (0xfful << EMAC_CAM10M_MACADDR4_Pos) |
| #define | EMAC_CAM10M_MACADDR5_Pos (24) |
| #define | EMAC_CAM10M_MACADDR5_Msk (0xfful << EMAC_CAM10M_MACADDR5_Pos) |
| #define | EMAC_CAM10L_Rserved_Pos (0) |
| #define | EMAC_CAM10L_Rserved_Msk (0xfffful << EMAC_CAM10L_Rserved_Pos) |
| #define | EMAC_CAM10L_MACADDR0_Pos (16) |
| #define | EMAC_CAM10L_MACADDR0_Msk (0xfful << EMAC_CAM10L_MACADDR0_Pos) |
| #define | EMAC_CAM10L_MACADDR1_Pos (24) |
| #define | EMAC_CAM10L_MACADDR1_Msk (0xfful << EMAC_CAM10L_MACADDR1_Pos) |
| #define | EMAC_CAM11M_MACADDR2_Pos (0) |
| #define | EMAC_CAM11M_MACADDR2_Msk (0xfful << EMAC_CAM11M_MACADDR2_Pos) |
| #define | EMAC_CAM11M_MACADDR3_Pos (8) |
| #define | EMAC_CAM11M_MACADDR3_Msk (0xfful << EMAC_CAM11M_MACADDR3_Pos) |
| #define | EMAC_CAM11M_MACADDR4_Pos (16) |
| #define | EMAC_CAM11M_MACADDR4_Msk (0xfful << EMAC_CAM11M_MACADDR4_Pos) |
| #define | EMAC_CAM11M_MACADDR5_Pos (24) |
| #define | EMAC_CAM11M_MACADDR5_Msk (0xfful << EMAC_CAM11M_MACADDR5_Pos) |
| #define | EMAC_CAM11L_Rserved_Pos (0) |
| #define | EMAC_CAM11L_Rserved_Msk (0xfffful << EMAC_CAM11L_Rserved_Pos) |
| #define | EMAC_CAM11L_MACADDR0_Pos (16) |
| #define | EMAC_CAM11L_MACADDR0_Msk (0xfful << EMAC_CAM11L_MACADDR0_Pos) |
| #define | EMAC_CAM11L_MACADDR1_Pos (24) |
| #define | EMAC_CAM11L_MACADDR1_Msk (0xfful << EMAC_CAM11L_MACADDR1_Pos) |
| #define | EMAC_CAM12M_MACADDR2_Pos (0) |
| #define | EMAC_CAM12M_MACADDR2_Msk (0xfful << EMAC_CAM12M_MACADDR2_Pos) |
| #define | EMAC_CAM12M_MACADDR3_Pos (8) |
| #define | EMAC_CAM12M_MACADDR3_Msk (0xfful << EMAC_CAM12M_MACADDR3_Pos) |
| #define | EMAC_CAM12M_MACADDR4_Pos (16) |
| #define | EMAC_CAM12M_MACADDR4_Msk (0xfful << EMAC_CAM12M_MACADDR4_Pos) |
| #define | EMAC_CAM12M_MACADDR5_Pos (24) |
| #define | EMAC_CAM12M_MACADDR5_Msk (0xfful << EMAC_CAM12M_MACADDR5_Pos) |
| #define | EMAC_CAM12L_Rserved_Pos (0) |
| #define | EMAC_CAM12L_Rserved_Msk (0xfffful << EMAC_CAM12L_Rserved_Pos) |
| #define | EMAC_CAM12L_MACADDR0_Pos (16) |
| #define | EMAC_CAM12L_MACADDR0_Msk (0xfful << EMAC_CAM12L_MACADDR0_Pos) |
| #define | EMAC_CAM12L_MACADDR1_Pos (24) |
| #define | EMAC_CAM12L_MACADDR1_Msk (0xfful << EMAC_CAM12L_MACADDR1_Pos) |
| #define | EMAC_CAM13M_MACADDR2_Pos (0) |
| #define | EMAC_CAM13M_MACADDR2_Msk (0xfful << EMAC_CAM13M_MACADDR2_Pos) |
| #define | EMAC_CAM13M_MACADDR3_Pos (8) |
| #define | EMAC_CAM13M_MACADDR3_Msk (0xfful << EMAC_CAM13M_MACADDR3_Pos) |
| #define | EMAC_CAM13M_MACADDR4_Pos (16) |
| #define | EMAC_CAM13M_MACADDR4_Msk (0xfful << EMAC_CAM13M_MACADDR4_Pos) |
| #define | EMAC_CAM13M_MACADDR5_Pos (24) |
| #define | EMAC_CAM13M_MACADDR5_Msk (0xfful << EMAC_CAM13M_MACADDR5_Pos) |
| #define | EMAC_CAM13L_Rserved_Pos (0) |
| #define | EMAC_CAM13L_Rserved_Msk (0xfffful << EMAC_CAM13L_Rserved_Pos) |
| #define | EMAC_CAM13L_MACADDR0_Pos (16) |
| #define | EMAC_CAM13L_MACADDR0_Msk (0xfful << EMAC_CAM13L_MACADDR0_Pos) |
| #define | EMAC_CAM13L_MACADDR1_Pos (24) |
| #define | EMAC_CAM13L_MACADDR1_Msk (0xfful << EMAC_CAM13L_MACADDR1_Pos) |
| #define | EMAC_CAM14M_MACADDR2_Pos (0) |
| #define | EMAC_CAM14M_MACADDR2_Msk (0xfful << EMAC_CAM14M_MACADDR2_Pos) |
| #define | EMAC_CAM14M_MACADDR3_Pos (8) |
| #define | EMAC_CAM14M_MACADDR3_Msk (0xfful << EMAC_CAM14M_MACADDR3_Pos) |
| #define | EMAC_CAM14M_MACADDR4_Pos (16) |
| #define | EMAC_CAM14M_MACADDR4_Msk (0xfful << EMAC_CAM14M_MACADDR4_Pos) |
| #define | EMAC_CAM14M_MACADDR5_Pos (24) |
| #define | EMAC_CAM14M_MACADDR5_Msk (0xfful << EMAC_CAM14M_MACADDR5_Pos) |
| #define | EMAC_CAM14L_Rserved_Pos (0) |
| #define | EMAC_CAM14L_Rserved_Msk (0xfffful << EMAC_CAM14L_Rserved_Pos) |
| #define | EMAC_CAM14L_MACADDR0_Pos (16) |
| #define | EMAC_CAM14L_MACADDR0_Msk (0xfful << EMAC_CAM14L_MACADDR0_Pos) |
| #define | EMAC_CAM14L_MACADDR1_Pos (24) |
| #define | EMAC_CAM14L_MACADDR1_Msk (0xfful << EMAC_CAM14L_MACADDR1_Pos) |
| #define | EMAC_CAM15MSB_OPCODE_Pos (0) |
| #define | EMAC_CAM15MSB_OPCODE_Msk (0xfffful << EMAC_CAM15MSB_OPCODE_Pos) |
| #define | EMAC_CAM15MSB_LENGTH_Pos (16) |
| #define | EMAC_CAM15MSB_LENGTH_Msk (0xfffful << EMAC_CAM15MSB_LENGTH_Pos) |
| #define | EMAC_CAM15LSB_OPERAND_Pos (24) |
| #define | EMAC_CAM15LSB_OPERAND_Msk (0xfful << EMAC_CAM15LSB_OPERAND_Pos) |
| #define | EMAC_TXDSA_TXDSA_Pos (0) |
| #define | EMAC_TXDSA_TXDSA_Msk (0xfffffffful << EMAC_TXDSA_TXDSA_Pos) |
| #define | EMAC_RXDSA_RXDSA_Pos (0) |
| #define | EMAC_RXDSA_RXDSA_Msk (0xfffffffful << EMAC_RXDSA_RXDSA_Pos) |
| #define | EMAC_CTL_RXON_Pos (0) |
| #define | EMAC_CTL_RXON_Msk (0x1ul << EMAC_CTL_RXON_Pos) |
| #define | EMAC_CTL_ALP_Pos (1) |
| #define | EMAC_CTL_ALP_Msk (0x1ul << EMAC_CTL_ALP_Pos) |
| #define | EMAC_CTL_ARP_Pos (2) |
| #define | EMAC_CTL_ARP_Msk (0x1ul << EMAC_CTL_ARP_Pos) |
| #define | EMAC_CTL_ACP_Pos (3) |
| #define | EMAC_CTL_ACP_Msk (0x1ul << EMAC_CTL_ACP_Pos) |
| #define | EMAC_CTL_AEP_Pos (4) |
| #define | EMAC_CTL_AEP_Msk (0x1ul << EMAC_CTL_AEP_Pos) |
| #define | EMAC_CTL_STRIPCRC_Pos (5) |
| #define | EMAC_CTL_STRIPCRC_Msk (0x1ul << EMAC_CTL_STRIPCRC_Pos) |
| #define | EMAC_CTL_WOLEN_Pos (6) |
| #define | EMAC_CTL_WOLEN_Msk (0x1ul << EMAC_CTL_WOLEN_Pos) |
| #define | EMAC_CTL_TXON_Pos (8) |
| #define | EMAC_CTL_TXON_Msk (0x1ul << EMAC_CTL_TXON_Pos) |
| #define | EMAC_CTL_NODEF_Pos (9) |
| #define | EMAC_CTL_NODEF_Msk (0x1ul << EMAC_CTL_NODEF_Pos) |
| #define | EMAC_CTL_SDPZ_Pos (16) |
| #define | EMAC_CTL_SDPZ_Msk (0x1ul << EMAC_CTL_SDPZ_Pos) |
| #define | EMAC_CTL_SQECHKEN_Pos (17) |
| #define | EMAC_CTL_SQECHKEN_Msk (0x1ul << EMAC_CTL_SQECHKEN_Pos) |
| #define | EMAC_CTL_FUDUP_Pos (18) |
| #define | EMAC_CTL_FUDUP_Msk (0x1ul << EMAC_CTL_FUDUP_Pos) |
| #define | EMAC_CTL_RMIIRXCTL_Pos (19) |
| #define | EMAC_CTL_RMIIRXCTL_Msk (0x1ul << EMAC_CTL_RMIIRXCTL_Pos) |
| #define | EMAC_CTL_OPMODE_Pos (20) |
| #define | EMAC_CTL_OPMODE_Msk (0x1ul << EMAC_CTL_OPMODE_Pos) |
| #define | EMAC_CTL_RMIIEN_Pos (22) |
| #define | EMAC_CTL_RMIIEN_Msk (0x1ul << EMAC_CTL_RMIIEN_Pos) |
| #define | EMAC_CTL_RST_Pos (24) |
| #define | EMAC_CTL_RST_Msk (0x1ul << EMAC_CTL_RST_Pos) |
| #define | EMAC_MIIMDAT_DATA_Pos (0) |
| #define | EMAC_MIIMDAT_DATA_Msk (0xfffful << EMAC_MIIMDAT_DATA_Pos) |
| #define | EMAC_MIIMCTL_PHYREG_Pos (0) |
| #define | EMAC_MIIMCTL_PHYREG_Msk (0x1ful << EMAC_MIIMCTL_PHYREG_Pos) |
| #define | EMAC_MIIMCTL_PHYADDR_Pos (8) |
| #define | EMAC_MIIMCTL_PHYADDR_Msk (0x1ful << EMAC_MIIMCTL_PHYADDR_Pos) |
| #define | EMAC_MIIMCTL_WRITE_Pos (16) |
| #define | EMAC_MIIMCTL_WRITE_Msk (0x1ul << EMAC_MIIMCTL_WRITE_Pos) |
| #define | EMAC_MIIMCTL_BUSY_Pos (17) |
| #define | EMAC_MIIMCTL_BUSY_Msk (0x1ul << EMAC_MIIMCTL_BUSY_Pos) |
| #define | EMAC_MIIMCTL_PREAMSP_Pos (18) |
| #define | EMAC_MIIMCTL_PREAMSP_Msk (0x1ul << EMAC_MIIMCTL_PREAMSP_Pos) |
| #define | EMAC_MIIMCTL_MDCON_Pos (19) |
| #define | EMAC_MIIMCTL_MDCON_Msk (0x1ul << EMAC_MIIMCTL_MDCON_Pos) |
| #define | EMAC_FIFOCTL_RXFIFOTH_Pos (0) |
| #define | EMAC_FIFOCTL_RXFIFOTH_Msk (0x3ul << EMAC_FIFOCTL_RXFIFOTH_Pos) |
| #define | EMAC_FIFOCTL_TXFIFOTH_Pos (8) |
| #define | EMAC_FIFOCTL_TXFIFOTH_Msk (0x3ul << EMAC_FIFOCTL_TXFIFOTH_Pos) |
| #define | EMAC_FIFOCTL_BURSTLEN_Pos (20) |
| #define | EMAC_FIFOCTL_BURSTLEN_Msk (0x3ul << EMAC_FIFOCTL_BURSTLEN_Pos) |
| #define | EMAC_TXST_TXST_Pos (0) |
| #define | EMAC_TXST_TXST_Msk (0xfffffffful << EMAC_TXST_TXST_Pos) |
| #define | EMAC_RXST_RXST_Pos (0) |
| #define | EMAC_RXST_RXST_Msk (0xfffffffful << EMAC_RXST_RXST_Pos) |
| #define | EMAC_MRFL_MRFL_Pos (0) |
| #define | EMAC_MRFL_MRFL_Msk (0xfffful << EMAC_MRFL_MRFL_Pos) |
| #define | EMAC_INTEN_RXIEN_Pos (0) |
| #define | EMAC_INTEN_RXIEN_Msk (0x1ul << EMAC_INTEN_RXIEN_Pos) |
| #define | EMAC_INTEN_CRCEIEN_Pos (1) |
| #define | EMAC_INTEN_CRCEIEN_Msk (0x1ul << EMAC_INTEN_CRCEIEN_Pos) |
| #define | EMAC_INTEN_RXOVIEN_Pos (2) |
| #define | EMAC_INTEN_RXOVIEN_Msk (0x1ul << EMAC_INTEN_RXOVIEN_Pos) |
| #define | EMAC_INTEN_LPIEN_Pos (3) |
| #define | EMAC_INTEN_LPIEN_Msk (0x1ul << EMAC_INTEN_LPIEN_Pos) |
| #define | EMAC_INTEN_RXGDIEN_Pos (4) |
| #define | EMAC_INTEN_RXGDIEN_Msk (0x1ul << EMAC_INTEN_RXGDIEN_Pos) |
| #define | EMAC_INTEN_ALIEIEN_Pos (5) |
| #define | EMAC_INTEN_ALIEIEN_Msk (0x1ul << EMAC_INTEN_ALIEIEN_Pos) |
| #define | EMAC_INTEN_RPIEN_Pos (6) |
| #define | EMAC_INTEN_RPIEN_Msk (0x1ul << EMAC_INTEN_RPIEN_Pos) |
| #define | EMAC_INTEN_MPCOVIEN_Pos (7) |
| #define | EMAC_INTEN_MPCOVIEN_Msk (0x1ul << EMAC_INTEN_MPCOVIEN_Pos) |
| #define | EMAC_INTEN_MFLEIEN_Pos (8) |
| #define | EMAC_INTEN_MFLEIEN_Msk (0x1ul << EMAC_INTEN_MFLEIEN_Pos) |
| #define | EMAC_INTEN_DENIEN_Pos (9) |
| #define | EMAC_INTEN_DENIEN_Msk (0x1ul << EMAC_INTEN_DENIEN_Pos) |
| #define | EMAC_INTEN_RDUIEN_Pos (10) |
| #define | EMAC_INTEN_RDUIEN_Msk (0x1ul << EMAC_INTEN_RDUIEN_Pos) |
| #define | EMAC_INTEN_RXBEIEN_Pos (11) |
| #define | EMAC_INTEN_RXBEIEN_Msk (0x1ul << EMAC_INTEN_RXBEIEN_Pos) |
| #define | EMAC_INTEN_CFRIEN_Pos (14) |
| #define | EMAC_INTEN_CFRIEN_Msk (0x1ul << EMAC_INTEN_CFRIEN_Pos) |
| #define | EMAC_INTEN_WOLIEN_Pos (15) |
| #define | EMAC_INTEN_WOLIEN_Msk (0x1ul << EMAC_INTEN_WOLIEN_Pos) |
| #define | EMAC_INTEN_TXIEN_Pos (16) |
| #define | EMAC_INTEN_TXIEN_Msk (0x1ul << EMAC_INTEN_TXIEN_Pos) |
| #define | EMAC_INTEN_TXUDIEN_Pos (17) |
| #define | EMAC_INTEN_TXUDIEN_Msk (0x1ul << EMAC_INTEN_TXUDIEN_Pos) |
| #define | EMAC_INTEN_TXCPIEN_Pos (18) |
| #define | EMAC_INTEN_TXCPIEN_Msk (0x1ul << EMAC_INTEN_TXCPIEN_Pos) |
| #define | EMAC_INTEN_EXDEFIEN_Pos (19) |
| #define | EMAC_INTEN_EXDEFIEN_Msk (0x1ul << EMAC_INTEN_EXDEFIEN_Pos) |
| #define | EMAC_INTEN_NCSIEN_Pos (20) |
| #define | EMAC_INTEN_NCSIEN_Msk (0x1ul << EMAC_INTEN_NCSIEN_Pos) |
| #define | EMAC_INTEN_TXABTIEN_Pos (21) |
| #define | EMAC_INTEN_TXABTIEN_Msk (0x1ul << EMAC_INTEN_TXABTIEN_Pos) |
| #define | EMAC_INTEN_LCIEN_Pos (22) |
| #define | EMAC_INTEN_LCIEN_Msk (0x1ul << EMAC_INTEN_LCIEN_Pos) |
| #define | EMAC_INTEN_TDUIEN_Pos (23) |
| #define | EMAC_INTEN_TDUIEN_Msk (0x1ul << EMAC_INTEN_TDUIEN_Pos) |
| #define | EMAC_INTEN_TXBEIEN_Pos (24) |
| #define | EMAC_INTEN_TXBEIEN_Msk (0x1ul << EMAC_INTEN_TXBEIEN_Pos) |
| #define | EMAC_INTEN_TSALMIEN_Pos (28) |
| #define | EMAC_INTEN_TSALMIEN_Msk (0x1ul << EMAC_INTEN_TSALMIEN_Pos) |
| #define | EMAC_INTSTS_RXIF_Pos (0) |
| #define | EMAC_INTSTS_RXIF_Msk (0x1ul << EMAC_INTSTS_RXIF_Pos) |
| #define | EMAC_INTSTS_CRCEIF_Pos (1) |
| #define | EMAC_INTSTS_CRCEIF_Msk (0x1ul << EMAC_INTSTS_CRCEIF_Pos) |
| #define | EMAC_INTSTS_RXOVIF_Pos (2) |
| #define | EMAC_INTSTS_RXOVIF_Msk (0x1ul << EMAC_INTSTS_RXOVIF_Pos) |
| #define | EMAC_INTSTS_LPIF_Pos (3) |
| #define | EMAC_INTSTS_LPIF_Msk (0x1ul << EMAC_INTSTS_LPIF_Pos) |
| #define | EMAC_INTSTS_RXGDIF_Pos (4) |
| #define | EMAC_INTSTS_RXGDIF_Msk (0x1ul << EMAC_INTSTS_RXGDIF_Pos) |
| #define | EMAC_INTSTS_ALIEIF_Pos (5) |
| #define | EMAC_INTSTS_ALIEIF_Msk (0x1ul << EMAC_INTSTS_ALIEIF_Pos) |
| #define | EMAC_INTSTS_RPIF_Pos (6) |
| #define | EMAC_INTSTS_RPIF_Msk (0x1ul << EMAC_INTSTS_RPIF_Pos) |
| #define | EMAC_INTSTS_MPCOVIF_Pos (7) |
| #define | EMAC_INTSTS_MPCOVIF_Msk (0x1ul << EMAC_INTSTS_MPCOVIF_Pos) |
| #define | EMAC_INTSTS_MFLEIF_Pos (8) |
| #define | EMAC_INTSTS_MFLEIF_Msk (0x1ul << EMAC_INTSTS_MFLEIF_Pos) |
| #define | EMAC_INTSTS_DENIF_Pos (9) |
| #define | EMAC_INTSTS_DENIF_Msk (0x1ul << EMAC_INTSTS_DENIF_Pos) |
| #define | EMAC_INTSTS_RDUIF_Pos (10) |
| #define | EMAC_INTSTS_RDUIF_Msk (0x1ul << EMAC_INTSTS_RDUIF_Pos) |
| #define | EMAC_INTSTS_RXBEIF_Pos (11) |
| #define | EMAC_INTSTS_RXBEIF_Msk (0x1ul << EMAC_INTSTS_RXBEIF_Pos) |
| #define | EMAC_INTSTS_CFRIF_Pos (14) |
| #define | EMAC_INTSTS_CFRIF_Msk (0x1ul << EMAC_INTSTS_CFRIF_Pos) |
| #define | EMAC_INTSTS_WOLIF_Pos (15) |
| #define | EMAC_INTSTS_WOLIF_Msk (0x1ul << EMAC_INTSTS_WOLIF_Pos) |
| #define | EMAC_INTSTS_TXIF_Pos (16) |
| #define | EMAC_INTSTS_TXIF_Msk (0x1ul << EMAC_INTSTS_TXIF_Pos) |
| #define | EMAC_INTSTS_TXUDIF_Pos (17) |
| #define | EMAC_INTSTS_TXUDIF_Msk (0x1ul << EMAC_INTSTS_TXUDIF_Pos) |
| #define | EMAC_INTSTS_TXCPIF_Pos (18) |
| #define | EMAC_INTSTS_TXCPIF_Msk (0x1ul << EMAC_INTSTS_TXCPIF_Pos) |
| #define | EMAC_INTSTS_EXDEFIF_Pos (19) |
| #define | EMAC_INTSTS_EXDEFIF_Msk (0x1ul << EMAC_INTSTS_EXDEFIF_Pos) |
| #define | EMAC_INTSTS_NCSIF_Pos (20) |
| #define | EMAC_INTSTS_NCSIF_Msk (0x1ul << EMAC_INTSTS_NCSIF_Pos) |
| #define | EMAC_INTSTS_TXABTIF_Pos (21) |
| #define | EMAC_INTSTS_TXABTIF_Msk (0x1ul << EMAC_INTSTS_TXABTIF_Pos) |
| #define | EMAC_INTSTS_LCIF_Pos (22) |
| #define | EMAC_INTSTS_LCIF_Msk (0x1ul << EMAC_INTSTS_LCIF_Pos) |
| #define | EMAC_INTSTS_TDUIF_Pos (23) |
| #define | EMAC_INTSTS_TDUIF_Msk (0x1ul << EMAC_INTSTS_TDUIF_Pos) |
| #define | EMAC_INTSTS_TXBEIF_Pos (24) |
| #define | EMAC_INTSTS_TXBEIF_Msk (0x1ul << EMAC_INTSTS_TXBEIF_Pos) |
| #define | EMAC_INTSTS_TSALMIF_Pos (28) |
| #define | EMAC_INTSTS_TSALMIF_Msk (0x1ul << EMAC_INTSTS_TSALMIF_Pos) |
| #define | EMAC_GENSTS_CFRIF_Pos (0) |
| #define | EMAC_GENSTS_CFRIF_Msk (0x1ul << EMAC_GENSTS_CFRIF_Pos) |
| #define | EMAC_GENSTS_RXHALT_Pos (1) |
| #define | EMAC_GENSTS_RXHALT_Msk (0x1ul << EMAC_GENSTS_RXHALT_Pos) |
| #define | EMAC_GENSTS_RXFFULL_Pos (2) |
| #define | EMAC_GENSTS_RXFFULL_Msk (0x1ul << EMAC_GENSTS_RXFFULL_Pos) |
| #define | EMAC_GENSTS_COLCNT_Pos (4) |
| #define | EMAC_GENSTS_COLCNT_Msk (0xful << EMAC_GENSTS_COLCNT_Pos) |
| #define | EMAC_GENSTS_DEF_Pos (8) |
| #define | EMAC_GENSTS_DEF_Msk (0x1ul << EMAC_GENSTS_DEF_Pos) |
| #define | EMAC_GENSTS_TXPAUSED_Pos (9) |
| #define | EMAC_GENSTS_TXPAUSED_Msk (0x1ul << EMAC_GENSTS_TXPAUSED_Pos) |
| #define | EMAC_GENSTS_SQE_Pos (10) |
| #define | EMAC_GENSTS_SQE_Msk (0x1ul << EMAC_GENSTS_SQE_Pos) |
| #define | EMAC_GENSTS_TXHALT_Pos (11) |
| #define | EMAC_GENSTS_TXHALT_Msk (0x1ul << EMAC_GENSTS_TXHALT_Pos) |
| #define | EMAC_GENSTS_RPSTS_Pos (12) |
| #define | EMAC_GENSTS_RPSTS_Msk (0x1ul << EMAC_GENSTS_RPSTS_Pos) |
| #define | EMAC_MPCNT_MPCNT_Pos (0) |
| #define | EMAC_MPCNT_MPCNT_Msk (0xfffful << EMAC_MPCNT_MPCNT_Pos) |
| #define | EMAC_RPCNT_RPCNT_Pos (0) |
| #define | EMAC_RPCNT_RPCNT_Msk (0xfffful << EMAC_RPCNT_RPCNT_Pos) |
| #define | EMAC_FRSTS_RXFLT_Pos (0) |
| #define | EMAC_FRSTS_RXFLT_Msk (0xfffful << EMAC_FRSTS_RXFLT_Pos) |
| #define | EMAC_CTXDSA_CTXDSA_Pos (0) |
| #define | EMAC_CTXDSA_CTXDSA_Msk (0xfffffffful << EMAC_CTXDSA_CTXDSA_Pos) |
| #define | EMAC_CTXBSA_CTXBSA_Pos (0) |
| #define | EMAC_CTXBSA_CTXBSA_Msk (0xfffffffful << EMAC_CTXBSA_CTXBSA_Pos) |
| #define | EMAC_CRXDSA_CRXDSA_Pos (0) |
| #define | EMAC_CRXDSA_CRXDSA_Msk (0xfffffffful << EMAC_CRXDSA_CRXDSA_Pos) |
| #define | EMAC_CRXBSA_CRXBSA_Pos (0) |
| #define | EMAC_CRXBSA_CRXBSA_Msk (0xfffffffful << EMAC_CRXBSA_CRXBSA_Pos) |
| #define | EMAC_TSCTL_TSEN_Pos (0) |
| #define | EMAC_TSCTL_TSEN_Msk (0x1ul << EMAC_TSCTL_TSEN_Pos) |
| #define | EMAC_TSCTL_TSIEN_Pos (1) |
| #define | EMAC_TSCTL_TSIEN_Msk (0x1ul << EMAC_TSCTL_TSIEN_Pos) |
| #define | EMAC_TSCTL_TSMODE_Pos (2) |
| #define | EMAC_TSCTL_TSMODE_Msk (0x1ul << EMAC_TSCTL_TSMODE_Pos) |
| #define | EMAC_TSCTL_TSUPDATE_Pos (3) |
| #define | EMAC_TSCTL_TSUPDATE_Msk (0x1ul << EMAC_TSCTL_TSUPDATE_Pos) |
| #define | EMAC_TSCTL_TSALMEN_Pos (5) |
| #define | EMAC_TSCTL_TSALMEN_Msk (0x1ul << EMAC_TSCTL_TSALMEN_Pos) |
| #define | EMAC_TSSEC_SEC_Pos (0) |
| #define | EMAC_TSSEC_SEC_Msk (0xfffffffful << EMAC_TSSEC_SEC_Pos) |
| #define | EMAC_TSSUBSEC_SUBSEC_Pos (0) |
| #define | EMAC_TSSUBSEC_SUBSEC_Msk (0xfffffffful << EMAC_TSSUBSEC_SUBSEC_Pos) |
| #define | EMAC_TSINC_CNTINC_Pos (0) |
| #define | EMAC_TSINC_CNTINC_Msk (0xfful << EMAC_TSINC_CNTINC_Pos) |
| #define | EMAC_TSADDEND_ADDEND_Pos (0) |
| #define | EMAC_TSADDEND_ADDEND_Msk (0xfffffffful << EMAC_TSADDEND_ADDEND_Pos) |
| #define | EMAC_UPDSEC_SEC_Pos (0) |
| #define | EMAC_UPDSEC_SEC_Msk (0xfffffffful << EMAC_UPDSEC_SEC_Pos) |
| #define | EMAC_UPDSUBSEC_SUBSEC_Pos (0) |
| #define | EMAC_UPDSUBSEC_SUBSEC_Msk (0xfffffffful << EMAC_UPDSUBSEC_SUBSEC_Pos) |
| #define | EMAC_ALMSEC_SEC_Pos (0) |
| #define | EMAC_ALMSEC_SEC_Msk (0xfffffffful << EMAC_ALMSEC_SEC_Pos) |
| #define | EMAC_ALMSUBSEC_SUBSEC_Pos (0) |
| #define | EMAC_ALMSUBSEC_SUBSEC_Msk (0xfffffffful << EMAC_ALMSUBSEC_SUBSEC_Pos) |
| #define | EPWM_CTL_MODE_Pos (0) |
| #define | EPWM_CTL_MODE_Msk (0x3ul << EPWM_CTL_MODE_Pos) |
| #define | EPWM_CTL_CLKDIV_Pos (2) |
| #define | EPWM_CTL_CLKDIV_Msk (0x3ul << EPWM_CTL_CLKDIV_Pos) |
| #define | EPWM_CTL_PWMIEN_Pos (4) |
| #define | EPWM_CTL_PWMIEN_Msk (0x1ul << EPWM_CTL_PWMIEN_Pos) |
| #define | EPWM_CTL_BRKIEN_Pos (5) |
| #define | EPWM_CTL_BRKIEN_Msk (0x1ul << EPWM_CTL_BRKIEN_Pos) |
| #define | EPWM_CTL_LOAD_Pos (6) |
| #define | EPWM_CTL_LOAD_Msk (0x1ul << EPWM_CTL_LOAD_Pos) |
| #define | EPWM_CTL_CNTEN_Pos (7) |
| #define | EPWM_CTL_CNTEN_Msk (0x1ul << EPWM_CTL_CNTEN_Pos) |
| #define | EPWM_CTL_INTTYPE_Pos (8) |
| #define | EPWM_CTL_INTTYPE_Msk (0x1ul << EPWM_CTL_INTTYPE_Pos) |
| #define | EPWM_CTL_PINV_Pos (9) |
| #define | EPWM_CTL_PINV_Msk (0x1ul << EPWM_CTL_PINV_Pos) |
| #define | EPWM_CTL_CNTCLR_Pos (11) |
| #define | EPWM_CTL_CNTCLR_Msk (0x1ul << EPWM_CTL_CNTCLR_Pos) |
| #define | EPWM_CTL_CNTTYPE_Pos (12) |
| #define | EPWM_CTL_CNTTYPE_Msk (0x1ul << EPWM_CTL_CNTTYPE_Pos) |
| #define | EPWM_CTL_GROUPEN_Pos (13) |
| #define | EPWM_CTL_GROUPEN_Msk (0x1ul << EPWM_CTL_GROUPEN_Pos) |
| #define | EPWM_CTL_BRKP0INV_Pos (14) |
| #define | EPWM_CTL_BRKP0INV_Msk (0x1ul << EPWM_CTL_BRKP0INV_Pos) |
| #define | EPWM_CTL_BRKP1INV_Pos (15) |
| #define | EPWM_CTL_BRKP1INV_Msk (0x1ul << EPWM_CTL_BRKP1INV_Pos) |
| #define | EPWM_CTL_BRKP0EN_Pos (16) |
| #define | EPWM_CTL_BRKP0EN_Msk (0x1ul << EPWM_CTL_BRKP0EN_Pos) |
| #define | EPWM_CTL_BRKP1EN_Pos (17) |
| #define | EPWM_CTL_BRKP1EN_Msk (0x1ul << EPWM_CTL_BRKP1EN_Pos) |
| #define | EPWM_CTL_BRK1SEL_Pos (18) |
| #define | EPWM_CTL_BRK1SEL_Msk (0x3ul << EPWM_CTL_BRK1SEL_Pos) |
| #define | EPWM_CTL_BRK0NFSEL_Pos (20) |
| #define | EPWM_CTL_BRK0NFSEL_Msk (0x3ul << EPWM_CTL_BRK0NFSEL_Pos) |
| #define | EPWM_CTL_BRK1NFSEL_Pos (22) |
| #define | EPWM_CTL_BRK1NFSEL_Msk (0x3ul << EPWM_CTL_BRK1NFSEL_Pos) |
| #define | EPWM_CTL_CPO0BKEN_Pos (24) |
| #define | EPWM_CTL_CPO0BKEN_Msk (0x1ul << EPWM_CTL_CPO0BKEN_Pos) |
| #define | EPWM_CTL_CPO1BKEN_Pos (25) |
| #define | EPWM_CTL_CPO1BKEN_Msk (0x1ul << EPWM_CTL_CPO1BKEN_Pos) |
| #define | EPWM_CTL_CPO2BKEN_Pos (26) |
| #define | EPWM_CTL_CPO2BKEN_Msk (0x1ul << EPWM_CTL_CPO2BKEN_Pos) |
| #define | EPWM_CTL_LVDBKEN_Pos (27) |
| #define | EPWM_CTL_LVDBKEN_Msk (0x1ul << EPWM_CTL_LVDBKEN_Pos) |
| #define | EPWM_CTL_BRK0NFDIS_Pos (28) |
| #define | EPWM_CTL_BRK0NFDIS_Msk (0x1ul << EPWM_CTL_BRK0NFDIS_Pos) |
| #define | EPWM_CTL_BRK1NFDIS_Pos (29) |
| #define | EPWM_CTL_BRK1NFDIS_Msk (0x1ul << EPWM_CTL_BRK1NFDIS_Pos) |
| #define | EPWM_CTL_CTRLD_Pos (31) |
| #define | EPWM_CTL_CTRLD_Msk (0x1ul << EPWM_CTL_CTRLD_Pos) |
| #define | EPWM_STATUS_BRKIF0_Pos (0) |
| #define | EPWM_STATUS_BRKIF0_Msk (0x1ul << EPWM_STATUS_BRKIF0_Pos) |
| #define | EPWM_STATUS_BRKIF1_Pos (1) |
| #define | EPWM_STATUS_BRKIF1_Msk (0x1ul << EPWM_STATUS_BRKIF1_Pos) |
| #define | EPWM_STATUS_PIF_Pos (2) |
| #define | EPWM_STATUS_PIF_Msk (0x1ul << EPWM_STATUS_PIF_Pos) |
| #define | EPWM_STATUS_EIF0_Pos (4) |
| #define | EPWM_STATUS_EIF0_Msk (0x1ul << EPWM_STATUS_EIF0_Pos) |
| #define | EPWM_STATUS_EIF2_Pos (5) |
| #define | EPWM_STATUS_EIF2_Msk (0x1ul << EPWM_STATUS_EIF2_Pos) |
| #define | EPWM_STATUS_EIF4_Pos (6) |
| #define | EPWM_STATUS_EIF4_Msk (0x1ul << EPWM_STATUS_EIF4_Pos) |
| #define | EPWM_STATUS_BRK0LOCK_Pos (8) |
| #define | EPWM_STATUS_BRK0LOCK_Msk (0x1ul << EPWM_STATUS_BRK0LOCK_Pos) |
| #define | EPWM_STATUS_BRK0STS_Pos (24) |
| #define | EPWM_STATUS_BRK0STS_Msk (0x1ul << EPWM_STATUS_BRK0STS_Pos) |
| #define | EPWM_STATUS_BRK1STS_Pos (25) |
| #define | EPWM_STATUS_BRK1STS_Msk (0x1ul << EPWM_STATUS_BRK1STS_Pos) |
| #define | EPWM_PERIOD_PERIOD_Pos (0) |
| #define | EPWM_PERIOD_PERIOD_Msk (0xfffful << EPWM_PERIOD_PERIOD_Pos) |
| #define | EPWM_CMPDAT0_CMP_Pos (0) |
| #define | EPWM_CMPDAT0_CMP_Msk (0xfffful << EPWM_CMPDAT0_CMP_Pos) |
| #define | EPWM_CMPDAT2_CMP_Pos (0) |
| #define | EPWM_CMPDAT2_CMP_Msk (0xfffful << EPWM_CMPDAT2_CMP_Pos) |
| #define | EPWM_CMPDAT4_CMP_Pos (0) |
| #define | EPWM_CMPDAT4_CMP_Msk (0xfffful << EPWM_CMPDAT4_CMP_Pos) |
| #define | EPWM_MSKEN_MSKEN_Pos (0) |
| #define | EPWM_MSKEN_MSKEN_Msk (0x3ful << EPWM_MSKEN_MSKEN_Pos) |
| #define | EPWM_MSK_MSKDAT_Pos (0) |
| #define | EPWM_MSK_MSKDAT_Msk (0x3ful << EPWM_MSK_MSKDAT_Pos) |
| #define | EPWM_ASYMCMP0_CMP_Pos (0) |
| #define | EPWM_ASYMCMP0_CMP_Msk (0xfffful << EPWM_ASYMCMP0_CMP_Pos) |
| #define | EPWM_ASYMCMP2_CMP_Pos (0) |
| #define | EPWM_ASYMCMP2_CMP_Msk (0xfffful << EPWM_ASYMCMP2_CMP_Pos) |
| #define | EPWM_ASYMCMP4_CMP_Pos (0) |
| #define | EPWM_ASYMCMP4_CMP_Msk (0xfffful << EPWM_ASYMCMP4_CMP_Pos) |
| #define | EPWM_DTCTL_DTCNT_Pos (0) |
| #define | EPWM_DTCTL_DTCNT_Msk (0x7fful << EPWM_DTCTL_DTCNT_Pos) |
| #define | EPWM_DTCTL_DTEN0_Pos (16) |
| #define | EPWM_DTCTL_DTEN0_Msk (0x1ul << EPWM_DTCTL_DTEN0_Pos) |
| #define | EPWM_DTCTL_DTEN2_Pos (17) |
| #define | EPWM_DTCTL_DTEN2_Msk (0x1ul << EPWM_DTCTL_DTEN2_Pos) |
| #define | EPWM_DTCTL_DTEN4_Pos (18) |
| #define | EPWM_DTCTL_DTEN4_Msk (0x1ul << EPWM_DTCTL_DTEN4_Pos) |
| #define | EPWM_BRKOUT_BRKOUT_Pos (0) |
| #define | EPWM_BRKOUT_BRKOUT_Msk (0x3ful << EPWM_BRKOUT_BRKOUT_Pos) |
| #define | EPWM_NPCTL_NEGPOLAR_Pos (0) |
| #define | EPWM_NPCTL_NEGPOLAR_Msk (0x3ful << EPWM_NPCTL_NEGPOLAR_Pos) |
| #define | EPWM_ASYMCTL_ASYMEN_Pos (0) |
| #define | EPWM_ASYMCTL_ASYMEN_Msk (0x1ul << EPWM_ASYMCTL_ASYMEN_Pos) |
| #define | EPWM_ASYMCTL_ASYMMODE0_Pos (8) |
| #define | EPWM_ASYMCTL_ASYMMODE0_Msk (0x3ul << EPWM_ASYMCTL_ASYMMODE0_Pos) |
| #define | EPWM_ASYMCTL_ASYMMODE2_Pos (16) |
| #define | EPWM_ASYMCTL_ASYMMODE2_Msk (0x3ul << EPWM_ASYMCTL_ASYMMODE2_Pos) |
| #define | EPWM_ASYMCTL_ASYMMODE4_Pos (24) |
| #define | EPWM_ASYMCTL_ASYMMODE4_Msk (0x3ul << EPWM_ASYMCTL_ASYMMODE4_Pos) |
| #define | EPWM_PERIODCNT_PERIODCNT_Pos (0) |
| #define | EPWM_PERIODCNT_PERIODCNT_Msk (0xful << EPWM_PERIODCNT_PERIODCNT_Pos) |
| #define | EPWM_EINTCTL_EDGEIEN0_Pos (0) |
| #define | EPWM_EINTCTL_EDGEIEN0_Msk (0x1ul << EPWM_EINTCTL_EDGEIEN0_Pos) |
| #define | EPWM_EINTCTL_EDGEIEN2_Pos (1) |
| #define | EPWM_EINTCTL_EDGEIEN2_Msk (0x1ul << EPWM_EINTCTL_EDGEIEN2_Pos) |
| #define | EPWM_EINTCTL_EDGEIEN4_Pos (2) |
| #define | EPWM_EINTCTL_EDGEIEN4_Msk (0x1ul << EPWM_EINTCTL_EDGEIEN4_Pos) |
| #define | EPWM_EINTCTL_EINTTYPE0_Pos (8) |
| #define | EPWM_EINTCTL_EINTTYPE0_Msk (0x1ul << EPWM_EINTCTL_EINTTYPE0_Pos) |
| #define | EPWM_EINTCTL_EINTTYPE2_Pos (9) |
| #define | EPWM_EINTCTL_EINTTYPE2_Msk (0x1ul << EPWM_EINTCTL_EINTTYPE2_Pos) |
| #define | EPWM_EINTCTL_EINTTYPE4_Pos (10) |
| #define | EPWM_EINTCTL_EINTTYPE4_Msk (0x1ul << EPWM_EINTCTL_EINTTYPE4_Pos) |
| #define | EPWM_OUTEN0_EVENOUTEN_Pos (0) |
| #define | EPWM_OUTEN0_EVENOUTEN_Msk (0x1ul << EPWM_OUTEN0_EVENOUTEN_Pos) |
| #define | EPWM_OUTEN0_ODDOUTEN_Pos (1) |
| #define | EPWM_OUTEN0_ODDOUTEN_Msk (0x1ul << EPWM_OUTEN0_ODDOUTEN_Pos) |
| #define | FMC_ISPCTL_ISPEN_Pos (0) |
| #define | FMC_ISPCTL_ISPEN_Msk (0x1ul << FMC_ISPCTL_ISPEN_Pos) |
| #define | FMC_ISPCTL_BS_Pos (1) |
| #define | FMC_ISPCTL_BS_Msk (0x1ul << FMC_ISPCTL_BS_Pos) |
| #define | FMC_ISPCTL_APUEN_Pos (3) |
| #define | FMC_ISPCTL_APUEN_Msk (0x1ul << FMC_ISPCTL_APUEN_Pos) |
| #define | FMC_ISPCTL_CFGUEN_Pos (4) |
| #define | FMC_ISPCTL_CFGUEN_Msk (0x1ul << FMC_ISPCTL_CFGUEN_Pos) |
| #define | FMC_ISPCTL_LDUEN_Pos (5) |
| #define | FMC_ISPCTL_LDUEN_Msk (0x1ul << FMC_ISPCTL_LDUEN_Pos) |
| #define | FMC_ISPCTL_ISPFF_Pos (6) |
| #define | FMC_ISPCTL_ISPFF_Msk (0x1ul << FMC_ISPCTL_ISPFF_Pos) |
| #define | FMC_ISPADDR_ISPADDR_Pos (0) |
| #define | FMC_ISPADDR_ISPADDR_Msk (0xfffffffful << FMC_ISPADDR_ISPADDR_Pos) |
| #define | FMC_ISPDAT_ISPDAT_Pos (0) |
| #define | FMC_ISPDAT_ISPDAT_Msk (0xfffffffful << FMC_ISPDAT_ISPDAT_Pos) |
| #define | FMC_ISPCMD_CMD_Pos (0) |
| #define | FMC_ISPCMD_CMD_Msk (0x3ful << FMC_ISPCMD_CMD_Pos) |
| #define | FMC_ISPTRG_ISPGO_Pos (0) |
| #define | FMC_ISPTRG_ISPGO_Msk (0x1ul << FMC_ISPTRG_ISPGO_Pos) |
| #define | FMC_DFBA_DFBA_Pos (0) |
| #define | FMC_DFBA_DFBA_Msk (0xfffffffful << FMC_DFBA_DFBA_Pos) |
| #define | FMC_FTCTL_FOM_Pos (4) |
| #define | FMC_FTCTL_FOM_Msk (0x7ul << FMC_FTCTL_FOM_Pos) |
| #define | FMC_ISPSTS_ISPBUSY_Pos (0) |
| #define | FMC_ISPSTS_ISPBUSY_Msk (0x1ul << FMC_ISPSTS_ISPBUSY_Pos) |
| #define | FMC_ISPSTS_CBS_Pos (1) |
| #define | FMC_ISPSTS_CBS_Msk (0x3ul << FMC_ISPSTS_CBS_Pos) |
| #define | FMC_ISPSTS_ISPFF_Pos (6) |
| #define | FMC_ISPSTS_ISPFF_Msk (0x1ul << FMC_ISPSTS_ISPFF_Pos) |
| #define | FMC_ISPSTS_VECMAP_Pos (9) |
| #define | FMC_ISPSTS_VECMAP_Msk (0xffful << FMC_ISPSTS_VECMAP_Pos) |
| #define | FMC_ISPSTS_CFGCRCF_Pos (26) |
| #define | FMC_ISPSTS_CFGCRCF_Msk (0x1ul << FMC_ISPSTS_CFGCRCF_Pos) |
| #define | FMC_FBWP_BWP_Pos (0) |
| #define | FMC_FBWP_BWP_Msk (0xfffffffful << FMC_FBWP_BWP_Pos) |
| #define | FMC_MPDAT0_ISPDAT0_Pos (0) |
| #define | FMC_MPDAT0_ISPDAT0_Msk (0xfffffffful << FMC_MPDAT0_ISPDAT0_Pos) |
| #define | FMC_MPDAT1_ISPDAT1_Pos (0) |
| #define | FMC_MPDAT1_ISPDAT1_Msk (0xfffffffful << FMC_MPDAT1_ISPDAT1_Pos) |
| #define | FMC_MPDAT2_ISPDAT2_Pos (0) |
| #define | FMC_MPDAT2_ISPDAT2_Msk (0xfffffffful << FMC_MPDAT2_ISPDAT2_Pos) |
| #define | FMC_MPDAT3_ISPDAT3_Pos (0) |
| #define | FMC_MPDAT3_ISPDAT3_Msk (0xfffffffful << FMC_MPDAT3_ISPDAT3_Pos) |
| #define | FMC_MPSTS_MPBUSY_Pos (0) |
| #define | FMC_MPSTS_MPBUSY_Msk (0x1ul << FMC_MPSTS_MPBUSY_Pos) |
| #define | FMC_MPSTS_ISPFF_Pos (2) |
| #define | FMC_MPSTS_ISPFF_Msk (0x1ul << FMC_MPSTS_ISPFF_Pos) |
| #define | FMC_MPSTS_D0_Pos (4) |
| #define | FMC_MPSTS_D0_Msk (0x1ul << FMC_MPSTS_D0_Pos) |
| #define | FMC_MPSTS_D1_Pos (5) |
| #define | FMC_MPSTS_D1_Msk (0x1ul << FMC_MPSTS_D1_Pos) |
| #define | FMC_MPSTS_D2_Pos (6) |
| #define | FMC_MPSTS_D2_Msk (0x1ul << FMC_MPSTS_D2_Pos) |
| #define | FMC_MPSTS_D3_Pos (7) |
| #define | FMC_MPSTS_D3_Msk (0x1ul << FMC_MPSTS_D3_Pos) |
| #define | FMC_MPADDR_MPADDR_Pos (0) |
| #define | FMC_MPADDR_MPADDR_Msk (0xfffffffful << FMC_MPADDR_MPADDR_Pos) |
| #define | GPIO_MODE_MODE0_Pos (0) |
| #define | GPIO_MODE_MODE0_Msk (0x3ul << GPIO_MODE_MODE0_Pos) |
| #define | GPIO_MODE_MODE1_Pos (2) |
| #define | GPIO_MODE_MODE1_Msk (0x3ul << GPIO_MODE_MODE1_Pos) |
| #define | GPIO_MODE_MODE2_Pos (4) |
| #define | GPIO_MODE_MODE2_Msk (0x3ul << GPIO_MODE_MODE2_Pos) |
| #define | GPIO_MODE_MODE3_Pos (6) |
| #define | GPIO_MODE_MODE3_Msk (0x3ul << GPIO_MODE_MODE3_Pos) |
| #define | GPIO_MODE_MODE4_Pos (8) |
| #define | GPIO_MODE_MODE4_Msk (0x3ul << GPIO_MODE_MODE4_Pos) |
| #define | GPIO_MODE_MODE5_Pos (10) |
| #define | GPIO_MODE_MODE5_Msk (0x3ul << GPIO_MODE_MODE5_Pos) |
| #define | GPIO_MODE_MODE6_Pos (12) |
| #define | GPIO_MODE_MODE6_Msk (0x3ul << GPIO_MODE_MODE6_Pos) |
| #define | GPIO_MODE_MODE7_Pos (14) |
| #define | GPIO_MODE_MODE7_Msk (0x3ul << GPIO_MODE_MODE7_Pos) |
| #define | GPIO_MODE_MODE8_Pos (16) |
| #define | GPIO_MODE_MODE8_Msk (0x3ul << GPIO_MODE_MODE8_Pos) |
| #define | GPIO_MODE_MODE9_Pos (18) |
| #define | GPIO_MODE_MODE9_Msk (0x3ul << GPIO_MODE_MODE9_Pos) |
| #define | GPIO_MODE_MODE10_Pos (20) |
| #define | GPIO_MODE_MODE10_Msk (0x3ul << GPIO_MODE_MODE10_Pos) |
| #define | GPIO_MODE_MODE11_Pos (22) |
| #define | GPIO_MODE_MODE11_Msk (0x3ul << GPIO_MODE_MODE11_Pos) |
| #define | GPIO_MODE_MODE12_Pos (24) |
| #define | GPIO_MODE_MODE12_Msk (0x3ul << GPIO_MODE_MODE12_Pos) |
| #define | GPIO_MODE_MODE13_Pos (26) |
| #define | GPIO_MODE_MODE13_Msk (0x3ul << GPIO_MODE_MODE13_Pos) |
| #define | GPIO_MODE_MODE14_Pos (28) |
| #define | GPIO_MODE_MODE14_Msk (0x3ul << GPIO_MODE_MODE14_Pos) |
| #define | GPIO_MODE_MODE15_Pos (30) |
| #define | GPIO_MODE_MODE15_Msk (0x3ul << GPIO_MODE_MODE15_Pos) |
| #define | GPIO_DINOFF_DINOFF0_Pos (16) |
| #define | GPIO_DINOFF_DINOFF0_Msk (0x1ul << GPIO_DINOFF_DINOFF0_Pos) |
| #define | GPIO_DINOFF_DINOFF1_Pos (17) |
| #define | GPIO_DINOFF_DINOFF1_Msk (0x1ul << GPIO_DINOFF_DINOFF1_Pos) |
| #define | GPIO_DINOFF_DINOFF2_Pos (18) |
| #define | GPIO_DINOFF_DINOFF2_Msk (0x1ul << GPIO_DINOFF_DINOFF2_Pos) |
| #define | GPIO_DINOFF_DINOFF3_Pos (19) |
| #define | GPIO_DINOFF_DINOFF3_Msk (0x1ul << GPIO_DINOFF_DINOFF3_Pos) |
| #define | GPIO_DINOFF_DINOFF4_Pos (20) |
| #define | GPIO_DINOFF_DINOFF4_Msk (0x1ul << GPIO_DINOFF_DINOFF4_Pos) |
| #define | GPIO_DINOFF_DINOFF5_Pos (21) |
| #define | GPIO_DINOFF_DINOFF5_Msk (0x1ul << GPIO_DINOFF_DINOFF5_Pos) |
| #define | GPIO_DINOFF_DINOFF6_Pos (22) |
| #define | GPIO_DINOFF_DINOFF6_Msk (0x1ul << GPIO_DINOFF_DINOFF6_Pos) |
| #define | GPIO_DINOFF_DINOFF7_Pos (23) |
| #define | GPIO_DINOFF_DINOFF7_Msk (0x1ul << GPIO_DINOFF_DINOFF7_Pos) |
| #define | GPIO_DINOFF_DINOFF8_Pos (24) |
| #define | GPIO_DINOFF_DINOFF8_Msk (0x1ul << GPIO_DINOFF_DINOFF8_Pos) |
| #define | GPIO_DINOFF_DINOFF9_Pos (25) |
| #define | GPIO_DINOFF_DINOFF9_Msk (0x1ul << GPIO_DINOFF_DINOFF9_Pos) |
| #define | GPIO_DINOFF_DINOFF10_Pos (26) |
| #define | GPIO_DINOFF_DINOFF10_Msk (0x1ul << GPIO_DINOFF_DINOFF10_Pos) |
| #define | GPIO_DINOFF_DINOFF11_Pos (27) |
| #define | GPIO_DINOFF_DINOFF11_Msk (0x1ul << GPIO_DINOFF_DINOFF11_Pos) |
| #define | GPIO_DINOFF_DINOFF12_Pos (28) |
| #define | GPIO_DINOFF_DINOFF12_Msk (0x1ul << GPIO_DINOFF_DINOFF12_Pos) |
| #define | GPIO_DINOFF_DINOFF13_Pos (29) |
| #define | GPIO_DINOFF_DINOFF13_Msk (0x1ul << GPIO_DINOFF_DINOFF13_Pos) |
| #define | GPIO_DINOFF_DINOFF14_Pos (30) |
| #define | GPIO_DINOFF_DINOFF14_Msk (0x1ul << GPIO_DINOFF_DINOFF14_Pos) |
| #define | GPIO_DINOFF_DINOFF15_Pos (31) |
| #define | GPIO_DINOFF_DINOFF15_Msk (0x1ul << GPIO_DINOFF_DINOFF15_Pos) |
| #define | GPIO_DOUT_DOUT0_Pos (0) |
| #define | GPIO_DOUT_DOUT0_Msk (0x1ul << GPIO_DOUT_DOUT0_Pos) |
| #define | GPIO_DOUT_DOUT1_Pos (1) |
| #define | GPIO_DOUT_DOUT1_Msk (0x1ul << GPIO_DOUT_DOUT1_Pos) |
| #define | GPIO_DOUT_DOUT2_Pos (2) |
| #define | GPIO_DOUT_DOUT2_Msk (0x1ul << GPIO_DOUT_DOUT2_Pos) |
| #define | GPIO_DOUT_DOUT3_Pos (3) |
| #define | GPIO_DOUT_DOUT3_Msk (0x1ul << GPIO_DOUT_DOUT3_Pos) |
| #define | GPIO_DOUT_DOUT4_Pos (4) |
| #define | GPIO_DOUT_DOUT4_Msk (0x1ul << GPIO_DOUT_DOUT4_Pos) |
| #define | GPIO_DOUT_DOUT5_Pos (5) |
| #define | GPIO_DOUT_DOUT5_Msk (0x1ul << GPIO_DOUT_DOUT5_Pos) |
| #define | GPIO_DOUT_DOUT6_Pos (6) |
| #define | GPIO_DOUT_DOUT6_Msk (0x1ul << GPIO_DOUT_DOUT6_Pos) |
| #define | GPIO_DOUT_DOUT7_Pos (7) |
| #define | GPIO_DOUT_DOUT7_Msk (0x1ul << GPIO_DOUT_DOUT7_Pos) |
| #define | GPIO_DOUT_DOUT8_Pos (8) |
| #define | GPIO_DOUT_DOUT8_Msk (0x1ul << GPIO_DOUT_DOUT8_Pos) |
| #define | GPIO_DOUT_DOUT9_Pos (9) |
| #define | GPIO_DOUT_DOUT9_Msk (0x1ul << GPIO_DOUT_DOUT9_Pos) |
| #define | GPIO_DOUT_DOUT10_Pos (10) |
| #define | GPIO_DOUT_DOUT10_Msk (0x1ul << GPIO_DOUT_DOUT10_Pos) |
| #define | GPIO_DOUT_DOUT11_Pos (11) |
| #define | GPIO_DOUT_DOUT11_Msk (0x1ul << GPIO_DOUT_DOUT11_Pos) |
| #define | GPIO_DOUT_DOUT12_Pos (12) |
| #define | GPIO_DOUT_DOUT12_Msk (0x1ul << GPIO_DOUT_DOUT12_Pos) |
| #define | GPIO_DOUT_DOUT13_Pos (13) |
| #define | GPIO_DOUT_DOUT13_Msk (0x1ul << GPIO_DOUT_DOUT13_Pos) |
| #define | GPIO_DOUT_DOUT14_Pos (14) |
| #define | GPIO_DOUT_DOUT14_Msk (0x1ul << GPIO_DOUT_DOUT14_Pos) |
| #define | GPIO_DOUT_DOUT15_Pos (15) |
| #define | GPIO_DOUT_DOUT15_Msk (0x1ul << GPIO_DOUT_DOUT15_Pos) |
| #define | GPIO_DATMSK_DATMSK0_Pos (0) |
| #define | GPIO_DATMSK_DATMSK0_Msk (0x1ul << GPIO_DATMSK_DATMSK0_Pos) |
| #define | GPIO_DATMSK_DATMSK1_Pos (1) |
| #define | GPIO_DATMSK_DATMSK1_Msk (0x1ul << GPIO_DATMSK_DATMSK1_Pos) |
| #define | GPIO_DATMSK_DATMSK2_Pos (2) |
| #define | GPIO_DATMSK_DATMSK2_Msk (0x1ul << GPIO_DATMSK_DATMSK2_Pos) |
| #define | GPIO_DATMSK_DATMSK3_Pos (3) |
| #define | GPIO_DATMSK_DATMSK3_Msk (0x1ul << GPIO_DATMSK_DATMSK3_Pos) |
| #define | GPIO_DATMSK_DATMSK4_Pos (4) |
| #define | GPIO_DATMSK_DATMSK4_Msk (0x1ul << GPIO_DATMSK_DATMSK4_Pos) |
| #define | GPIO_DATMSK_DATMSK5_Pos (5) |
| #define | GPIO_DATMSK_DATMSK5_Msk (0x1ul << GPIO_DATMSK_DATMSK5_Pos) |
| #define | GPIO_DATMSK_DATMSK6_Pos (6) |
| #define | GPIO_DATMSK_DATMSK6_Msk (0x1ul << GPIO_DATMSK_DATMSK6_Pos) |
| #define | GPIO_DATMSK_DATMSK7_Pos (7) |
| #define | GPIO_DATMSK_DATMSK7_Msk (0x1ul << GPIO_DATMSK_DATMSK7_Pos) |
| #define | GPIO_DATMSK_DATMSK8_Pos (8) |
| #define | GPIO_DATMSK_DATMSK8_Msk (0x1ul << GPIO_DATMSK_DATMSK8_Pos) |
| #define | GPIO_DATMSK_DATMSK9_Pos (9) |
| #define | GPIO_DATMSK_DATMSK9_Msk (0x1ul << GPIO_DATMSK_DATMSK9_Pos) |
| #define | GPIO_DATMSK_DATMSK10_Pos (10) |
| #define | GPIO_DATMSK_DATMSK10_Msk (0x1ul << GPIO_DATMSK_DATMSK10_Pos) |
| #define | GPIO_DATMSK_DATMSK11_Pos (11) |
| #define | GPIO_DATMSK_DATMSK11_Msk (0x1ul << GPIO_DATMSK_DATMSK11_Pos) |
| #define | GPIO_DATMSK_DATMSK12_Pos (12) |
| #define | GPIO_DATMSK_DATMSK12_Msk (0x1ul << GPIO_DATMSK_DATMSK12_Pos) |
| #define | GPIO_DATMSK_DATMSK13_Pos (13) |
| #define | GPIO_DATMSK_DATMSK13_Msk (0x1ul << GPIO_DATMSK_DATMSK13_Pos) |
| #define | GPIO_DATMSK_DATMSK14_Pos (14) |
| #define | GPIO_DATMSK_DATMSK14_Msk (0x1ul << GPIO_DATMSK_DATMSK14_Pos) |
| #define | GPIO_DATMSK_DATMSK15_Pos (15) |
| #define | GPIO_DATMSK_DATMSK15_Msk (0x1ul << GPIO_DATMSK_DATMSK15_Pos) |
| #define | GPIO_PIN_PIN0_Pos (0) |
| #define | GPIO_PIN_PIN0_Msk (0x1ul << GPIO_PIN_PIN0_Pos) |
| #define | GPIO_PIN_PIN1_Pos (1) |
| #define | GPIO_PIN_PIN1_Msk (0x1ul << GPIO_PIN_PIN1_Pos) |
| #define | GPIO_PIN_PIN2_Pos (2) |
| #define | GPIO_PIN_PIN2_Msk (0x1ul << GPIO_PIN_PIN2_Pos) |
| #define | GPIO_PIN_PIN3_Pos (3) |
| #define | GPIO_PIN_PIN3_Msk (0x1ul << GPIO_PIN_PIN3_Pos) |
| #define | GPIO_PIN_PIN4_Pos (4) |
| #define | GPIO_PIN_PIN4_Msk (0x1ul << GPIO_PIN_PIN4_Pos) |
| #define | GPIO_PIN_PIN5_Pos (5) |
| #define | GPIO_PIN_PIN5_Msk (0x1ul << GPIO_PIN_PIN5_Pos) |
| #define | GPIO_PIN_PIN6_Pos (6) |
| #define | GPIO_PIN_PIN6_Msk (0x1ul << GPIO_PIN_PIN6_Pos) |
| #define | GPIO_PIN_PIN7_Pos (7) |
| #define | GPIO_PIN_PIN7_Msk (0x1ul << GPIO_PIN_PIN7_Pos) |
| #define | GPIO_PIN_PIN8_Pos (8) |
| #define | GPIO_PIN_PIN8_Msk (0x1ul << GPIO_PIN_PIN8_Pos) |
| #define | GPIO_PIN_PIN9_Pos (9) |
| #define | GPIO_PIN_PIN9_Msk (0x1ul << GPIO_PIN_PIN9_Pos) |
| #define | GPIO_PIN_PIN10_Pos (10) |
| #define | GPIO_PIN_PIN10_Msk (0x1ul << GPIO_PIN_PIN10_Pos) |
| #define | GPIO_PIN_PIN11_Pos (11) |
| #define | GPIO_PIN_PIN11_Msk (0x1ul << GPIO_PIN_PIN11_Pos) |
| #define | GPIO_PIN_PIN12_Pos (12) |
| #define | GPIO_PIN_PIN12_Msk (0x1ul << GPIO_PIN_PIN12_Pos) |
| #define | GPIO_PIN_PIN13_Pos (13) |
| #define | GPIO_PIN_PIN13_Msk (0x1ul << GPIO_PIN_PIN13_Pos) |
| #define | GPIO_PIN_PIN14_Pos (14) |
| #define | GPIO_PIN_PIN14_Msk (0x1ul << GPIO_PIN_PIN14_Pos) |
| #define | GPIO_PIN_PIN15_Pos (15) |
| #define | GPIO_PIN_PIN15_Msk (0x1ul << GPIO_PIN_PIN15_Pos) |
| #define | GPIO_DBEN_DBEN0_Pos (0) |
| #define | GPIO_DBEN_DBEN0_Msk (0x1ul << GPIO_DBEN_DBEN0_Pos) |
| #define | GPIO_DBEN_DBEN1_Pos (1) |
| #define | GPIO_DBEN_DBEN1_Msk (0x1ul << GPIO_DBEN_DBEN1_Pos) |
| #define | GPIO_DBEN_DBEN2_Pos (2) |
| #define | GPIO_DBEN_DBEN2_Msk (0x1ul << GPIO_DBEN_DBEN2_Pos) |
| #define | GPIO_DBEN_DBEN3_Pos (3) |
| #define | GPIO_DBEN_DBEN3_Msk (0x1ul << GPIO_DBEN_DBEN3_Pos) |
| #define | GPIO_DBEN_DBEN4_Pos (4) |
| #define | GPIO_DBEN_DBEN4_Msk (0x1ul << GPIO_DBEN_DBEN4_Pos) |
| #define | GPIO_DBEN_DBEN5_Pos (5) |
| #define | GPIO_DBEN_DBEN5_Msk (0x1ul << GPIO_DBEN_DBEN5_Pos) |
| #define | GPIO_DBEN_DBEN6_Pos (6) |
| #define | GPIO_DBEN_DBEN6_Msk (0x1ul << GPIO_DBEN_DBEN6_Pos) |
| #define | GPIO_DBEN_DBEN7_Pos (7) |
| #define | GPIO_DBEN_DBEN7_Msk (0x1ul << GPIO_DBEN_DBEN7_Pos) |
| #define | GPIO_DBEN_DBEN8_Pos (8) |
| #define | GPIO_DBEN_DBEN8_Msk (0x1ul << GPIO_DBEN_DBEN8_Pos) |
| #define | GPIO_DBEN_DBEN9_Pos (9) |
| #define | GPIO_DBEN_DBEN9_Msk (0x1ul << GPIO_DBEN_DBEN9_Pos) |
| #define | GPIO_DBEN_DBEN10_Pos (10) |
| #define | GPIO_DBEN_DBEN10_Msk (0x1ul << GPIO_DBEN_DBEN10_Pos) |
| #define | GPIO_DBEN_DBEN11_Pos (11) |
| #define | GPIO_DBEN_DBEN11_Msk (0x1ul << GPIO_DBEN_DBEN11_Pos) |
| #define | GPIO_DBEN_DBEN12_Pos (12) |
| #define | GPIO_DBEN_DBEN12_Msk (0x1ul << GPIO_DBEN_DBEN12_Pos) |
| #define | GPIO_DBEN_DBEN13_Pos (13) |
| #define | GPIO_DBEN_DBEN13_Msk (0x1ul << GPIO_DBEN_DBEN13_Pos) |
| #define | GPIO_DBEN_DBEN14_Pos (14) |
| #define | GPIO_DBEN_DBEN14_Msk (0x1ul << GPIO_DBEN_DBEN14_Pos) |
| #define | GPIO_DBEN_DBEN15_Pos (15) |
| #define | GPIO_DBEN_DBEN15_Msk (0x1ul << GPIO_DBEN_DBEN15_Pos) |
| #define | GPIO_INTTYPE_TYPE0_Pos (0) |
| #define | GPIO_INTTYPE_TYPE0_Msk (0x1ul << GPIO_INTTYPE_TYPE0_Pos) |
| #define | GPIO_INTTYPE_TYPE1_Pos (1) |
| #define | GPIO_INTTYPE_TYPE1_Msk (0x1ul << GPIO_INTTYPE_TYPE1_Pos) |
| #define | GPIO_INTTYPE_TYPE2_Pos (2) |
| #define | GPIO_INTTYPE_TYPE2_Msk (0x1ul << GPIO_INTTYPE_TYPE2_Pos) |
| #define | GPIO_INTTYPE_TYPE3_Pos (3) |
| #define | GPIO_INTTYPE_TYPE3_Msk (0x1ul << GPIO_INTTYPE_TYPE3_Pos) |
| #define | GPIO_INTTYPE_TYPE4_Pos (4) |
| #define | GPIO_INTTYPE_TYPE4_Msk (0x1ul << GPIO_INTTYPE_TYPE4_Pos) |
| #define | GPIO_INTTYPE_TYPE5_Pos (5) |
| #define | GPIO_INTTYPE_TYPE5_Msk (0x1ul << GPIO_INTTYPE_TYPE5_Pos) |
| #define | GPIO_INTTYPE_TYPE6_Pos (6) |
| #define | GPIO_INTTYPE_TYPE6_Msk (0x1ul << GPIO_INTTYPE_TYPE6_Pos) |
| #define | GPIO_INTTYPE_TYPE7_Pos (7) |
| #define | GPIO_INTTYPE_TYPE7_Msk (0x1ul << GPIO_INTTYPE_TYPE7_Pos) |
| #define | GPIO_INTTYPE_TYPE8_Pos (8) |
| #define | GPIO_INTTYPE_TYPE8_Msk (0x1ul << GPIO_INTTYPE_TYPE8_Pos) |
| #define | GPIO_INTTYPE_TYPE9_Pos (9) |
| #define | GPIO_INTTYPE_TYPE9_Msk (0x1ul << GPIO_INTTYPE_TYPE9_Pos) |
| #define | GPIO_INTTYPE_TYPE10_Pos (10) |
| #define | GPIO_INTTYPE_TYPE10_Msk (0x1ul << GPIO_INTTYPE_TYPE10_Pos) |
| #define | GPIO_INTTYPE_TYPE11_Pos (11) |
| #define | GPIO_INTTYPE_TYPE11_Msk (0x1ul << GPIO_INTTYPE_TYPE11_Pos) |
| #define | GPIO_INTTYPE_TYPE12_Pos (12) |
| #define | GPIO_INTTYPE_TYPE12_Msk (0x1ul << GPIO_INTTYPE_TYPE12_Pos) |
| #define | GPIO_INTTYPE_TYPE13_Pos (13) |
| #define | GPIO_INTTYPE_TYPE13_Msk (0x1ul << GPIO_INTTYPE_TYPE13_Pos) |
| #define | GPIO_INTTYPE_TYPE14_Pos (14) |
| #define | GPIO_INTTYPE_TYPE14_Msk (0x1ul << GPIO_INTTYPE_TYPE14_Pos) |
| #define | GPIO_INTTYPE_TYPE15_Pos (15) |
| #define | GPIO_INTTYPE_TYPE15_Msk (0x1ul << GPIO_INTTYPE_TYPE15_Pos) |
| #define | GPIO_INTEN_FLIEN0_Pos (0) |
| #define | GPIO_INTEN_FLIEN0_Msk (0x1ul << GPIO_INTEN_FLIEN0_Pos) |
| #define | GPIO_INTEN_FLIEN1_Pos (1) |
| #define | GPIO_INTEN_FLIEN1_Msk (0x1ul << GPIO_INTEN_FLIEN1_Pos) |
| #define | GPIO_INTEN_FLIEN2_Pos (2) |
| #define | GPIO_INTEN_FLIEN2_Msk (0x1ul << GPIO_INTEN_FLIEN2_Pos) |
| #define | GPIO_INTEN_FLIEN3_Pos (3) |
| #define | GPIO_INTEN_FLIEN3_Msk (0x1ul << GPIO_INTEN_FLIEN3_Pos) |
| #define | GPIO_INTEN_FLIEN4_Pos (4) |
| #define | GPIO_INTEN_FLIEN4_Msk (0x1ul << GPIO_INTEN_FLIEN4_Pos) |
| #define | GPIO_INTEN_FLIEN5_Pos (5) |
| #define | GPIO_INTEN_FLIEN5_Msk (0x1ul << GPIO_INTEN_FLIEN5_Pos) |
| #define | GPIO_INTEN_FLIEN6_Pos (6) |
| #define | GPIO_INTEN_FLIEN6_Msk (0x1ul << GPIO_INTEN_FLIEN6_Pos) |
| #define | GPIO_INTEN_FLIEN7_Pos (7) |
| #define | GPIO_INTEN_FLIEN7_Msk (0x1ul << GPIO_INTEN_FLIEN7_Pos) |
| #define | GPIO_INTEN_FLIEN8_Pos (8) |
| #define | GPIO_INTEN_FLIEN8_Msk (0x1ul << GPIO_INTEN_FLIEN8_Pos) |
| #define | GPIO_INTEN_FLIEN9_Pos (9) |
| #define | GPIO_INTEN_FLIEN9_Msk (0x1ul << GPIO_INTEN_FLIEN9_Pos) |
| #define | GPIO_INTEN_FLIEN10_Pos (10) |
| #define | GPIO_INTEN_FLIEN10_Msk (0x1ul << GPIO_INTEN_FLIEN10_Pos) |
| #define | GPIO_INTEN_FLIEN11_Pos (11) |
| #define | GPIO_INTEN_FLIEN11_Msk (0x1ul << GPIO_INTEN_FLIEN11_Pos) |
| #define | GPIO_INTEN_FLIEN12_Pos (12) |
| #define | GPIO_INTEN_FLIEN12_Msk (0x1ul << GPIO_INTEN_FLIEN12_Pos) |
| #define | GPIO_INTEN_FLIEN13_Pos (13) |
| #define | GPIO_INTEN_FLIEN13_Msk (0x1ul << GPIO_INTEN_FLIEN13_Pos) |
| #define | GPIO_INTEN_FLIEN14_Pos (14) |
| #define | GPIO_INTEN_FLIEN14_Msk (0x1ul << GPIO_INTEN_FLIEN14_Pos) |
| #define | GPIO_INTEN_FLIEN15_Pos (15) |
| #define | GPIO_INTEN_FLIEN15_Msk (0x1ul << GPIO_INTEN_FLIEN15_Pos) |
| #define | GPIO_INTEN_RHIEN0_Pos (16) |
| #define | GPIO_INTEN_RHIEN0_Msk (0x1ul << GPIO_INTEN_RHIEN0_Pos) |
| #define | GPIO_INTEN_RHIEN1_Pos (17) |
| #define | GPIO_INTEN_RHIEN1_Msk (0x1ul << GPIO_INTEN_RHIEN1_Pos) |
| #define | GPIO_INTEN_RHIEN2_Pos (18) |
| #define | GPIO_INTEN_RHIEN2_Msk (0x1ul << GPIO_INTEN_RHIEN2_Pos) |
| #define | GPIO_INTEN_RHIEN3_Pos (19) |
| #define | GPIO_INTEN_RHIEN3_Msk (0x1ul << GPIO_INTEN_RHIEN3_Pos) |
| #define | GPIO_INTEN_RHIEN4_Pos (20) |
| #define | GPIO_INTEN_RHIEN4_Msk (0x1ul << GPIO_INTEN_RHIEN4_Pos) |
| #define | GPIO_INTEN_RHIEN5_Pos (21) |
| #define | GPIO_INTEN_RHIEN5_Msk (0x1ul << GPIO_INTEN_RHIEN5_Pos) |
| #define | GPIO_INTEN_RHIEN6_Pos (22) |
| #define | GPIO_INTEN_RHIEN6_Msk (0x1ul << GPIO_INTEN_RHIEN6_Pos) |
| #define | GPIO_INTEN_RHIEN7_Pos (23) |
| #define | GPIO_INTEN_RHIEN7_Msk (0x1ul << GPIO_INTEN_RHIEN7_Pos) |
| #define | GPIO_INTEN_RHIEN8_Pos (24) |
| #define | GPIO_INTEN_RHIEN8_Msk (0x1ul << GPIO_INTEN_RHIEN8_Pos) |
| #define | GPIO_INTEN_RHIEN9_Pos (25) |
| #define | GPIO_INTEN_RHIEN9_Msk (0x1ul << GPIO_INTEN_RHIEN9_Pos) |
| #define | GPIO_INTEN_RHIEN10_Pos (26) |
| #define | GPIO_INTEN_RHIEN10_Msk (0x1ul << GPIO_INTEN_RHIEN10_Pos) |
| #define | GPIO_INTEN_RHIEN11_Pos (27) |
| #define | GPIO_INTEN_RHIEN11_Msk (0x1ul << GPIO_INTEN_RHIEN11_Pos) |
| #define | GPIO_INTEN_RHIEN12_Pos (28) |
| #define | GPIO_INTEN_RHIEN12_Msk (0x1ul << GPIO_INTEN_RHIEN12_Pos) |
| #define | GPIO_INTEN_RHIEN13_Pos (29) |
| #define | GPIO_INTEN_RHIEN13_Msk (0x1ul << GPIO_INTEN_RHIEN13_Pos) |
| #define | GPIO_INTEN_RHIEN14_Pos (30) |
| #define | GPIO_INTEN_RHIEN14_Msk (0x1ul << GPIO_INTEN_RHIEN14_Pos) |
| #define | GPIO_INTEN_RHIEN15_Pos (31) |
| #define | GPIO_INTEN_RHIEN15_Msk (0x1ul << GPIO_INTEN_RHIEN15_Pos) |
| #define | GPIO_INTSRC_INTSRC0_Pos (0) |
| #define | GPIO_INTSRC_INTSRC0_Msk (0x1ul << GPIO_INTSRC_INTSRC0_Pos) |
| #define | GPIO_INTSRC_INTSRC1_Pos (1) |
| #define | GPIO_INTSRC_INTSRC1_Msk (0x1ul << GPIO_INTSRC_INTSRC1_Pos) |
| #define | GPIO_INTSRC_INTSRC2_Pos (2) |
| #define | GPIO_INTSRC_INTSRC2_Msk (0x1ul << GPIO_INTSRC_INTSRC2_Pos) |
| #define | GPIO_INTSRC_INTSRC3_Pos (3) |
| #define | GPIO_INTSRC_INTSRC3_Msk (0x1ul << GPIO_INTSRC_INTSRC3_Pos) |
| #define | GPIO_INTSRC_INTSRC4_Pos (4) |
| #define | GPIO_INTSRC_INTSRC4_Msk (0x1ul << GPIO_INTSRC_INTSRC4_Pos) |
| #define | GPIO_INTSRC_INTSRC5_Pos (5) |
| #define | GPIO_INTSRC_INTSRC5_Msk (0x1ul << GPIO_INTSRC_INTSRC5_Pos) |
| #define | GPIO_INTSRC_INTSRC6_Pos (6) |
| #define | GPIO_INTSRC_INTSRC6_Msk (0x1ul << GPIO_INTSRC_INTSRC6_Pos) |
| #define | GPIO_INTSRC_INTSRC7_Pos (7) |
| #define | GPIO_INTSRC_INTSRC7_Msk (0x1ul << GPIO_INTSRC_INTSRC7_Pos) |
| #define | GPIO_INTSRC_INTSRC8_Pos (8) |
| #define | GPIO_INTSRC_INTSRC8_Msk (0x1ul << GPIO_INTSRC_INTSRC8_Pos) |
| #define | GPIO_INTSRC_INTSRC9_Pos (9) |
| #define | GPIO_INTSRC_INTSRC9_Msk (0x1ul << GPIO_INTSRC_INTSRC9_Pos) |
| #define | GPIO_INTSRC_INTSRC10_Pos (10) |
| #define | GPIO_INTSRC_INTSRC10_Msk (0x1ul << GPIO_INTSRC_INTSRC10_Pos) |
| #define | GPIO_INTSRC_INTSRC11_Pos (11) |
| #define | GPIO_INTSRC_INTSRC11_Msk (0x1ul << GPIO_INTSRC_INTSRC11_Pos) |
| #define | GPIO_INTSRC_INTSRC12_Pos (12) |
| #define | GPIO_INTSRC_INTSRC12_Msk (0x1ul << GPIO_INTSRC_INTSRC12_Pos) |
| #define | GPIO_INTSRC_INTSRC13_Pos (13) |
| #define | GPIO_INTSRC_INTSRC13_Msk (0x1ul << GPIO_INTSRC_INTSRC13_Pos) |
| #define | GPIO_INTSRC_INTSRC14_Pos (14) |
| #define | GPIO_INTSRC_INTSRC14_Msk (0x1ul << GPIO_INTSRC_INTSRC14_Pos) |
| #define | GPIO_INTSRC_INTSRC15_Pos (15) |
| #define | GPIO_INTSRC_INTSRC15_Msk (0x1ul << GPIO_INTSRC_INTSRC15_Pos) |
| #define | GPIO_SMTEN_SMTEN0_Pos (0) |
| #define | GPIO_SMTEN_SMTEN0_Msk (0x1ul << GPIO_SMTEN_SMTEN0_Pos) |
| #define | GPIO_SMTEN_SMTEN1_Pos (1) |
| #define | GPIO_SMTEN_SMTEN1_Msk (0x1ul << GPIO_SMTEN_SMTEN1_Pos) |
| #define | GPIO_SMTEN_SMTEN2_Pos (2) |
| #define | GPIO_SMTEN_SMTEN2_Msk (0x1ul << GPIO_SMTEN_SMTEN2_Pos) |
| #define | GPIO_SMTEN_SMTEN3_Pos (3) |
| #define | GPIO_SMTEN_SMTEN3_Msk (0x1ul << GPIO_SMTEN_SMTEN3_Pos) |
| #define | GPIO_SMTEN_SMTEN4_Pos (4) |
| #define | GPIO_SMTEN_SMTEN4_Msk (0x1ul << GPIO_SMTEN_SMTEN4_Pos) |
| #define | GPIO_SMTEN_SMTEN5_Pos (5) |
| #define | GPIO_SMTEN_SMTEN5_Msk (0x1ul << GPIO_SMTEN_SMTEN5_Pos) |
| #define | GPIO_SMTEN_SMTEN6_Pos (6) |
| #define | GPIO_SMTEN_SMTEN6_Msk (0x1ul << GPIO_SMTEN_SMTEN6_Pos) |
| #define | GPIO_SMTEN_SMTEN7_Pos (7) |
| #define | GPIO_SMTEN_SMTEN7_Msk (0x1ul << GPIO_SMTEN_SMTEN7_Pos) |
| #define | GPIO_SMTEN_SMTEN8_Pos (8) |
| #define | GPIO_SMTEN_SMTEN8_Msk (0x1ul << GPIO_SMTEN_SMTEN8_Pos) |
| #define | GPIO_SMTEN_SMTEN9_Pos (9) |
| #define | GPIO_SMTEN_SMTEN9_Msk (0x1ul << GPIO_SMTEN_SMTEN9_Pos) |
| #define | GPIO_SMTEN_SMTEN10_Pos (10) |
| #define | GPIO_SMTEN_SMTEN10_Msk (0x1ul << GPIO_SMTEN_SMTEN10_Pos) |
| #define | GPIO_SMTEN_SMTEN11_Pos (11) |
| #define | GPIO_SMTEN_SMTEN11_Msk (0x1ul << GPIO_SMTEN_SMTEN11_Pos) |
| #define | GPIO_SMTEN_SMTEN12_Pos (12) |
| #define | GPIO_SMTEN_SMTEN12_Msk (0x1ul << GPIO_SMTEN_SMTEN12_Pos) |
| #define | GPIO_SMTEN_SMTEN13_Pos (13) |
| #define | GPIO_SMTEN_SMTEN13_Msk (0x1ul << GPIO_SMTEN_SMTEN13_Pos) |
| #define | GPIO_SMTEN_SMTEN14_Pos (14) |
| #define | GPIO_SMTEN_SMTEN14_Msk (0x1ul << GPIO_SMTEN_SMTEN14_Pos) |
| #define | GPIO_SMTEN_SMTEN15_Pos (15) |
| #define | GPIO_SMTEN_SMTEN15_Msk (0x1ul << GPIO_SMTEN_SMTEN15_Pos) |
| #define | GPIO_SLEWCTL_HSREN0_Pos (0) |
| #define | GPIO_SLEWCTL_HSREN0_Msk (0x1ul << GPIO_SLEWCTL_HSREN0_Pos) |
| #define | GPIO_SLEWCTL_HSREN1_Pos (1) |
| #define | GPIO_SLEWCTL_HSREN1_Msk (0x1ul << GPIO_SLEWCTL_HSREN1_Pos) |
| #define | GPIO_SLEWCTL_HSREN2_Pos (2) |
| #define | GPIO_SLEWCTL_HSREN2_Msk (0x1ul << GPIO_SLEWCTL_HSREN2_Pos) |
| #define | GPIO_SLEWCTL_HSREN3_Pos (3) |
| #define | GPIO_SLEWCTL_HSREN3_Msk (0x1ul << GPIO_SLEWCTL_HSREN3_Pos) |
| #define | GPIO_SLEWCTL_HSREN4_Pos (4) |
| #define | GPIO_SLEWCTL_HSREN4_Msk (0x1ul << GPIO_SLEWCTL_HSREN4_Pos) |
| #define | GPIO_SLEWCTL_HSREN5_Pos (5) |
| #define | GPIO_SLEWCTL_HSREN5_Msk (0x1ul << GPIO_SLEWCTL_HSREN5_Pos) |
| #define | GPIO_SLEWCTL_HSREN6_Pos (6) |
| #define | GPIO_SLEWCTL_HSREN6_Msk (0x1ul << GPIO_SLEWCTL_HSREN6_Pos) |
| #define | GPIO_SLEWCTL_HSREN7_Pos (7) |
| #define | GPIO_SLEWCTL_HSREN7_Msk (0x1ul << GPIO_SLEWCTL_HSREN7_Pos) |
| #define | GPIO_SLEWCTL_HSREN8_Pos (8) |
| #define | GPIO_SLEWCTL_HSREN8_Msk (0x1ul << GPIO_SLEWCTL_HSREN8_Pos) |
| #define | GPIO_SLEWCTL_HSREN9_Pos (9) |
| #define | GPIO_SLEWCTL_HSREN9_Msk (0x1ul << GPIO_SLEWCTL_HSREN9_Pos) |
| #define | GPIO_SLEWCTL_HSREN10_Pos (10) |
| #define | GPIO_SLEWCTL_HSREN10_Msk (0x1ul << GPIO_SLEWCTL_HSREN10_Pos) |
| #define | GPIO_SLEWCTL_HSREN11_Pos (11) |
| #define | GPIO_SLEWCTL_HSREN11_Msk (0x1ul << GPIO_SLEWCTL_HSREN11_Pos) |
| #define | GPIO_SLEWCTL_HSREN12_Pos (12) |
| #define | GPIO_SLEWCTL_HSREN12_Msk (0x1ul << GPIO_SLEWCTL_HSREN12_Pos) |
| #define | GPIO_SLEWCTL_HSREN13_Pos (13) |
| #define | GPIO_SLEWCTL_HSREN13_Msk (0x1ul << GPIO_SLEWCTL_HSREN13_Pos) |
| #define | GPIO_SLEWCTL_HSREN14_Pos (14) |
| #define | GPIO_SLEWCTL_HSREN14_Msk (0x1ul << GPIO_SLEWCTL_HSREN14_Pos) |
| #define | GPIO_SLEWCTL_HSREN15_Pos (15) |
| #define | GPIO_SLEWCTL_HSREN15_Msk (0x1ul << GPIO_SLEWCTL_HSREN15_Pos) |
| #define | GPIO_DBCTL_DBCLKSEL_Pos (0) |
| #define | GPIO_DBCTL_DBCLKSEL_Msk (0xful << GPIO_DBCTL_DBCLKSEL_Pos) |
| #define | GPIO_DBCTL_DBCLKSRC_Pos (4) |
| #define | GPIO_DBCTL_DBCLKSRC_Msk (0x1ul << GPIO_DBCTL_DBCLKSRC_Pos) |
| #define | GPIO_DBCTL_ICLKON_Pos (5) |
| #define | GPIO_DBCTL_ICLKON_Msk (0x1ul << GPIO_DBCTL_ICLKON_Pos) |
| #define | I2C_CTL_AA_Pos (2) |
| #define | I2C_CTL_AA_Msk (0x1ul << I2C_CTL_AA_Pos) |
| #define | I2C_CTL_SI_Pos (3) |
| #define | I2C_CTL_SI_Msk (0x1ul << I2C_CTL_SI_Pos) |
| #define | I2C_CTL_STO_Pos (4) |
| #define | I2C_CTL_STO_Msk (0x1ul << I2C_CTL_STO_Pos) |
| #define | I2C_CTL_STA_Pos (5) |
| #define | I2C_CTL_STA_Msk (0x1ul << I2C_CTL_STA_Pos) |
| #define | I2C_CTL_I2CEN_Pos (6) |
| #define | I2C_CTL_I2CEN_Msk (0x1ul << I2C_CTL_I2CEN_Pos) |
| #define | I2C_CTL_INTEN_Pos (7) |
| #define | I2C_CTL_INTEN_Msk (0x1ul << I2C_CTL_INTEN_Pos) |
| #define | I2C_ADDR0_GC_Pos (0) |
| #define | I2C_ADDR0_GC_Msk (0x1ul << I2C_ADDR0_GC_Pos) |
| #define | I2C_ADDR0_ADDR_Pos (1) |
| #define | I2C_ADDR0_ADDR_Msk (0x7ful << I2C_ADDR0_ADDR_Pos) |
| #define | I2C_DAT_DAT_Pos (0) |
| #define | I2C_DAT_DAT_Msk (0xfful << I2C_DAT_DAT_Pos) |
| #define | I2C_STATUS_STATUS_Pos (0) |
| #define | I2C_STATUS_STATUS_Msk (0xfful << I2C_STATUS_STATUS_Pos) |
| #define | I2C_CLKDIV_DIVIDER_Pos (0) |
| #define | I2C_CLKDIV_DIVIDER_Msk (0xfful << I2C_CLKDIV_DIVIDER_Pos) |
| #define | I2C_TOCTL_TOIF_Pos (0) |
| #define | I2C_TOCTL_TOIF_Msk (0x1ul << I2C_TOCTL_TOIF_Pos) |
| #define | I2C_TOCTL_TOCDIV4_Pos (1) |
| #define | I2C_TOCTL_TOCDIV4_Msk (0x1ul << I2C_TOCTL_TOCDIV4_Pos) |
| #define | I2C_TOCTL_TOCEN_Pos (2) |
| #define | I2C_TOCTL_TOCEN_Msk (0x1ul << I2C_TOCTL_TOCEN_Pos) |
| #define | I2C_ADDR1_GC_Pos (0) |
| #define | I2C_ADDR1_GC_Msk (0x1ul << I2C_ADDR1_GC_Pos) |
| #define | I2C_ADDR1_ADDR_Pos (1) |
| #define | I2C_ADDR1_ADDR_Msk (0x7ful << I2C_ADDR1_ADDR_Pos) |
| #define | I2C_ADDR2_GC_Pos (0) |
| #define | I2C_ADDR2_GC_Msk (0x1ul << I2C_ADDR2_GC_Pos) |
| #define | I2C_ADDR2_ADDR_Pos (1) |
| #define | I2C_ADDR2_ADDR_Msk (0x7ful << I2C_ADDR2_ADDR_Pos) |
| #define | I2C_ADDR3_GC_Pos (0) |
| #define | I2C_ADDR3_GC_Msk (0x1ul << I2C_ADDR3_GC_Pos) |
| #define | I2C_ADDR3_ADDR_Pos (1) |
| #define | I2C_ADDR3_ADDR_Msk (0x7ful << I2C_ADDR3_ADDR_Pos) |
| #define | I2C_ADDRMSK0_ADDRMSK_Pos (1) |
| #define | I2C_ADDRMSK0_ADDRMSK_Msk (0x7ful << I2C_ADDRMSK0_ADDRMSK_Pos) |
| #define | I2C_ADDRMSK1_ADDRMSK_Pos (1) |
| #define | I2C_ADDRMSK1_ADDRMSK_Msk (0x7ful << I2C_ADDRMSK1_ADDRMSK_Pos) |
| #define | I2C_ADDRMSK2_ADDRMSK_Pos (1) |
| #define | I2C_ADDRMSK2_ADDRMSK_Msk (0x7ful << I2C_ADDRMSK2_ADDRMSK_Pos) |
| #define | I2C_ADDRMSK3_ADDRMSK_Pos (1) |
| #define | I2C_ADDRMSK3_ADDRMSK_Msk (0x7ful << I2C_ADDRMSK3_ADDRMSK_Pos) |
| #define | I2C_WKCTL_WKEN_Pos (0) |
| #define | I2C_WKCTL_WKEN_Msk (0x1ul << I2C_WKCTL_WKEN_Pos) |
| #define | I2C_WKSTS_WKIF_Pos (0) |
| #define | I2C_WKSTS_WKIF_Msk (0x1ul << I2C_WKSTS_WKIF_Pos) |
| #define | I2S_CTL_I2SEN_Pos (0) |
| #define | I2S_CTL_I2SEN_Msk (0x1ul << I2S_CTL_I2SEN_Pos) |
| #define | I2S_CTL_TXEN_Pos (1) |
| #define | I2S_CTL_TXEN_Msk (0x1ul << I2S_CTL_TXEN_Pos) |
| #define | I2S_CTL_RXEN_Pos (2) |
| #define | I2S_CTL_RXEN_Msk (0x1ul << I2S_CTL_RXEN_Pos) |
| #define | I2S_CTL_MUTE_Pos (3) |
| #define | I2S_CTL_MUTE_Msk (0x1ul << I2S_CTL_MUTE_Pos) |
| #define | I2S_CTL_WDWIDTH_Pos (4) |
| #define | I2S_CTL_WDWIDTH_Msk (0x3ul << I2S_CTL_WDWIDTH_Pos) |
| #define | I2S_CTL_MONO_Pos (6) |
| #define | I2S_CTL_MONO_Msk (0x1ul << I2S_CTL_MONO_Pos) |
| #define | I2S_CTL_FORMAT_Pos (7) |
| #define | I2S_CTL_FORMAT_Msk (0x1ul << I2S_CTL_FORMAT_Pos) |
| #define | I2S_CTL_SLAVE_Pos (8) |
| #define | I2S_CTL_SLAVE_Msk (0x1ul << I2S_CTL_SLAVE_Pos) |
| #define | I2S_CTL_TXTH_Pos (9) |
| #define | I2S_CTL_TXTH_Msk (0x7ul << I2S_CTL_TXTH_Pos) |
| #define | I2S_CTL_RXTH_Pos (12) |
| #define | I2S_CTL_RXTH_Msk (0x7ul << I2S_CTL_RXTH_Pos) |
| #define | I2S_CTL_MCLKEN_Pos (15) |
| #define | I2S_CTL_MCLKEN_Msk (0x1ul << I2S_CTL_MCLKEN_Pos) |
| #define | I2S_CTL_RZCEN_Pos (16) |
| #define | I2S_CTL_RZCEN_Msk (0x1ul << I2S_CTL_RZCEN_Pos) |
| #define | I2S_CTL_LZCEN_Pos (17) |
| #define | I2S_CTL_LZCEN_Msk (0x1ul << I2S_CTL_LZCEN_Pos) |
| #define | I2S_CTL_TXCLR_Pos (18) |
| #define | I2S_CTL_TXCLR_Msk (0x1ul << I2S_CTL_TXCLR_Pos) |
| #define | I2S_CTL_RXCLR_Pos (19) |
| #define | I2S_CTL_RXCLR_Msk (0x1ul << I2S_CTL_RXCLR_Pos) |
| #define | I2S_CTL_TXPDMAEN_Pos (20) |
| #define | I2S_CTL_TXPDMAEN_Msk (0x1ul << I2S_CTL_TXPDMAEN_Pos) |
| #define | I2S_CTL_RXPDMAEN_Pos (21) |
| #define | I2S_CTL_RXPDMAEN_Msk (0x1ul << I2S_CTL_RXPDMAEN_Pos) |
| #define | I2S_CTL_RXLCH_Pos (23) |
| #define | I2S_CTL_RXLCH_Msk (0x1ul << I2S_CTL_RXLCH_Pos) |
| #define | I2S_CTL_PCMEN_Pos (24) |
| #define | I2S_CTL_PCMEN_Msk (0x1ul << I2S_CTL_PCMEN_Pos) |
| #define | I2S_CLKDIV_MCLKDIV_Pos (0) |
| #define | I2S_CLKDIV_MCLKDIV_Msk (0x3ful << I2S_CLKDIV_MCLKDIV_Pos) |
| #define | I2S_CLKDIV_BCLKDIV_Pos (8) |
| #define | I2S_CLKDIV_BCLKDIV_Msk (0x1fful << I2S_CLKDIV_BCLKDIV_Pos) |
| #define | I2S_IEN_RXUDIEN_Pos (0) |
| #define | I2S_IEN_RXUDIEN_Msk (0x1ul << I2S_IEN_RXUDIEN_Pos) |
| #define | I2S_IEN_RXOVIEN_Pos (1) |
| #define | I2S_IEN_RXOVIEN_Msk (0x1ul << I2S_IEN_RXOVIEN_Pos) |
| #define | I2S_IEN_RXTHIEN_Pos (2) |
| #define | I2S_IEN_RXTHIEN_Msk (0x1ul << I2S_IEN_RXTHIEN_Pos) |
| #define | I2S_IEN_TXUDIEN_Pos (8) |
| #define | I2S_IEN_TXUDIEN_Msk (0x1ul << I2S_IEN_TXUDIEN_Pos) |
| #define | I2S_IEN_TXOVIEN_Pos (9) |
| #define | I2S_IEN_TXOVIEN_Msk (0x1ul << I2S_IEN_TXOVIEN_Pos) |
| #define | I2S_IEN_TXTHIEN_Pos (10) |
| #define | I2S_IEN_TXTHIEN_Msk (0x1ul << I2S_IEN_TXTHIEN_Pos) |
| #define | I2S_IEN_RZCIEN_Pos (11) |
| #define | I2S_IEN_RZCIEN_Msk (0x1ul << I2S_IEN_RZCIEN_Pos) |
| #define | I2S_IEN_LZCIEN_Pos (12) |
| #define | I2S_IEN_LZCIEN_Msk (0x1ul << I2S_IEN_LZCIEN_Pos) |
| #define | I2S_STATUS_I2SIF_Pos (0) |
| #define | I2S_STATUS_I2SIF_Msk (0x1ul << I2S_STATUS_I2SIF_Pos) |
| #define | I2S_STATUS_RXIF_Pos (1) |
| #define | I2S_STATUS_RXIF_Msk (0x1ul << I2S_STATUS_RXIF_Pos) |
| #define | I2S_STATUS_TXIF_Pos (2) |
| #define | I2S_STATUS_TXIF_Msk (0x1ul << I2S_STATUS_TXIF_Pos) |
| #define | I2S_STATUS_RIGHT_Pos (3) |
| #define | I2S_STATUS_RIGHT_Msk (0x1ul << I2S_STATUS_RIGHT_Pos) |
| #define | I2S_STATUS_RXUDIF_Pos (8) |
| #define | I2S_STATUS_RXUDIF_Msk (0x1ul << I2S_STATUS_RXUDIF_Pos) |
| #define | I2S_STATUS_RXOVIF_Pos (9) |
| #define | I2S_STATUS_RXOVIF_Msk (0x1ul << I2S_STATUS_RXOVIF_Pos) |
| #define | I2S_STATUS_RXTHIF_Pos (10) |
| #define | I2S_STATUS_RXTHIF_Msk (0x1ul << I2S_STATUS_RXTHIF_Pos) |
| #define | I2S_STATUS_RXFULL_Pos (11) |
| #define | I2S_STATUS_RXFULL_Msk (0x1ul << I2S_STATUS_RXFULL_Pos) |
| #define | I2S_STATUS_RXEMPTY_Pos (12) |
| #define | I2S_STATUS_RXEMPTY_Msk (0x1ul << I2S_STATUS_RXEMPTY_Pos) |
| #define | I2S_STATUS_TXUDIF_Pos (16) |
| #define | I2S_STATUS_TXUDIF_Msk (0x1ul << I2S_STATUS_TXUDIF_Pos) |
| #define | I2S_STATUS_TXOVIF_Pos (17) |
| #define | I2S_STATUS_TXOVIF_Msk (0x1ul << I2S_STATUS_TXOVIF_Pos) |
| #define | I2S_STATUS_TXTHIF_Pos (18) |
| #define | I2S_STATUS_TXTHIF_Msk (0x1ul << I2S_STATUS_TXTHIF_Pos) |
| #define | I2S_STATUS_TXFULL_Pos (19) |
| #define | I2S_STATUS_TXFULL_Msk (0x1ul << I2S_STATUS_TXFULL_Pos) |
| #define | I2S_STATUS_TXEMPTY_Pos (20) |
| #define | I2S_STATUS_TXEMPTY_Msk (0x1ul << I2S_STATUS_TXEMPTY_Pos) |
| #define | I2S_STATUS_TXBUSY_Pos (21) |
| #define | I2S_STATUS_TXBUSY_Msk (0x1ul << I2S_STATUS_TXBUSY_Pos) |
| #define | I2S_STATUS_RZCIF_Pos (22) |
| #define | I2S_STATUS_RZCIF_Msk (0x1ul << I2S_STATUS_RZCIF_Pos) |
| #define | I2S_STATUS_LZCIF_Pos (23) |
| #define | I2S_STATUS_LZCIF_Msk (0x1ul << I2S_STATUS_LZCIF_Pos) |
| #define | I2S_STATUS_RXCNT_Pos (24) |
| #define | I2S_STATUS_RXCNT_Msk (0xful << I2S_STATUS_RXCNT_Pos) |
| #define | I2S_STATUS_TXCNT_Pos (28) |
| #define | I2S_STATUS_TXCNT_Msk (0xful << I2S_STATUS_TXCNT_Pos) |
| #define | I2S_TX_TX_Pos (0) |
| #define | I2S_TX_TX_Msk (0xfffffffful << I2S_TX_TX_Pos) |
| #define | I2S_RX_RX_Pos (0) |
| #define | I2S_RX_RX_Msk (0xfffffffful << I2S_RX_RX_Pos) |
| #define | OPA_CTL_OPEN0_Pos (0) |
| #define | OPA_CTL_OPEN0_Msk (0x1ul << OPA_CTL_OPEN0_Pos) |
| #define | OPA_CTL_OPEN1_Pos (1) |
| #define | OPA_CTL_OPEN1_Msk (0x1ul << OPA_CTL_OPEN1_Pos) |
| #define | OPA_CTL_OPSMTEN0_Pos (4) |
| #define | OPA_CTL_OPSMTEN0_Msk (0x1ul << OPA_CTL_OPSMTEN0_Pos) |
| #define | OPA_CTL_OPSMTEN1_Pos (5) |
| #define | OPA_CTL_OPSMTEN1_Msk (0x1ul << OPA_CTL_OPSMTEN1_Pos) |
| #define | OPA_CTL_OPAIE0_Pos (8) |
| #define | OPA_CTL_OPAIE0_Msk (0x1ul << OPA_CTL_OPAIE0_Pos) |
| #define | OPA_CTL_OPAIE1_Pos (9) |
| #define | OPA_CTL_OPAIE1_Msk (0x1ul << OPA_CTL_OPAIE1_Pos) |
| #define | OPA_STATUS_OPDO0_Pos (0) |
| #define | OPA_STATUS_OPDO0_Msk (0x1ul << OPA_STATUS_OPDO0_Pos) |
| #define | OPA_STATUS_OPDO1_Pos (1) |
| #define | OPA_STATUS_OPDO1_Msk (0x1ul << OPA_STATUS_OPDO1_Pos) |
| #define | OPA_STATUS_OPDF0_Pos (4) |
| #define | OPA_STATUS_OPDF0_Msk (0x1ul << OPA_STATUS_OPDF0_Pos) |
| #define | OPA_STATUS_OPDF1_Pos (5) |
| #define | OPA_STATUS_OPDF1_Msk (0x1ul << OPA_STATUS_OPDF1_Pos) |
| #define | OTG_CTL_VBUSDROP_Pos (0) |
| #define | OTG_CTL_VBUSDROP_Msk (0x1ul << OTG_CTL_VBUSDROP_Pos) |
| #define | OTG_CTL_BUSREQ_Pos (1) |
| #define | OTG_CTL_BUSREQ_Msk (0x1ul << OTG_CTL_BUSREQ_Pos) |
| #define | OTG_CTL_HNPREQEN_Pos (2) |
| #define | OTG_CTL_HNPREQEN_Msk (0x1ul << OTG_CTL_HNPREQEN_Pos) |
| #define | OTG_CTL_OTGEN_Pos (4) |
| #define | OTG_CTL_OTGEN_Msk (0x1ul << OTG_CTL_OTGEN_Pos) |
| #define | OTG_CTL_PDEVCKON_Pos (7) |
| #define | OTG_CTL_PDEVCKON_Msk (0x1ul << OTG_CTL_PDEVCKON_Pos) |
| #define | OTG_CTL_WKEN_Pos (8) |
| #define | OTG_CTL_WKEN_Msk (0x1ul << OTG_CTL_WKEN_Pos) |
| #define | OTG_PHYCTL_SWPDEN_Pos (0) |
| #define | OTG_PHYCTL_SWPDEN_Msk (0x1ul << OTG_PHYCTL_SWPDEN_Pos) |
| #define | OTG_PHYCTL_DPPDEN_Pos (1) |
| #define | OTG_PHYCTL_DPPDEN_Msk (0x1ul << OTG_PHYCTL_DPPDEN_Pos) |
| #define | OTG_PHYCTL_DMPDEN_Pos (2) |
| #define | OTG_PHYCTL_DMPDEN_Msk (0x1ul << OTG_PHYCTL_DMPDEN_Pos) |
| #define | OTG_PHYCTL_VBSTSPOL_Pos (5) |
| #define | OTG_PHYCTL_VBSTSPOL_Msk (0x1ul << OTG_PHYCTL_VBSTSPOL_Pos) |
| #define | OTG_PHYCTL_VBENPOL_Pos (6) |
| #define | OTG_PHYCTL_VBENPOL_Msk (0x1ul << OTG_PHYCTL_VBENPOL_Pos) |
| #define | OTG_PHYCTL_IDDETEN_Pos (7) |
| #define | OTG_PHYCTL_IDDETEN_Msk (0x1ul << OTG_PHYCTL_IDDETEN_Pos) |
| #define | OTG_PHYCTL_PHYCLK_Pos (8) |
| #define | OTG_PHYCTL_PHYCLK_Msk (0x1ul << OTG_PHYCTL_PHYCLK_Pos) |
| #define | OTG_PHYCTL_OTGPHYEN_Pos (9) |
| #define | OTG_PHYCTL_OTGPHYEN_Msk (0x1ul << OTG_PHYCTL_OTGPHYEN_Pos) |
| #define | OTG_INTEN_ROLECHGIEN_Pos (0) |
| #define | OTG_INTEN_ROLECHGIEN_Msk (0x1ul << OTG_INTEN_ROLECHGIEN_Pos) |
| #define | OTG_INTEN_VBEIEN_Pos (1) |
| #define | OTG_INTEN_VBEIEN_Msk (0x1ul << OTG_INTEN_VBEIEN_Pos) |
| #define | OTG_INTEN_SRPFIEN_Pos (2) |
| #define | OTG_INTEN_SRPFIEN_Msk (0x1ul << OTG_INTEN_SRPFIEN_Pos) |
| #define | OTG_INTEN_HNPFIEN_Pos (3) |
| #define | OTG_INTEN_HNPFIEN_Msk (0x1ul << OTG_INTEN_HNPFIEN_Pos) |
| #define | OTG_INTEN_GOIDLEIEN_Pos (4) |
| #define | OTG_INTEN_GOIDLEIEN_Msk (0x1ul << OTG_INTEN_GOIDLEIEN_Pos) |
| #define | OTG_INTEN_IDCHGIEN_Pos (5) |
| #define | OTG_INTEN_IDCHGIEN_Msk (0x1ul << OTG_INTEN_IDCHGIEN_Pos) |
| #define | OTG_INTEN_PDEVIEN_Pos (6) |
| #define | OTG_INTEN_PDEVIEN_Msk (0x1ul << OTG_INTEN_PDEVIEN_Pos) |
| #define | OTG_INTEN_HOSTIEN_Pos (7) |
| #define | OTG_INTEN_HOSTIEN_Msk (0x1ul << OTG_INTEN_HOSTIEN_Pos) |
| #define | OTG_INTEN_BVLDCHGIEN_Pos (8) |
| #define | OTG_INTEN_BVLDCHGIEN_Msk (0x1ul << OTG_INTEN_BVLDCHGIEN_Pos) |
| #define | OTG_INTEN_AVLDCHGIEN_Pos (9) |
| #define | OTG_INTEN_AVLDCHGIEN_Msk (0x1ul << OTG_INTEN_AVLDCHGIEN_Pos) |
| #define | OTG_INTEN_VBCHGIEN_Pos (10) |
| #define | OTG_INTEN_VBCHGIEN_Msk (0x1ul << OTG_INTEN_VBCHGIEN_Pos) |
| #define | OTG_INTEN_SECHGIEN_Pos (11) |
| #define | OTG_INTEN_SECHGIEN_Msk (0x1ul << OTG_INTEN_SECHGIEN_Pos) |
| #define | OTG_INTEN_SRPDETIEN_Pos (13) |
| #define | OTG_INTEN_SRPDETIEN_Msk (0x1ul << OTG_INTEN_SRPDETIEN_Pos) |
| #define | OTG_INTSTS_ROLECHGIF_Pos (0) |
| #define | OTG_INTSTS_ROLECHGIF_Msk (0x1ul << OTG_INTSTS_ROLECHGIF_Pos) |
| #define | OTG_INTSTS_VBEIF_Pos (1) |
| #define | OTG_INTSTS_VBEIF_Msk (0x1ul << OTG_INTSTS_VBEIF_Pos) |
| #define | OTG_INTSTS_SRPFIF_Pos (2) |
| #define | OTG_INTSTS_SRPFIF_Msk (0x1ul << OTG_INTSTS_SRPFIF_Pos) |
| #define | OTG_INTSTS_HNPFIF_Pos (3) |
| #define | OTG_INTSTS_HNPFIF_Msk (0x1ul << OTG_INTSTS_HNPFIF_Pos) |
| #define | OTG_INTSTS_GOIDLEIF_Pos (4) |
| #define | OTG_INTSTS_GOIDLEIF_Msk (0x1ul << OTG_INTSTS_GOIDLEIF_Pos) |
| #define | OTG_INTSTS_IDCHGIF_Pos (5) |
| #define | OTG_INTSTS_IDCHGIF_Msk (0x1ul << OTG_INTSTS_IDCHGIF_Pos) |
| #define | OTG_INTSTS_PDEVIF_Pos (6) |
| #define | OTG_INTSTS_PDEVIF_Msk (0x1ul << OTG_INTSTS_PDEVIF_Pos) |
| #define | OTG_INTSTS_HOSTIF_Pos (7) |
| #define | OTG_INTSTS_HOSTIF_Msk (0x1ul << OTG_INTSTS_HOSTIF_Pos) |
| #define | OTG_INTSTS_BVLDCHGIF_Pos (8) |
| #define | OTG_INTSTS_BVLDCHGIF_Msk (0x1ul << OTG_INTSTS_BVLDCHGIF_Pos) |
| #define | OTG_INTSTS_AVLDCHGIF_Pos (9) |
| #define | OTG_INTSTS_AVLDCHGIF_Msk (0x1ul << OTG_INTSTS_AVLDCHGIF_Pos) |
| #define | OTG_INTSTS_VBCHGIF_Pos (10) |
| #define | OTG_INTSTS_VBCHGIF_Msk (0x1ul << OTG_INTSTS_VBCHGIF_Pos) |
| #define | OTG_INTSTS_SECHGIF_Pos (11) |
| #define | OTG_INTSTS_SECHGIF_Msk (0x1ul << OTG_INTSTS_SECHGIF_Pos) |
| #define | OTG_INTSTS_SRPDETIF_Pos (13) |
| #define | OTG_INTSTS_SRPDETIF_Msk (0x1ul << OTG_INTSTS_SRPDETIF_Pos) |
| #define | OTG_STATUS_OVERCUR_Pos (0) |
| #define | OTG_STATUS_OVERCUR_Msk (0x1ul << OTG_STATUS_OVERCUR_Pos) |
| #define | OTG_STATUS_IDSTS_Pos (1) |
| #define | OTG_STATUS_IDSTS_Msk (0x1ul << OTG_STATUS_IDSTS_Pos) |
| #define | OTG_STATUS_SESSEND_Pos (2) |
| #define | OTG_STATUS_SESSEND_Msk (0x1ul << OTG_STATUS_SESSEND_Pos) |
| #define | OTG_STATUS_BVLD_Pos (3) |
| #define | OTG_STATUS_BVLD_Msk (0x1ul << OTG_STATUS_BVLD_Pos) |
| #define | OTG_STATUS_AVLD_Pos (4) |
| #define | OTG_STATUS_AVLD_Msk (0x1ul << OTG_STATUS_AVLD_Pos) |
| #define | OTG_STATUS_VBUSVLD_Pos (5) |
| #define | OTG_STATUS_VBUSVLD_Msk (0x1ul << OTG_STATUS_VBUSVLD_Pos) |
| #define | PDMA_DSCT_CTL_OPMODE_Pos (0) |
| #define | PDMA_DSCT_CTL_OPMODE_Msk (0x3ul << PDMA_DSCT_CTL_OPMODE_Pos) |
| #define | PDMA_DSCT_CTL_TXTYPE_Pos (2) |
| #define | PDMA_DSCT_CTL_TXTYPE_Msk (0x1ul << PDMA_DSCT_CTL_TXTYPE_Pos) |
| #define | PDMA_DSCT_CTL_BURSIZE_Pos (4) |
| #define | PDMA_DSCT_CTL_BURSIZE_Msk (0x7ul << PDMA_DSCT_CTL_BURSIZE_Pos) |
| #define | PDMA_DSCT_CTL_TBINTDIS_Pos (7) |
| #define | PDMA_DSCT_CTL_TBINTDIS_Msk (0x1ul << PDMA_DSCT_CTL_TBINTDIS_Pos) |
| #define | PDMA_DSCT_CTL_SAINC_Pos (8) |
| #define | PDMA_DSCT_CTL_SAINC_Msk (0x3ul << PDMA_DSCT_CTL_SAINC_Pos) |
| #define | PDMA_DSCT_CTL_DAINC_Pos (10) |
| #define | PDMA_DSCT_CTL_DAINC_Msk (0x3ul << PDMA_DSCT_CTL_DAINC_Pos) |
| #define | PDMA_DSCT_CTL_TXWIDTH_Pos (12) |
| #define | PDMA_DSCT_CTL_TXWIDTH_Msk (0x3ul << PDMA_DSCT_CTL_TXWIDTH_Pos) |
| #define | PDMA_DSCT_CTL_TXCNT_Pos (16) |
| #define | PDMA_DSCT_CTL_TXCNT_Msk (0x3ffful << PDMA_DSCT_CTL_TXCNT_Pos) |
| #define | PDMA_DSCT_ENDSA_ENDSA_Pos (0) |
| #define | PDMA_DSCT_ENDSA_ENDSA_Msk (0xfffffffful << PDMA_DSCT_ENDSA_ENDSA_Pos) |
| #define | PDMA_DSCT_ENDDA_ENDDA_Pos (0) |
| #define | PDMA_DSCT_ENDDA_ENDDA_Msk (0xfffffffful << PDMA_DSCT_ENDDA_ENDDA_Pos) |
| #define | PDMA_DSCT_NEXT_NEXT_Pos (2) |
| #define | PDMA_DSCT_NEXT_NEXT_Msk (0x3ffful << PDMA_DSCT_NEXT_NEXT_Pos) |
| #define | PDMA_CHCTL_CHEN_Pos (0) |
| #define | PDMA_CHCTL_CHEN_Msk (0xfffful << PDMA_CHCTL_CHEN_Pos) |
| #define | PDMA_STOP_STOP_Pos (0) |
| #define | PDMA_STOP_STOP_Msk (0xfffful << PDMA_STOP_STOP_Pos) |
| #define | PDMA_SWREQ_SWREQ_Pos (0) |
| #define | PDMA_SWREQ_SWREQ_Msk (0xffful << PDMA_SWREQ_SWREQ_Pos) |
| #define | PDMA_TRGSTS_REQSTS_Pos (0) |
| #define | PDMA_TRGSTS_REQSTS_Msk (0xfffful << PDMA_TRGSTS_REQSTS_Pos) |
| #define | PDMA_PRISET_FPRISET_Pos (0) |
| #define | PDMA_PRISET_FPRISET_Msk (0xfffful << PDMA_PRISET_FPRISET_Pos) |
| #define | PDMA_PRICLR_FPRICLR_Pos (0) |
| #define | PDMA_PRICLR_FPRICLR_Msk (0xfffful << PDMA_PRICLR_FPRICLR_Pos) |
| #define | PDMA_INTEN_INTEN_Pos (0) |
| #define | PDMA_INTEN_INTEN_Msk (0xfffful << PDMA_INTEN_INTEN_Pos) |
| #define | PDMA_INTSTS_ABTIF_Pos (0) |
| #define | PDMA_INTSTS_ABTIF_Msk (0x1ul << PDMA_INTSTS_ABTIF_Pos) |
| #define | PDMA_INTSTS_TDIF_Pos (1) |
| #define | PDMA_INTSTS_TDIF_Msk (0x1ul << PDMA_INTSTS_TDIF_Pos) |
| #define | PDMA_INTSTS_TEIF_Pos (2) |
| #define | PDMA_INTSTS_TEIF_Msk (0x1ul << PDMA_INTSTS_TEIF_Pos) |
| #define | PDMA_ABTSTS_ABTIF_Pos (0) |
| #define | PDMA_ABTSTS_ABTIF_Msk (0xfffful << PDMA_ABTSTS_ABTIF_Pos) |
| #define | PDMA_TDSTS_TDIF_Pos (0) |
| #define | PDMA_TDSTS_TDIF_Msk (0xfffful << PDMA_TDSTS_TDIF_Pos) |
| #define | PDMA_SCATSTS_TEMPTYF_Pos (0) |
| #define | PDMA_SCATSTS_TEMPTYF_Msk (0xfffful << PDMA_SCATSTS_TEMPTYF_Pos) |
| #define | PDMA_TACTSTS_TXACTF_Pos (0) |
| #define | PDMA_TACTSTS_TXACTF_Msk (0xfffful << PDMA_TACTSTS_TXACTF_Pos) |
| #define | PDMA_SCATBA_SCATBA_Pos (16) |
| #define | PDMA_SCATBA_SCATBA_Msk (0xfffful << PDMA_SCATBA_SCATBA_Pos) |
| #define | PDMA_REQSEL0_3_REQSRC0_Pos (0) |
| #define | PDMA_REQSEL0_3_REQSRC0_Msk (0x1ful << PDMA_REQSEL0_3_REQSRC0_Pos) |
| #define | PDMA_REQSEL0_3_REQSRC1_Pos (8) |
| #define | PDMA_REQSEL0_3_REQSRC1_Msk (0x1ful << PDMA_REQSEL0_3_REQSRC1_Pos) |
| #define | PDMA_REQSEL0_3_REQSRC2_Pos (16) |
| #define | PDMA_REQSEL0_3_REQSRC2_Msk (0x1ful << PDMA_REQSEL0_3_REQSRC2_Pos) |
| #define | PDMA_REQSEL0_3_REQSRC3_Pos (24) |
| #define | PDMA_REQSEL0_3_REQSRC3_Msk (0x1ful << PDMA_REQSEL0_3_REQSRC3_Pos) |
| #define | PDMA_REQSEL4_7_REQSRC4_Pos (0) |
| #define | PDMA_REQSEL4_7_REQSRC4_Msk (0x1ful << PDMA_REQSEL4_7_REQSRC4_Pos) |
| #define | PDMA_REQSEL4_7_REQSRC5_Pos (8) |
| #define | PDMA_REQSEL4_7_REQSRC5_Msk (0x1ful << PDMA_REQSEL4_7_REQSRC5_Pos) |
| #define | PDMA_REQSEL4_7_REQSRC6_Pos (16) |
| #define | PDMA_REQSEL4_7_REQSRC6_Msk (0x1ful << PDMA_REQSEL4_7_REQSRC6_Pos) |
| #define | PDMA_REQSEL4_7_REQSRC7_Pos (24) |
| #define | PDMA_REQSEL4_7_REQSRC7_Msk (0x1ful << PDMA_REQSEL4_7_REQSRC7_Pos) |
| #define | PDMA_REQSEL8_11_REQSRC8_Pos (0) |
| #define | PDMA_REQSEL8_11_REQSRC8_Msk (0x1ful << PDMA_REQSEL8_11_REQSRC8_Pos) |
| #define | PDMA_REQSEL8_11_REQSRC9_Pos (8) |
| #define | PDMA_REQSEL8_11_REQSRC9_Msk (0x1ful << PDMA_REQSEL8_11_REQSRC9_Pos) |
| #define | PDMA_REQSEL8_11_REQSRC10_Pos (16) |
| #define | PDMA_REQSEL8_11_REQSRC10_Msk (0x1ful << PDMA_REQSEL8_11_REQSRC10_Pos) |
| #define | PDMA_REQSEL8_11_REQSRC11_Pos (24) |
| #define | PDMA_REQSEL8_11_REQSRC11_Msk (0x1ful << PDMA_REQSEL8_11_REQSRC11_Pos) |
| #define | PDMA_REQSEL12_15_REQSRC12_Pos (0) |
| #define | PDMA_REQSEL12_15_REQSRC12_Msk (0x1ful << PDMA_REQSEL12_15_REQSRC12_Pos) |
| #define | PDMA_REQSEL12_15_REQSRC13_Pos (8) |
| #define | PDMA_REQSEL12_15_REQSRC13_Msk (0x1ful << PDMA_REQSEL12_15_REQSRC13_Pos) |
| #define | PDMA_REQSEL12_15_REQSRC14_Pos (16) |
| #define | PDMA_REQSEL12_15_REQSRC14_Msk (0x1ful << PDMA_REQSEL12_15_REQSRC14_Pos) |
| #define | PDMA_REQSEL12_15_REQSRC15_Pos (24) |
| #define | PDMA_REQSEL12_15_REQSRC15_Msk (0x1ful << PDMA_REQSEL12_15_REQSRC15_Pos) |
| #define | PS2_CTL_PS2EN_Pos (0) |
| #define | PS2_CTL_PS2EN_Msk (0x1ul << PS2_CTL_PS2EN_Pos) |
| #define | PS2_CTL_TXIEN_Pos (1) |
| #define | PS2_CTL_TXIEN_Msk (0x1ul << PS2_CTL_TXIEN_Pos) |
| #define | PS2_CTL_RXIEN_Pos (2) |
| #define | PS2_CTL_RXIEN_Msk (0x1ul << PS2_CTL_RXIEN_Pos) |
| #define | PS2_CTL_TXFDEPTH_Pos (3) |
| #define | PS2_CTL_TXFDEPTH_Msk (0xful << PS2_CTL_TXFDEPTH_Pos) |
| #define | PS2_CTL_ACK_Pos (7) |
| #define | PS2_CTL_ACK_Msk (0x1ul << PS2_CTL_ACK_Pos) |
| #define | PS2_CTL_CLRFIFO_Pos (8) |
| #define | PS2_CTL_CLRFIFO_Msk (0x1ul << PS2_CTL_CLRFIFO_Pos) |
| #define | PS2_CTL_OVERRIDE_Pos (9) |
| #define | PS2_CTL_OVERRIDE_Msk (0x1ul << PS2_CTL_OVERRIDE_Pos) |
| #define | PS2_CTL_FPS2CLK_Pos (10) |
| #define | PS2_CTL_FPS2CLK_Msk (0x1ul << PS2_CTL_FPS2CLK_Pos) |
| #define | PS2_CTL_FPS2DAT_Pos (11) |
| #define | PS2_CTL_FPS2DAT_Msk (0x1ul << PS2_CTL_FPS2DAT_Pos) |
| #define | PS2_TXDAT0_DAT_Pos (0) |
| #define | PS2_TXDAT0_DAT_Msk (0xfffffffful << PS2_TXDAT0_DAT_Pos) |
| #define | PS2_TXDAT1_DAT_Pos (0) |
| #define | PS2_TXDAT1_DAT_Msk (0xfffffffful << PS2_TXDAT1_DAT_Pos) |
| #define | PS2_TXDAT2_DAT_Pos (0) |
| #define | PS2_TXDAT2_DAT_Msk (0xfffffffful << PS2_TXDAT2_DAT_Pos) |
| #define | PS2_TXDAT3_DAT_Pos (0) |
| #define | PS2_TXDAT3_DAT_Msk (0xfffffffful << PS2_TXDAT3_DAT_Pos) |
| #define | PS2_RXDAT_DAT_Pos (0) |
| #define | PS2_RXDAT_DAT_Msk (0xfful << PS2_RXDAT_DAT_Pos) |
| #define | PS2_STATUS_CLKSTAT_Pos (0) |
| #define | PS2_STATUS_CLKSTAT_Msk (0x1ul << PS2_STATUS_CLKSTAT_Pos) |
| #define | PS2_STATUS_DATSTAT_Pos (1) |
| #define | PS2_STATUS_DATSTAT_Msk (0x1ul << PS2_STATUS_DATSTAT_Pos) |
| #define | PS2_STATUS_FRAMEERR_Pos (2) |
| #define | PS2_STATUS_FRAMEERR_Msk (0x1ul << PS2_STATUS_FRAMEERR_Pos) |
| #define | PS2_STATUS_RXPARITY_Pos (3) |
| #define | PS2_STATUS_RXPARITY_Msk (0x1ul << PS2_STATUS_RXPARITY_Pos) |
| #define | PS2_STATUS_RXBUSY_Pos (4) |
| #define | PS2_STATUS_RXBUSY_Msk (0x1ul << PS2_STATUS_RXBUSY_Pos) |
| #define | PS2_STATUS_TXBUSY_Pos (5) |
| #define | PS2_STATUS_TXBUSY_Msk (0x1ul << PS2_STATUS_TXBUSY_Pos) |
| #define | PS2_STATUS_RXOV_Pos (6) |
| #define | PS2_STATUS_RXOV_Msk (0x1ul << PS2_STATUS_RXOV_Pos) |
| #define | PS2_STATUS_TXEMPTY_Pos (7) |
| #define | PS2_STATUS_TXEMPTY_Msk (0x1ul << PS2_STATUS_TXEMPTY_Pos) |
| #define | PS2_STATUS_BYTEIDX_Pos (8) |
| #define | PS2_STATUS_BYTEIDX_Msk (0xful << PS2_STATUS_BYTEIDX_Pos) |
| #define | PS2_INTSTS_RXIF_Pos (0) |
| #define | PS2_INTSTS_RXIF_Msk (0x1ul << PS2_INTSTS_RXIF_Pos) |
| #define | PS2_INTSTS_TXIF_Pos (1) |
| #define | PS2_INTSTS_TXIF_Msk (0x1ul << PS2_INTSTS_TXIF_Pos) |
| #define | PWM_CLKPSC_CLKPSC01_Pos (0) |
| #define | PWM_CLKPSC_CLKPSC01_Msk (0xfful << PWM_CLKPSC_CLKPSC01_Pos) |
| #define | PWM_CLKPSC_CLKPSC23_Pos (8) |
| #define | PWM_CLKPSC_CLKPSC23_Msk (0xfful << PWM_CLKPSC_CLKPSC23_Pos) |
| #define | PWM_CLKPSC_CLKPSC45_Pos (16) |
| #define | PWM_CLKPSC_CLKPSC45_Msk (0xfful << PWM_CLKPSC_CLKPSC45_Pos) |
| #define | PWM_CLKDIV_CLKDIV0_Pos (0) |
| #define | PWM_CLKDIV_CLKDIV0_Msk (0x7ul << PWM_CLKDIV_CLKDIV0_Pos) |
| #define | PWM_CLKDIV_CLKDIV1_Pos (4) |
| #define | PWM_CLKDIV_CLKDIV1_Msk (0x7ul << PWM_CLKDIV_CLKDIV1_Pos) |
| #define | PWM_CLKDIV_CLKDIV2_Pos (8) |
| #define | PWM_CLKDIV_CLKDIV2_Msk (0x7ul << PWM_CLKDIV_CLKDIV2_Pos) |
| #define | PWM_CLKDIV_CLKDIV3_Pos (12) |
| #define | PWM_CLKDIV_CLKDIV3_Msk (0x7ul << PWM_CLKDIV_CLKDIV3_Pos) |
| #define | PWM_CLKDIV_CLKDIV4_Pos (16) |
| #define | PWM_CLKDIV_CLKDIV4_Msk (0x7ul << PWM_CLKDIV_CLKDIV4_Pos) |
| #define | PWM_CLKDIV_CLKDIV5_Pos (20) |
| #define | PWM_CLKDIV_CLKDIV5_Msk (0x7ul << PWM_CLKDIV_CLKDIV5_Pos) |
| #define | PWM_CTL_CMPINV_Pos (0) |
| #define | PWM_CTL_CMPINV_Msk (0x3ful << PWM_CTL_CMPINV_Pos) |
| #define | PWM_CTL_OUTMODE_Pos (6) |
| #define | PWM_CTL_OUTMODE_Msk (0x1ul << PWM_CTL_OUTMODE_Pos) |
| #define | PWM_CTL_GROUPEN_Pos (7) |
| #define | PWM_CTL_GROUPEN_Msk (0x1ul << PWM_CTL_GROUPEN_Pos) |
| #define | PWM_CTL_PINV_Pos (8) |
| #define | PWM_CTL_PINV_Msk (0x3ful << PWM_CTL_PINV_Pos) |
| #define | PWM_CTL_SYNCEN_Pos (15) |
| #define | PWM_CTL_SYNCEN_Msk (0x1ul << PWM_CTL_SYNCEN_Pos) |
| #define | PWM_CTL_CNTMODE_Pos (16) |
| #define | PWM_CTL_CNTMODE_Msk (0x3ful << PWM_CTL_CNTMODE_Pos) |
| #define | PWM_CTL_CNTTYPE_Pos (24) |
| #define | PWM_CTL_CNTTYPE_Msk (0x3ful << PWM_CTL_CNTTYPE_Pos) |
| #define | PWM_CTL_DBGTRIOFF_Pos (31) |
| #define | PWM_CTL_DBGTRIOFF_Msk (0x1ul << PWM_CTL_DBGTRIOFF_Pos) |
| #define | PWM_CNTEN_CNTEN_Pos (0) |
| #define | PWM_CNTEN_CNTEN_Msk (0x3ful << PWM_CNTEN_CNTEN_Pos) |
| #define | PWM_PERIOD0_PERIOD_Pos (0) |
| #define | PWM_PERIOD0_PERIOD_Msk (0xfffful << PWM_PERIOD0_PERIOD_Pos) |
| #define | PWM_PERIOD1_PERIOD_Pos (0) |
| #define | PWM_PERIOD1_PERIOD_Msk (0xfffful << PWM_PERIOD1_PERIOD_Pos) |
| #define | PWM_PERIOD2_PERIOD_Pos (0) |
| #define | PWM_PERIOD2_PERIOD_Msk (0xfffful << PWM_PERIOD2_PERIOD_Pos) |
| #define | PWM_PERIOD3_PERIOD_Pos (0) |
| #define | PWM_PERIOD3_PERIOD_Msk (0xfffful << PWM_PERIOD3_PERIOD_Pos) |
| #define | PWM_PERIOD4_PERIOD_Pos (0) |
| #define | PWM_PERIOD4_PERIOD_Msk (0xfffful << PWM_PERIOD4_PERIOD_Pos) |
| #define | PWM_PERIOD5_PERIOD_Pos (0) |
| #define | PWM_PERIOD5_PERIOD_Msk (0xfffful << PWM_PERIOD5_PERIOD_Pos) |
| #define | PWM_CMPDAT0_CMP_Pos (0) |
| #define | PWM_CMPDAT0_CMP_Msk (0xfffful << PWM_CMPDAT0_CMP_Pos) |
| #define | PWM_CMPDAT1_CMP_Pos (0) |
| #define | PWM_CMPDAT1_CMP_Msk (0xfffful << PWM_CMPDAT1_CMP_Pos) |
| #define | PWM_CMPDAT2_CMP_Pos (0) |
| #define | PWM_CMPDAT2_CMP_Msk (0xfffful << PWM_CMPDAT2_CMP_Pos) |
| #define | PWM_CMPDAT3_CMP_Pos (0) |
| #define | PWM_CMPDAT3_CMP_Msk (0xfffful << PWM_CMPDAT3_CMP_Pos) |
| #define | PWM_CMPDAT4_CMP_Pos (0) |
| #define | PWM_CMPDAT4_CMP_Msk (0xfffful << PWM_CMPDAT4_CMP_Pos) |
| #define | PWM_CMPDAT5_CMP_Pos (0) |
| #define | PWM_CMPDAT5_CMP_Msk (0xfffful << PWM_CMPDAT5_CMP_Pos) |
| #define | PWM_CNT0_CNT_Pos (0) |
| #define | PWM_CNT0_CNT_Msk (0xfffful << PWM_CNT0_CNT_Pos) |
| #define | PWM_CNT1_CNT_Pos (0) |
| #define | PWM_CNT1_CNT_Msk (0xfffful << PWM_CNT1_CNT_Pos) |
| #define | PWM_CNT2_CNT_Pos (0) |
| #define | PWM_CNT2_CNT_Msk (0xfffful << PWM_CNT2_CNT_Pos) |
| #define | PWM_CNT3_CNT_Pos (0) |
| #define | PWM_CNT3_CNT_Msk (0xfffful << PWM_CNT3_CNT_Pos) |
| #define | PWM_CNT4_CNT_Pos (0) |
| #define | PWM_CNT4_CNT_Msk (0xfffful << PWM_CNT4_CNT_Pos) |
| #define | PWM_CNT5_CNT_Pos (0) |
| #define | PWM_CNT5_CNT_Msk (0xfffful << PWM_CNT5_CNT_Pos) |
| #define | PWM_MSKEN_MSKEN_Pos (0) |
| #define | PWM_MSKEN_MSKEN_Msk (0x3ful << PWM_MSKEN_MSKEN_Pos) |
| #define | PWM_MSK_MSKDAT_Pos (0) |
| #define | PWM_MSK_MSKDAT_Msk (0x3ful << PWM_MSK_MSKDAT_Pos) |
| #define | PWM_DTCTL_DTCNT01_Pos (0) |
| #define | PWM_DTCTL_DTCNT01_Msk (0xfful << PWM_DTCTL_DTCNT01_Pos) |
| #define | PWM_DTCTL_DTCNT23_Pos (8) |
| #define | PWM_DTCTL_DTCNT23_Msk (0xfful << PWM_DTCTL_DTCNT23_Pos) |
| #define | PWM_DTCTL_DTCNT45_Pos (16) |
| #define | PWM_DTCTL_DTCNT45_Msk (0xfful << PWM_DTCTL_DTCNT45_Pos) |
| #define | PWM_DTCTL_DTDIV_Pos (24) |
| #define | PWM_DTCTL_DTDIV_Msk (0x3ul << PWM_DTCTL_DTDIV_Pos) |
| #define | PWM_DTCTL_DTEN01_Pos (28) |
| #define | PWM_DTCTL_DTEN01_Msk (0x1ul << PWM_DTCTL_DTEN01_Pos) |
| #define | PWM_DTCTL_DTEN23_Pos (29) |
| #define | PWM_DTCTL_DTEN23_Msk (0x1ul << PWM_DTCTL_DTEN23_Pos) |
| #define | PWM_DTCTL_DTEN45_Pos (30) |
| #define | PWM_DTCTL_DTEN45_Msk (0x1ul << PWM_DTCTL_DTEN45_Pos) |
| #define | PWM_TRGADCTL_PTRGEN_Pos (0) |
| #define | PWM_TRGADCTL_PTRGEN_Msk (0x3ful << PWM_TRGADCTL_PTRGEN_Pos) |
| #define | PWM_TRGADCTL_CTRGEN_Pos (8) |
| #define | PWM_TRGADCTL_CTRGEN_Msk (0x3ful << PWM_TRGADCTL_CTRGEN_Pos) |
| #define | PWM_TRGADCTL_FTRGEN_Pos (16) |
| #define | PWM_TRGADCTL_FTRGEN_Msk (0x3ful << PWM_TRGADCTL_FTRGEN_Pos) |
| #define | PWM_TRGADCTL_RTRGEN_Pos (24) |
| #define | PWM_TRGADCTL_RTRGEN_Msk (0x3ful << PWM_TRGADCTL_RTRGEN_Pos) |
| #define | PWM_TRGADCSTS_PTRGF_Pos (0) |
| #define | PWM_TRGADCSTS_PTRGF_Msk (0x3ful << PWM_TRGADCSTS_PTRGF_Pos) |
| #define | PWM_TRGADCSTS_CTRGF_Pos (8) |
| #define | PWM_TRGADCSTS_CTRGF_Msk (0x3ful << PWM_TRGADCSTS_CTRGF_Pos) |
| #define | PWM_TRGADCSTS_FTRGF_Pos (16) |
| #define | PWM_TRGADCSTS_FTRGF_Msk (0x3ful << PWM_TRGADCSTS_FTRGF_Pos) |
| #define | PWM_TRGADCSTS_RTRGF_Pos (24) |
| #define | PWM_TRGADCSTS_RTRGF_Msk (0x3ful << PWM_TRGADCSTS_RTRGF_Pos) |
| #define | PWM_BRKCTL_BRK0EN_Pos (0) |
| #define | PWM_BRKCTL_BRK0EN_Msk (0x1ul << PWM_BRKCTL_BRK0EN_Pos) |
| #define | PWM_BRKCTL_BRK0NFDIS_Pos (1) |
| #define | PWM_BRKCTL_BRK0NFDIS_Msk (0x1ul << PWM_BRKCTL_BRK0NFDIS_Pos) |
| #define | PWM_BRKCTL_BRK0INV_Pos (2) |
| #define | PWM_BRKCTL_BRK0INV_Msk (0x1ul << PWM_BRKCTL_BRK0INV_Pos) |
| #define | PWM_BRKCTL_BRK0NFSEL_Pos (6) |
| #define | PWM_BRKCTL_BRK0NFSEL_Msk (0x3ul << PWM_BRKCTL_BRK0NFSEL_Pos) |
| #define | PWM_BRKCTL_BRK1EN_Pos (8) |
| #define | PWM_BRKCTL_BRK1EN_Msk (0x1ul << PWM_BRKCTL_BRK1EN_Pos) |
| #define | PWM_BRKCTL_BRK1NFDIS_Pos (9) |
| #define | PWM_BRKCTL_BRK1NFDIS_Msk (0x1ul << PWM_BRKCTL_BRK1NFDIS_Pos) |
| #define | PWM_BRKCTL_BRK1INV_Pos (10) |
| #define | PWM_BRKCTL_BRK1INV_Msk (0x1ul << PWM_BRKCTL_BRK1INV_Pos) |
| #define | PWM_BRKCTL_BK1SEL_Pos (12) |
| #define | PWM_BRKCTL_BK1SEL_Msk (0x3ul << PWM_BRKCTL_BK1SEL_Pos) |
| #define | PWM_BRKCTL_BRK1NFSEL_Pos (14) |
| #define | PWM_BRKCTL_BRK1NFSEL_Msk (0x3ul << PWM_BRKCTL_BRK1NFSEL_Pos) |
| #define | PWM_BRKCTL_CPO0BKEN_Pos (16) |
| #define | PWM_BRKCTL_CPO0BKEN_Msk (0x1ul << PWM_BRKCTL_CPO0BKEN_Pos) |
| #define | PWM_BRKCTL_CPO1BKEN_Pos (17) |
| #define | PWM_BRKCTL_CPO1BKEN_Msk (0x1ul << PWM_BRKCTL_CPO1BKEN_Pos) |
| #define | PWM_BRKCTL_CPO2BKEN_Pos (18) |
| #define | PWM_BRKCTL_CPO2BKEN_Msk (0x1ul << PWM_BRKCTL_CPO2BKEN_Pos) |
| #define | PWM_BRKCTL_LVDBKEN_Pos (19) |
| #define | PWM_BRKCTL_LVDBKEN_Msk (0x1ul << PWM_BRKCTL_LVDBKEN_Pos) |
| #define | PWM_BRKCTL_BKOD_Pos (24) |
| #define | PWM_BRKCTL_BKOD_Msk (0x3ful << PWM_BRKCTL_BKOD_Pos) |
| #define | PWM_INTCTL_PINTTYPE_Pos (0) |
| #define | PWM_INTCTL_PINTTYPE_Msk (0x3ful << PWM_INTCTL_PINTTYPE_Pos) |
| #define | PWM_INTCTL_DINTTYPE_Pos (8) |
| #define | PWM_INTCTL_DINTTYPE_Msk (0x3ful << PWM_INTCTL_DINTTYPE_Pos) |
| #define | PWM_INTEN_PIEN_Pos (0) |
| #define | PWM_INTEN_PIEN_Msk (0x3ful << PWM_INTEN_PIEN_Pos) |
| #define | PWM_INTEN_BRKIEN_Pos (6) |
| #define | PWM_INTEN_BRKIEN_Msk (0x1ul << PWM_INTEN_BRKIEN_Pos) |
| #define | PWM_INTEN_DIEN_Pos (8) |
| #define | PWM_INTEN_DIEN_Msk (0x3ful << PWM_INTEN_DIEN_Pos) |
| #define | PWM_INTEN_RLIEN_Pos (16) |
| #define | PWM_INTEN_RLIEN_Msk (0x3ful << PWM_INTEN_RLIEN_Pos) |
| #define | PWM_INTEN_FLIEN_Pos (24) |
| #define | PWM_INTEN_FLIEN_Msk (0x3ful << PWM_INTEN_FLIEN_Pos) |
| #define | PWM_INTSTS_PIF_Pos (0) |
| #define | PWM_INTSTS_PIF_Msk (0x3ful << PWM_INTSTS_PIF_Pos) |
| #define | PWM_INTSTS_BRKIF0_Pos (6) |
| #define | PWM_INTSTS_BRKIF0_Msk (0x1ul << PWM_INTSTS_BRKIF0_Pos) |
| #define | PWM_INTSTS_BRKIF1_Pos (7) |
| #define | PWM_INTSTS_BRKIF1_Msk (0x1ul << PWM_INTSTS_BRKIF1_Pos) |
| #define | PWM_INTSTS_DIF_Pos (8) |
| #define | PWM_INTSTS_DIF_Msk (0x3ful << PWM_INTSTS_DIF_Pos) |
| #define | PWM_INTSTS_BRKLK0_Pos (14) |
| #define | PWM_INTSTS_BRKLK0_Msk (0x1ul << PWM_INTSTS_BRKLK0_Pos) |
| #define | PWM_INTSTS_CRLIF_Pos (16) |
| #define | PWM_INTSTS_CRLIF_Msk (0x3ful << PWM_INTSTS_CRLIF_Pos) |
| #define | PWM_INTSTS_BRKSTS0_Pos (22) |
| #define | PWM_INTSTS_BRKSTS0_Msk (0x1ul << PWM_INTSTS_BRKSTS0_Pos) |
| #define | PWM_INTSTS_BRKSTS1_Pos (23) |
| #define | PWM_INTSTS_BRKSTS1_Msk (0x1ul << PWM_INTSTS_BRKSTS1_Pos) |
| #define | PWM_INTSTS_CFLIF_Pos (24) |
| #define | PWM_INTSTS_CFLIF_Msk (0x3ful << PWM_INTSTS_CFLIF_Pos) |
| #define | PWM_POEN_POEN_Pos (0) |
| #define | PWM_POEN_POEN_Msk (0x3ful << PWM_POEN_POEN_Pos) |
| #define | PWM_CAPCTL_CAPEN_Pos (0) |
| #define | PWM_CAPCTL_CAPEN_Msk (0x3ful << PWM_CAPCTL_CAPEN_Pos) |
| #define | PWM_CAPCTL_CAPINV_Pos (8) |
| #define | PWM_CAPCTL_CAPINV_Msk (0x3ful << PWM_CAPCTL_CAPINV_Pos) |
| #define | PWM_CAPCTL_RCRLDEN_Pos (16) |
| #define | PWM_CAPCTL_RCRLDEN_Msk (0x3ful << PWM_CAPCTL_RCRLDEN_Pos) |
| #define | PWM_CAPCTL_FCRLDEN_Pos (24) |
| #define | PWM_CAPCTL_FCRLDEN_Msk (0x3ful << PWM_CAPCTL_FCRLDEN_Pos) |
| #define | PWM_CAPINEN_CAPINEN_Pos (0) |
| #define | PWM_CAPINEN_CAPINEN_Msk (0x3ful << PWM_CAPINEN_CAPINEN_Pos) |
| #define | PWM_CAPSTS_CRIFOV_Pos (0) |
| #define | PWM_CAPSTS_CRIFOV_Msk (0x3ful << PWM_CAPSTS_CRIFOV_Pos) |
| #define | PWM_CAPSTS_FLIFOV_Pos (8) |
| #define | PWM_CAPSTS_FLIFOV_Msk (0x3ful << PWM_CAPSTS_FLIFOV_Pos) |
| #define | PWM_RCAPDAT0_RCAPDAT_Pos (0) |
| #define | PWM_RCAPDAT0_RCAPDAT_Msk (0xfffful << PWM_RCAPDAT0_RCAPDAT_Pos) |
| #define | PWM_FCAPDAT0_FCAPDAT_Pos (0) |
| #define | PWM_FCAPDAT0_FCAPDAT_Msk (0xfffful << PWM_FCAPDAT0_FCAPDAT_Pos) |
| #define | PWM_RCAPDAT1_RCAPDAT_Pos (0) |
| #define | PWM_RCAPDAT1_RCAPDAT_Msk (0xfffful << PWM_RCAPDAT1_RCAPDAT_Pos) |
| #define | PWM_FCAPDAT1_FCAPDAT_Pos (0) |
| #define | PWM_FCAPDAT1_FCAPDAT_Msk (0xfffful << PWM_FCAPDAT1_FCAPDAT_Pos) |
| #define | PWM_RCAPDAT2_RCAPDAT_Pos (0) |
| #define | PWM_RCAPDAT2_RCAPDAT_Msk (0xfffful << PWM_RCAPDAT2_RCAPDAT_Pos) |
| #define | PWM_FCAPDAT2_FCAPDAT_Pos (0) |
| #define | PWM_FCAPDAT2_FCAPDAT_Msk (0xfffful << PWM_FCAPDAT2_FCAPDAT_Pos) |
| #define | PWM_RCAPDAT3_RCAPDAT_Pos (0) |
| #define | PWM_RCAPDAT3_RCAPDAT_Msk (0xfffful << PWM_RCAPDAT3_RCAPDAT_Pos) |
| #define | PWM_FCAPDAT3_FCAPDAT_Pos (0) |
| #define | PWM_FCAPDAT3_FCAPDAT_Msk (0xfffful << PWM_FCAPDAT3_FCAPDAT_Pos) |
| #define | PWM_RCAPDAT4_RCAPDAT_Pos (0) |
| #define | PWM_RCAPDAT4_RCAPDAT_Msk (0xfffful << PWM_RCAPDAT4_RCAPDAT_Pos) |
| #define | PWM_FCAPDAT4_FCAPDAT_Pos (0) |
| #define | PWM_FCAPDAT4_FCAPDAT_Msk (0xfffful << PWM_FCAPDAT4_FCAPDAT_Pos) |
| #define | PWM_RCAPDAT5_RCAPDAT_Pos (0) |
| #define | PWM_RCAPDAT5_RCAPDAT_Msk (0xfffful << PWM_RCAPDAT5_RCAPDAT_Pos) |
| #define | PWM_FCAPDAT5_FCAPDAT_Pos (0) |
| #define | PWM_FCAPDAT5_FCAPDAT_Msk (0xfffful << PWM_FCAPDAT5_FCAPDAT_Pos) |
| #define | PWM_SBS0_SYNCBUSY_Pos (0) |
| #define | PWM_SBS0_SYNCBUSY_Msk (0x1ul << PWM_SBS0_SYNCBUSY_Pos) |
| #define | PWM_SBS1_SYNCBUSY_Pos (0) |
| #define | PWM_SBS1_SYNCBUSY_Msk (0x1ul << PWM_SBS1_SYNCBUSY_Pos) |
| #define | PWM_SBS2_SYNCBUSY_Pos (0) |
| #define | PWM_SBS2_SYNCBUSY_Msk (0x1ul << PWM_SBS2_SYNCBUSY_Pos) |
| #define | PWM_SBS3_SYNCBUSY_Pos (0) |
| #define | PWM_SBS3_SYNCBUSY_Msk (0x1ul << PWM_SBS3_SYNCBUSY_Pos) |
| #define | PWM_SBS4_SYNCBUSY_Pos (0) |
| #define | PWM_SBS4_SYNCBUSY_Msk (0x1ul << PWM_SBS4_SYNCBUSY_Pos) |
| #define | PWM_SBS5_SYNCBUSY_Pos (0) |
| #define | PWM_SBS5_SYNCBUSY_Msk (0x1ul << PWM_SBS5_SYNCBUSY_Pos) |
| #define | QEI_CNT_VAL_Pos (0) |
| #define | QEI_CNT_VAL_Msk (0xfffffffful << QEI_CNT_VAL_Pos) |
| #define | QEI_CNTHOLD_VAL_Pos (0) |
| #define | QEI_CNTHOLD_VAL_Msk (0xfffffffful << QEI_CNTHOLD_VAL_Pos) |
| #define | QEI_CNTLATCH_VAL_Pos (0) |
| #define | QEI_CNTLATCH_VAL_Msk (0xfffffffful << QEI_CNTLATCH_VAL_Pos) |
| #define | QEI_CNTCMP_VAL_Pos (0) |
| #define | QEI_CNTCMP_VAL_Msk (0xfffffffful << QEI_CNTCMP_VAL_Pos) |
| #define | QEI_CNTMAX_VAL_Pos (0) |
| #define | QEI_CNTMAX_VAL_Msk (0xfffffffful << QEI_CNTMAX_VAL_Pos) |
| #define | QEI_CTR_NFCLKSEL_Pos (0) |
| #define | QEI_CTR_NFCLKSEL_Msk (0x3ul << QEI_CTR_NFCLKSEL_Pos) |
| #define | QEI_CTR_NFDIS_Pos (3) |
| #define | QEI_CTR_NFDIS_Msk (0x1ul << QEI_CTR_NFDIS_Pos) |
| #define | QEI_CTR_CHAEN_Pos (4) |
| #define | QEI_CTR_CHAEN_Msk (0x1ul << QEI_CTR_CHAEN_Pos) |
| #define | QEI_CTR_CHBEN_Pos (5) |
| #define | QEI_CTR_CHBEN_Msk (0x1ul << QEI_CTR_CHBEN_Pos) |
| #define | QEI_CTR_IDXEN_Pos (6) |
| #define | QEI_CTR_IDXEN_Msk (0x1ul << QEI_CTR_IDXEN_Pos) |
| #define | QEI_CTR_MODE_Pos (8) |
| #define | QEI_CTR_MODE_Msk (0x3ul << QEI_CTR_MODE_Pos) |
| #define | QEI_CTR_CHAINV_Pos (12) |
| #define | QEI_CTR_CHAINV_Msk (0x1ul << QEI_CTR_CHAINV_Pos) |
| #define | QEI_CTR_CHBINV_Pos (13) |
| #define | QEI_CTR_CHBINV_Msk (0x1ul << QEI_CTR_CHBINV_Pos) |
| #define | QEI_CTR_IDXINV_Pos (14) |
| #define | QEI_CTR_IDXINV_Msk (0x1ul << QEI_CTR_IDXINV_Pos) |
| #define | QEI_CTR_OVUNIEN_Pos (16) |
| #define | QEI_CTR_OVUNIEN_Msk (0x1ul << QEI_CTR_OVUNIEN_Pos) |
| #define | QEI_CTR_DIRIEN_Pos (17) |
| #define | QEI_CTR_DIRIEN_Msk (0x1ul << QEI_CTR_DIRIEN_Pos) |
| #define | QEI_CTR_CMPIEN_Pos (18) |
| #define | QEI_CTR_CMPIEN_Msk (0x1ul << QEI_CTR_CMPIEN_Pos) |
| #define | QEI_CTR_IDXIEN_Pos (19) |
| #define | QEI_CTR_IDXIEN_Msk (0x1ul << QEI_CTR_IDXIEN_Pos) |
| #define | QEI_CTR_HOLDTMR0_Pos (20) |
| #define | QEI_CTR_HOLDTMR0_Msk (0x1ul << QEI_CTR_HOLDTMR0_Pos) |
| #define | QEI_CTR_HOLDTMR1_Pos (21) |
| #define | QEI_CTR_HOLDTMR1_Msk (0x1ul << QEI_CTR_HOLDTMR1_Pos) |
| #define | QEI_CTR_HOLDTMR2_Pos (22) |
| #define | QEI_CTR_HOLDTMR2_Msk (0x1ul << QEI_CTR_HOLDTMR2_Pos) |
| #define | QEI_CTR_HOLDTMR3_Pos (23) |
| #define | QEI_CTR_HOLDTMR3_Msk (0x1ul << QEI_CTR_HOLDTMR3_Pos) |
| #define | QEI_CTR_HOLDCNT_Pos (24) |
| #define | QEI_CTR_HOLDCNT_Msk (0x1ul << QEI_CTR_HOLDCNT_Pos) |
| #define | QEI_CTR_IDXLATEN_Pos (25) |
| #define | QEI_CTR_IDXLATEN_Msk (0x1ul << QEI_CTR_IDXLATEN_Pos) |
| #define | QEI_CTR_IDXRLDEN_Pos (27) |
| #define | QEI_CTR_IDXRLDEN_Msk (0x1ul << QEI_CTR_IDXRLDEN_Pos) |
| #define | QEI_CTR_CMPENN_Pos (28) |
| #define | QEI_CTR_CMPENN_Msk (0x1ul << QEI_CTR_CMPENN_Pos) |
| #define | QEI_CTR_QEIEN_Pos (29) |
| #define | QEI_CTR_QEIEN_Msk (0x1ul << QEI_CTR_QEIEN_Pos) |
| #define | QEI_STATUS_IDXF_Pos (0) |
| #define | QEI_STATUS_IDXF_Msk (0x1ul << QEI_STATUS_IDXF_Pos) |
| #define | QEI_STATUS_CMPF_Pos (1) |
| #define | QEI_STATUS_CMPF_Msk (0x1ul << QEI_STATUS_CMPF_Pos) |
| #define | QEI_STATUS_OVUNF_Pos (2) |
| #define | QEI_STATUS_OVUNF_Msk (0x1ul << QEI_STATUS_OVUNF_Pos) |
| #define | QEI_STATUS_DIRCHGF_Pos (3) |
| #define | QEI_STATUS_DIRCHGF_Msk (0x1ul << QEI_STATUS_DIRCHGF_Pos) |
| #define | QEI_STATUS_DIRF_Pos (8) |
| #define | QEI_STATUS_DIRF_Msk (0x1ul << QEI_STATUS_DIRF_Pos) |
| #define | RTC_INIT_INIT_Active_Pos (0) |
| #define | RTC_INIT_INIT_Active_Msk (0x1ul << RTC_INIT_INIT_Active_Pos) |
| #define | RTC_INIT_INIT_Pos (1) |
| #define | RTC_INIT_INIT_Msk (0x7ffffffful << RTC_INIT_INIT_Pos) |
| #define | RTC_RWEN_RWEN_Pos (0) |
| #define | RTC_RWEN_RWEN_Msk (0xfffful << RTC_RWEN_RWEN_Pos) |
| #define | RTC_RWEN_RWENF_Pos (16) |
| #define | RTC_RWEN_RWENF_Msk (0x1ul << RTC_RWEN_RWENF_Pos) |
| #define | RTC_FREQADJ_FRACTION_Pos (0) |
| #define | RTC_FREQADJ_FRACTION_Msk (0x3ful << RTC_FREQADJ_FRACTION_Pos) |
| #define | RTC_FREQADJ_INTEGER_Pos (8) |
| #define | RTC_FREQADJ_INTEGER_Msk (0xful << RTC_FREQADJ_INTEGER_Pos) |
| #define | RTC_TIME_SEC_Pos (0) |
| #define | RTC_TIME_SEC_Msk (0xful << RTC_TIME_SEC_Pos) |
| #define | RTC_TIME_TENSEC_Pos (4) |
| #define | RTC_TIME_TENSEC_Msk (0x7ul << RTC_TIME_TENSEC_Pos) |
| #define | RTC_TIME_MIN_Pos (8) |
| #define | RTC_TIME_MIN_Msk (0xful << RTC_TIME_MIN_Pos) |
| #define | RTC_TIME_TENMIN_Pos (12) |
| #define | RTC_TIME_TENMIN_Msk (0x7ul << RTC_TIME_TENMIN_Pos) |
| #define | RTC_TIME_HR_Pos (16) |
| #define | RTC_TIME_HR_Msk (0xful << RTC_TIME_HR_Pos) |
| #define | RTC_TIME_TENHR_Pos (20) |
| #define | RTC_TIME_TENHR_Msk (0x3ul << RTC_TIME_TENHR_Pos) |
| #define | RTC_CAL_DAY_Pos (0) |
| #define | RTC_CAL_DAY_Msk (0xful << RTC_CAL_DAY_Pos) |
| #define | RTC_CAL_TENDAY_Pos (4) |
| #define | RTC_CAL_TENDAY_Msk (0x3ul << RTC_CAL_TENDAY_Pos) |
| #define | RTC_CAL_MON_Pos (8) |
| #define | RTC_CAL_MON_Msk (0xful << RTC_CAL_MON_Pos) |
| #define | RTC_CAL_TENMON_Pos (12) |
| #define | RTC_CAL_TENMON_Msk (0x1ul << RTC_CAL_TENMON_Pos) |
| #define | RTC_CAL_YEAR_Pos (16) |
| #define | RTC_CAL_YEAR_Msk (0xful << RTC_CAL_YEAR_Pos) |
| #define | RTC_CAL_TENYEAR_Pos (20) |
| #define | RTC_CAL_TENYEAR_Msk (0xful << RTC_CAL_TENYEAR_Pos) |
| #define | RTC_CLKFMT_24HEN_Pos (0) |
| #define | RTC_CLKFMT_24HEN_Msk (0x1ul << RTC_CLKFMT_24HEN_Pos) |
| #define | RTC_WEEKDAY_WEEKDAY_Pos (0) |
| #define | RTC_WEEKDAY_WEEKDAY_Msk (0x7ul << RTC_WEEKDAY_WEEKDAY_Pos) |
| #define | RTC_TALM_SEC_Pos (0) |
| #define | RTC_TALM_SEC_Msk (0xful << RTC_TALM_SEC_Pos) |
| #define | RTC_TALM_TENSEC_Pos (4) |
| #define | RTC_TALM_TENSEC_Msk (0x7ul << RTC_TALM_TENSEC_Pos) |
| #define | RTC_TALM_MIN_Pos (8) |
| #define | RTC_TALM_MIN_Msk (0xful << RTC_TALM_MIN_Pos) |
| #define | RTC_TALM_TENMIN_Pos (12) |
| #define | RTC_TALM_TENMIN_Msk (0x7ul << RTC_TALM_TENMIN_Pos) |
| #define | RTC_TALM_HR_Pos (16) |
| #define | RTC_TALM_HR_Msk (0xful << RTC_TALM_HR_Pos) |
| #define | RTC_TALM_TENHR_Pos (20) |
| #define | RTC_TALM_TENHR_Msk (0x3ul << RTC_TALM_TENHR_Pos) |
| #define | RTC_CALM_DAY_Pos (0) |
| #define | RTC_CALM_DAY_Msk (0xful << RTC_CALM_DAY_Pos) |
| #define | RTC_CALM_TENDAY_Pos (4) |
| #define | RTC_CALM_TENDAY_Msk (0x3ul << RTC_CALM_TENDAY_Pos) |
| #define | RTC_CALM_MON_Pos (8) |
| #define | RTC_CALM_MON_Msk (0xful << RTC_CALM_MON_Pos) |
| #define | RTC_CALM_TENMON_Pos (12) |
| #define | RTC_CALM_TENMON_Msk (0x1ul << RTC_CALM_TENMON_Pos) |
| #define | RTC_CALM_YEAR_Pos (16) |
| #define | RTC_CALM_YEAR_Msk (0xful << RTC_CALM_YEAR_Pos) |
| #define | RTC_CALM_TENYEAR_Pos (20) |
| #define | RTC_CALM_TENYEAR_Msk (0xful << RTC_CALM_TENYEAR_Pos) |
| #define | RTC_LEAPYEAR_LEAPYEAR_Pos (0) |
| #define | RTC_LEAPYEAR_LEAPYEAR_Msk (0x1ul << RTC_LEAPYEAR_LEAPYEAR_Pos) |
| #define | RTC_INTEN_ALMIEN_Pos (0) |
| #define | RTC_INTEN_ALMIEN_Msk (0x1ul << RTC_INTEN_ALMIEN_Pos) |
| #define | RTC_INTEN_TICKIEN_Pos (1) |
| #define | RTC_INTEN_TICKIEN_Msk (0x1ul << RTC_INTEN_TICKIEN_Pos) |
| #define | RTC_INTSTS_ALMIF_Pos (0) |
| #define | RTC_INTSTS_ALMIF_Msk (0x1ul << RTC_INTSTS_ALMIF_Pos) |
| #define | RTC_INTSTS_TICKIF_Pos (1) |
| #define | RTC_INTSTS_TICKIF_Msk (0x1ul << RTC_INTSTS_TICKIF_Pos) |
| #define | RTC_TICK_TICKSEL_Pos (0) |
| #define | RTC_TICK_TICKSEL_Msk (0x7ul << RTC_TICK_TICKSEL_Pos) |
| #define | RTC_SPRCTL_SPRRWEN_Pos (2) |
| #define | RTC_SPRCTL_SPRRWEN_Msk (0x1ul << RTC_SPRCTL_SPRRWEN_Pos) |
| #define | RTC_SPRCTL_SPRRWRDY_Pos (7) |
| #define | RTC_SPRCTL_SPRRWRDY_Msk (0x1ul << RTC_SPRCTL_SPRRWRDY_Pos) |
| #define | RTC_TAMPCTL_TIEN_Pos (0) |
| #define | RTC_TAMPCTL_TIEN_Msk (0x1ul << RTC_TAMPCTL_TIEN_Pos) |
| #define | RTC_TAMPCTL_DESTROYEN_Pos (1) |
| #define | RTC_TAMPCTL_DESTROYEN_Msk (0x1ul << RTC_TAMPCTL_DESTROYEN_Pos) |
| #define | RTC_TAMPCTL_TAMPEN0_Pos (2) |
| #define | RTC_TAMPCTL_TAMPEN0_Msk (0x1ul << RTC_TAMPCTL_TAMPEN0_Pos) |
| #define | RTC_TAMPCTL_TAMPEN1_Pos (3) |
| #define | RTC_TAMPCTL_TAMPEN1_Msk (0x1ul << RTC_TAMPCTL_TAMPEN1_Pos) |
| #define | RTC_TAMPCTL_TAMPDBEN0_Pos (4) |
| #define | RTC_TAMPCTL_TAMPDBEN0_Msk (0x1ul << RTC_TAMPCTL_TAMPDBEN0_Pos) |
| #define | RTC_TAMPCTL_TAMPDBEN1_Pos (5) |
| #define | RTC_TAMPCTL_TAMPDBEN1_Msk (0x1ul << RTC_TAMPCTL_TAMPDBEN1_Pos) |
| #define | RTC_TAMPCTL_TAMPLV0_Pos (6) |
| #define | RTC_TAMPCTL_TAMPLV0_Msk (0x1ul << RTC_TAMPCTL_TAMPLV0_Pos) |
| #define | RTC_TAMPCTL_TAMPLV1_Pos (7) |
| #define | RTC_TAMPCTL_TAMPLV1_Msk (0x1ul << RTC_TAMPCTL_TAMPLV1_Pos) |
| #define | RTC_TAMPSTS_TAMPSTS0_Pos (0) |
| #define | RTC_TAMPSTS_TAMPSTS0_Msk (0x1ul << RTC_TAMPSTS_TAMPSTS0_Pos) |
| #define | RTC_TAMPSTS_TAMPSTS1_Pos (1) |
| #define | RTC_TAMPSTS_TAMPSTS1_Msk (0x1ul << RTC_TAMPSTS_TAMPSTS1_Pos) |
| #define | RTC_TAMP0PCTL_OUTLV_Pos (0) |
| #define | RTC_TAMP0PCTL_OUTLV_Msk (0x1ul << RTC_TAMP0PCTL_OUTLV_Pos) |
| #define | RTC_TAMP0PCTL_OUTEN_Pos (1) |
| #define | RTC_TAMP0PCTL_OUTEN_Msk (0x1ul << RTC_TAMP0PCTL_OUTEN_Pos) |
| #define | RTC_TAMP0PCTL_TRIEN_Pos (2) |
| #define | RTC_TAMP0PCTL_TRIEN_Msk (0x1ul << RTC_TAMP0PCTL_TRIEN_Pos) |
| #define | RTC_TAMP0PCTL_TYPE_Pos (3) |
| #define | RTC_TAMP0PCTL_TYPE_Msk (0x1ul << RTC_TAMP0PCTL_TYPE_Pos) |
| #define | RTC_TAMP0PCTL_DINOFF_Pos (4) |
| #define | RTC_TAMP0PCTL_DINOFF_Msk (0x1ul << RTC_TAMP0PCTL_DINOFF_Pos) |
| #define | RTC_TAMP1PCTL_OUTLV_Pos (0) |
| #define | RTC_TAMP1PCTL_OUTLV_Msk (0x1ul << RTC_TAMP1PCTL_OUTLV_Pos) |
| #define | RTC_TAMP1PCTL_OUTEN_Pos (1) |
| #define | RTC_TAMP1PCTL_OUTEN_Msk (0x1ul << RTC_TAMP1PCTL_OUTEN_Pos) |
| #define | RTC_TAMP1PCTL_TRIEN_Pos (2) |
| #define | RTC_TAMP1PCTL_TRIEN_Msk (0x1ul << RTC_TAMP1PCTL_TRIEN_Pos) |
| #define | RTC_TAMP1PCTL_TYPE_Pos (3) |
| #define | RTC_TAMP1PCTL_TYPE_Msk (0x1ul << RTC_TAMP1PCTL_TYPE_Pos) |
| #define | RTC_TAMP1PCTL_DINOFF_Pos (4) |
| #define | RTC_TAMP1PCTL_DINOFF_Msk (0x1ul << RTC_TAMP1PCTL_DINOFF_Pos) |
| #define | RTC_LXTIPCTL_OUTLV_Pos (0) |
| #define | RTC_LXTIPCTL_OUTLV_Msk (0x1ul << RTC_LXTIPCTL_OUTLV_Pos) |
| #define | RTC_LXTIPCTL_OUTEN_Pos (1) |
| #define | RTC_LXTIPCTL_OUTEN_Msk (0x1ul << RTC_LXTIPCTL_OUTEN_Pos) |
| #define | RTC_LXTIPCTL_TRIEN_Pos (2) |
| #define | RTC_LXTIPCTL_TRIEN_Msk (0x1ul << RTC_LXTIPCTL_TRIEN_Pos) |
| #define | RTC_LXTIPCTL_TYPE_Pos (3) |
| #define | RTC_LXTIPCTL_TYPE_Msk (0x1ul << RTC_LXTIPCTL_TYPE_Pos) |
| #define | RTC_LXTIPCTL_DINOFF_Pos (4) |
| #define | RTC_LXTIPCTL_DINOFF_Msk (0x1ul << RTC_LXTIPCTL_DINOFF_Pos) |
| #define | RTC_LXTOPCTL_OUTLV_Pos (0) |
| #define | RTC_LXTOPCTL_OUTLV_Msk (0x1ul << RTC_LXTOPCTL_OUTLV_Pos) |
| #define | RTC_LXTOPCTL_OUTEN_Pos (1) |
| #define | RTC_LXTOPCTL_OUTEN_Msk (0x1ul << RTC_LXTOPCTL_OUTEN_Pos) |
| #define | RTC_LXTOPCTL_TRIEN_Pos (2) |
| #define | RTC_LXTOPCTL_TRIEN_Msk (0x1ul << RTC_LXTOPCTL_TRIEN_Pos) |
| #define | RTC_LXTOPCTL_TYPE_Pos (3) |
| #define | RTC_LXTOPCTL_TYPE_Msk (0x1ul << RTC_LXTOPCTL_TYPE_Pos) |
| #define | RTC_LXTOPCTL_DINOFF_Pos (4) |
| #define | RTC_LXTOPCTL_DINOFF_Msk (0x1ul << RTC_LXTOPCTL_DINOFF_Pos) |
| #define | RTC_TAMSK_MSEC_Pos (0) |
| #define | RTC_TAMSK_MSEC_Msk (0x1ul << RTC_TAMSK_MSEC_Pos) |
| #define | RTC_TAMSK_MTENSEC_Pos (1) |
| #define | RTC_TAMSK_MTENSEC_Msk (0x1ul << RTC_TAMSK_MTENSEC_Pos) |
| #define | RTC_TAMSK_MMIN_Pos (2) |
| #define | RTC_TAMSK_MMIN_Msk (0x1ul << RTC_TAMSK_MMIN_Pos) |
| #define | RTC_TAMSK_MTENMIN_Pos (3) |
| #define | RTC_TAMSK_MTENMIN_Msk (0x1ul << RTC_TAMSK_MTENMIN_Pos) |
| #define | RTC_TAMSK_MHR_Pos (4) |
| #define | RTC_TAMSK_MHR_Msk (0x1ul << RTC_TAMSK_MHR_Pos) |
| #define | RTC_TAMSK_MTENHR_Pos (5) |
| #define | RTC_TAMSK_MTENHR_Msk (0x1ul << RTC_TAMSK_MTENHR_Pos) |
| #define | RTC_CAMSK_MDAY_Pos (0) |
| #define | RTC_CAMSK_MDAY_Msk (0x1ul << RTC_CAMSK_MDAY_Pos) |
| #define | RTC_CAMSK_MTENDAY_Pos (1) |
| #define | RTC_CAMSK_MTENDAY_Msk (0x1ul << RTC_CAMSK_MTENDAY_Pos) |
| #define | RTC_CAMSK_MMON_Pos (2) |
| #define | RTC_CAMSK_MMON_Msk (0x1ul << RTC_CAMSK_MMON_Pos) |
| #define | RTC_CAMSK_MTENMON_Pos (3) |
| #define | RTC_CAMSK_MTENMON_Msk (0x1ul << RTC_CAMSK_MTENMON_Pos) |
| #define | RTC_CAMSK_MYEAR_Pos (4) |
| #define | RTC_CAMSK_MYEAR_Msk (0x1ul << RTC_CAMSK_MYEAR_Pos) |
| #define | RTC_CAMSK_MTENYEAR_Pos (5) |
| #define | RTC_CAMSK_MTENYEAR_Msk (0x1ul << RTC_CAMSK_MTENYEAR_Pos) |
| #define | SC_DAT_DAT_Pos (0) |
| #define | SC_DAT_DAT_Msk (0xfful << SC_DAT_DAT_Pos) |
| #define | SC_CTL_SCEN_Pos (0) |
| #define | SC_CTL_SCEN_Msk (0x1ul << SC_CTL_SCEN_Pos) |
| #define | SC_CTL_RXOFF_Pos (1) |
| #define | SC_CTL_RXOFF_Msk (0x1ul << SC_CTL_RXOFF_Pos) |
| #define | SC_CTL_TXOFF_Pos (2) |
| #define | SC_CTL_TXOFF_Msk (0x1ul << SC_CTL_TXOFF_Pos) |
| #define | SC_CTL_AUTOCEN_Pos (3) |
| #define | SC_CTL_AUTOCEN_Msk (0x1ul << SC_CTL_AUTOCEN_Pos) |
| #define | SC_CTL_CONSEL_Pos (4) |
| #define | SC_CTL_CONSEL_Msk (0x3ul << SC_CTL_CONSEL_Pos) |
| #define | SC_CTL_RXTRGLV_Pos (6) |
| #define | SC_CTL_RXTRGLV_Msk (0x3ul << SC_CTL_RXTRGLV_Pos) |
| #define | SC_CTL_BGT_Pos (8) |
| #define | SC_CTL_BGT_Msk (0x1ful << SC_CTL_BGT_Pos) |
| #define | SC_CTL_TMRSEL_Pos (13) |
| #define | SC_CTL_TMRSEL_Msk (0x3ul << SC_CTL_TMRSEL_Pos) |
| #define | SC_CTL_NSB_Pos (15) |
| #define | SC_CTL_NSB_Msk (0x1ul << SC_CTL_NSB_Pos) |
| #define | SC_CTL_RXRTY_Pos (16) |
| #define | SC_CTL_RXRTY_Msk (0x7ul << SC_CTL_RXRTY_Pos) |
| #define | SC_CTL_RXRTYEN_Pos (19) |
| #define | SC_CTL_RXRTYEN_Msk (0x1ul << SC_CTL_RXRTYEN_Pos) |
| #define | SC_CTL_TXRTY_Pos (20) |
| #define | SC_CTL_TXRTY_Msk (0x7ul << SC_CTL_TXRTY_Pos) |
| #define | SC_CTL_TXRTYEN_Pos (23) |
| #define | SC_CTL_TXRTYEN_Msk (0x1ul << SC_CTL_TXRTYEN_Pos) |
| #define | SC_CTL_CDDBSEL_Pos (24) |
| #define | SC_CTL_CDDBSEL_Msk (0x3ul << SC_CTL_CDDBSEL_Pos) |
| #define | SC_CTL_CDLV_Pos (26) |
| #define | SC_CTL_CDLV_Msk (0x1ul << SC_CTL_CDLV_Pos) |
| #define | SC_CTL_SYNC_Pos (30) |
| #define | SC_CTL_SYNC_Msk (0x1ul << SC_CTL_SYNC_Pos) |
| #define | SC_ALTCTL_TXRST_Pos (0) |
| #define | SC_ALTCTL_TXRST_Msk (0x1ul << SC_ALTCTL_TXRST_Pos) |
| #define | SC_ALTCTL_RXRST_Pos (1) |
| #define | SC_ALTCTL_RXRST_Msk (0x1ul << SC_ALTCTL_RXRST_Pos) |
| #define | SC_ALTCTL_DACTEN_Pos (2) |
| #define | SC_ALTCTL_DACTEN_Msk (0x1ul << SC_ALTCTL_DACTEN_Pos) |
| #define | SC_ALTCTL_ACTEN_Pos (3) |
| #define | SC_ALTCTL_ACTEN_Msk (0x1ul << SC_ALTCTL_ACTEN_Pos) |
| #define | SC_ALTCTL_WARSTEN_Pos (4) |
| #define | SC_ALTCTL_WARSTEN_Msk (0x1ul << SC_ALTCTL_WARSTEN_Pos) |
| #define | SC_ALTCTL_CNTEN0_Pos (5) |
| #define | SC_ALTCTL_CNTEN0_Msk (0x1ul << SC_ALTCTL_CNTEN0_Pos) |
| #define | SC_ALTCTL_CNTEN1_Pos (6) |
| #define | SC_ALTCTL_CNTEN1_Msk (0x1ul << SC_ALTCTL_CNTEN1_Pos) |
| #define | SC_ALTCTL_CNTEN2_Pos (7) |
| #define | SC_ALTCTL_CNTEN2_Msk (0x1ul << SC_ALTCTL_CNTEN2_Pos) |
| #define | SC_ALTCTL_INITSEL_Pos (8) |
| #define | SC_ALTCTL_INITSEL_Msk (0x3ul << SC_ALTCTL_INITSEL_Pos) |
| #define | SC_ALTCTL_ADACEN_Pos (11) |
| #define | SC_ALTCTL_ADACEN_Msk (0x1ul << SC_ALTCTL_ADACEN_Pos) |
| #define | SC_ALTCTL_RXBGTEN_Pos (12) |
| #define | SC_ALTCTL_RXBGTEN_Msk (0x1ul << SC_ALTCTL_RXBGTEN_Pos) |
| #define | SC_ALTCTL_ACTSTS0_Pos (13) |
| #define | SC_ALTCTL_ACTSTS0_Msk (0x1ul << SC_ALTCTL_ACTSTS0_Pos) |
| #define | SC_ALTCTL_ACTSTS1_Pos (14) |
| #define | SC_ALTCTL_ACTSTS1_Msk (0x1ul << SC_ALTCTL_ACTSTS1_Pos) |
| #define | SC_ALTCTL_ACTSTS2_Pos (15) |
| #define | SC_ALTCTL_ACTSTS2_Msk (0x1ul << SC_ALTCTL_ACTSTS2_Pos) |
| #define | SC_EGT_EGT_Pos (0) |
| #define | SC_EGT_EGT_Msk (0xfful << SC_EGT_EGT_Pos) |
| #define | SC_RXTOUT_RFTM_Pos (0) |
| #define | SC_RXTOUT_RFTM_Msk (0x1fful << SC_RXTOUT_RFTM_Pos) |
| #define | SC_ETUCTL_ETURDIV_Pos (0) |
| #define | SC_ETUCTL_ETURDIV_Msk (0xffful << SC_ETUCTL_ETURDIV_Pos) |
| #define | SC_ETUCTL_CMPEN_Pos (15) |
| #define | SC_ETUCTL_CMPEN_Msk (0x1ul << SC_ETUCTL_CMPEN_Pos) |
| #define | SC_INTEN_RDAIEN_Pos (0) |
| #define | SC_INTEN_RDAIEN_Msk (0x1ul << SC_INTEN_RDAIEN_Pos) |
| #define | SC_INTEN_TBEIEN_Pos (1) |
| #define | SC_INTEN_TBEIEN_Msk (0x1ul << SC_INTEN_TBEIEN_Pos) |
| #define | SC_INTEN_TERRIEN_Pos (2) |
| #define | SC_INTEN_TERRIEN_Msk (0x1ul << SC_INTEN_TERRIEN_Pos) |
| #define | SC_INTEN_TMR0IEN_Pos (3) |
| #define | SC_INTEN_TMR0IEN_Msk (0x1ul << SC_INTEN_TMR0IEN_Pos) |
| #define | SC_INTEN_TMR1IEN_Pos (4) |
| #define | SC_INTEN_TMR1IEN_Msk (0x1ul << SC_INTEN_TMR1IEN_Pos) |
| #define | SC_INTEN_TMR2IEN_Pos (5) |
| #define | SC_INTEN_TMR2IEN_Msk (0x1ul << SC_INTEN_TMR2IEN_Pos) |
| #define | SC_INTEN_BGTIEN_Pos (6) |
| #define | SC_INTEN_BGTIEN_Msk (0x1ul << SC_INTEN_BGTIEN_Pos) |
| #define | SC_INTEN_CDIEN_Pos (7) |
| #define | SC_INTEN_CDIEN_Msk (0x1ul << SC_INTEN_CDIEN_Pos) |
| #define | SC_INTEN_INITIEN_Pos (8) |
| #define | SC_INTEN_INITIEN_Msk (0x1ul << SC_INTEN_INITIEN_Pos) |
| #define | SC_INTEN_RXTOIF_Pos (9) |
| #define | SC_INTEN_RXTOIF_Msk (0x1ul << SC_INTEN_RXTOIF_Pos) |
| #define | SC_INTEN_ACERRIEN_Pos (10) |
| #define | SC_INTEN_ACERRIEN_Msk (0x1ul << SC_INTEN_ACERRIEN_Pos) |
| #define | SC_INTSTS_RDAIF_Pos (0) |
| #define | SC_INTSTS_RDAIF_Msk (0x1ul << SC_INTSTS_RDAIF_Pos) |
| #define | SC_INTSTS_TBEIF_Pos (1) |
| #define | SC_INTSTS_TBEIF_Msk (0x1ul << SC_INTSTS_TBEIF_Pos) |
| #define | SC_INTSTS_TERRIF_Pos (2) |
| #define | SC_INTSTS_TERRIF_Msk (0x1ul << SC_INTSTS_TERRIF_Pos) |
| #define | SC_INTSTS_TMR0IF_Pos (3) |
| #define | SC_INTSTS_TMR0IF_Msk (0x1ul << SC_INTSTS_TMR0IF_Pos) |
| #define | SC_INTSTS_TMR1IF_Pos (4) |
| #define | SC_INTSTS_TMR1IF_Msk (0x1ul << SC_INTSTS_TMR1IF_Pos) |
| #define | SC_INTSTS_TMR2IF_Pos (5) |
| #define | SC_INTSTS_TMR2IF_Msk (0x1ul << SC_INTSTS_TMR2IF_Pos) |
| #define | SC_INTSTS_BGTIF_Pos (6) |
| #define | SC_INTSTS_BGTIF_Msk (0x1ul << SC_INTSTS_BGTIF_Pos) |
| #define | SC_INTSTS_CDIF_Pos (7) |
| #define | SC_INTSTS_CDIF_Msk (0x1ul << SC_INTSTS_CDIF_Pos) |
| #define | SC_INTSTS_INITIF_Pos (8) |
| #define | SC_INTSTS_INITIF_Msk (0x1ul << SC_INTSTS_INITIF_Pos) |
| #define | SC_INTSTS_RBTOIF_Pos (9) |
| #define | SC_INTSTS_RBTOIF_Msk (0x1ul << SC_INTSTS_RBTOIF_Pos) |
| #define | SC_INTSTS_ACERRIF_Pos (10) |
| #define | SC_INTSTS_ACERRIF_Msk (0x1ul << SC_INTSTS_ACERRIF_Pos) |
| #define | SC_STATUS_RXOV_Pos (0) |
| #define | SC_STATUS_RXOV_Msk (0x1ul << SC_STATUS_RXOV_Pos) |
| #define | SC_STATUS_RXEMPTY_Pos (1) |
| #define | SC_STATUS_RXEMPTY_Msk (0x1ul << SC_STATUS_RXEMPTY_Pos) |
| #define | SC_STATUS_RXFULL_Pos (2) |
| #define | SC_STATUS_RXFULL_Msk (0x1ul << SC_STATUS_RXFULL_Pos) |
| #define | SC_STATUS_PEF_Pos (4) |
| #define | SC_STATUS_PEF_Msk (0x1ul << SC_STATUS_PEF_Pos) |
| #define | SC_STATUS_FEF_Pos (5) |
| #define | SC_STATUS_FEF_Msk (0x1ul << SC_STATUS_FEF_Pos) |
| #define | SC_STATUS_BEF_Pos (6) |
| #define | SC_STATUS_BEF_Msk (0x1ul << SC_STATUS_BEF_Pos) |
| #define | SC_STATUS_TXOV_Pos (8) |
| #define | SC_STATUS_TXOV_Msk (0x1ul << SC_STATUS_TXOV_Pos) |
| #define | SC_STATUS_TXEMPTY_Pos (9) |
| #define | SC_STATUS_TXEMPTY_Msk (0x1ul << SC_STATUS_TXEMPTY_Pos) |
| #define | SC_STATUS_TXFULL_Pos (10) |
| #define | SC_STATUS_TXFULL_Msk (0x1ul << SC_STATUS_TXFULL_Pos) |
| #define | SC_STATUS_CREMOVE_Pos (11) |
| #define | SC_STATUS_CREMOVE_Msk (0x1ul << SC_STATUS_CREMOVE_Pos) |
| #define | SC_STATUS_CINSERT_Pos (12) |
| #define | SC_STATUS_CINSERT_Msk (0x1ul << SC_STATUS_CINSERT_Pos) |
| #define | SC_STATUS_CDPINSTS_Pos (13) |
| #define | SC_STATUS_CDPINSTS_Msk (0x1ul << SC_STATUS_CDPINSTS_Pos) |
| #define | SC_STATUS_RXPOINT_Pos (16) |
| #define | SC_STATUS_RXPOINT_Msk (0x3ul << SC_STATUS_RXPOINT_Pos) |
| #define | SC_STATUS_RXRERR_Pos (21) |
| #define | SC_STATUS_RXRERR_Msk (0x1ul << SC_STATUS_RXRERR_Pos) |
| #define | SC_STATUS_RXOVERR_Pos (22) |
| #define | SC_STATUS_RXOVERR_Msk (0x1ul << SC_STATUS_RXOVERR_Pos) |
| #define | SC_STATUS_RXACT_Pos (23) |
| #define | SC_STATUS_RXACT_Msk (0x1ul << SC_STATUS_RXACT_Pos) |
| #define | SC_STATUS_TXPOINT_Pos (24) |
| #define | SC_STATUS_TXPOINT_Msk (0x3ul << SC_STATUS_TXPOINT_Pos) |
| #define | SC_STATUS_TXRERR_Pos (29) |
| #define | SC_STATUS_TXRERR_Msk (0x1ul << SC_STATUS_TXRERR_Pos) |
| #define | SC_STATUS_TXOVERR_Pos (30) |
| #define | SC_STATUS_TXOVERR_Msk (0x1ul << SC_STATUS_TXOVERR_Pos) |
| #define | SC_STATUS_TXACT_Pos (31) |
| #define | SC_STATUS_TXACT_Msk (0x1ul << SC_STATUS_TXACT_Pos) |
| #define | SC_PINCTL_PWREN_Pos (0) |
| #define | SC_PINCTL_PWREN_Msk (0x1ul << SC_PINCTL_PWREN_Pos) |
| #define | SC_PINCTL_SCRST_Pos (1) |
| #define | SC_PINCTL_SCRST_Msk (0x1ul << SC_PINCTL_SCRST_Pos) |
| #define | SC_PINCTL_CLKKEEP_Pos (6) |
| #define | SC_PINCTL_CLKKEEP_Msk (0x1ul << SC_PINCTL_CLKKEEP_Pos) |
| #define | SC_PINCTL_SCDOUT_Pos (9) |
| #define | SC_PINCTL_SCDOUT_Msk (0x1ul << SC_PINCTL_SCDOUT_Pos) |
| #define | SC_PINCTL_PWRINV_Pos (11) |
| #define | SC_PINCTL_PWRINV_Msk (0x1ul << SC_PINCTL_PWRINV_Pos) |
| #define | SC_PINCTL_DATSTS_Pos (16) |
| #define | SC_PINCTL_DATSTS_Msk (0x1ul << SC_PINCTL_DATSTS_Pos) |
| #define | SC_PINCTL_PWRSTS_Pos (17) |
| #define | SC_PINCTL_PWRSTS_Msk (0x1ul << SC_PINCTL_PWRSTS_Pos) |
| #define | SC_PINCTL_RSTSTS_Pos (18) |
| #define | SC_PINCTL_RSTSTS_Msk (0x1ul << SC_PINCTL_RSTSTS_Pos) |
| #define | SC_PINCTL_SYNC_Pos (30) |
| #define | SC_PINCTL_SYNC_Msk (0x1ul << SC_PINCTL_SYNC_Pos) |
| #define | SC_TMRCTL0_CNT_Pos (0) |
| #define | SC_TMRCTL0_CNT_Msk (0xfffffful << SC_TMRCTL0_CNT_Pos) |
| #define | SC_TMRCTL0_OPMODE_Pos (24) |
| #define | SC_TMRCTL0_OPMODE_Msk (0xful << SC_TMRCTL0_OPMODE_Pos) |
| #define | SC_TMRCTL1_CNT_Pos (0) |
| #define | SC_TMRCTL1_CNT_Msk (0xfful << SC_TMRCTL1_CNT_Pos) |
| #define | SC_TMRCTL1_OPMODE_Pos (24) |
| #define | SC_TMRCTL1_OPMODE_Msk (0xful << SC_TMRCTL1_OPMODE_Pos) |
| #define | SC_TMRCTL2_CNT_Pos (0) |
| #define | SC_TMRCTL2_CNT_Msk (0xfful << SC_TMRCTL2_CNT_Pos) |
| #define | SC_TMRCTL2_OPMODE_Pos (24) |
| #define | SC_TMRCTL2_OPMODE_Msk (0xful << SC_TMRCTL2_OPMODE_Pos) |
| #define | SC_UARTCTL_UARTEN_Pos (0) |
| #define | SC_UARTCTL_UARTEN_Msk (0x1ul << SC_UARTCTL_UARTEN_Pos) |
| #define | SC_UARTCTL_WLS_Pos (4) |
| #define | SC_UARTCTL_WLS_Msk (0x3ul << SC_UARTCTL_WLS_Pos) |
| #define | SC_UARTCTL_PBOFF_Pos (6) |
| #define | SC_UARTCTL_PBOFF_Msk (0x1ul << SC_UARTCTL_PBOFF_Pos) |
| #define | SC_UARTCTL_OPE_Pos (7) |
| #define | SC_UARTCTL_OPE_Msk (0x1ul << SC_UARTCTL_OPE_Pos) |
| #define | SC_TMRDAT0_TDR0_Pos (0) |
| #define | SC_TMRDAT0_TDR0_Msk (0xfffffful << SC_TMRDAT0_TDR0_Pos) |
| #define | SC_TMRDAT1_2_TDR1_Pos (0) |
| #define | SC_TMRDAT1_2_TDR1_Msk (0xfful << SC_TMRDAT1_2_TDR1_Pos) |
| #define | SC_TMRDAT1_2_TDR2_Pos (8) |
| #define | SC_TMRDAT1_2_TDR2_Msk (0xfful << SC_TMRDAT1_2_TDR2_Pos) |
| #define | SDH_DMACTL_DMAEN_Pos (0) |
| #define | SDH_DMACTL_DMAEN_Msk (0x1ul << SDH_DMACTL_DMAEN_Pos) |
| #define | SDH_DMACTL_DMARST_Pos (1) |
| #define | SDH_DMACTL_DMARST_Msk (0x1ul << SDH_DMACTL_DMARST_Pos) |
| #define | SDH_DMACTL_SGEN_Pos (3) |
| #define | SDH_DMACTL_SGEN_Msk (0x1ul << SDH_DMACTL_SGEN_Pos) |
| #define | SDH_DMACTL_DMABUSY_Pos (9) |
| #define | SDH_DMACTL_DMABUSY_Msk (0x1ul << SDH_DMACTL_DMABUSY_Pos) |
| #define | SDH_DMASA_ORDER_Pos (0) |
| #define | SDH_DMASA_ORDER_Msk (0x1ul << SDH_DMASA_ORDER_Pos) |
| #define | SDH_DMASA_DMASA_Pos (1) |
| #define | SDH_DMASA_DMASA_Msk (0x7ffffffful << SDH_DMASA_DMASA_Pos) |
| #define | SDH_DMABCNT_BCNT_Pos (0) |
| #define | SDH_DMABCNT_BCNT_Msk (0x3fffffful << SDH_DMABCNT_BCNT_Pos) |
| #define | SDH_DMAINTEN_ABORTIEN_Pos (0) |
| #define | SDH_DMAINTEN_ABORTIEN_Msk (0x1ul << SDH_DMAINTEN_ABORTIEN_Pos) |
| #define | SDH_DMAINTEN_WEOTIEN_Pos (1) |
| #define | SDH_DMAINTEN_WEOTIEN_Msk (0x1ul << SDH_DMAINTEN_WEOTIEN_Pos) |
| #define | SDH_DMAINTSTS_ABORTIF_Pos (0) |
| #define | SDH_DMAINTSTS_ABORTIF_Msk (0x1ul << SDH_DMAINTSTS_ABORTIF_Pos) |
| #define | SDH_DMAINTSTS_WEOTIF_Pos (1) |
| #define | SDH_DMAINTSTS_WEOTIF_Msk (0x1ul << SDH_DMAINTSTS_WEOTIF_Pos) |
| #define | SDH_GCTL_GCTLRST_Pos (0) |
| #define | SDH_GCTL_GCTLRST_Msk (0x1ul << SDH_GCTL_GCTLRST_Pos) |
| #define | SDH_GCTL_SDEN_Pos (1) |
| #define | SDH_GCTL_SDEN_Msk (0x1ul << SDH_GCTL_SDEN_Pos) |
| #define | SDH_GINTEN_DTAIEN_Pos (0) |
| #define | SDH_GINTEN_DTAIEN_Msk (0x1ul << SDH_GINTEN_DTAIEN_Pos) |
| #define | SDH_GINTSTS_DTAIF_Pos (0) |
| #define | SDH_GINTSTS_DTAIF_Msk (0x1ul << SDH_GINTSTS_DTAIF_Pos) |
| #define | SDH_CTL_COEN_Pos (0) |
| #define | SDH_CTL_COEN_Msk (0x1ul << SDH_CTL_COEN_Pos) |
| #define | SDH_CTL_RIEN_Pos (1) |
| #define | SDH_CTL_RIEN_Msk (0x1ul << SDH_CTL_RIEN_Pos) |
| #define | SDH_CTL_DIEN_Pos (2) |
| #define | SDH_CTL_DIEN_Msk (0x1ul << SDH_CTL_DIEN_Pos) |
| #define | SDH_CTL_DOEN_Pos (3) |
| #define | SDH_CTL_DOEN_Msk (0x1ul << SDH_CTL_DOEN_Pos) |
| #define | SDH_CTL_R2EN_Pos (4) |
| #define | SDH_CTL_R2EN_Msk (0x1ul << SDH_CTL_R2EN_Pos) |
| #define | SDH_CTL_CLK74OEN_Pos (5) |
| #define | SDH_CTL_CLK74OEN_Msk (0x1ul << SDH_CTL_CLK74OEN_Pos) |
| #define | SDH_CTL_CLK8OEN_Pos (6) |
| #define | SDH_CTL_CLK8OEN_Msk (0x1ul << SDH_CTL_CLK8OEN_Pos) |
| #define | SDH_CTL_CLKKEEP0_Pos (7) |
| #define | SDH_CTL_CLKKEEP0_Msk (0x1ul << SDH_CTL_CLKKEEP0_Pos) |
| #define | SDH_CTL_CMDCODE_Pos (8) |
| #define | SDH_CTL_CMDCODE_Msk (0x3ful << SDH_CTL_CMDCODE_Pos) |
| #define | SDH_CTL_CTLRST_Pos (14) |
| #define | SDH_CTL_CTLRST_Msk (0x1ul << SDH_CTL_CTLRST_Pos) |
| #define | SDH_CTL_DBW_Pos (15) |
| #define | SDH_CTL_DBW_Msk (0x1ul << SDH_CTL_DBW_Pos) |
| #define | SDH_CTL_BLKCNT_Pos (16) |
| #define | SDH_CTL_BLKCNT_Msk (0xfful << SDH_CTL_BLKCNT_Pos) |
| #define | SDH_CTL_SDNWR_Pos (24) |
| #define | SDH_CTL_SDNWR_Msk (0xful << SDH_CTL_SDNWR_Pos) |
| #define | SDH_CTL_SDPORT_Pos (29) |
| #define | SDH_CTL_SDPORT_Msk (0x3ul << SDH_CTL_SDPORT_Pos) |
| #define | SDH_CTL_CLKKEEP1_Pos (31) |
| #define | SDH_CTL_CLKKEEP1_Msk (0x1ul << SDH_CTL_CLKKEEP1_Pos) |
| #define | SDH_CMDARG_ARGUMENT_Pos (0) |
| #define | SDH_CMDARG_ARGUMENT_Msk (0xfffffffful << SDH_CMDARG_ARGUMENT_Pos) |
| #define | SDH_INTEN_BLKDIEN_Pos (0) |
| #define | SDH_INTEN_BLKDIEN_Msk (0x1ul << SDH_INTEN_BLKDIEN_Pos) |
| #define | SDH_INTEN_CRCIEN_Pos (1) |
| #define | SDH_INTEN_CRCIEN_Msk (0x1ul << SDH_INTEN_CRCIEN_Pos) |
| #define | SDH_INTEN_CDIEN0_Pos (8) |
| #define | SDH_INTEN_CDIEN0_Msk (0x1ul << SDH_INTEN_CDIEN0_Pos) |
| #define | SDH_INTEN_CDIEN1_Pos (9) |
| #define | SDH_INTEN_CDIEN1_Msk (0x1ul << SDH_INTEN_CDIEN1_Pos) |
| #define | SDH_INTEN_SDHOST0IEN_Pos (10) |
| #define | SDH_INTEN_SDHOST0IEN_Msk (0x1ul << SDH_INTEN_SDHOST0IEN_Pos) |
| #define | SDH_INTEN_SDHOST1IEN_Pos (11) |
| #define | SDH_INTEN_SDHOST1IEN_Msk (0x1ul << SDH_INTEN_SDHOST1IEN_Pos) |
| #define | SDH_INTEN_RTOIEN_Pos (12) |
| #define | SDH_INTEN_RTOIEN_Msk (0x1ul << SDH_INTEN_RTOIEN_Pos) |
| #define | SDH_INTEN_DITOIEN_Pos (13) |
| #define | SDH_INTEN_DITOIEN_Msk (0x1ul << SDH_INTEN_DITOIEN_Pos) |
| #define | SDH_INTEN_WKIEN_Pos (14) |
| #define | SDH_INTEN_WKIEN_Msk (0x1ul << SDH_INTEN_WKIEN_Pos) |
| #define | SDH_INTEN_CDSRC0_Pos (30) |
| #define | SDH_INTEN_CDSRC0_Msk (0x1ul << SDH_INTEN_CDSRC0_Pos) |
| #define | SDH_INTEN_CDSRC1_Pos (31) |
| #define | SDH_INTEN_CDSRC1_Msk (0x1ul << SDH_INTEN_CDSRC1_Pos) |
| #define | SDH_INTSTS_BLKDIF_Pos (0) |
| #define | SDH_INTSTS_BLKDIF_Msk (0x1ul << SDH_INTSTS_BLKDIF_Pos) |
| #define | SDH_INTSTS_CRCIF_Pos (1) |
| #define | SDH_INTSTS_CRCIF_Msk (0x1ul << SDH_INTSTS_CRCIF_Pos) |
| #define | SDH_INTSTS_CRC7_Pos (2) |
| #define | SDH_INTSTS_CRC7_Msk (0x1ul << SDH_INTSTS_CRC7_Pos) |
| #define | SDH_INTSTS_CRC16_Pos (3) |
| #define | SDH_INTSTS_CRC16_Msk (0x1ul << SDH_INTSTS_CRC16_Pos) |
| #define | SDH_INTSTS_CRCSTS_Pos (4) |
| #define | SDH_INTSTS_CRCSTS_Msk (0x7ul << SDH_INTSTS_CRCSTS_Pos) |
| #define | SDH_INTSTS_DAT0STS_Pos (7) |
| #define | SDH_INTSTS_DAT0STS_Msk (0x1ul << SDH_INTSTS_DAT0STS_Pos) |
| #define | SDH_INTSTS_CDIF0_Pos (8) |
| #define | SDH_INTSTS_CDIF0_Msk (0x1ul << SDH_INTSTS_CDIF0_Pos) |
| #define | SDH_INTSTS_CDIF1_Pos (9) |
| #define | SDH_INTSTS_CDIF1_Msk (0x1ul << SDH_INTSTS_CDIF1_Pos) |
| #define | SDH_INTSTS_SDHOST0IF_Pos (10) |
| #define | SDH_INTSTS_SDHOST0IF_Msk (0x1ul << SDH_INTSTS_SDHOST0IF_Pos) |
| #define | SDH_INTSTS_SDHOST1IF_Pos (11) |
| #define | SDH_INTSTS_SDHOST1IF_Msk (0x1ul << SDH_INTSTS_SDHOST1IF_Pos) |
| #define | SDH_INTSTS_RTOIF_Pos (12) |
| #define | SDH_INTSTS_RTOIF_Msk (0x1ul << SDH_INTSTS_RTOIF_Pos) |
| #define | SDH_INTSTS_DINTOIF_Pos (13) |
| #define | SDH_INTSTS_DINTOIF_Msk (0x1ul << SDH_INTSTS_DINTOIF_Pos) |
| #define | SDH_INTSTS_CDSTS0_Pos (16) |
| #define | SDH_INTSTS_CDSTS0_Msk (0x1ul << SDH_INTSTS_CDSTS0_Pos) |
| #define | SDH_INTSTS_CDSTS1_Pos (17) |
| #define | SDH_INTSTS_CDSTS1_Msk (0x1ul << SDH_INTSTS_CDSTS1_Pos) |
| #define | SDH_INTSTS_DAT1STS_Pos (18) |
| #define | SDH_INTSTS_DAT1STS_Msk (0x1ul << SDH_INTSTS_DAT1STS_Pos) |
| #define | SDH_RESP0_RESPTK0_Pos (0) |
| #define | SDH_RESP0_RESPTK0_Msk (0xfffffffful << SDH_RESP0_RESPTK0_Pos) |
| #define | SDH_RESP1_RESPTK1_Pos (0) |
| #define | SDH_RESP1_RESPTK1_Msk (0xfful << SDH_RESP1_RESPTK1_Pos) |
| #define | SDH_BLEN_BLKLEN_Pos (0) |
| #define | SDH_BLEN_BLKLEN_Msk (0x7fful << SDH_BLEN_BLKLEN_Pos) |
| #define | SDH_TOUT_TOUT_Pos (0) |
| #define | SDH_TOUT_TOUT_Msk (0xfffffful << SDH_TOUT_TOUT_Pos) |
| #define | SPI_CTL_SPIEN_Pos (0) |
| #define | SPI_CTL_SPIEN_Msk (0x1ul << SPI_CTL_SPIEN_Pos) |
| #define | SPI_CTL_RXNEG_Pos (1) |
| #define | SPI_CTL_RXNEG_Msk (0x1ul << SPI_CTL_RXNEG_Pos) |
| #define | SPI_CTL_TXNEG_Pos (2) |
| #define | SPI_CTL_TXNEG_Msk (0x1ul << SPI_CTL_TXNEG_Pos) |
| #define | SPI_CTL_CLKPOL_Pos (3) |
| #define | SPI_CTL_CLKPOL_Msk (0x1ul << SPI_CTL_CLKPOL_Pos) |
| #define | SPI_CTL_SUSPITV_Pos (4) |
| #define | SPI_CTL_SUSPITV_Msk (0xful << SPI_CTL_SUSPITV_Pos) |
| #define | SPI_CTL_DWIDTH_Pos (8) |
| #define | SPI_CTL_DWIDTH_Msk (0x1ful << SPI_CTL_DWIDTH_Pos) |
| #define | SPI_CTL_LSB_Pos (13) |
| #define | SPI_CTL_LSB_Msk (0x1ul << SPI_CTL_LSB_Pos) |
| #define | SPI_CTL_TWOBIT_Pos (16) |
| #define | SPI_CTL_TWOBIT_Msk (0x1ul << SPI_CTL_TWOBIT_Pos) |
| #define | SPI_CTL_UNITIEN_Pos (17) |
| #define | SPI_CTL_UNITIEN_Msk (0x1ul << SPI_CTL_UNITIEN_Pos) |
| #define | SPI_CTL_SLAVE_Pos (18) |
| #define | SPI_CTL_SLAVE_Msk (0x1ul << SPI_CTL_SLAVE_Pos) |
| #define | SPI_CTL_REORDER_Pos (19) |
| #define | SPI_CTL_REORDER_Msk (0x1ul << SPI_CTL_REORDER_Pos) |
| #define | SPI_CTL_QDIODIR_Pos (20) |
| #define | SPI_CTL_QDIODIR_Msk (0x1ul << SPI_CTL_QDIODIR_Pos) |
| #define | SPI_CTL_DUALIOEN_Pos (21) |
| #define | SPI_CTL_DUALIOEN_Msk (0x1ul << SPI_CTL_DUALIOEN_Pos) |
| #define | SPI_CTL_QUADIOEN_Pos (22) |
| #define | SPI_CTL_QUADIOEN_Msk (0x1ul << SPI_CTL_QUADIOEN_Pos) |
| #define | SPI_CLKDIV_DIVIDER_Pos (0) |
| #define | SPI_CLKDIV_DIVIDER_Msk (0xfful << SPI_CLKDIV_DIVIDER_Pos) |
| #define | SPI_SSCTL_SS_Pos (0) |
| #define | SPI_SSCTL_SS_Msk (0x3ul << SPI_SSCTL_SS_Pos) |
| #define | SPI_SSCTL_SSACTPOL_Pos (2) |
| #define | SPI_SSCTL_SSACTPOL_Msk (0x1ul << SPI_SSCTL_SSACTPOL_Pos) |
| #define | SPI_SSCTL_AUTOSS_Pos (3) |
| #define | SPI_SSCTL_AUTOSS_Msk (0x1ul << SPI_SSCTL_AUTOSS_Pos) |
| #define | SPI_SSCTL_SLV3WIRE_Pos (4) |
| #define | SPI_SSCTL_SLV3WIRE_Msk (0x1ul << SPI_SSCTL_SLV3WIRE_Pos) |
| #define | SPI_SSCTL_SLVTOIEN_Pos (5) |
| #define | SPI_SSCTL_SLVTOIEN_Msk (0x1ul << SPI_SSCTL_SLVTOIEN_Pos) |
| #define | SPI_SSCTL_SLVTORST_Pos (6) |
| #define | SPI_SSCTL_SLVTORST_Msk (0x1ul << SPI_SSCTL_SLVTORST_Pos) |
| #define | SPI_SSCTL_SLVBEIEN_Pos (8) |
| #define | SPI_SSCTL_SLVBEIEN_Msk (0x1ul << SPI_SSCTL_SLVBEIEN_Pos) |
| #define | SPI_SSCTL_SLVURIEN_Pos (9) |
| #define | SPI_SSCTL_SLVURIEN_Msk (0x1ul << SPI_SSCTL_SLVURIEN_Pos) |
| #define | SPI_SSCTL_SSACTIEN_Pos (12) |
| #define | SPI_SSCTL_SSACTIEN_Msk (0x1ul << SPI_SSCTL_SSACTIEN_Pos) |
| #define | SPI_SSCTL_SSINAIEN_Pos (13) |
| #define | SPI_SSCTL_SSINAIEN_Msk (0x1ul << SPI_SSCTL_SSINAIEN_Pos) |
| #define | SPI_SSCTL_SLVTOCNT_Pos (16) |
| #define | SPI_SSCTL_SLVTOCNT_Msk (0xfffful << SPI_SSCTL_SLVTOCNT_Pos) |
| #define | SPI_PDMACTL_TXPDMAEN_Pos (0) |
| #define | SPI_PDMACTL_TXPDMAEN_Msk (0x1ul << SPI_PDMACTL_TXPDMAEN_Pos) |
| #define | SPI_PDMACTL_RXPDMAEN_Pos (1) |
| #define | SPI_PDMACTL_RXPDMAEN_Msk (0x1ul << SPI_PDMACTL_RXPDMAEN_Pos) |
| #define | SPI_PDMACTL_PDMARST_Pos (2) |
| #define | SPI_PDMACTL_PDMARST_Msk (0x1ul << SPI_PDMACTL_PDMARST_Pos) |
| #define | SPI_FIFOCTL_RXRST_Pos (0) |
| #define | SPI_FIFOCTL_RXRST_Msk (0x1ul << SPI_FIFOCTL_RXRST_Pos) |
| #define | SPI_FIFOCTL_TXRST_Pos (1) |
| #define | SPI_FIFOCTL_TXRST_Msk (0x1ul << SPI_FIFOCTL_TXRST_Pos) |
| #define | SPI_FIFOCTL_RXTHIEN_Pos (2) |
| #define | SPI_FIFOCTL_RXTHIEN_Msk (0x1ul << SPI_FIFOCTL_RXTHIEN_Pos) |
| #define | SPI_FIFOCTL_TXTHIEN_Pos (3) |
| #define | SPI_FIFOCTL_TXTHIEN_Msk (0x1ul << SPI_FIFOCTL_TXTHIEN_Pos) |
| #define | SPI_FIFOCTL_RXTOIEN_Pos (4) |
| #define | SPI_FIFOCTL_RXTOIEN_Msk (0x1ul << SPI_FIFOCTL_RXTOIEN_Pos) |
| #define | SPI_FIFOCTL_RXOVIEN_Pos (5) |
| #define | SPI_FIFOCTL_RXOVIEN_Msk (0x1ul << SPI_FIFOCTL_RXOVIEN_Pos) |
| #define | SPI_FIFOCTL_TXUFPOL_Pos (6) |
| #define | SPI_FIFOCTL_TXUFPOL_Msk (0x1ul << SPI_FIFOCTL_TXUFPOL_Pos) |
| #define | SPI_FIFOCTL_TXUFIEN_Pos (7) |
| #define | SPI_FIFOCTL_TXUFIEN_Msk (0x1ul << SPI_FIFOCTL_TXUFIEN_Pos) |
| #define | SPI_FIFOCTL_RXTH_Pos (24) |
| #define | SPI_FIFOCTL_RXTH_Msk (0x7ul << SPI_FIFOCTL_RXTH_Pos) |
| #define | SPI_FIFOCTL_TXTH_Pos (28) |
| #define | SPI_FIFOCTL_TXTH_Msk (0x7ul << SPI_FIFOCTL_TXTH_Pos) |
| #define | SPI_STATUS_BUSY_Pos (0) |
| #define | SPI_STATUS_BUSY_Msk (0x1ul << SPI_STATUS_BUSY_Pos) |
| #define | SPI_STATUS_UNITIF_Pos (1) |
| #define | SPI_STATUS_UNITIF_Msk (0x1ul << SPI_STATUS_UNITIF_Pos) |
| #define | SPI_STATUS_SSACTIF_Pos (2) |
| #define | SPI_STATUS_SSACTIF_Msk (0x1ul << SPI_STATUS_SSACTIF_Pos) |
| #define | SPI_STATUS_SSINAIF_Pos (3) |
| #define | SPI_STATUS_SSINAIF_Msk (0x1ul << SPI_STATUS_SSINAIF_Pos) |
| #define | SPI_STATUS_SSLINE_Pos (4) |
| #define | SPI_STATUS_SSLINE_Msk (0x1ul << SPI_STATUS_SSLINE_Pos) |
| #define | SPI_STATUS_SLVTOIF_Pos (5) |
| #define | SPI_STATUS_SLVTOIF_Msk (0x1ul << SPI_STATUS_SLVTOIF_Pos) |
| #define | SPI_STATUS_SLVBEIF_Pos (6) |
| #define | SPI_STATUS_SLVBEIF_Msk (0x1ul << SPI_STATUS_SLVBEIF_Pos) |
| #define | SPI_STATUS_SLVUDRIF_Pos (7) |
| #define | SPI_STATUS_SLVUDRIF_Msk (0x1ul << SPI_STATUS_SLVUDRIF_Pos) |
| #define | SPI_STATUS_RXEMPTY_Pos (8) |
| #define | SPI_STATUS_RXEMPTY_Msk (0x1ul << SPI_STATUS_RXEMPTY_Pos) |
| #define | SPI_STATUS_RXFULL_Pos (9) |
| #define | SPI_STATUS_RXFULL_Msk (0x1ul << SPI_STATUS_RXFULL_Pos) |
| #define | SPI_STATUS_RXTHIF_Pos (10) |
| #define | SPI_STATUS_RXTHIF_Msk (0x1ul << SPI_STATUS_RXTHIF_Pos) |
| #define | SPI_STATUS_RXOVIF_Pos (11) |
| #define | SPI_STATUS_RXOVIF_Msk (0x1ul << SPI_STATUS_RXOVIF_Pos) |
| #define | SPI_STATUS_RXTOIF_Pos (12) |
| #define | SPI_STATUS_RXTOIF_Msk (0x1ul << SPI_STATUS_RXTOIF_Pos) |
| #define | SPI_STATUS_SPIENSTS_Pos (15) |
| #define | SPI_STATUS_SPIENSTS_Msk (0x1ul << SPI_STATUS_SPIENSTS_Pos) |
| #define | SPI_STATUS_TXEMPTY_Pos (16) |
| #define | SPI_STATUS_TXEMPTY_Msk (0x1ul << SPI_STATUS_TXEMPTY_Pos) |
| #define | SPI_STATUS_TXFULL_Pos (17) |
| #define | SPI_STATUS_TXFULL_Msk (0x1ul << SPI_STATUS_TXFULL_Pos) |
| #define | SPI_STATUS_TXTHIF_Pos (18) |
| #define | SPI_STATUS_TXTHIF_Msk (0x1ul << SPI_STATUS_TXTHIF_Pos) |
| #define | SPI_STATUS_TXUFIF_Pos (19) |
| #define | SPI_STATUS_TXUFIF_Msk (0x1ul << SPI_STATUS_TXUFIF_Pos) |
| #define | SPI_STATUS_TXRXRST_Pos (23) |
| #define | SPI_STATUS_TXRXRST_Msk (0x1ul << SPI_STATUS_TXRXRST_Pos) |
| #define | SPI_STATUS_RXCNT_Pos (24) |
| #define | SPI_STATUS_RXCNT_Msk (0xful << SPI_STATUS_RXCNT_Pos) |
| #define | SPI_STATUS_TXCNT_Pos (28) |
| #define | SPI_STATUS_TXCNT_Msk (0xful << SPI_STATUS_TXCNT_Pos) |
| #define | SPI_TX_TX_Pos (0) |
| #define | SPI_TX_TX_Msk (0xfffffffful << SPI_TX_TX_Pos) |
| #define | SPI_RX_RX_Pos (0) |
| #define | SPI_RX_RX_Msk (0xfffffffful << SPI_RX_RX_Pos) |
| #define | SYS_PDID_SYS_PDID_Pos (0) |
| #define | SYS_PDID_SYS_PDID_Msk (0xfffffffful << SYS_PDID_SYS_PDID_Pos) |
| #define | SYS_RSTSTS_PORF_Pos (0) |
| #define | SYS_RSTSTS_PORF_Msk (0x1ul << SYS_RSTSTS_PORF_Pos) |
| #define | SYS_RSTSTS_PINRF_Pos (1) |
| #define | SYS_RSTSTS_PINRF_Msk (0x1ul << SYS_RSTSTS_PINRF_Pos) |
| #define | SYS_RSTSTS_WDTRF_Pos (2) |
| #define | SYS_RSTSTS_WDTRF_Msk (0x1ul << SYS_RSTSTS_WDTRF_Pos) |
| #define | SYS_RSTSTS_LVRF_Pos (3) |
| #define | SYS_RSTSTS_LVRF_Msk (0x1ul << SYS_RSTSTS_LVRF_Pos) |
| #define | SYS_RSTSTS_BODRF_Pos (4) |
| #define | SYS_RSTSTS_BODRF_Msk (0x1ul << SYS_RSTSTS_BODRF_Pos) |
| #define | SYS_RSTSTS_SYSRF_Pos (5) |
| #define | SYS_RSTSTS_SYSRF_Msk (0x1ul << SYS_RSTSTS_SYSRF_Pos) |
| #define | SYS_RSTSTS_CPURF_Pos (7) |
| #define | SYS_RSTSTS_CPURF_Msk (0x1ul << SYS_RSTSTS_CPURF_Pos) |
| #define | SYS_IPRST0_CHIPRST_Pos (0) |
| #define | SYS_IPRST0_CHIPRST_Msk (0x1ul << SYS_IPRST0_CHIPRST_Pos) |
| #define | SYS_IPRST0_CPURST_Pos (1) |
| #define | SYS_IPRST0_CPURST_Msk (0x1ul << SYS_IPRST0_CPURST_Pos) |
| #define | SYS_IPRST0_PDMARST_Pos (2) |
| #define | SYS_IPRST0_PDMARST_Msk (0x1ul << SYS_IPRST0_PDMARST_Pos) |
| #define | SYS_IPRST0_EBIRST_Pos (3) |
| #define | SYS_IPRST0_EBIRST_Msk (0x1ul << SYS_IPRST0_EBIRST_Pos) |
| #define | SYS_IPRST0_USBHRST_Pos (4) |
| #define | SYS_IPRST0_USBHRST_Msk (0x1ul << SYS_IPRST0_USBHRST_Pos) |
| #define | SYS_IPRST0_EMACRST_Pos (5) |
| #define | SYS_IPRST0_EMACRST_Msk (0x1ul << SYS_IPRST0_EMACRST_Pos) |
| #define | SYS_IPRST0_SDHRST_Pos (6) |
| #define | SYS_IPRST0_SDHRST_Msk (0x1ul << SYS_IPRST0_SDHRST_Pos) |
| #define | SYS_IPRST0_CRCRST_Pos (7) |
| #define | SYS_IPRST0_CRCRST_Msk (0x1ul << SYS_IPRST0_CRCRST_Pos) |
| #define | SYS_IPRST0_CAPRST_Pos (8) |
| #define | SYS_IPRST0_CAPRST_Msk (0x1ul << SYS_IPRST0_CAPRST_Pos) |
| #define | SYS_IPRST0_CRPTRST_Pos (12) |
| #define | SYS_IPRST0_CRPTRST_Msk (0x1ul << SYS_IPRST0_CRPTRST_Pos) |
| #define | SYS_IPRST1_GPIORST_Pos (1) |
| #define | SYS_IPRST1_GPIORST_Msk (0x1ul << SYS_IPRST1_GPIORST_Pos) |
| #define | SYS_IPRST1_TMR0RST_Pos (2) |
| #define | SYS_IPRST1_TMR0RST_Msk (0x1ul << SYS_IPRST1_TMR0RST_Pos) |
| #define | SYS_IPRST1_TMR1RST_Pos (3) |
| #define | SYS_IPRST1_TMR1RST_Msk (0x1ul << SYS_IPRST1_TMR1RST_Pos) |
| #define | SYS_IPRST1_TMR2RST_Pos (4) |
| #define | SYS_IPRST1_TMR2RST_Msk (0x1ul << SYS_IPRST1_TMR2RST_Pos) |
| #define | SYS_IPRST1_TMR3RST_Pos (5) |
| #define | SYS_IPRST1_TMR3RST_Msk (0x1ul << SYS_IPRST1_TMR3RST_Pos) |
| #define | SYS_IPRST1_ACMPRST_Pos (7) |
| #define | SYS_IPRST1_ACMPRST_Msk (0x1ul << SYS_IPRST1_ACMPRST_Pos) |
| #define | SYS_IPRST1_I2C0RST_Pos (8) |
| #define | SYS_IPRST1_I2C0RST_Msk (0x1ul << SYS_IPRST1_I2C0RST_Pos) |
| #define | SYS_IPRST1_I2C1RST_Pos (9) |
| #define | SYS_IPRST1_I2C1RST_Msk (0x1ul << SYS_IPRST1_I2C1RST_Pos) |
| #define | SYS_IPRST1_I2C2RST_Pos (10) |
| #define | SYS_IPRST1_I2C2RST_Msk (0x1ul << SYS_IPRST1_I2C2RST_Pos) |
| #define | SYS_IPRST1_I2C3RST_Pos (11) |
| #define | SYS_IPRST1_I2C3RST_Msk (0x1ul << SYS_IPRST1_I2C3RST_Pos) |
| #define | SYS_IPRST1_SPI0RST_Pos (12) |
| #define | SYS_IPRST1_SPI0RST_Msk (0x1ul << SYS_IPRST1_SPI0RST_Pos) |
| #define | SYS_IPRST1_SPI1RST_Pos (13) |
| #define | SYS_IPRST1_SPI1RST_Msk (0x1ul << SYS_IPRST1_SPI1RST_Pos) |
| #define | SYS_IPRST1_SPI2RST_Pos (14) |
| #define | SYS_IPRST1_SPI2RST_Msk (0x1ul << SYS_IPRST1_SPI2RST_Pos) |
| #define | SYS_IPRST1_SPI3RST_Pos (15) |
| #define | SYS_IPRST1_SPI3RST_Msk (0x1ul << SYS_IPRST1_SPI3RST_Pos) |
| #define | SYS_IPRST1_UART0RST_Pos (16) |
| #define | SYS_IPRST1_UART0RST_Msk (0x1ul << SYS_IPRST1_UART0RST_Pos) |
| #define | SYS_IPRST1_UART1RST_Pos (17) |
| #define | SYS_IPRST1_UART1RST_Msk (0x1ul << SYS_IPRST1_UART1RST_Pos) |
| #define | SYS_IPRST1_UART2RST_Pos (18) |
| #define | SYS_IPRST1_UART2RST_Msk (0x1ul << SYS_IPRST1_UART2RST_Pos) |
| #define | SYS_IPRST1_UART3RST_Pos (19) |
| #define | SYS_IPRST1_UART3RST_Msk (0x1ul << SYS_IPRST1_UART3RST_Pos) |
| #define | SYS_IPRST1_UART4RST_Pos (20) |
| #define | SYS_IPRST1_UART4RST_Msk (0x1ul << SYS_IPRST1_UART4RST_Pos) |
| #define | SYS_IPRST1_UART5RST_Pos (21) |
| #define | SYS_IPRST1_UART5RST_Msk (0x1ul << SYS_IPRST1_UART5RST_Pos) |
| #define | SYS_IPRST1_CAN0RST_Pos (24) |
| #define | SYS_IPRST1_CAN0RST_Msk (0x1ul << SYS_IPRST1_CAN0RST_Pos) |
| #define | SYS_IPRST1_CAN1RST_Pos (25) |
| #define | SYS_IPRST1_CAN1RST_Msk (0x1ul << SYS_IPRST1_CAN1RST_Pos) |
| #define | SYS_IPRST1_USBDRST_Pos (27) |
| #define | SYS_IPRST1_USBDRST_Msk (0x1ul << SYS_IPRST1_USBDRST_Pos) |
| #define | SYS_IPRST1_ADCRST_Pos (28) |
| #define | SYS_IPRST1_ADCRST_Msk (0x1ul << SYS_IPRST1_ADCRST_Pos) |
| #define | SYS_IPRST1_I2S0RST_Pos (29) |
| #define | SYS_IPRST1_I2S0RST_Msk (0x1ul << SYS_IPRST1_I2S0RST_Pos) |
| #define | SYS_IPRST1_I2S1RST_Pos (30) |
| #define | SYS_IPRST1_I2S1RST_Msk (0x1ul << SYS_IPRST1_I2S1RST_Pos) |
| #define | SYS_IPRST1_PS2RST_Pos (31) |
| #define | SYS_IPRST1_PS2RST_Msk (0x1ul << SYS_IPRST1_PS2RST_Pos) |
| #define | SYS_IPRST2_SC0RST_Pos (0) |
| #define | SYS_IPRST2_SC0RST_Msk (0x1ul << SYS_IPRST2_SC0RST_Pos) |
| #define | SYS_IPRST2_SC1RST_Pos (1) |
| #define | SYS_IPRST2_SC1RST_Msk (0x1ul << SYS_IPRST2_SC1RST_Pos) |
| #define | SYS_IPRST2_SC2RST_Pos (2) |
| #define | SYS_IPRST2_SC2RST_Msk (0x1ul << SYS_IPRST2_SC2RST_Pos) |
| #define | SYS_IPRST2_SC3RST_Pos (3) |
| #define | SYS_IPRST2_SC3RST_Msk (0x1ul << SYS_IPRST2_SC3RST_Pos) |
| #define | SYS_IPRST2_SC4RST_Pos (4) |
| #define | SYS_IPRST2_SC4RST_Msk (0x1ul << SYS_IPRST2_SC4RST_Pos) |
| #define | SYS_IPRST2_SC5RST_Pos (5) |
| #define | SYS_IPRST2_SC5RST_Msk (0x1ul << SYS_IPRST2_SC5RST_Pos) |
| #define | SYS_IPRST2_I2C4RST_Pos (8) |
| #define | SYS_IPRST2_I2C4RST_Msk (0x1ul << SYS_IPRST2_I2C4RST_Pos) |
| #define | SYS_IPRST2_PWM0RST_Pos (16) |
| #define | SYS_IPRST2_PWM0RST_Msk (0x1ul << SYS_IPRST2_PWM0RST_Pos) |
| #define | SYS_IPRST2_PWM1RST_Pos (17) |
| #define | SYS_IPRST2_PWM1RST_Msk (0x1ul << SYS_IPRST2_PWM1RST_Pos) |
| #define | SYS_IPRST2_QEI0RST_Pos (22) |
| #define | SYS_IPRST2_QEI0RST_Msk (0x1ul << SYS_IPRST2_QEI0RST_Pos) |
| #define | SYS_IPRST2_QEI1RST_Pos (23) |
| #define | SYS_IPRST2_QEI1RST_Msk (0x1ul << SYS_IPRST2_QEI1RST_Pos) |
| #define | SYS_BODCTL_BODEN_Pos (0) |
| #define | SYS_BODCTL_BODEN_Msk (0x1ul << SYS_BODCTL_BODEN_Pos) |
| #define | SYS_BODCTL_BODVL_Pos (1) |
| #define | SYS_BODCTL_BODVL_Msk (0x3ul << SYS_BODCTL_BODVL_Pos) |
| #define | SYS_BODCTL_BODRSTEN_Pos (3) |
| #define | SYS_BODCTL_BODRSTEN_Msk (0x1ul << SYS_BODCTL_BODRSTEN_Pos) |
| #define | SYS_BODCTL_BODINTF_Pos (4) |
| #define | SYS_BODCTL_BODINTF_Msk (0x1ul << SYS_BODCTL_BODINTF_Pos) |
| #define | SYS_BODCTL_BODLPM_Pos (5) |
| #define | SYS_BODCTL_BODLPM_Msk (0x1ul << SYS_BODCTL_BODLPM_Pos) |
| #define | SYS_BODCTL_BODOUT_Pos (6) |
| #define | SYS_BODCTL_BODOUT_Msk (0x1ul << SYS_BODCTL_BODOUT_Pos) |
| #define | SYS_BODCTL_LVREN_Pos (7) |
| #define | SYS_BODCTL_LVREN_Msk (0x1ul << SYS_BODCTL_LVREN_Pos) |
| #define | SYS_TEMPCTL_VTEMPEN_Pos (0) |
| #define | SYS_TEMPCTL_VTEMPEN_Msk (0x1ul << SYS_TEMPCTL_VTEMPEN_Pos) |
| #define | SYS_VCID_VCID_Pos (0) |
| #define | SYS_VCID_VCID_Msk (0xfffful << SYS_VCID_VCID_Pos) |
| #define | SYS_PORCTL_POROFF_Pos (0) |
| #define | SYS_PORCTL_POROFF_Msk (0xfffful << SYS_PORCTL_POROFF_Pos) |
| #define | SYS_VREFCTL_VREFCTL_Pos (0) |
| #define | SYS_VREFCTL_VREFCTL_Msk (0x1ful << SYS_VREFCTL_VREFCTL_Pos) |
| #define | SYS_VREFCTL_ADCMODESEL_Pos (8) |
| #define | SYS_VREFCTL_ADCMODESEL_Msk (0x1ul << SYS_VREFCTL_ADCMODESEL_Pos) |
| #define | SYS_VREFCTL_PWMSYNCMODE_Pos (9) |
| #define | SYS_VREFCTL_PWMSYNCMODE_Msk (0x1ul << SYS_VREFCTL_PWMSYNCMODE_Pos) |
| #define | SYS_USBPHY_USBROLE_Pos (0) |
| #define | SYS_USBPHY_USBROLE_Msk (0x3ul << SYS_USBPHY_USBROLE_Pos) |
| #define | SYS_USBPHY_LDO33EN_Pos (8) |
| #define | SYS_USBPHY_LDO33EN_Msk (0x1ul << SYS_USBPHY_LDO33EN_Pos) |
| #define | SYS_GPA_MFPL_PA0MFP_Pos (0) |
| #define | SYS_GPA_MFPL_PA0MFP_Msk (0xful << SYS_GPA_MFPL_PA0MFP_Pos) |
| #define | SYS_GPA_MFPL_PA1MFP_Pos (4) |
| #define | SYS_GPA_MFPL_PA1MFP_Msk (0xful << SYS_GPA_MFPL_PA1MFP_Pos) |
| #define | SYS_GPA_MFPL_PA2MFP_Pos (8) |
| #define | SYS_GPA_MFPL_PA2MFP_Msk (0xful << SYS_GPA_MFPL_PA2MFP_Pos) |
| #define | SYS_GPA_MFPL_PA3MFP_Pos (12) |
| #define | SYS_GPA_MFPL_PA3MFP_Msk (0xful << SYS_GPA_MFPL_PA3MFP_Pos) |
| #define | SYS_GPA_MFPL_PA4MFP_Pos (16) |
| #define | SYS_GPA_MFPL_PA4MFP_Msk (0xful << SYS_GPA_MFPL_PA4MFP_Pos) |
| #define | SYS_GPA_MFPL_PA5MFP_Pos (20) |
| #define | SYS_GPA_MFPL_PA5MFP_Msk (0xful << SYS_GPA_MFPL_PA5MFP_Pos) |
| #define | SYS_GPA_MFPL_PA6MFP_Pos (24) |
| #define | SYS_GPA_MFPL_PA6MFP_Msk (0xful << SYS_GPA_MFPL_PA6MFP_Pos) |
| #define | SYS_GPA_MFPL_PA7MFP_Pos (28) |
| #define | SYS_GPA_MFPL_PA7MFP_Msk (0xful << SYS_GPA_MFPL_PA7MFP_Pos) |
| #define | SYS_GPA_MFPH_PA8MFP_Pos (0) |
| #define | SYS_GPA_MFPH_PA8MFP_Msk (0xful << SYS_GPA_MFPH_PA8MFP_Pos) |
| #define | SYS_GPA_MFPH_PA9MFP_Pos (4) |
| #define | SYS_GPA_MFPH_PA9MFP_Msk (0xful << SYS_GPA_MFPH_PA9MFP_Pos) |
| #define | SYS_GPA_MFPH_PA10MFP_Pos (8) |
| #define | SYS_GPA_MFPH_PA10MFP_Msk (0xful << SYS_GPA_MFPH_PA10MFP_Pos) |
| #define | SYS_GPA_MFPH_PA11MFP_Pos (12) |
| #define | SYS_GPA_MFPH_PA11MFP_Msk (0xful << SYS_GPA_MFPH_PA11MFP_Pos) |
| #define | SYS_GPA_MFPH_PA12MFP_Pos (16) |
| #define | SYS_GPA_MFPH_PA12MFP_Msk (0xful << SYS_GPA_MFPH_PA12MFP_Pos) |
| #define | SYS_GPA_MFPH_PA13MFP_Pos (20) |
| #define | SYS_GPA_MFPH_PA13MFP_Msk (0xful << SYS_GPA_MFPH_PA13MFP_Pos) |
| #define | SYS_GPA_MFPH_PA14MFP_Pos (24) |
| #define | SYS_GPA_MFPH_PA14MFP_Msk (0xful << SYS_GPA_MFPH_PA14MFP_Pos) |
| #define | SYS_GPA_MFPH_PA15MFP_Pos (28) |
| #define | SYS_GPA_MFPH_PA15MFP_Msk (0xful << SYS_GPA_MFPH_PA15MFP_Pos) |
| #define | SYS_GPB_MFPL_PB0MFP_Pos (0) |
| #define | SYS_GPB_MFPL_PB0MFP_Msk (0xful << SYS_GPB_MFPL_PB0MFP_Pos) |
| #define | SYS_GPB_MFPL_PB1MFP_Pos (4) |
| #define | SYS_GPB_MFPL_PB1MFP_Msk (0xful << SYS_GPB_MFPL_PB1MFP_Pos) |
| #define | SYS_GPB_MFPL_PB2MFP_Pos (8) |
| #define | SYS_GPB_MFPL_PB2MFP_Msk (0xful << SYS_GPB_MFPL_PB2MFP_Pos) |
| #define | SYS_GPB_MFPL_PB3MFP_Pos (12) |
| #define | SYS_GPB_MFPL_PB3MFP_Msk (0xful << SYS_GPB_MFPL_PB3MFP_Pos) |
| #define | SYS_GPB_MFPL_PB4MFP_Pos (16) |
| #define | SYS_GPB_MFPL_PB4MFP_Msk (0xful << SYS_GPB_MFPL_PB4MFP_Pos) |
| #define | SYS_GPB_MFPL_PB5MFP_Pos (20) |
| #define | SYS_GPB_MFPL_PB5MFP_Msk (0xful << SYS_GPB_MFPL_PB5MFP_Pos) |
| #define | SYS_GPB_MFPL_PB6MFP_Pos (24) |
| #define | SYS_GPB_MFPL_PB6MFP_Msk (0xful << SYS_GPB_MFPL_PB6MFP_Pos) |
| #define | SYS_GPB_MFPL_PB7MFP_Pos (28) |
| #define | SYS_GPB_MFPL_PB7MFP_Msk (0xful << SYS_GPB_MFPL_PB7MFP_Pos) |
| #define | SYS_GPB_MFPH_PB8MFP_Pos (0) |
| #define | SYS_GPB_MFPH_PB8MFP_Msk (0xful << SYS_GPB_MFPH_PB8MFP_Pos) |
| #define | SYS_GPB_MFPH_PB9MFP_Pos (4) |
| #define | SYS_GPB_MFPH_PB9MFP_Msk (0xful << SYS_GPB_MFPH_PB9MFP_Pos) |
| #define | SYS_GPB_MFPH_PB10MFP_Pos (8) |
| #define | SYS_GPB_MFPH_PB10MFP_Msk (0xful << SYS_GPB_MFPH_PB10MFP_Pos) |
| #define | SYS_GPB_MFPH_PB11MFP_Pos (12) |
| #define | SYS_GPB_MFPH_PB11MFP_Msk (0xful << SYS_GPB_MFPH_PB11MFP_Pos) |
| #define | SYS_GPB_MFPH_PB12MFP_Pos (16) |
| #define | SYS_GPB_MFPH_PB12MFP_Msk (0xful << SYS_GPB_MFPH_PB12MFP_Pos) |
| #define | SYS_GPB_MFPH_PB13MFP_Pos (20) |
| #define | SYS_GPB_MFPH_PB13MFP_Msk (0xful << SYS_GPB_MFPH_PB13MFP_Pos) |
| #define | SYS_GPB_MFPH_PB14MFP_Pos (24) |
| #define | SYS_GPB_MFPH_PB14MFP_Msk (0xful << SYS_GPB_MFPH_PB14MFP_Pos) |
| #define | SYS_GPB_MFPH_PB15MFP_Pos (28) |
| #define | SYS_GPB_MFPH_PB15MFP_Msk (0xful << SYS_GPB_MFPH_PB15MFP_Pos) |
| #define | SYS_GPC_MFPL_PC0MFP_Pos (0) |
| #define | SYS_GPC_MFPL_PC0MFP_Msk (0xful << SYS_GPC_MFPL_PC0MFP_Pos) |
| #define | SYS_GPC_MFPL_PC1MFP_Pos (4) |
| #define | SYS_GPC_MFPL_PC1MFP_Msk (0xful << SYS_GPC_MFPL_PC1MFP_Pos) |
| #define | SYS_GPC_MFPL_PC2MFP_Pos (8) |
| #define | SYS_GPC_MFPL_PC2MFP_Msk (0xful << SYS_GPC_MFPL_PC2MFP_Pos) |
| #define | SYS_GPC_MFPL_PC3MFP_Pos (12) |
| #define | SYS_GPC_MFPL_PC3MFP_Msk (0xful << SYS_GPC_MFPL_PC3MFP_Pos) |
| #define | SYS_GPC_MFPL_PC4MFP_Pos (16) |
| #define | SYS_GPC_MFPL_PC4MFP_Msk (0xful << SYS_GPC_MFPL_PC4MFP_Pos) |
| #define | SYS_GPC_MFPL_PC5MFP_Pos (20) |
| #define | SYS_GPC_MFPL_PC5MFP_Msk (0xful << SYS_GPC_MFPL_PC5MFP_Pos) |
| #define | SYS_GPC_MFPL_PC6MFP_Pos (24) |
| #define | SYS_GPC_MFPL_PC6MFP_Msk (0xful << SYS_GPC_MFPL_PC6MFP_Pos) |
| #define | SYS_GPC_MFPL_PC7MFP_Pos (28) |
| #define | SYS_GPC_MFPL_PC7MFP_Msk (0xful << SYS_GPC_MFPL_PC7MFP_Pos) |
| #define | SYS_GPC_MFPH_PC8MFP_Pos (0) |
| #define | SYS_GPC_MFPH_PC8MFP_Msk (0xful << SYS_GPC_MFPH_PC8MFP_Pos) |
| #define | SYS_GPC_MFPH_PC9MFP_Pos (4) |
| #define | SYS_GPC_MFPH_PC9MFP_Msk (0xful << SYS_GPC_MFPH_PC9MFP_Pos) |
| #define | SYS_GPC_MFPH_PC10MFP_Pos (8) |
| #define | SYS_GPC_MFPH_PC10MFP_Msk (0xful << SYS_GPC_MFPH_PC10MFP_Pos) |
| #define | SYS_GPC_MFPH_PC11MFP_Pos (12) |
| #define | SYS_GPC_MFPH_PC11MFP_Msk (0xful << SYS_GPC_MFPH_PC11MFP_Pos) |
| #define | SYS_GPC_MFPH_PC12MFP_Pos (16) |
| #define | SYS_GPC_MFPH_PC12MFP_Msk (0xful << SYS_GPC_MFPH_PC12MFP_Pos) |
| #define | SYS_GPC_MFPH_PC13MFP_Pos (20) |
| #define | SYS_GPC_MFPH_PC13MFP_Msk (0xful << SYS_GPC_MFPH_PC13MFP_Pos) |
| #define | SYS_GPC_MFPH_PC14MFP_Pos (24) |
| #define | SYS_GPC_MFPH_PC14MFP_Msk (0xful << SYS_GPC_MFPH_PC14MFP_Pos) |
| #define | SYS_GPC_MFPH_PC15MFP_Pos (28) |
| #define | SYS_GPC_MFPH_PC15MFP_Msk (0xful << SYS_GPC_MFPH_PC15MFP_Pos) |
| #define | SYS_GPD_MFPL_PD0MFP_Pos (0) |
| #define | SYS_GPD_MFPL_PD0MFP_Msk (0xful << SYS_GPD_MFPL_PD0MFP_Pos) |
| #define | SYS_GPD_MFPL_PD1MFP_Pos (4) |
| #define | SYS_GPD_MFPL_PD1MFP_Msk (0xful << SYS_GPD_MFPL_PD1MFP_Pos) |
| #define | SYS_GPD_MFPL_PD2MFP_Pos (8) |
| #define | SYS_GPD_MFPL_PD2MFP_Msk (0xful << SYS_GPD_MFPL_PD2MFP_Pos) |
| #define | SYS_GPD_MFPL_PD3MFP_Pos (12) |
| #define | SYS_GPD_MFPL_PD3MFP_Msk (0xful << SYS_GPD_MFPL_PD3MFP_Pos) |
| #define | SYS_GPD_MFPL_PD4MFP_Pos (16) |
| #define | SYS_GPD_MFPL_PD4MFP_Msk (0xful << SYS_GPD_MFPL_PD4MFP_Pos) |
| #define | SYS_GPD_MFPL_PD5MFP_Pos (20) |
| #define | SYS_GPD_MFPL_PD5MFP_Msk (0xful << SYS_GPD_MFPL_PD5MFP_Pos) |
| #define | SYS_GPD_MFPL_PD6MFP_Pos (24) |
| #define | SYS_GPD_MFPL_PD6MFP_Msk (0xful << SYS_GPD_MFPL_PD6MFP_Pos) |
| #define | SYS_GPD_MFPL_PD7MFP_Pos (28) |
| #define | SYS_GPD_MFPL_PD7MFP_Msk (0xful << SYS_GPD_MFPL_PD7MFP_Pos) |
| #define | SYS_GPD_MFPH_PD8MFP_Pos (0) |
| #define | SYS_GPD_MFPH_PD8MFP_Msk (0xful << SYS_GPD_MFPH_PD8MFP_Pos) |
| #define | SYS_GPD_MFPH_PD9MFP_Pos (4) |
| #define | SYS_GPD_MFPH_PD9MFP_Msk (0xful << SYS_GPD_MFPH_PD9MFP_Pos) |
| #define | SYS_GPD_MFPH_PD10MFP_Pos (8) |
| #define | SYS_GPD_MFPH_PD10MFP_Msk (0xful << SYS_GPD_MFPH_PD10MFP_Pos) |
| #define | SYS_GPD_MFPH_PD11MFP_Pos (12) |
| #define | SYS_GPD_MFPH_PD11MFP_Msk (0xful << SYS_GPD_MFPH_PD11MFP_Pos) |
| #define | SYS_GPD_MFPH_PD12MFP_Pos (16) |
| #define | SYS_GPD_MFPH_PD12MFP_Msk (0xful << SYS_GPD_MFPH_PD12MFP_Pos) |
| #define | SYS_GPD_MFPH_PD13MFP_Pos (20) |
| #define | SYS_GPD_MFPH_PD13MFP_Msk (0xful << SYS_GPD_MFPH_PD13MFP_Pos) |
| #define | SYS_GPD_MFPH_PD14MFP_Pos (24) |
| #define | SYS_GPD_MFPH_PD14MFP_Msk (0xful << SYS_GPD_MFPH_PD14MFP_Pos) |
| #define | SYS_GPD_MFPH_PD15MFP_Pos (28) |
| #define | SYS_GPD_MFPH_PD15MFP_Msk (0xful << SYS_GPD_MFPH_PD15MFP_Pos) |
| #define | SYS_GPE_MFPL_PE0MFP_Pos (0) |
| #define | SYS_GPE_MFPL_PE0MFP_Msk (0xful << SYS_GPE_MFPL_PE0MFP_Pos) |
| #define | SYS_GPE_MFPL_PE1MFP_Pos (4) |
| #define | SYS_GPE_MFPL_PE1MFP_Msk (0xful << SYS_GPE_MFPL_PE1MFP_Pos) |
| #define | SYS_GPE_MFPL_PE2MFP_Pos (8) |
| #define | SYS_GPE_MFPL_PE2MFP_Msk (0xful << SYS_GPE_MFPL_PE2MFP_Pos) |
| #define | SYS_GPE_MFPL_PE3MFP_Pos (12) |
| #define | SYS_GPE_MFPL_PE3MFP_Msk (0xful << SYS_GPE_MFPL_PE3MFP_Pos) |
| #define | SYS_GPE_MFPL_PE4MFP_Pos (16) |
| #define | SYS_GPE_MFPL_PE4MFP_Msk (0xful << SYS_GPE_MFPL_PE4MFP_Pos) |
| #define | SYS_GPE_MFPL_PE5MFP_Pos (20) |
| #define | SYS_GPE_MFPL_PE5MFP_Msk (0xful << SYS_GPE_MFPL_PE5MFP_Pos) |
| #define | SYS_GPE_MFPL_PE6MFP_Pos (24) |
| #define | SYS_GPE_MFPL_PE6MFP_Msk (0xful << SYS_GPE_MFPL_PE6MFP_Pos) |
| #define | SYS_GPE_MFPL_PE7MFP_Pos (28) |
| #define | SYS_GPE_MFPL_PE7MFP_Msk (0xful << SYS_GPE_MFPL_PE7MFP_Pos) |
| #define | SYS_GPE_MFPH_PE8MFP_Pos (0) |
| #define | SYS_GPE_MFPH_PE8MFP_Msk (0xful << SYS_GPE_MFPH_PE8MFP_Pos) |
| #define | SYS_GPE_MFPH_PE9MFP_Pos (4) |
| #define | SYS_GPE_MFPH_PE9MFP_Msk (0xful << SYS_GPE_MFPH_PE9MFP_Pos) |
| #define | SYS_GPE_MFPH_PE10MFP_Pos (8) |
| #define | SYS_GPE_MFPH_PE10MFP_Msk (0xful << SYS_GPE_MFPH_PE10MFP_Pos) |
| #define | SYS_GPE_MFPH_PE11MFP_Pos (12) |
| #define | SYS_GPE_MFPH_PE11MFP_Msk (0xful << SYS_GPE_MFPH_PE11MFP_Pos) |
| #define | SYS_GPE_MFPH_PE12MFP_Pos (16) |
| #define | SYS_GPE_MFPH_PE12MFP_Msk (0xful << SYS_GPE_MFPH_PE12MFP_Pos) |
| #define | SYS_GPE_MFPH_PE13MFP_Pos (20) |
| #define | SYS_GPE_MFPH_PE13MFP_Msk (0xful << SYS_GPE_MFPH_PE13MFP_Pos) |
| #define | SYS_GPE_MFPH_PE14MFP_Pos (24) |
| #define | SYS_GPE_MFPH_PE14MFP_Msk (0xful << SYS_GPE_MFPH_PE14MFP_Pos) |
| #define | SYS_GPE_MFPH_PE15MFP_Pos (28) |
| #define | SYS_GPE_MFPH_PE15MFP_Msk (0xful << SYS_GPE_MFPH_PE15MFP_Pos) |
| #define | SYS_GPF_MFPL_PF0MFP_Pos (0) |
| #define | SYS_GPF_MFPL_PF0MFP_Msk (0xful << SYS_GPF_MFPL_PF0MFP_Pos) |
| #define | SYS_GPF_MFPL_PF1MFP_Pos (4) |
| #define | SYS_GPF_MFPL_PF1MFP_Msk (0xful << SYS_GPF_MFPL_PF1MFP_Pos) |
| #define | SYS_GPF_MFPL_PF2MFP_Pos (8) |
| #define | SYS_GPF_MFPL_PF2MFP_Msk (0xful << SYS_GPF_MFPL_PF2MFP_Pos) |
| #define | SYS_GPF_MFPL_PF3MFP_Pos (12) |
| #define | SYS_GPF_MFPL_PF3MFP_Msk (0xful << SYS_GPF_MFPL_PF3MFP_Pos) |
| #define | SYS_GPF_MFPL_PF4MFP_Pos (16) |
| #define | SYS_GPF_MFPL_PF4MFP_Msk (0xful << SYS_GPF_MFPL_PF4MFP_Pos) |
| #define | SYS_GPF_MFPL_PF5MFP_Pos (20) |
| #define | SYS_GPF_MFPL_PF5MFP_Msk (0xful << SYS_GPF_MFPL_PF5MFP_Pos) |
| #define | SYS_GPF_MFPL_PF6MFP_Pos (24) |
| #define | SYS_GPF_MFPL_PF6MFP_Msk (0xful << SYS_GPF_MFPL_PF6MFP_Pos) |
| #define | SYS_GPF_MFPL_PF7MFP_Pos (28) |
| #define | SYS_GPF_MFPL_PF7MFP_Msk (0xful << SYS_GPF_MFPL_PF7MFP_Pos) |
| #define | SYS_GPF_MFPH_PF8MFP_Pos (0) |
| #define | SYS_GPF_MFPH_PF8MFP_Msk (0xful << SYS_GPF_MFPH_PF8MFP_Pos) |
| #define | SYS_GPF_MFPH_PF9MFP_Pos (4) |
| #define | SYS_GPF_MFPH_PF9MFP_Msk (0xful << SYS_GPF_MFPH_PF9MFP_Pos) |
| #define | SYS_GPF_MFPH_PF10MFP_Pos (8) |
| #define | SYS_GPF_MFPH_PF10MFP_Msk (0xful << SYS_GPF_MFPH_PF10MFP_Pos) |
| #define | SYS_GPF_MFPH_PF11MFP_Pos (12) |
| #define | SYS_GPF_MFPH_PF11MFP_Msk (0xful << SYS_GPF_MFPH_PF11MFP_Pos) |
| #define | SYS_GPF_MFPH_PF12MFP_Pos (16) |
| #define | SYS_GPF_MFPH_PF12MFP_Msk (0xful << SYS_GPF_MFPH_PF12MFP_Pos) |
| #define | SYS_GPF_MFPH_PF13MFP_Pos (20) |
| #define | SYS_GPF_MFPH_PF13MFP_Msk (0xful << SYS_GPF_MFPH_PF13MFP_Pos) |
| #define | SYS_GPF_MFPH_PF14MFP_Pos (24) |
| #define | SYS_GPF_MFPH_PF14MFP_Msk (0xful << SYS_GPF_MFPH_PF14MFP_Pos) |
| #define | SYS_GPF_MFPH_PF15MFP_Pos (28) |
| #define | SYS_GPF_MFPH_PF15MFP_Msk (0xful << SYS_GPF_MFPH_PF15MFP_Pos) |
| #define | SYS_GPG_MFPL_PG0MFP_Pos (0) |
| #define | SYS_GPG_MFPL_PG0MFP_Msk (0xful << SYS_GPG_MFPL_PG0MFP_Pos) |
| #define | SYS_GPG_MFPL_PG1MFP_Pos (4) |
| #define | SYS_GPG_MFPL_PG1MFP_Msk (0xful << SYS_GPG_MFPL_PG1MFP_Pos) |
| #define | SYS_GPG_MFPL_PG2MFP_Pos (8) |
| #define | SYS_GPG_MFPL_PG2MFP_Msk (0xful << SYS_GPG_MFPL_PG2MFP_Pos) |
| #define | SYS_GPG_MFPL_PG3MFP_Pos (12) |
| #define | SYS_GPG_MFPL_PG3MFP_Msk (0xful << SYS_GPG_MFPL_PG3MFP_Pos) |
| #define | SYS_GPG_MFPL_PG4MFP_Pos (16) |
| #define | SYS_GPG_MFPL_PG4MFP_Msk (0xful << SYS_GPG_MFPL_PG4MFP_Pos) |
| #define | SYS_GPG_MFPL_PG5MFP_Pos (20) |
| #define | SYS_GPG_MFPL_PG5MFP_Msk (0xful << SYS_GPG_MFPL_PG5MFP_Pos) |
| #define | SYS_GPG_MFPL_PG6MFP_Pos (24) |
| #define | SYS_GPG_MFPL_PG6MFP_Msk (0xful << SYS_GPG_MFPL_PG6MFP_Pos) |
| #define | SYS_GPG_MFPL_PG7MFP_Pos (28) |
| #define | SYS_GPG_MFPL_PG7MFP_Msk (0xful << SYS_GPG_MFPL_PG7MFP_Pos) |
| #define | SYS_GPG_MFPH_PG8MFP_Pos (0) |
| #define | SYS_GPG_MFPH_PG8MFP_Msk (0xful << SYS_GPG_MFPH_PG8MFP_Pos) |
| #define | SYS_GPG_MFPH_PG9MFP_Pos (4) |
| #define | SYS_GPG_MFPH_PG9MFP_Msk (0xful << SYS_GPG_MFPH_PG9MFP_Pos) |
| #define | SYS_GPG_MFPH_PG10MFP_Pos (8) |
| #define | SYS_GPG_MFPH_PG10MFP_Msk (0xful << SYS_GPG_MFPH_PG10MFP_Pos) |
| #define | SYS_GPG_MFPH_PG11MFP_Pos (12) |
| #define | SYS_GPG_MFPH_PG11MFP_Msk (0xful << SYS_GPG_MFPH_PG11MFP_Pos) |
| #define | SYS_GPG_MFPH_PG12MFP_Pos (16) |
| #define | SYS_GPG_MFPH_PG12MFP_Msk (0xful << SYS_GPG_MFPH_PG12MFP_Pos) |
| #define | SYS_GPG_MFPH_PG13MFP_Pos (20) |
| #define | SYS_GPG_MFPH_PG13MFP_Msk (0xful << SYS_GPG_MFPH_PG13MFP_Pos) |
| #define | SYS_GPG_MFPH_PG14MFP_Pos (24) |
| #define | SYS_GPG_MFPH_PG14MFP_Msk (0xful << SYS_GPG_MFPH_PG14MFP_Pos) |
| #define | SYS_GPG_MFPH_PG15MFP_Pos (28) |
| #define | SYS_GPG_MFPH_PG15MFP_Msk (0xful << SYS_GPG_MFPH_PG15MFP_Pos) |
| #define | SYS_GPH_MFPL_PH0MFP_Pos (0) |
| #define | SYS_GPH_MFPL_PH0MFP_Msk (0xful << SYS_GPH_MFPL_PH0MFP_Pos) |
| #define | SYS_GPH_MFPL_PH1MFP_Pos (4) |
| #define | SYS_GPH_MFPL_PH1MFP_Msk (0xful << SYS_GPH_MFPL_PH1MFP_Pos) |
| #define | SYS_GPH_MFPL_PH2MFP_Pos (8) |
| #define | SYS_GPH_MFPL_PH2MFP_Msk (0xful << SYS_GPH_MFPL_PH2MFP_Pos) |
| #define | SYS_GPH_MFPL_PH3MFP_Pos (12) |
| #define | SYS_GPH_MFPL_PH3MFP_Msk (0xful << SYS_GPH_MFPL_PH3MFP_Pos) |
| #define | SYS_GPH_MFPL_PH4MFP_Pos (16) |
| #define | SYS_GPH_MFPL_PH4MFP_Msk (0xful << SYS_GPH_MFPL_PH4MFP_Pos) |
| #define | SYS_GPH_MFPL_PH5MFP_Pos (20) |
| #define | SYS_GPH_MFPL_PH5MFP_Msk (0xful << SYS_GPH_MFPL_PH5MFP_Pos) |
| #define | SYS_GPH_MFPL_PH6MFP_Pos (24) |
| #define | SYS_GPH_MFPL_PH6MFP_Msk (0xful << SYS_GPH_MFPL_PH6MFP_Pos) |
| #define | SYS_GPH_MFPL_PH7MFP_Pos (28) |
| #define | SYS_GPH_MFPL_PH7MFP_Msk (0xful << SYS_GPH_MFPL_PH7MFP_Pos) |
| #define | SYS_GPH_MFPH_PH8MFP_Pos (0) |
| #define | SYS_GPH_MFPH_PH8MFP_Msk (0xful << SYS_GPH_MFPH_PH8MFP_Pos) |
| #define | SYS_GPH_MFPH_PH9MFP_Pos (4) |
| #define | SYS_GPH_MFPH_PH9MFP_Msk (0xful << SYS_GPH_MFPH_PH9MFP_Pos) |
| #define | SYS_GPH_MFPH_PH10MFP_Pos (8) |
| #define | SYS_GPH_MFPH_PH10MFP_Msk (0xful << SYS_GPH_MFPH_PH10MFP_Pos) |
| #define | SYS_GPH_MFPH_PH11MFP_Pos (12) |
| #define | SYS_GPH_MFPH_PH11MFP_Msk (0xful << SYS_GPH_MFPH_PH11MFP_Pos) |
| #define | SYS_GPH_MFPH_PH12MFP_Pos (16) |
| #define | SYS_GPH_MFPH_PH12MFP_Msk (0xful << SYS_GPH_MFPH_PH12MFP_Pos) |
| #define | SYS_GPH_MFPH_PH13MFP_Pos (20) |
| #define | SYS_GPH_MFPH_PH13MFP_Msk (0xful << SYS_GPH_MFPH_PH13MFP_Pos) |
| #define | SYS_GPH_MFPH_PH14MFP_Pos (24) |
| #define | SYS_GPH_MFPH_PH14MFP_Msk (0xful << SYS_GPH_MFPH_PH14MFP_Pos) |
| #define | SYS_GPH_MFPH_PH15MFP_Pos (28) |
| #define | SYS_GPH_MFPH_PH15MFP_Msk (0xful << SYS_GPH_MFPH_PH15MFP_Pos) |
| #define | SYS_GPI_MFPL_PI0MFP_Pos (0) |
| #define | SYS_GPI_MFPL_PI0MFP_Msk (0xful << SYS_GPI_MFPL_PI0MFP_Pos) |
| #define | SYS_GPI_MFPL_PI1MFP_Pos (4) |
| #define | SYS_GPI_MFPL_PI1MFP_Msk (0xful << SYS_GPI_MFPL_PI1MFP_Pos) |
| #define | SYS_GPI_MFPL_PI2MFP_Pos (8) |
| #define | SYS_GPI_MFPL_PI2MFP_Msk (0xful << SYS_GPI_MFPL_PI2MFP_Pos) |
| #define | SYS_GPI_MFPL_PI3MFP_Pos (12) |
| #define | SYS_GPI_MFPL_PI3MFP_Msk (0xful << SYS_GPI_MFPL_PI3MFP_Pos) |
| #define | SYS_GPI_MFPL_PI4MFP_Pos (16) |
| #define | SYS_GPI_MFPL_PI4MFP_Msk (0xful << SYS_GPI_MFPL_PI4MFP_Pos) |
| #define | SYS_GPI_MFPL_PI5MFP_Pos (20) |
| #define | SYS_GPI_MFPL_PI5MFP_Msk (0xful << SYS_GPI_MFPL_PI5MFP_Pos) |
| #define | SYS_GPI_MFPL_PI6MFP_Pos (24) |
| #define | SYS_GPI_MFPL_PI6MFP_Msk (0xful << SYS_GPI_MFPL_PI6MFP_Pos) |
| #define | SYS_GPI_MFPL_PI7MFP_Pos (28) |
| #define | SYS_GPI_MFPL_PI7MFP_Msk (0xful << SYS_GPI_MFPL_PI7MFP_Pos) |
| #define | SYS_GPI_MFPH_PI8MFP_Pos (0) |
| #define | SYS_GPI_MFPH_PI8MFP_Msk (0xful << SYS_GPI_MFPH_PI8MFP_Pos) |
| #define | SYS_GPI_MFPH_PI9MFP_Pos (4) |
| #define | SYS_GPI_MFPH_PI9MFP_Msk (0xful << SYS_GPI_MFPH_PI9MFP_Pos) |
| #define | SYS_GPI_MFPH_PI10MFP_Pos (8) |
| #define | SYS_GPI_MFPH_PI10MFP_Msk (0xful << SYS_GPI_MFPH_PI10MFP_Pos) |
| #define | SYS_GPI_MFPH_PI11MFP_Pos (12) |
| #define | SYS_GPI_MFPH_PI11MFP_Msk (0xful << SYS_GPI_MFPH_PI11MFP_Pos) |
| #define | SYS_GPI_MFPH_PI12MFP_Pos (16) |
| #define | SYS_GPI_MFPH_PI12MFP_Msk (0xful << SYS_GPI_MFPH_PI12MFP_Pos) |
| #define | SYS_GPI_MFPH_PI13MFP_Pos (20) |
| #define | SYS_GPI_MFPH_PI13MFP_Msk (0xful << SYS_GPI_MFPH_PI13MFP_Pos) |
| #define | SYS_GPI_MFPH_PI14MFP_Pos (24) |
| #define | SYS_GPI_MFPH_PI14MFP_Msk (0xful << SYS_GPI_MFPH_PI14MFP_Pos) |
| #define | SYS_GPI_MFPH_PI15MFP_Pos (28) |
| #define | SYS_GPI_MFPH_PI15MFP_Msk (0xful << SYS_GPI_MFPH_PI15MFP_Pos) |
| #define | SYS_SRAM_INTCTL_PERRIEN_Pos (0) |
| #define | SYS_SRAM_INTCTL_PERRIEN_Msk (0x1ul << SYS_SRAM_INTCTL_PERRIEN_Pos) |
| #define | SYS_SRAM_STATUS_PERRIF0_Pos (0) |
| #define | SYS_SRAM_STATUS_PERRIF0_Msk (0x1ul << SYS_SRAM_STATUS_PERRIF0_Pos) |
| #define | SYS_SRAM_STATUS_PERRIF1_Pos (1) |
| #define | SYS_SRAM_STATUS_PERRIF1_Msk (0x1ul << SYS_SRAM_STATUS_PERRIF1_Pos) |
| #define | SYS_SRAM0_ERRADDR_PERRADDR_Pos (0) |
| #define | SYS_SRAM0_ERRADDR_PERRADDR_Msk (0xfffffffful << SYS_SRAM0_ERRADDR_PERRADDR_Pos) |
| #define | SYS_SRAM1_ERRADDR_PERRADDR_Pos (0) |
| #define | SYS_SRAM1_ERRADDR_PERRADDR_Msk (0xfffffffful << SYS_SRAM1_ERRADDR_PERRADDR_Pos) |
| #define | SYS_IRCTCTL_FREQSEL_Pos (0) |
| #define | SYS_IRCTCTL_FREQSEL_Msk (0x3ul << SYS_IRCTCTL_FREQSEL_Pos) |
| #define | SYS_IRCTCTL_CALCLOOP_Pos (4) |
| #define | SYS_IRCTCTL_CALCLOOP_Msk (0x3ul << SYS_IRCTCTL_CALCLOOP_Pos) |
| #define | SYS_IRCTCTL_RETRYCNT_Pos (6) |
| #define | SYS_IRCTCTL_RETRYCNT_Msk (0x3ul << SYS_IRCTCTL_RETRYCNT_Pos) |
| #define | SYS_IRCTCTL_CESTOPEN_Pos (8) |
| #define | SYS_IRCTCTL_CESTOPEN_Msk (0x1ul << SYS_IRCTCTL_CESTOPEN_Pos) |
| #define | SYS_IRCTIEN_TFAILIEN_Pos (1) |
| #define | SYS_IRCTIEN_TFAILIEN_Msk (0x1ul << SYS_IRCTIEN_TFAILIEN_Pos) |
| #define | SYS_IRCTIEN_CLKEIEN_Pos (2) |
| #define | SYS_IRCTIEN_CLKEIEN_Msk (0x1ul << SYS_IRCTIEN_CLKEIEN_Pos) |
| #define | SYS_IRCTISTS_FREQLOCK_Pos (0) |
| #define | SYS_IRCTISTS_FREQLOCK_Msk (0x1ul << SYS_IRCTISTS_FREQLOCK_Pos) |
| #define | SYS_IRCTISTS_TFAILIF_Pos (1) |
| #define | SYS_IRCTISTS_TFAILIF_Msk (0x1ul << SYS_IRCTISTS_TFAILIF_Pos) |
| #define | SYS_IRCTISTS_CLKERRIF_Pos (2) |
| #define | SYS_IRCTISTS_CLKERRIF_Msk (0x1ul << SYS_IRCTISTS_CLKERRIF_Pos) |
| #define | SYS_REGLCTL_REGLCTL_Pos (0) |
| #define | SYS_REGLCTL_REGLCTL_Msk (0x1ul << SYS_REGLCTL_REGLCTL_Pos) |
| #define | SYS_REGLCTL_SYS_REGLCTL_Pos (0) |
| #define | SYS_REGLCTL_SYS_REGLCTL_Msk (0xfful << SYS_REGLCTL_SYS_REGLCTL_Pos) |
| #define | TIMER_CTL_PSC_Pos (0) |
| #define | TIMER_CTL_PSC_Msk (0xfful << TIMER_CTL_PSC_Pos) |
| #define | TIMER_CTL_CNTDATEN_Pos (16) |
| #define | TIMER_CTL_CNTDATEN_Msk (0x1ul << TIMER_CTL_CNTDATEN_Pos) |
| #define | TIMER_CTL_TOGDIS1_Pos (21) |
| #define | TIMER_CTL_TOGDIS1_Msk (0x1ul << TIMER_CTL_TOGDIS1_Pos) |
| #define | TIMER_CTL_TOGDIS2_Pos (22) |
| #define | TIMER_CTL_TOGDIS2_Msk (0x1ul << TIMER_CTL_TOGDIS2_Pos) |
| #define | TIMER_CTL_WKEN_Pos (23) |
| #define | TIMER_CTL_WKEN_Msk (0x1ul << TIMER_CTL_WKEN_Pos) |
| #define | TIMER_CTL_EXTCNTEN_Pos (24) |
| #define | TIMER_CTL_EXTCNTEN_Msk (0x1ul << TIMER_CTL_EXTCNTEN_Pos) |
| #define | TIMER_CTL_ACTSTS_Pos (25) |
| #define | TIMER_CTL_ACTSTS_Msk (0x1ul << TIMER_CTL_ACTSTS_Pos) |
| #define | TIMER_CTL_RSTCNT_Pos (26) |
| #define | TIMER_CTL_RSTCNT_Msk (0x1ul << TIMER_CTL_RSTCNT_Pos) |
| #define | TIMER_CTL_OPMODE_Pos (27) |
| #define | TIMER_CTL_OPMODE_Msk (0x3ul << TIMER_CTL_OPMODE_Pos) |
| #define | TIMER_CTL_INTEN_Pos (29) |
| #define | TIMER_CTL_INTEN_Msk (0x1ul << TIMER_CTL_INTEN_Pos) |
| #define | TIMER_CTL_CNTEN_Pos (30) |
| #define | TIMER_CTL_CNTEN_Msk (0x1ul << TIMER_CTL_CNTEN_Pos) |
| #define | TIMER_CTL_ICEDEBUG_Pos (31) |
| #define | TIMER_CTL_ICEDEBUG_Msk (0x1ul << TIMER_CTL_ICEDEBUG_Pos) |
| #define | TIMER_CMP_CMPDAT_Pos (0) |
| #define | TIMER_CMP_CMPDAT_Msk (0xfffffful << TIMER_CMP_CMPDAT_Pos) |
| #define | TIMER_INTSTS_TIF_Pos (0) |
| #define | TIMER_INTSTS_TIF_Msk (0x1ul << TIMER_INTSTS_TIF_Pos) |
| #define | TIMER_INTSTS_TWKF_Pos (1) |
| #define | TIMER_INTSTS_TWKF_Msk (0x1ul << TIMER_INTSTS_TWKF_Pos) |
| #define | TIMER_CNT_TIMER_CNT_Pos (0) |
| #define | TIMER_CNT_TIMER_CNT_Msk (0xfffffful << TIMER_CNT_TIMER_CNT_Pos) |
| #define | TIMER_CAP_CAPDAT_Pos (0) |
| #define | TIMER_CAP_CAPDAT_Msk (0xfffffful << TIMER_CAP_CAPDAT_Pos) |
| #define | TIMER_EXTCTL_CNTPHASE_Pos (0) |
| #define | TIMER_EXTCTL_CNTPHASE_Msk (0x1ul << TIMER_EXTCTL_CNTPHASE_Pos) |
| #define | TIMER_EXTCTL_CAPEDGE_Pos (1) |
| #define | TIMER_EXTCTL_CAPEDGE_Msk (0x3ul << TIMER_EXTCTL_CAPEDGE_Pos) |
| #define | TIMER_EXTCTL_CAPEN_Pos (3) |
| #define | TIMER_EXTCTL_CAPEN_Msk (0x1ul << TIMER_EXTCTL_CAPEN_Pos) |
| #define | TIMER_EXTCTL_CAPFUNCS_Pos (4) |
| #define | TIMER_EXTCTL_CAPFUNCS_Msk (0x1ul << TIMER_EXTCTL_CAPFUNCS_Pos) |
| #define | TIMER_EXTCTL_CAPIEN_Pos (5) |
| #define | TIMER_EXTCTL_CAPIEN_Msk (0x1ul << TIMER_EXTCTL_CAPIEN_Pos) |
| #define | TIMER_EXTCTL_CAPDBEN_Pos (6) |
| #define | TIMER_EXTCTL_CAPDBEN_Msk (0x1ul << TIMER_EXTCTL_CAPDBEN_Pos) |
| #define | TIMER_EXTCTL_ECNTDBEN_Pos (7) |
| #define | TIMER_EXTCTL_ECNTDBEN_Msk (0x1ul << TIMER_EXTCTL_ECNTDBEN_Pos) |
| #define | TIMER_EINTSTS_CAPIF_Pos (0) |
| #define | TIMER_EINTSTS_CAPIF_Msk (0x1ul << TIMER_EINTSTS_CAPIF_Pos) |
| #define | UART_DAT_DAT_Pos (0) |
| #define | UART_DAT_DAT_Msk (0xfful << UART_DAT_DAT_Pos) |
| #define | UART_INTEN_RDAIEN_Pos (0) |
| #define | UART_INTEN_RDAIEN_Msk (0x1ul << UART_INTEN_RDAIEN_Pos) |
| #define | UART_INTEN_THREIEN_Pos (1) |
| #define | UART_INTEN_THREIEN_Msk (0x1ul << UART_INTEN_THREIEN_Pos) |
| #define | UART_INTEN_RLSIEN_Pos (2) |
| #define | UART_INTEN_RLSIEN_Msk (0x1ul << UART_INTEN_RLSIEN_Pos) |
| #define | UART_INTEN_MODEMIEN_Pos (3) |
| #define | UART_INTEN_MODEMIEN_Msk (0x1ul << UART_INTEN_MODEMIEN_Pos) |
| #define | UART_INTEN_RXTOIEN_Pos (4) |
| #define | UART_INTEN_RXTOIEN_Msk (0x1ul << UART_INTEN_RXTOIEN_Pos) |
| #define | UART_INTEN_BUFERRIEN_Pos (5) |
| #define | UART_INTEN_BUFERRIEN_Msk (0x1ul << UART_INTEN_BUFERRIEN_Pos) |
| #define | UART_INTEN_WKCTSIEN_Pos (6) |
| #define | UART_INTEN_WKCTSIEN_Msk (0x1ul << UART_INTEN_WKCTSIEN_Pos) |
| #define | UART_INTEN_LINIEN_Pos (8) |
| #define | UART_INTEN_LINIEN_Msk (0x1ul << UART_INTEN_LINIEN_Pos) |
| #define | UART_INTEN_TOCNTEN_Pos (11) |
| #define | UART_INTEN_TOCNTEN_Msk (0x1ul << UART_INTEN_TOCNTEN_Pos) |
| #define | UART_INTEN_ATORTSEN_Pos (12) |
| #define | UART_INTEN_ATORTSEN_Msk (0x1ul << UART_INTEN_ATORTSEN_Pos) |
| #define | UART_INTEN_ATOCTSEN_Pos (13) |
| #define | UART_INTEN_ATOCTSEN_Msk (0x1ul << UART_INTEN_ATOCTSEN_Pos) |
| #define | UART_INTEN_TXPDMAEN_Pos (14) |
| #define | UART_INTEN_TXPDMAEN_Msk (0x1ul << UART_INTEN_TXPDMAEN_Pos) |
| #define | UART_INTEN_RXPDMAEN_Pos (15) |
| #define | UART_INTEN_RXPDMAEN_Msk (0x1ul << UART_INTEN_RXPDMAEN_Pos) |
| #define | UART_FIFO_RXRST_Pos (1) |
| #define | UART_FIFO_RXRST_Msk (0x1ul << UART_FIFO_RXRST_Pos) |
| #define | UART_FIFO_TXRST_Pos (2) |
| #define | UART_FIFO_TXRST_Msk (0x1ul << UART_FIFO_TXRST_Pos) |
| #define | UART_FIFO_RFITL_Pos (4) |
| #define | UART_FIFO_RFITL_Msk (0xful << UART_FIFO_RFITL_Pos) |
| #define | UART_FIFO_RXOFF_Pos (8) |
| #define | UART_FIFO_RXOFF_Msk (0x1ul << UART_FIFO_RXOFF_Pos) |
| #define | UART_FIFO_RTSTRGLV_Pos (16) |
| #define | UART_FIFO_RTSTRGLV_Msk (0xful << UART_FIFO_RTSTRGLV_Pos) |
| #define | UART_LINE_WLS_Pos (0) |
| #define | UART_LINE_WLS_Msk (0x3ul << UART_LINE_WLS_Pos) |
| #define | UART_LINE_NSB_Pos (2) |
| #define | UART_LINE_NSB_Msk (0x1ul << UART_LINE_NSB_Pos) |
| #define | UART_LINE_PBE_Pos (3) |
| #define | UART_LINE_PBE_Msk (0x1ul << UART_LINE_PBE_Pos) |
| #define | UART_LINE_EPE_Pos (4) |
| #define | UART_LINE_EPE_Msk (0x1ul << UART_LINE_EPE_Pos) |
| #define | UART_LINE_SPE_Pos (5) |
| #define | UART_LINE_SPE_Msk (0x1ul << UART_LINE_SPE_Pos) |
| #define | UART_LINE_BCB_Pos (6) |
| #define | UART_LINE_BCB_Msk (0x1ul << UART_LINE_BCB_Pos) |
| #define | UART_MODEM_RTS_Pos (1) |
| #define | UART_MODEM_RTS_Msk (0x1ul << UART_MODEM_RTS_Pos) |
| #define | UART_MODEM_RTSACTLV_Pos (9) |
| #define | UART_MODEM_RTSACTLV_Msk (0x1ul << UART_MODEM_RTSACTLV_Pos) |
| #define | UART_MODEM_RTSSTS_Pos (13) |
| #define | UART_MODEM_RTSSTS_Msk (0x1ul << UART_MODEM_RTSSTS_Pos) |
| #define | UART_MODEMSTS_CTSDETF_Pos (0) |
| #define | UART_MODEMSTS_CTSDETF_Msk (0x1ul << UART_MODEMSTS_CTSDETF_Pos) |
| #define | UART_MODEMSTS_CTSSTS_Pos (4) |
| #define | UART_MODEMSTS_CTSSTS_Msk (0x1ul << UART_MODEMSTS_CTSSTS_Pos) |
| #define | UART_MODEMSTS_CTSACTLV_Pos (8) |
| #define | UART_MODEMSTS_CTSACTLV_Msk (0x1ul << UART_MODEMSTS_CTSACTLV_Pos) |
| #define | UART_FIFOSTS_RXOVIF_Pos (0) |
| #define | UART_FIFOSTS_RXOVIF_Msk (0x1ul << UART_FIFOSTS_RXOVIF_Pos) |
| #define | UART_FIFOSTS_SCERR_Pos (2) |
| #define | UART_FIFOSTS_SCERR_Msk (0x1ul << UART_FIFOSTS_SCERR_Pos) |
| #define | UART_FIFOSTS_ADDRDETF_Pos (3) |
| #define | UART_FIFOSTS_ADDRDETF_Msk (0x1ul << UART_FIFOSTS_ADDRDETF_Pos) |
| #define | UART_FIFOSTS_PEF_Pos (4) |
| #define | UART_FIFOSTS_PEF_Msk (0x1ul << UART_FIFOSTS_PEF_Pos) |
| #define | UART_FIFOSTS_FEF_Pos (5) |
| #define | UART_FIFOSTS_FEF_Msk (0x1ul << UART_FIFOSTS_FEF_Pos) |
| #define | UART_FIFOSTS_BIF_Pos (6) |
| #define | UART_FIFOSTS_BIF_Msk (0x1ul << UART_FIFOSTS_BIF_Pos) |
| #define | UART_FIFOSTS_RXPTR_Pos (8) |
| #define | UART_FIFOSTS_RXPTR_Msk (0x3ful << UART_FIFOSTS_RXPTR_Pos) |
| #define | UART_FIFOSTS_RXEMPTY_Pos (14) |
| #define | UART_FIFOSTS_RXEMPTY_Msk (0x1ul << UART_FIFOSTS_RXEMPTY_Pos) |
| #define | UART_FIFOSTS_RXFULL_Pos (15) |
| #define | UART_FIFOSTS_RXFULL_Msk (0x1ul << UART_FIFOSTS_RXFULL_Pos) |
| #define | UART_FIFOSTS_TXPTR_Pos (16) |
| #define | UART_FIFOSTS_TXPTR_Msk (0x3ful << UART_FIFOSTS_TXPTR_Pos) |
| #define | UART_FIFOSTS_TXEMPTY_Pos (22) |
| #define | UART_FIFOSTS_TXEMPTY_Msk (0x1ul << UART_FIFOSTS_TXEMPTY_Pos) |
| #define | UART_FIFOSTS_TXFULL_Pos (23) |
| #define | UART_FIFOSTS_TXFULL_Msk (0x1ul << UART_FIFOSTS_TXFULL_Pos) |
| #define | UART_FIFOSTS_TXOVIF_Pos (24) |
| #define | UART_FIFOSTS_TXOVIF_Msk (0x1ul << UART_FIFOSTS_TXOVIF_Pos) |
| #define | UART_FIFOSTS_TXEMPTYF_Pos (28) |
| #define | UART_FIFOSTS_TXEMPTYF_Msk (0x1ul << UART_FIFOSTS_TXEMPTYF_Pos) |
| #define | UART_INTSTS_RDAIF_Pos (0) |
| #define | UART_INTSTS_RDAIF_Msk (0x1ul << UART_INTSTS_RDAIF_Pos) |
| #define | UART_INTSTS_THREIF_Pos (1) |
| #define | UART_INTSTS_THREIF_Msk (0x1ul << UART_INTSTS_THREIF_Pos) |
| #define | UART_INTSTS_RLSIF_Pos (2) |
| #define | UART_INTSTS_RLSIF_Msk (0x1ul << UART_INTSTS_RLSIF_Pos) |
| #define | UART_INTSTS_MODEMIF_Pos (3) |
| #define | UART_INTSTS_MODEMIF_Msk (0x1ul << UART_INTSTS_MODEMIF_Pos) |
| #define | UART_INTSTS_RXTOIF_Pos (4) |
| #define | UART_INTSTS_RXTOIF_Msk (0x1ul << UART_INTSTS_RXTOIF_Pos) |
| #define | UART_INTSTS_BUFERRIF_Pos (5) |
| #define | UART_INTSTS_BUFERRIF_Msk (0x1ul << UART_INTSTS_BUFERRIF_Pos) |
| #define | UART_INTSTS_LINIF_Pos (7) |
| #define | UART_INTSTS_LINIF_Msk (0x1ul << UART_INTSTS_LINIF_Pos) |
| #define | UART_INTSTS_RDAINT_Pos (8) |
| #define | UART_INTSTS_RDAINT_Msk (0x1ul << UART_INTSTS_RDAINT_Pos) |
| #define | UART_INTSTS_THREINT_Pos (9) |
| #define | UART_INTSTS_THREINT_Msk (0x1ul << UART_INTSTS_THREINT_Pos) |
| #define | UART_INTSTS_RLSINT_Pos (10) |
| #define | UART_INTSTS_RLSINT_Msk (0x1ul << UART_INTSTS_RLSINT_Pos) |
| #define | UART_INTSTS_MODEMINT_Pos (11) |
| #define | UART_INTSTS_MODEMINT_Msk (0x1ul << UART_INTSTS_MODEMINT_Pos) |
| #define | UART_INTSTS_RXTOINT_Pos (12) |
| #define | UART_INTSTS_RXTOINT_Msk (0x1ul << UART_INTSTS_RXTOINT_Pos) |
| #define | UART_INTSTS_BUFERRINT_Pos (13) |
| #define | UART_INTSTS_BUFERRINT_Msk (0x1ul << UART_INTSTS_BUFERRINT_Pos) |
| #define | UART_INTSTS_LININT_Pos (15) |
| #define | UART_INTSTS_LININT_Msk (0x1ul << UART_INTSTS_LININT_Pos) |
| #define | UART_INTSTS_HWRLSIF_Pos (18) |
| #define | UART_INTSTS_HWRLSIF_Msk (0x1ul << UART_INTSTS_HWRLSIF_Pos) |
| #define | UART_INTSTS_HWMODIF_Pos (19) |
| #define | UART_INTSTS_HWMODIF_Msk (0x1ul << UART_INTSTS_HWMODIF_Pos) |
| #define | UART_INTSTS_HWTOIF_Pos (20) |
| #define | UART_INTSTS_HWTOIF_Msk (0x1ul << UART_INTSTS_HWTOIF_Pos) |
| #define | UART_INTSTS_HWBUFEIF_Pos (21) |
| #define | UART_INTSTS_HWBUFEIF_Msk (0x1ul << UART_INTSTS_HWBUFEIF_Pos) |
| #define | UART_INTSTS_HWRLSINT_Pos (26) |
| #define | UART_INTSTS_HWRLSINT_Msk (0x1ul << UART_INTSTS_HWRLSINT_Pos) |
| #define | UART_INTSTS_HWMODINT_Pos (27) |
| #define | UART_INTSTS_HWMODINT_Msk (0x1ul << UART_INTSTS_HWMODINT_Pos) |
| #define | UART_INTSTS_HWTOINT_Pos (28) |
| #define | UART_INTSTS_HWTOINT_Msk (0x1ul << UART_INTSTS_HWTOINT_Pos) |
| #define | UART_INTSTS_HWBUFEINT_Pos (29) |
| #define | UART_INTSTS_HWBUFEINT_Msk (0x1ul << UART_INTSTS_HWBUFEINT_Pos) |
| #define | UART_TOUT_TOIC_Pos (0) |
| #define | UART_TOUT_TOIC_Msk (0xfful << UART_TOUT_TOIC_Pos) |
| #define | UART_TOUT_DLY_Pos (8) |
| #define | UART_TOUT_DLY_Msk (0xfful << UART_TOUT_DLY_Pos) |
| #define | UART_BAUD_BRD_Pos (0) |
| #define | UART_BAUD_BRD_Msk (0xfffful << UART_BAUD_BRD_Pos) |
| #define | UART_BAUD_EDIVM1_Pos (24) |
| #define | UART_BAUD_EDIVM1_Msk (0xful << UART_BAUD_EDIVM1_Pos) |
| #define | UART_BAUD_BAUDM0_Pos (28) |
| #define | UART_BAUD_BAUDM0_Msk (0x1ul << UART_BAUD_BAUDM0_Pos) |
| #define | UART_BAUD_BAUDM1_Pos (29) |
| #define | UART_BAUD_BAUDM1_Msk (0x1ul << UART_BAUD_BAUDM1_Pos) |
| #define | UART_IRDA_TXEN_Pos (1) |
| #define | UART_IRDA_TXEN_Msk (0x1ul << UART_IRDA_TXEN_Pos) |
| #define | UART_IRDA_TXINV_Pos (5) |
| #define | UART_IRDA_TXINV_Msk (0x1ul << UART_IRDA_TXINV_Pos) |
| #define | UART_IRDA_RXINV_Pos (6) |
| #define | UART_IRDA_RXINV_Msk (0x1ul << UART_IRDA_RXINV_Pos) |
| #define | UART_IRDA_FIXPULSE_Pos (7) |
| #define | UART_IRDA_FIXPULSE_Msk (0x1ul << UART_IRDA_FIXPULSE_Pos) |
| #define | UART_ALTCTL_BKFL_Pos (0) |
| #define | UART_ALTCTL_BKFL_Msk (0xful << UART_ALTCTL_BKFL_Pos) |
| #define | UART_ALTCTL_LINRXEN_Pos (6) |
| #define | UART_ALTCTL_LINRXEN_Msk (0x1ul << UART_ALTCTL_LINRXEN_Pos) |
| #define | UART_ALTCTL_LINTXEN_Pos (7) |
| #define | UART_ALTCTL_LINTXEN_Msk (0x1ul << UART_ALTCTL_LINTXEN_Pos) |
| #define | UART_ALTCTL_RS485NMM_Pos (8) |
| #define | UART_ALTCTL_RS485NMM_Msk (0x1ul << UART_ALTCTL_RS485NMM_Pos) |
| #define | UART_ALTCTL_RS485AAD_Pos (9) |
| #define | UART_ALTCTL_RS485AAD_Msk (0x1ul << UART_ALTCTL_RS485AAD_Pos) |
| #define | UART_ALTCTL_RS485AUD_Pos (10) |
| #define | UART_ALTCTL_RS485AUD_Msk (0x1ul << UART_ALTCTL_RS485AUD_Pos) |
| #define | UART_ALTCTL_ADDRDEN_Pos (15) |
| #define | UART_ALTCTL_ADDRDEN_Msk (0x1ul << UART_ALTCTL_ADDRDEN_Pos) |
| #define | UART_ALTCTL_ADDRMV_Pos (24) |
| #define | UART_ALTCTL_ADDRMV_Msk (0xfful << UART_ALTCTL_ADDRMV_Pos) |
| #define | UART_FUNCSEL_FUNCSEL_Pos (0) |
| #define | UART_FUNCSEL_FUNCSEL_Msk (0x7ul << UART_FUNCSEL_FUNCSEL_Pos) |
| #define | UART_LINCTL_SLVEN_Pos (0) |
| #define | UART_LINCTL_SLVEN_Msk (0x1ul << UART_LINCTL_SLVEN_Pos) |
| #define | UART_LINCTL_SLVHDEN_Pos (1) |
| #define | UART_LINCTL_SLVHDEN_Msk (0x1ul << UART_LINCTL_SLVHDEN_Pos) |
| #define | UART_LINCTL_SLVAREN_Pos (2) |
| #define | UART_LINCTL_SLVAREN_Msk (0x1ul << UART_LINCTL_SLVAREN_Pos) |
| #define | UART_LINCTL_SLVDUEN_Pos (3) |
| #define | UART_LINCTL_SLVDUEN_Msk (0x1ul << UART_LINCTL_SLVDUEN_Pos) |
| #define | UART_LINCTL_MUTE_Pos (4) |
| #define | UART_LINCTL_MUTE_Msk (0x1ul << UART_LINCTL_MUTE_Pos) |
| #define | UART_LINCTL_SENDH_Pos (8) |
| #define | UART_LINCTL_SENDH_Msk (0x1ul << UART_LINCTL_SENDH_Pos) |
| #define | UART_LINCTL_IDPEN_Pos (9) |
| #define | UART_LINCTL_IDPEN_Msk (0x1ul << UART_LINCTL_IDPEN_Pos) |
| #define | UART_LINCTL_BRKDETEN_Pos (10) |
| #define | UART_LINCTL_BRKDETEN_Msk (0x1ul << UART_LINCTL_BRKDETEN_Pos) |
| #define | UART_LINCTL_RXOFF_Pos (11) |
| #define | UART_LINCTL_RXOFF_Msk (0x1ul << UART_LINCTL_RXOFF_Pos) |
| #define | UART_LINCTL_BITERREN_Pos (12) |
| #define | UART_LINCTL_BITERREN_Msk (0x1ul << UART_LINCTL_BITERREN_Pos) |
| #define | UART_LINCTL_BRKFL_Pos (16) |
| #define | UART_LINCTL_BRKFL_Msk (0xful << UART_LINCTL_BRKFL_Pos) |
| #define | UART_LINCTL_BSL_Pos (20) |
| #define | UART_LINCTL_BSL_Msk (0x3ul << UART_LINCTL_BSL_Pos) |
| #define | UART_LINCTL_HSEL_Pos (22) |
| #define | UART_LINCTL_HSEL_Msk (0x3ul << UART_LINCTL_HSEL_Pos) |
| #define | UART_LINCTL_PID_Pos (24) |
| #define | UART_LINCTL_PID_Msk (0xfful << UART_LINCTL_PID_Pos) |
| #define | UART_LINSTS_SLVHDETF_Pos (0) |
| #define | UART_LINSTS_SLVHDETF_Msk (0x1ul << UART_LINSTS_SLVHDETF_Pos) |
| #define | UART_LINSTS_SLVHEF_Pos (1) |
| #define | UART_LINSTS_SLVHEF_Msk (0x1ul << UART_LINSTS_SLVHEF_Pos) |
| #define | UART_LINSTS_SLVIDPEF_Pos (2) |
| #define | UART_LINSTS_SLVIDPEF_Msk (0x1ul << UART_LINSTS_SLVIDPEF_Pos) |
| #define | UART_LINSTS_SLVSYNCF_Pos (3) |
| #define | UART_LINSTS_SLVSYNCF_Msk (0x1ul << UART_LINSTS_SLVSYNCF_Pos) |
| #define | UART_LINSTS_BRKDETF_Pos (8) |
| #define | UART_LINSTS_BRKDETF_Msk (0x1ul << UART_LINSTS_BRKDETF_Pos) |
| #define | UART_LINSTS_BITEF_Pos (9) |
| #define | UART_LINSTS_BITEF_Msk (0x1ul << UART_LINSTS_BITEF_Pos) |
| #define | UART_LINDEBUG_DEVERRF_Pos (0) |
| #define | UART_LINDEBUG_DEVERRF_Msk (0x1ul << UART_LINDEBUG_DEVERRF_Pos) |
| #define | UART_LINDEBUG_TOF_Pos (1) |
| #define | UART_LINDEBUG_TOF_Msk (0x1ul << UART_LINDEBUG_TOF_Pos) |
| #define | UART_LINDEBUG_FRAMEERRF_Pos (2) |
| #define | UART_LINDEBUG_FRAMEERRF_Msk (0x1ul << UART_LINDEBUG_FRAMEERRF_Pos) |
| #define | UART_LINDEBUG_SYNCERRF_Pos (3) |
| #define | UART_LINDEBUG_SYNCERRF_Msk (0x1ul << UART_LINDEBUG_SYNCERRF_Pos) |
| #define | USBH_HcRevision_REV_Pos (0) |
| #define | USBH_HcRevision_REV_Msk (0xfful << USBH_HcRevision_REV_Pos) |
| #define | USBH_HcControl_CBSR_Pos (0) |
| #define | USBH_HcControl_CBSR_Msk (0x3ul << USBH_HcControl_CBSR_Pos) |
| #define | USBH_HcControl_PLE_Pos (2) |
| #define | USBH_HcControl_PLE_Msk (0x1ul << USBH_HcControl_PLE_Pos) |
| #define | USBH_HcControl_IE_Pos (3) |
| #define | USBH_HcControl_IE_Msk (0x1ul << USBH_HcControl_IE_Pos) |
| #define | USBH_HcControl_CLE_Pos (4) |
| #define | USBH_HcControl_CLE_Msk (0x1ul << USBH_HcControl_CLE_Pos) |
| #define | USBH_HcControl_BLE_Pos (5) |
| #define | USBH_HcControl_BLE_Msk (0x1ul << USBH_HcControl_BLE_Pos) |
| #define | USBH_HcControl_HCFS_Pos (6) |
| #define | USBH_HcControl_HCFS_Msk (0x3ul << USBH_HcControl_HCFS_Pos) |
| #define | USBH_HcCommandStatus_HCR_Pos (0) |
| #define | USBH_HcCommandStatus_HCR_Msk (0x1ul << USBH_HcCommandStatus_HCR_Pos) |
| #define | USBH_HcCommandStatus_CLF_Pos (1) |
| #define | USBH_HcCommandStatus_CLF_Msk (0x1ul << USBH_HcCommandStatus_CLF_Pos) |
| #define | USBH_HcCommandStatus_BLF_Pos (2) |
| #define | USBH_HcCommandStatus_BLF_Msk (0x1ul << USBH_HcCommandStatus_BLF_Pos) |
| #define | USBH_HcCommandStatus_SOC_Pos (16) |
| #define | USBH_HcCommandStatus_SOC_Msk (0x3ul << USBH_HcCommandStatus_SOC_Pos) |
| #define | USBH_HcInterruptStatus_SO_Pos (0) |
| #define | USBH_HcInterruptStatus_SO_Msk (0x1ul << USBH_HcInterruptStatus_SO_Pos) |
| #define | USBH_HcInterruptStatus_WDH_Pos (1) |
| #define | USBH_HcInterruptStatus_WDH_Msk (0x1ul << USBH_HcInterruptStatus_WDH_Pos) |
| #define | USBH_HcInterruptStatus_SF_Pos (2) |
| #define | USBH_HcInterruptStatus_SF_Msk (0x1ul << USBH_HcInterruptStatus_SF_Pos) |
| #define | USBH_HcInterruptStatus_RD_Pos (3) |
| #define | USBH_HcInterruptStatus_RD_Msk (0x1ul << USBH_HcInterruptStatus_RD_Pos) |
| #define | USBH_HcInterruptStatus_FNO_Pos (5) |
| #define | USBH_HcInterruptStatus_FNO_Msk (0x1ul << USBH_HcInterruptStatus_FNO_Pos) |
| #define | USBH_HcInterruptStatus_RHSC_Pos (6) |
| #define | USBH_HcInterruptStatus_RHSC_Msk (0x1ul << USBH_HcInterruptStatus_RHSC_Pos) |
| #define | USBH_HcInterruptEnable_SO_Pos (0) |
| #define | USBH_HcInterruptEnable_SO_Msk (0x1ul << USBH_HcInterruptEnable_SO_Pos) |
| #define | USBH_HcInterruptEnable_WDH_Pos (1) |
| #define | USBH_HcInterruptEnable_WDH_Msk (0x1ul << USBH_HcInterruptEnable_WDH_Pos) |
| #define | USBH_HcInterruptEnable_SF_Pos (2) |
| #define | USBH_HcInterruptEnable_SF_Msk (0x1ul << USBH_HcInterruptEnable_SF_Pos) |
| #define | USBH_HcInterruptEnable_RD_Pos (3) |
| #define | USBH_HcInterruptEnable_RD_Msk (0x1ul << USBH_HcInterruptEnable_RD_Pos) |
| #define | USBH_HcInterruptEnable_FNO_Pos (5) |
| #define | USBH_HcInterruptEnable_FNO_Msk (0x1ul << USBH_HcInterruptEnable_FNO_Pos) |
| #define | USBH_HcInterruptEnable_RHSC_Pos (6) |
| #define | USBH_HcInterruptEnable_RHSC_Msk (0x1ul << USBH_HcInterruptEnable_RHSC_Pos) |
| #define | USBH_HcInterruptEnable_MIE_Pos (31) |
| #define | USBH_HcInterruptEnable_MIE_Msk (0x1ul << USBH_HcInterruptEnable_MIE_Pos) |
| #define | USBH_HcInterruptDisable_SO_Pos (0) |
| #define | USBH_HcInterruptDisable_SO_Msk (0x1ul << USBH_HcInterruptDisable_SO_Pos) |
| #define | USBH_HcInterruptDisable_WDH_Pos (1) |
| #define | USBH_HcInterruptDisable_WDH_Msk (0x1ul << USBH_HcInterruptDisable_WDH_Pos) |
| #define | USBH_HcInterruptDisable_SF_Pos (2) |
| #define | USBH_HcInterruptDisable_SF_Msk (0x1ul << USBH_HcInterruptDisable_SF_Pos) |
| #define | USBH_HcInterruptDisable_RD_Pos (3) |
| #define | USBH_HcInterruptDisable_RD_Msk (0x1ul << USBH_HcInterruptDisable_RD_Pos) |
| #define | USBH_HcInterruptDisable_FNO_Pos (5) |
| #define | USBH_HcInterruptDisable_FNO_Msk (0x1ul << USBH_HcInterruptDisable_FNO_Pos) |
| #define | USBH_HcInterruptDisable_RHSC_Pos (6) |
| #define | USBH_HcInterruptDisable_RHSC_Msk (0x1ul << USBH_HcInterruptDisable_RHSC_Pos) |
| #define | USBH_HcInterruptDisable_MIE_Pos (31) |
| #define | USBH_HcInterruptDisable_MIE_Msk (0x1ul << USBH_HcInterruptDisable_MIE_Pos) |
| #define | USBH_HcHCCA_HCCA_Pos (8) |
| #define | USBH_HcHCCA_HCCA_Msk (0xfffffful << USBH_HcHCCA_HCCA_Pos) |
| #define | USBH_HcPeriodCurrentED_PCED_Pos (4) |
| #define | USBH_HcPeriodCurrentED_PCED_Msk (0xffffffful << USBH_HcPeriodCurrentED_PCED_Pos) |
| #define | USBH_HcControlHeadED_CHED_Pos (4) |
| #define | USBH_HcControlHeadED_CHED_Msk (0xffffffful << USBH_HcControlHeadED_CHED_Pos) |
| #define | USBH_HcControlCurrentED_CCED_Pos (4) |
| #define | USBH_HcControlCurrentED_CCED_Msk (0xffffffful << USBH_HcControlCurrentED_CCED_Pos) |
| #define | USBH_HcBulkHeadED_BHED_Pos (4) |
| #define | USBH_HcBulkHeadED_BHED_Msk (0xffffffful << USBH_HcBulkHeadED_BHED_Pos) |
| #define | USBH_HcBulkCurrentED_BCED_Pos (4) |
| #define | USBH_HcBulkCurrentED_BCED_Msk (0xffffffful << USBH_HcBulkCurrentED_BCED_Pos) |
| #define | USBH_HcDoneHead_DH_Pos (4) |
| #define | USBH_HcDoneHead_DH_Msk (0xffffffful << USBH_HcDoneHead_DH_Pos) |
| #define | USBH_HcFmInterval_FI_Pos (0) |
| #define | USBH_HcFmInterval_FI_Msk (0x3ffful << USBH_HcFmInterval_FI_Pos) |
| #define | USBH_HcFmInterval_FSMPS_Pos (16) |
| #define | USBH_HcFmInterval_FSMPS_Msk (0x7ffful << USBH_HcFmInterval_FSMPS_Pos) |
| #define | USBH_HcFmInterval_FIT_Pos (31) |
| #define | USBH_HcFmInterval_FIT_Msk (0x1ul << USBH_HcFmInterval_FIT_Pos) |
| #define | USBH_HcFmRemaining_FR_Pos (0) |
| #define | USBH_HcFmRemaining_FR_Msk (0x3ffful << USBH_HcFmRemaining_FR_Pos) |
| #define | USBH_HcFmRemaining_FRT_Pos (31) |
| #define | USBH_HcFmRemaining_FRT_Msk (0x1ul << USBH_HcFmRemaining_FRT_Pos) |
| #define | USBH_HcFmNumber_FN_Pos (0) |
| #define | USBH_HcFmNumber_FN_Msk (0xfffful << USBH_HcFmNumber_FN_Pos) |
| #define | USBH_HcPeriodicStart_PS_Pos (0) |
| #define | USBH_HcPeriodicStart_PS_Msk (0x3ffful << USBH_HcPeriodicStart_PS_Pos) |
| #define | USBH_HcLSThreshold_LST_Pos (0) |
| #define | USBH_HcLSThreshold_LST_Msk (0xffful << USBH_HcLSThreshold_LST_Pos) |
| #define | USBH_HcRhDescriptorA_NDP_Pos (0) |
| #define | USBH_HcRhDescriptorA_NDP_Msk (0xfful << USBH_HcRhDescriptorA_NDP_Pos) |
| #define | USBH_HcRhDescriptorA_PSM_Pos (8) |
| #define | USBH_HcRhDescriptorA_PSM_Msk (0x1ul << USBH_HcRhDescriptorA_PSM_Pos) |
| #define | USBH_HcRhDescriptorA_NPS_Pos (9) |
| #define | USBH_HcRhDescriptorA_NPS_Msk (0x1ul << USBH_HcRhDescriptorA_NPS_Pos) |
| #define | USBH_HcRhDescriptorA_DT_Pos (10) |
| #define | USBH_HcRhDescriptorA_DT_Msk (0x1ul << USBH_HcRhDescriptorA_DT_Pos) |
| #define | USBH_HcRhDescriptorA_OCPM_Pos (11) |
| #define | USBH_HcRhDescriptorA_OCPM_Msk (0x1ul << USBH_HcRhDescriptorA_OCPM_Pos) |
| #define | USBH_HcRhDescriptorA_NOCP_Pos (12) |
| #define | USBH_HcRhDescriptorA_NOCP_Msk (0x1ul << USBH_HcRhDescriptorA_NOCP_Pos) |
| #define | USBH_HcRhDescriptorA_POTPGT_Pos (24) |
| #define | USBH_HcRhDescriptorA_POTPGT_Msk (0xfful << USBH_HcRhDescriptorA_POTPGT_Pos) |
| #define | USBH_HcRhDescriptorB_PPCM_Pos (16) |
| #define | USBH_HcRhDescriptorB_PPCM_Msk (0xfffful << USBH_HcRhDescriptorB_PPCM_Pos) |
| #define | USBH_HcRhStatus_LPS_Pos (0) |
| #define | USBH_HcRhStatus_LPS_Msk (0x1ul << USBH_HcRhStatus_LPS_Pos) |
| #define | USBH_HcRhStatus_OCI_Pos (1) |
| #define | USBH_HcRhStatus_OCI_Msk (0x1ul << USBH_HcRhStatus_OCI_Pos) |
| #define | USBH_HcRhStatus_DRWE_Pos (15) |
| #define | USBH_HcRhStatus_DRWE_Msk (0x1ul << USBH_HcRhStatus_DRWE_Pos) |
| #define | USBH_HcRhStatus_LPSC_Pos (16) |
| #define | USBH_HcRhStatus_LPSC_Msk (0x1ul << USBH_HcRhStatus_LPSC_Pos) |
| #define | USBH_HcRhStatus_OCIC_Pos (17) |
| #define | USBH_HcRhStatus_OCIC_Msk (0x1ul << USBH_HcRhStatus_OCIC_Pos) |
| #define | USBH_HcRhStatus_CRWE_Pos (31) |
| #define | USBH_HcRhStatus_CRWE_Msk (0x1ul << USBH_HcRhStatus_CRWE_Pos) |
| #define | USBH_HcRhPortStatus_CCS_Pos (0) |
| #define | USBH_HcRhPortStatus_CCS_Msk (0x1ul << USBH_HcRhPortStatus_CCS_Pos) |
| #define | USBH_HcRhPortStatus_PES_Pos (1) |
| #define | USBH_HcRhPortStatus_PES_Msk (0x1ul << USBH_HcRhPortStatus_PES_Pos) |
| #define | USBH_HcRhPortStatus_PSS_Pos (2) |
| #define | USBH_HcRhPortStatus_PSS_Msk (0x1ul << USBH_HcRhPortStatus_PSS_Pos) |
| #define | USBH_HcRhPortStatus_POCI_Pos (3) |
| #define | USBH_HcRhPortStatus_POCI_Msk (0x1ul << USBH_HcRhPortStatus_POCI_Pos) |
| #define | USBH_HcRhPortStatus_PRS_Pos (4) |
| #define | USBH_HcRhPortStatus_PRS_Msk (0x1ul << USBH_HcRhPortStatus_PRS_Pos) |
| #define | USBH_HcRhPortStatus_PPS_Pos (8) |
| #define | USBH_HcRhPortStatus_PPS_Msk (0x1ul << USBH_HcRhPortStatus_PPS_Pos) |
| #define | USBH_HcRhPortStatus_LSDA_Pos (9) |
| #define | USBH_HcRhPortStatus_LSDA_Msk (0x1ul << USBH_HcRhPortStatus_LSDA_Pos) |
| #define | USBH_HcRhPortStatus_CSC_Pos (16) |
| #define | USBH_HcRhPortStatus_CSC_Msk (0x1ul << USBH_HcRhPortStatus_CSC_Pos) |
| #define | USBH_HcRhPortStatus_PESC_Pos (17) |
| #define | USBH_HcRhPortStatus_PESC_Msk (0x1ul << USBH_HcRhPortStatus_PESC_Pos) |
| #define | USBH_HcRhPortStatus_PSSC_Pos (18) |
| #define | USBH_HcRhPortStatus_PSSC_Msk (0x1ul << USBH_HcRhPortStatus_PSSC_Pos) |
| #define | USBH_HcRhPortStatus_OCIC_Pos (19) |
| #define | USBH_HcRhPortStatus_OCIC_Msk (0x1ul << USBH_HcRhPortStatus_OCIC_Pos) |
| #define | USBH_HcRhPortStatus_PRSC_Pos (20) |
| #define | USBH_HcRhPortStatus_PRSC_Msk (0x1ul << USBH_HcRhPortStatus_PRSC_Pos) |
| #define | USBH_HcPhyControl_STBYEN_Pos (27) |
| #define | USBH_HcPhyControl_STBYEN_Msk (0x1ul << USBH_HcPhyControl_STBYEN_Pos) |
| #define | USBH_HcMiscControl_DBR16_Pos (0) |
| #define | USBH_HcMiscControl_DBR16_Msk (0x1ul << USBH_HcMiscControl_DBR16_Pos) |
| #define | USBH_HcMiscControl_ABORT_Pos (1) |
| #define | USBH_HcMiscControl_ABORT_Msk (0x1ul << USBH_HcMiscControl_ABORT_Pos) |
| #define | USBH_HcMiscControl_OCAL_Pos (3) |
| #define | USBH_HcMiscControl_OCAL_Msk (0x1ul << USBH_HcMiscControl_OCAL_Pos) |
| #define | USBH_HcMiscControl_PCAL_Pos (4) |
| #define | USBH_HcMiscControl_PCAL_Msk (0x1ul << USBH_HcMiscControl_PCAL_Pos) |
| #define | USBH_HcMiscControl_SIEPD_Pos (8) |
| #define | USBH_HcMiscControl_SIEPD_Msk (0x1ul << USBH_HcMiscControl_SIEPD_Pos) |
| #define | USBH_HcMiscControl_DPRT1_Pos (16) |
| #define | USBH_HcMiscControl_DPRT1_Msk (0x1ul << USBH_HcMiscControl_DPRT1_Pos) |
| #define | USBH_HcMiscControl_DPRT2_Pos (17) |
| #define | USBH_HcMiscControl_DPRT2_Msk (0x1ul << USBH_HcMiscControl_DPRT2_Pos) |
| #define | USBD_GINTSTS_USBIF_Pos (0) |
| #define | USBD_GINTSTS_USBIF_Msk (0x1ul << USBD_GINTSTS_USBIF_Pos) |
| #define | USBD_GINTSTS_CEPIF_Pos (1) |
| #define | USBD_GINTSTS_CEPIF_Msk (0x1ul << USBD_GINTSTS_CEPIF_Pos) |
| #define | USBD_GINTSTS_EPAIF_Pos (2) |
| #define | USBD_GINTSTS_EPAIF_Msk (0x1ul << USBD_GINTSTS_EPAIF_Pos) |
| #define | USBD_GINTSTS_EPBIF_Pos (3) |
| #define | USBD_GINTSTS_EPBIF_Msk (0x1ul << USBD_GINTSTS_EPBIF_Pos) |
| #define | USBD_GINTSTS_EPCIF_Pos (4) |
| #define | USBD_GINTSTS_EPCIF_Msk (0x1ul << USBD_GINTSTS_EPCIF_Pos) |
| #define | USBD_GINTSTS_EPDIF_Pos (5) |
| #define | USBD_GINTSTS_EPDIF_Msk (0x1ul << USBD_GINTSTS_EPDIF_Pos) |
| #define | USBD_GINTSTS_EPEIF_Pos (6) |
| #define | USBD_GINTSTS_EPEIF_Msk (0x1ul << USBD_GINTSTS_EPEIF_Pos) |
| #define | USBD_GINTSTS_EPFIF_Pos (7) |
| #define | USBD_GINTSTS_EPFIF_Msk (0x1ul << USBD_GINTSTS_EPFIF_Pos) |
| #define | USBD_GINTSTS_EPGIF_Pos (8) |
| #define | USBD_GINTSTS_EPGIF_Msk (0x1ul << USBD_GINTSTS_EPGIF_Pos) |
| #define | USBD_GINTSTS_EPHIF_Pos (9) |
| #define | USBD_GINTSTS_EPHIF_Msk (0x1ul << USBD_GINTSTS_EPHIF_Pos) |
| #define | USBD_GINTSTS_EPIIF_Pos (10) |
| #define | USBD_GINTSTS_EPIIF_Msk (0x1ul << USBD_GINTSTS_EPIIF_Pos) |
| #define | USBD_GINTSTS_EPJIF_Pos (11) |
| #define | USBD_GINTSTS_EPJIF_Msk (0x1ul << USBD_GINTSTS_EPJIF_Pos) |
| #define | USBD_GINTSTS_EPKIF_Pos (12) |
| #define | USBD_GINTSTS_EPKIF_Msk (0x1ul << USBD_GINTSTS_EPKIF_Pos) |
| #define | USBD_GINTSTS_EPLIF_Pos (13) |
| #define | USBD_GINTSTS_EPLIF_Msk (0x1ul << USBD_GINTSTS_EPLIF_Pos) |
| #define | USBD_GINTEN_USBIE_Pos (0) |
| #define | USBD_GINTEN_USBIE_Msk (0x1ul << USBD_GINTEN_USBIE_Pos) |
| #define | USBD_GINTEN_CEPIE_Pos (1) |
| #define | USBD_GINTEN_CEPIE_Msk (0x1ul << USBD_GINTEN_CEPIE_Pos) |
| #define | USBD_GINTEN_EPAIE_Pos (2) |
| #define | USBD_GINTEN_EPAIE_Msk (0x1ul << USBD_GINTEN_EPAIE_Pos) |
| #define | USBD_GINTEN_EPBIE_Pos (3) |
| #define | USBD_GINTEN_EPBIE_Msk (0x1ul << USBD_GINTEN_EPBIE_Pos) |
| #define | USBD_GINTEN_EPCIE_Pos (4) |
| #define | USBD_GINTEN_EPCIE_Msk (0x1ul << USBD_GINTEN_EPCIE_Pos) |
| #define | USBD_GINTEN_EPDIE_Pos (5) |
| #define | USBD_GINTEN_EPDIE_Msk (0x1ul << USBD_GINTEN_EPDIE_Pos) |
| #define | USBD_GINTEN_EPEIE_Pos (6) |
| #define | USBD_GINTEN_EPEIE_Msk (0x1ul << USBD_GINTEN_EPEIE_Pos) |
| #define | USBD_GINTEN_EPFIE_Pos (7) |
| #define | USBD_GINTEN_EPFIE_Msk (0x1ul << USBD_GINTEN_EPFIE_Pos) |
| #define | USBD_GINTEN_EPGIE_Pos (8) |
| #define | USBD_GINTEN_EPGIE_Msk (0x1ul << USBD_GINTEN_EPGIE_Pos) |
| #define | USBD_GINTEN_EPHIE_Pos (9) |
| #define | USBD_GINTEN_EPHIE_Msk (0x1ul << USBD_GINTEN_EPHIE_Pos) |
| #define | USBD_GINTEN_EPIIE_Pos (10) |
| #define | USBD_GINTEN_EPIIE_Msk (0x1ul << USBD_GINTEN_EPIIE_Pos) |
| #define | USBD_GINTEN_EPJIE_Pos (11) |
| #define | USBD_GINTEN_EPJIE_Msk (0x1ul << USBD_GINTEN_EPJIE_Pos) |
| #define | USBD_GINTEN_EPKIE_Pos (12) |
| #define | USBD_GINTEN_EPKIE_Msk (0x1ul << USBD_GINTEN_EPKIE_Pos) |
| #define | USBD_GINTEN_EPLIE_Pos (13) |
| #define | USBD_GINTEN_EPLIE_Msk (0x1ul << USBD_GINTEN_EPLIE_Pos) |
| #define | USBD_BUSINTSTS_SOFIF_Pos (0) |
| #define | USBD_BUSINTSTS_SOFIF_Msk (0x1ul << USBD_BUSINTSTS_SOFIF_Pos) |
| #define | USBD_BUSINTSTS_RSTIF_Pos (1) |
| #define | USBD_BUSINTSTS_RSTIF_Msk (0x1ul << USBD_BUSINTSTS_RSTIF_Pos) |
| #define | USBD_BUSINTSTS_RESUMEIF_Pos (2) |
| #define | USBD_BUSINTSTS_RESUMEIF_Msk (0x1ul << USBD_BUSINTSTS_RESUMEIF_Pos) |
| #define | USBD_BUSINTSTS_SUSPENDIF_Pos (3) |
| #define | USBD_BUSINTSTS_SUSPENDIF_Msk (0x1ul << USBD_BUSINTSTS_SUSPENDIF_Pos) |
| #define | USBD_BUSINTSTS_HISPDIF_Pos (4) |
| #define | USBD_BUSINTSTS_HISPDIF_Msk (0x1ul << USBD_BUSINTSTS_HISPDIF_Pos) |
| #define | USBD_BUSINTSTS_DMADONEIF_Pos (5) |
| #define | USBD_BUSINTSTS_DMADONEIF_Msk (0x1ul << USBD_BUSINTSTS_DMADONEIF_Pos) |
| #define | USBD_BUSINTSTS_PHYCLKVLDIF_Pos (6) |
| #define | USBD_BUSINTSTS_PHYCLKVLDIF_Msk (0x1ul << USBD_BUSINTSTS_PHYCLKVLDIF_Pos) |
| #define | USBD_BUSINTSTS_VBUSDETIF_Pos (8) |
| #define | USBD_BUSINTSTS_VBUSDETIF_Msk (0x1ul << USBD_BUSINTSTS_VBUSDETIF_Pos) |
| #define | USBD_BUSINTEN_SOFIEN_Pos (0) |
| #define | USBD_BUSINTEN_SOFIEN_Msk (0x1ul << USBD_BUSINTEN_SOFIEN_Pos) |
| #define | USBD_BUSINTEN_RSTIEN_Pos (1) |
| #define | USBD_BUSINTEN_RSTIEN_Msk (0x1ul << USBD_BUSINTEN_RSTIEN_Pos) |
| #define | USBD_BUSINTEN_RESUMEIEN_Pos (2) |
| #define | USBD_BUSINTEN_RESUMEIEN_Msk (0x1ul << USBD_BUSINTEN_RESUMEIEN_Pos) |
| #define | USBD_BUSINTEN_SUSPENDIEN_Pos (3) |
| #define | USBD_BUSINTEN_SUSPENDIEN_Msk (0x1ul << USBD_BUSINTEN_SUSPENDIEN_Pos) |
| #define | USBD_BUSINTEN_HISPDIEN_Pos (4) |
| #define | USBD_BUSINTEN_HISPDIEN_Msk (0x1ul << USBD_BUSINTEN_HISPDIEN_Pos) |
| #define | USBD_BUSINTEN_DMADONEIEN_Pos (5) |
| #define | USBD_BUSINTEN_DMADONEIEN_Msk (0x1ul << USBD_BUSINTEN_DMADONEIEN_Pos) |
| #define | USBD_BUSINTEN_PHYCLKVLDIEN_Pos (6) |
| #define | USBD_BUSINTEN_PHYCLKVLDIEN_Msk (0x1ul << USBD_BUSINTEN_PHYCLKVLDIEN_Pos) |
| #define | USBD_BUSINTEN_VBUSDETIEN_Pos (8) |
| #define | USBD_BUSINTEN_VBUSDETIEN_Msk (0x1ul << USBD_BUSINTEN_VBUSDETIEN_Pos) |
| #define | USBD_OPER_RESUMEEN_Pos (0) |
| #define | USBD_OPER_RESUMEEN_Msk (0x1ul << USBD_OPER_RESUMEEN_Pos) |
| #define | USBD_OPER_HISPDEN_Pos (1) |
| #define | USBD_OPER_HISPDEN_Msk (0x1ul << USBD_OPER_HISPDEN_Pos) |
| #define | USBD_OPER_CURSPD_Pos (2) |
| #define | USBD_OPER_CURSPD_Msk (0x1ul << USBD_OPER_CURSPD_Pos) |
| #define | USBD_FRAMECNT_MFRAMECNT_Pos (0) |
| #define | USBD_FRAMECNT_MFRAMECNT_Msk (0x7ul << USBD_FRAMECNT_MFRAMECNT_Pos) |
| #define | USBD_FRAMECNT_FRAMECNT_Pos (3) |
| #define | USBD_FRAMECNT_FRAMECNT_Msk (0x7fful << USBD_FRAMECNT_FRAMECNT_Pos) |
| #define | USBD_FADDR_FADDR_Pos (0) |
| #define | USBD_FADDR_FADDR_Msk (0x7ful << USBD_FADDR_FADDR_Pos) |
| #define | USBD_TEST_TESTMODE_Pos (0) |
| #define | USBD_TEST_TESTMODE_Msk (0x7ul << USBD_TEST_TESTMODE_Pos) |
| #define | USBD_CEPDAT_DAT_Pos (0) |
| #define | USBD_CEPDAT_DAT_Msk (0xfffffffful << USBD_CEPDAT_DAT_Pos) |
| #define | USBD_CEPCTL_NAKCLR_Pos (0) |
| #define | USBD_CEPCTL_NAKCLR_Msk (0x1ul << USBD_CEPCTL_NAKCLR_Pos) |
| #define | USBD_CEPCTL_STALLEN_Pos (1) |
| #define | USBD_CEPCTL_STALLEN_Msk (0x1ul << USBD_CEPCTL_STALLEN_Pos) |
| #define | USBD_CEPCTL_ZEROLEN_Pos (2) |
| #define | USBD_CEPCTL_ZEROLEN_Msk (0x1ul << USBD_CEPCTL_ZEROLEN_Pos) |
| #define | USBD_CEPCTL_FLUSH_Pos (3) |
| #define | USBD_CEPCTL_FLUSH_Msk (0x1ul << USBD_CEPCTL_FLUSH_Pos) |
| #define | USBD_CEPINTEN_SETUPTKIEN_Pos (0) |
| #define | USBD_CEPINTEN_SETUPTKIEN_Msk (0x1ul << USBD_CEPINTEN_SETUPTKIEN_Pos) |
| #define | USBD_CEPINTEN_SETUPPKIEN_Pos (1) |
| #define | USBD_CEPINTEN_SETUPPKIEN_Msk (0x1ul << USBD_CEPINTEN_SETUPPKIEN_Pos) |
| #define | USBD_CEPINTEN_OUTTKIEN_Pos (2) |
| #define | USBD_CEPINTEN_OUTTKIEN_Msk (0x1ul << USBD_CEPINTEN_OUTTKIEN_Pos) |
| #define | USBD_CEPINTEN_INTKIEN_Pos (3) |
| #define | USBD_CEPINTEN_INTKIEN_Msk (0x1ul << USBD_CEPINTEN_INTKIEN_Pos) |
| #define | USBD_CEPINTEN_PINGIEN_Pos (4) |
| #define | USBD_CEPINTEN_PINGIEN_Msk (0x1ul << USBD_CEPINTEN_PINGIEN_Pos) |
| #define | USBD_CEPINTEN_TXPKIEN_Pos (5) |
| #define | USBD_CEPINTEN_TXPKIEN_Msk (0x1ul << USBD_CEPINTEN_TXPKIEN_Pos) |
| #define | USBD_CEPINTEN_RXPKIEN_Pos (6) |
| #define | USBD_CEPINTEN_RXPKIEN_Msk (0x1ul << USBD_CEPINTEN_RXPKIEN_Pos) |
| #define | USBD_CEPINTEN_NAKIEN_Pos (7) |
| #define | USBD_CEPINTEN_NAKIEN_Msk (0x1ul << USBD_CEPINTEN_NAKIEN_Pos) |
| #define | USBD_CEPINTEN_STALLIEN_Pos (8) |
| #define | USBD_CEPINTEN_STALLIEN_Msk (0x1ul << USBD_CEPINTEN_STALLIEN_Pos) |
| #define | USBD_CEPINTEN_ERRIEN_Pos (9) |
| #define | USBD_CEPINTEN_ERRIEN_Msk (0x1ul << USBD_CEPINTEN_ERRIEN_Pos) |
| #define | USBD_CEPINTEN_STSDONEIEN_Pos (10) |
| #define | USBD_CEPINTEN_STSDONEIEN_Msk (0x1ul << USBD_CEPINTEN_STSDONEIEN_Pos) |
| #define | USBD_CEPINTEN_BUFFULLIEN_Pos (11) |
| #define | USBD_CEPINTEN_BUFFULLIEN_Msk (0x1ul << USBD_CEPINTEN_BUFFULLIEN_Pos) |
| #define | USBD_CEPINTEN_BUFEMPTYIEN_Pos (12) |
| #define | USBD_CEPINTEN_BUFEMPTYIEN_Msk (0x1ul << USBD_CEPINTEN_BUFEMPTYIEN_Pos) |
| #define | USBD_CEPINTSTS_SETUPTKIF_Pos (0) |
| #define | USBD_CEPINTSTS_SETUPTKIF_Msk (0x1ul << USBD_CEPINTSTS_SETUPTKIF_Pos) |
| #define | USBD_CEPINTSTS_SETUPPKIF_Pos (1) |
| #define | USBD_CEPINTSTS_SETUPPKIF_Msk (0x1ul << USBD_CEPINTSTS_SETUPPKIF_Pos) |
| #define | USBD_CEPINTSTS_OUTTKIF_Pos (2) |
| #define | USBD_CEPINTSTS_OUTTKIF_Msk (0x1ul << USBD_CEPINTSTS_OUTTKIF_Pos) |
| #define | USBD_CEPINTSTS_INTKIF_Pos (3) |
| #define | USBD_CEPINTSTS_INTKIF_Msk (0x1ul << USBD_CEPINTSTS_INTKIF_Pos) |
| #define | USBD_CEPINTSTS_PINGIF_Pos (4) |
| #define | USBD_CEPINTSTS_PINGIF_Msk (0x1ul << USBD_CEPINTSTS_PINGIF_Pos) |
| #define | USBD_CEPINTSTS_TXPKIF_Pos (5) |
| #define | USBD_CEPINTSTS_TXPKIF_Msk (0x1ul << USBD_CEPINTSTS_TXPKIF_Pos) |
| #define | USBD_CEPINTSTS_RXPKIF_Pos (6) |
| #define | USBD_CEPINTSTS_RXPKIF_Msk (0x1ul << USBD_CEPINTSTS_RXPKIF_Pos) |
| #define | USBD_CEPINTSTS_NAKIF_Pos (7) |
| #define | USBD_CEPINTSTS_NAKIF_Msk (0x1ul << USBD_CEPINTSTS_NAKIF_Pos) |
| #define | USBD_CEPINTSTS_STALLIF_Pos (8) |
| #define | USBD_CEPINTSTS_STALLIF_Msk (0x1ul << USBD_CEPINTSTS_STALLIF_Pos) |
| #define | USBD_CEPINTSTS_ERRIF_Pos (9) |
| #define | USBD_CEPINTSTS_ERRIF_Msk (0x1ul << USBD_CEPINTSTS_ERRIF_Pos) |
| #define | USBD_CEPINTSTS_STSDONEIF_Pos (10) |
| #define | USBD_CEPINTSTS_STSDONEIF_Msk (0x1ul << USBD_CEPINTSTS_STSDONEIF_Pos) |
| #define | USBD_CEPINTSTS_BUFFULLIF_Pos (11) |
| #define | USBD_CEPINTSTS_BUFFULLIF_Msk (0x1ul << USBD_CEPINTSTS_BUFFULLIF_Pos) |
| #define | USBD_CEPINTSTS_BUFEMPTYIF_Pos (12) |
| #define | USBD_CEPINTSTS_BUFEMPTYIF_Msk (0x1ul << USBD_CEPINTSTS_BUFEMPTYIF_Pos) |
| #define | USBD_CEPTXCNT_TXCNT_Pos (0) |
| #define | USBD_CEPTXCNT_TXCNT_Msk (0xfful << USBD_CEPTXCNT_TXCNT_Pos) |
| #define | USBD_CEPRXCNT_RXCNT_Pos (0) |
| #define | USBD_CEPRXCNT_RXCNT_Msk (0xfful << USBD_CEPRXCNT_RXCNT_Pos) |
| #define | USBD_CEPDATCNT_DATCNT_Pos (0) |
| #define | USBD_CEPDATCNT_DATCNT_Msk (0xfffful << USBD_CEPDATCNT_DATCNT_Pos) |
| #define | USBD_SETUP1_0_SETUP0_Pos (0) |
| #define | USBD_SETUP1_0_SETUP0_Msk (0xfful << USBD_SETUP1_0_SETUP0_Pos) |
| #define | USBD_SETUP1_0_SETUP1_Pos (8) |
| #define | USBD_SETUP1_0_SETUP1_Msk (0xfful << USBD_SETUP1_0_SETUP1_Pos) |
| #define | USBD_SETUP3_2_SETUP2_Pos (0) |
| #define | USBD_SETUP3_2_SETUP2_Msk (0xfful << USBD_SETUP3_2_SETUP2_Pos) |
| #define | USBD_SETUP3_2_SETUP3_Pos (8) |
| #define | USBD_SETUP3_2_SETUP3_Msk (0xfful << USBD_SETUP3_2_SETUP3_Pos) |
| #define | USBD_SETUP5_4_SETUP4_Pos (0) |
| #define | USBD_SETUP5_4_SETUP4_Msk (0xfful << USBD_SETUP5_4_SETUP4_Pos) |
| #define | USBD_SETUP5_4_SETUP5_Pos (8) |
| #define | USBD_SETUP5_4_SETUP5_Msk (0xfful << USBD_SETUP5_4_SETUP5_Pos) |
| #define | USBD_SETUP7_6_SETUP6_Pos (0) |
| #define | USBD_SETUP7_6_SETUP6_Msk (0xfful << USBD_SETUP7_6_SETUP6_Pos) |
| #define | USBD_SETUP7_6_SETUP7_Pos (8) |
| #define | USBD_SETUP7_6_SETUP7_Msk (0xfful << USBD_SETUP7_6_SETUP7_Pos) |
| #define | USBD_CEPBUFSTART_SADDR_Pos (0) |
| #define | USBD_CEPBUFSTART_SADDR_Msk (0xffful << USBD_CEPBUFSTART_SADDR_Pos) |
| #define | USBD_CEPBUFEND_EADDR_Pos (0) |
| #define | USBD_CEPBUFEND_EADDR_Msk (0xffful << USBD_CEPBUFEND_EADDR_Pos) |
| #define | USBD_DMACTL_EPNUM_Pos (0) |
| #define | USBD_DMACTL_EPNUM_Msk (0xful << USBD_DMACTL_EPNUM_Pos) |
| #define | USBD_DMACTL_DMARD_Pos (4) |
| #define | USBD_DMACTL_DMARD_Msk (0x1ul << USBD_DMACTL_DMARD_Pos) |
| #define | USBD_DMACTL_DMAEN_Pos (5) |
| #define | USBD_DMACTL_DMAEN_Msk (0x1ul << USBD_DMACTL_DMAEN_Pos) |
| #define | USBD_DMACTL_SGEN_Pos (6) |
| #define | USBD_DMACTL_SGEN_Msk (0x1ul << USBD_DMACTL_SGEN_Pos) |
| #define | USBD_DMACTL_DMARST_Pos (7) |
| #define | USBD_DMACTL_DMARST_Msk (0x1ul << USBD_DMACTL_DMARST_Pos) |
| #define | USBD_DMACNT_DMACNT_Pos (0) |
| #define | USBD_DMACNT_DMACNT_Msk (0xffffful << USBD_DMACNT_DMACNT_Pos) |
| #define | USBD_EPDAT_EPDAT_Pos (0) |
| #define | USBD_EPDAT_EPDAT_Msk (0xfffffffful << USBD_EPDAT_EPDAT_Pos) |
| #define | USBD_EPINTSTS_BUFFULLIF_Pos (0) |
| #define | USBD_EPINTSTS_BUFFULLIF_Msk (0x1ul << USBD_EPINTSTS_BUFFULLIF_Pos) |
| #define | USBD_EPINTSTS_BUFEMPTYIF_Pos (1) |
| #define | USBD_EPINTSTS_BUFEMPTYIF_Msk (0x1ul << USBD_EPINTSTS_BUFEMPTYIF_Pos) |
| #define | USBD_EPINTSTS_SHORTTXIF_Pos (2) |
| #define | USBD_EPINTSTS_SHORTTXIF_Msk (0x1ul << USBD_EPINTSTS_SHORTTXIF_Pos) |
| #define | USBD_EPINTSTS_TXPKIF_Pos (3) |
| #define | USBD_EPINTSTS_TXPKIF_Msk (0x1ul << USBD_EPINTSTS_TXPKIF_Pos) |
| #define | USBD_EPINTSTS_RXPKIF_Pos (4) |
| #define | USBD_EPINTSTS_RXPKIF_Msk (0x1ul << USBD_EPINTSTS_RXPKIF_Pos) |
| #define | USBD_EPINTSTS_OUTTKIF_Pos (5) |
| #define | USBD_EPINTSTS_OUTTKIF_Msk (0x1ul << USBD_EPINTSTS_OUTTKIF_Pos) |
| #define | USBD_EPINTSTS_INTKIF_Pos (6) |
| #define | USBD_EPINTSTS_INTKIF_Msk (0x1ul << USBD_EPINTSTS_INTKIF_Pos) |
| #define | USBD_EPINTSTS_PINGIF_Pos (7) |
| #define | USBD_EPINTSTS_PINGIF_Msk (0x1ul << USBD_EPINTSTS_PINGIF_Pos) |
| #define | USBD_EPINTSTS_NAKIF_Pos (8) |
| #define | USBD_EPINTSTS_NAKIF_Msk (0x1ul << USBD_EPINTSTS_NAKIF_Pos) |
| #define | USBD_EPINTSTS_STALLIF_Pos (9) |
| #define | USBD_EPINTSTS_STALLIF_Msk (0x1ul << USBD_EPINTSTS_STALLIF_Pos) |
| #define | USBD_EPINTSTS_NYETIF_Pos (10) |
| #define | USBD_EPINTSTS_NYETIF_Msk (0x1ul << USBD_EPINTSTS_NYETIF_Pos) |
| #define | USBD_EPINTSTS_ERRIF_Pos (11) |
| #define | USBD_EPINTSTS_ERRIF_Msk (0x1ul << USBD_EPINTSTS_ERRIF_Pos) |
| #define | USBD_EPINTSTS_SHORTRXIF_Pos (12) |
| #define | USBD_EPINTSTS_SHORTRXIF_Msk (0x1ul << USBD_EPINTSTS_SHORTRXIF_Pos) |
| #define | USBD_EPINTEN_BUFFULLIEN_Pos (0) |
| #define | USBD_EPINTEN_BUFFULLIEN_Msk (0x1ul << USBD_EPINTEN_BUFFULLIEN_Pos) |
| #define | USBD_EPINTEN_BUFEMPTYIEN_Pos (1) |
| #define | USBD_EPINTEN_BUFEMPTYIEN_Msk (0x1ul << USBD_EPINTEN_BUFEMPTYIEN_Pos) |
| #define | USBD_EPINTEN_SHORTTXIEN_Pos (2) |
| #define | USBD_EPINTEN_SHORTTXIEN_Msk (0x1ul << USBD_EPINTEN_SHORTTXIEN_Pos) |
| #define | USBD_EPINTEN_TXPKIEN_Pos (3) |
| #define | USBD_EPINTEN_TXPKIEN_Msk (0x1ul << USBD_EPINTEN_TXPKIEN_Pos) |
| #define | USBD_EPINTEN_RXPKIEN_Pos (4) |
| #define | USBD_EPINTEN_RXPKIEN_Msk (0x1ul << USBD_EPINTEN_RXPKIEN_Pos) |
| #define | USBD_EPINTEN_OUTTKIEN_Pos (5) |
| #define | USBD_EPINTEN_OUTTKIEN_Msk (0x1ul << USBD_EPINTEN_OUTTKIEN_Pos) |
| #define | USBD_EPINTEN_INTKIEN_Pos (6) |
| #define | USBD_EPINTEN_INTKIEN_Msk (0x1ul << USBD_EPINTEN_INTKIEN_Pos) |
| #define | USBD_EPINTEN_PINGIEN_Pos (7) |
| #define | USBD_EPINTEN_PINGIEN_Msk (0x1ul << USBD_EPINTEN_PINGIEN_Pos) |
| #define | USBD_EPINTEN_NAKIEN_Pos (8) |
| #define | USBD_EPINTEN_NAKIEN_Msk (0x1ul << USBD_EPINTEN_NAKIEN_Pos) |
| #define | USBD_EPINTEN_STALLIEN_Pos (9) |
| #define | USBD_EPINTEN_STALLIEN_Msk (0x1ul << USBD_EPINTEN_STALLIEN_Pos) |
| #define | USBD_EPINTEN_NYETIEN_Pos (10) |
| #define | USBD_EPINTEN_NYETIEN_Msk (0x1ul << USBD_EPINTEN_NYETIEN_Pos) |
| #define | USBD_EPINTEN_ERRIEN_Pos (11) |
| #define | USBD_EPINTEN_ERRIEN_Msk (0x1ul << USBD_EPINTEN_ERRIEN_Pos) |
| #define | USBD_EPINTEN_SHORTRXIEN_Pos (12) |
| #define | USBD_EPINTEN_SHORTRXIEN_Msk (0x1ul << USBD_EPINTEN_SHORTRXIEN_Pos) |
| #define | USBD_EPDATCNT_DATCNT_Pos (0) |
| #define | USBD_EPDATCNT_DATCNT_Msk (0xfffful << USBD_EPDATCNT_DATCNT_Pos) |
| #define | USBD_EPDATCNT_DMALOOP_Pos (16) |
| #define | USBD_EPDATCNT_DMALOOP_Msk (0x7ffful << USBD_EPDATCNT_DMALOOP_Pos) |
| #define | USBD_EPRSPCTL_FLUSH_Pos (0) |
| #define | USBD_EPRSPCTL_FLUSH_Msk (0x1ul << USBD_EPRSPCTL_FLUSH_Pos) |
| #define | USBD_EPRSPCTL_MODE_Pos (1) |
| #define | USBD_EPRSPCTL_MODE_Msk (0x3ul << USBD_EPRSPCTL_MODE_Pos) |
| #define | USBD_EPRSPCTL_TOGGLE_Pos (3) |
| #define | USBD_EPRSPCTL_TOGGLE_Msk (0x1ul << USBD_EPRSPCTL_TOGGLE_Pos) |
| #define | USBD_EPRSPCTL_HALT_Pos (4) |
| #define | USBD_EPRSPCTL_HALT_Msk (0x1ul << USBD_EPRSPCTL_HALT_Pos) |
| #define | USBD_EPRSPCTL_ZEROLEN_Pos (5) |
| #define | USBD_EPRSPCTL_ZEROLEN_Msk (0x1ul << USBD_EPRSPCTL_ZEROLEN_Pos) |
| #define | USBD_EPRSPCTL_SHORTTXEN_Pos (6) |
| #define | USBD_EPRSPCTL_SHORTTXEN_Msk (0x1ul << USBD_EPRSPCTL_SHORTTXEN_Pos) |
| #define | USBD_EPRSPCTL_DISBUF_Pos (7) |
| #define | USBD_EPRSPCTL_DISBUF_Msk (0x1ul << USBD_EPRSPCTL_DISBUF_Pos) |
| #define | USBD_EPMPS_EPMPS_Pos (0) |
| #define | USBD_EPMPS_EPMPS_Msk (0x7fful << USBD_EPMPS_EPMPS_Pos) |
| #define | USBD_EPTXCNT_TXCNT_Pos (0) |
| #define | USBD_EPTXCNT_TXCNT_Msk (0x7fful << USBD_EPTXCNT_TXCNT_Pos) |
| #define | USBD_EPCFG_EPEN_Pos (0) |
| #define | USBD_EPCFG_EPEN_Msk (0x1ul << USBD_EPCFG_EPEN_Pos) |
| #define | USBD_EPCFG_EPTYPE_Pos (1) |
| #define | USBD_EPCFG_EPTYPE_Msk (0x3ul << USBD_EPCFG_EPTYPE_Pos) |
| #define | USBD_EPCFG_EPDIR_Pos (3) |
| #define | USBD_EPCFG_EPDIR_Msk (0x1ul << USBD_EPCFG_EPDIR_Pos) |
| #define | USBD_EPCFG_EPNUM_Pos (4) |
| #define | USBD_EPCFG_EPNUM_Msk (0xful << USBD_EPCFG_EPNUM_Pos) |
| #define | USBD_EPBUFSTART_SADDR_Pos (0) |
| #define | USBD_EPBUFSTART_SADDR_Msk (0xffful << USBD_EPBUFSTART_SADDR_Pos) |
| #define | USBD_EPBUFEND_EADDR_Pos (0) |
| #define | USBD_EPBUFEND_EADDR_Msk (0xffful << USBD_EPBUFEND_EADDR_Pos) |
| #define | USBD_DMAADDR_DMAADDR_Pos (0) |
| #define | USBD_DMAADDR_DMAADDR_Msk (0xfffffffful << USBD_DMAADDR_DMAADDR_Pos) |
| #define | USBD_PHYCTL_DPPUEN_Pos (8) |
| #define | USBD_PHYCTL_DPPUEN_Msk (0x1ul << USBD_PHYCTL_DPPUEN_Pos) |
| #define | USBD_PHYCTL_PHYEN_Pos (9) |
| #define | USBD_PHYCTL_PHYEN_Msk (0x1ul << USBD_PHYCTL_PHYEN_Pos) |
| #define | USBD_PHYCTL_WKEN_Pos (24) |
| #define | USBD_PHYCTL_WKEN_Msk (0x1ul << USBD_PHYCTL_WKEN_Pos) |
| #define | USBD_PHYCTL_VBUSDET_Pos (31) |
| #define | USBD_PHYCTL_VBUSDET_Msk (0x1ul << USBD_PHYCTL_VBUSDET_Pos) |
| #define | WDT_CTL_RSTCNT_Pos (0) |
| #define | WDT_CTL_RSTCNT_Msk (0x1ul << WDT_CTL_RSTCNT_Pos) |
| #define | WDT_CTL_RSTEN_Pos (1) |
| #define | WDT_CTL_RSTEN_Msk (0x1ul << WDT_CTL_RSTEN_Pos) |
| #define | WDT_CTL_RSTF_Pos (2) |
| #define | WDT_CTL_RSTF_Msk (0x1ul << WDT_CTL_RSTF_Pos) |
| #define | WDT_CTL_IF_Pos (3) |
| #define | WDT_CTL_IF_Msk (0x1ul << WDT_CTL_IF_Pos) |
| #define | WDT_CTL_WKEN_Pos (4) |
| #define | WDT_CTL_WKEN_Msk (0x1ul << WDT_CTL_WKEN_Pos) |
| #define | WDT_CTL_WKF_Pos (5) |
| #define | WDT_CTL_WKF_Msk (0x1ul << WDT_CTL_WKF_Pos) |
| #define | WDT_CTL_INTEN_Pos (6) |
| #define | WDT_CTL_INTEN_Msk (0x1ul << WDT_CTL_INTEN_Pos) |
| #define | WDT_CTL_WDTEN_Pos (7) |
| #define | WDT_CTL_WDTEN_Msk (0x1ul << WDT_CTL_WDTEN_Pos) |
| #define | WDT_CTL_TOUTSEL_Pos (8) |
| #define | WDT_CTL_TOUTSEL_Msk (0x7ul << WDT_CTL_TOUTSEL_Pos) |
| #define | WDT_CTL_ICEDEBUG_Pos (31) |
| #define | WDT_CTL_ICEDEBUG_Msk (0x1ul << WDT_CTL_ICEDEBUG_Pos) |
| #define | WDT_ALTCTL_RSTDSEL_Pos (0) |
| #define | WDT_ALTCTL_RSTDSEL_Msk (0x3ul << WDT_ALTCTL_RSTDSEL_Pos) |
| #define | WWDT_RLDCNT_RLDCNT_Pos (0) |
| #define | WWDT_RLDCNT_RLDCNT_Msk (0xfffffffful << WWDT_RLDCNT_RLDCNT_Pos) |
| #define | WWDT_CTL_WWDTEN_Pos (0) |
| #define | WWDT_CTL_WWDTEN_Msk (0x1ul << WWDT_CTL_WWDTEN_Pos) |
| #define | WWDT_CTL_INTEN_Pos (1) |
| #define | WWDT_CTL_INTEN_Msk (0x1ul << WWDT_CTL_INTEN_Pos) |
| #define | WWDT_CTL_PSCSEL_Pos (8) |
| #define | WWDT_CTL_PSCSEL_Msk (0xful << WWDT_CTL_PSCSEL_Pos) |
| #define | WWDT_CTL_CMPDAT_Pos (16) |
| #define | WWDT_CTL_CMPDAT_Msk (0x3ful << WWDT_CTL_CMPDAT_Pos) |
| #define | WWDT_CTL_ICEDEBUG_Pos (31) |
| #define | WWDT_CTL_ICEDEBUG_Msk (0x1ul << WWDT_CTL_ICEDEBUG_Pos) |
| #define | WWDT_STATUS_WWDTIF_Pos (0) |
| #define | WWDT_STATUS_WWDTIF_Msk (0x1ul << WWDT_STATUS_WWDTIF_Pos) |
| #define | WWDT_STATUS_WWDTRF_Pos (1) |
| #define | WWDT_STATUS_WWDTRF_Msk (0x1ul << WWDT_STATUS_WWDTRF_Pos) |
| #define | WWDT_CNT_CNTDAT_Pos (0) |
| #define | WWDT_CNT_CNTDAT_Msk (0x3ful << WWDT_CNT_CNTDAT_Pos) |
Typedefs | |
| typedef enum IRQn | IRQn_Type |
| typedef volatile unsigned char | vu8 |
| Define 8-bit unsigned volatile data type. More... | |
| typedef volatile unsigned short | vu16 |
| Define 16-bit unsigned volatile data type. More... | |
| typedef volatile unsigned long | vu32 |
| Define 32-bit unsigned volatile data type. More... | |
NUC472/NUC442 peripheral access layer header file. This file contains all the peripheral register's definitions, bits definitions and memory mapping for NuMicro NUC472/NUC442 MCU.
Definition in file NUC472_442.h.
| #define ADC_CHEN_ADBGEN_Msk (0x1ul << ADC_CHEN_ADBGEN_Pos) |
ADC_T::CHEN: ADBGEN Mask
Definition at line 776 of file NUC472_442.h.
| #define ADC_CHEN_ADBGEN_Pos (17) |
ADC_T::CHEN: ADBGEN Position
Definition at line 775 of file NUC472_442.h.
| #define ADC_CHEN_ADTSEN_Msk (0x1ul << ADC_CHEN_ADTSEN_Pos) |
ADC_T::CHEN: ADTSEN Mask
Definition at line 773 of file NUC472_442.h.
| #define ADC_CHEN_ADTSEN_Pos (16) |
ADC_T::CHEN: ADTSEN Position
Definition at line 772 of file NUC472_442.h.
| #define ADC_CHEN_CHEN_Msk (0xffful << ADC_CHEN_CHEN_Pos) |
ADC_T::CHEN: CHEN Mask
Definition at line 770 of file NUC472_442.h.
| #define ADC_CHEN_CHEN_Pos (0) |
ADC_T::CHEN: CHEN Position
Definition at line 769 of file NUC472_442.h.
| #define ADC_CMP0_ADCMPEN_Msk (0x1ul << ADC_CMP0_ADCMPEN_Pos) |
ADC_T::CMP: ADCMPEN Mask
Definition at line 779 of file NUC472_442.h.
| #define ADC_CMP0_ADCMPEN_Pos (0) |
ADC_T::CMP: ADCMPEN Position
Definition at line 778 of file NUC472_442.h.
| #define ADC_CMP0_ADCMPIE_Msk (0x1ul << ADC_CMP0_ADCMPIE_Pos) |
ADC_T::CMP: ADCMPIE Mask
Definition at line 782 of file NUC472_442.h.
| #define ADC_CMP0_ADCMPIE_Pos (1) |
ADC_T::CMP: ADCMPIE Position
Definition at line 781 of file NUC472_442.h.
| #define ADC_CMP0_CMPCH_Msk (0xful << ADC_CMP0_CMPCH_Pos) |
ADC_T::CMP: CMPCH Mask
Definition at line 788 of file NUC472_442.h.
| #define ADC_CMP0_CMPCH_Pos (3) |
ADC_T::CMP: CMPCH Position
Definition at line 787 of file NUC472_442.h.
| #define ADC_CMP0_CMPCOND_Msk (0x1ul << ADC_CMP0_CMPCOND_Pos) |
ADC_T::CMP: CMPCOND Mask
Definition at line 785 of file NUC472_442.h.
| #define ADC_CMP0_CMPCOND_Pos (2) |
ADC_T::CMP: CMPCOND Position
Definition at line 784 of file NUC472_442.h.
| #define ADC_CMP0_CMPDAT_Msk (0xffful << ADC_CMP0_CMPDAT_Pos) |
ADC_T::CMP: CMPDAT Mask
Definition at line 794 of file NUC472_442.h.
| #define ADC_CMP0_CMPDAT_Pos (16) |
ADC_T::CMP: CMPDAT Position
Definition at line 793 of file NUC472_442.h.
| #define ADC_CMP0_CMPMCNT_Msk (0xful << ADC_CMP0_CMPMCNT_Pos) |
ADC_T::CMP: CMPMCNT Mask
Definition at line 791 of file NUC472_442.h.
| #define ADC_CMP0_CMPMCNT_Pos (8) |
ADC_T::CMP: CMPMCNT Position
Definition at line 790 of file NUC472_442.h.
| #define ADC_CMP1_ADCMPEN_Msk (0x1ul << ADC_CMP1_ADCMPEN_Pos) |
ADC_T::CMP: ADCMPEN Mask
Definition at line 797 of file NUC472_442.h.
| #define ADC_CMP1_ADCMPEN_Pos (0) |
ADC_T::CMP: ADCMPEN Position
Definition at line 796 of file NUC472_442.h.
| #define ADC_CMP1_ADCMPIE_Msk (0x1ul << ADC_CMP1_ADCMPIE_Pos) |
ADC_T::CMP: ADCMPIE Mask
Definition at line 800 of file NUC472_442.h.
| #define ADC_CMP1_ADCMPIE_Pos (1) |
ADC_T::CMP: ADCMPIE Position
Definition at line 799 of file NUC472_442.h.
| #define ADC_CMP1_CMPCH_Msk (0xful << ADC_CMP1_CMPCH_Pos) |
ADC_T::CMP: CMPCH Mask
Definition at line 806 of file NUC472_442.h.
| #define ADC_CMP1_CMPCH_Pos (3) |
ADC_T::CMP: CMPCH Position
Definition at line 805 of file NUC472_442.h.
| #define ADC_CMP1_CMPCOND_Msk (0x1ul << ADC_CMP1_CMPCOND_Pos) |
ADC_T::CMP: CMPCOND Mask
Definition at line 803 of file NUC472_442.h.
| #define ADC_CMP1_CMPCOND_Pos (2) |
ADC_T::CMP: CMPCOND Position
Definition at line 802 of file NUC472_442.h.
| #define ADC_CMP1_CMPDAT_Msk (0xffful << ADC_CMP1_CMPDAT_Pos) |
ADC_T::CMP: CMPDAT Mask
Definition at line 812 of file NUC472_442.h.
| #define ADC_CMP1_CMPDAT_Pos (16) |
ADC_T::CMP: CMPDAT Position
Definition at line 811 of file NUC472_442.h.
| #define ADC_CMP1_CMPMCNT_Msk (0xful << ADC_CMP1_CMPMCNT_Pos) |
ADC_T::CMP: CMPMCNT Mask
Definition at line 809 of file NUC472_442.h.
| #define ADC_CMP1_CMPMCNT_Pos (8) |
ADC_T::CMP: CMPMCNT Position
Definition at line 808 of file NUC472_442.h.
| #define ADC_CTL_ADCEN_Msk (0x1ul << ADC_CTL_ADCEN_Pos) |
ADC_T::CTL: ADCEN Mask
Definition at line 737 of file NUC472_442.h.
| #define ADC_CTL_ADCEN_Pos (0) |
ADC_T::CTL: ADCEN Position
Definition at line 736 of file NUC472_442.h.
| #define ADC_CTL_ADCIEN_Msk (0x1ul << ADC_CTL_ADCIEN_Pos) |
ADC_T::CTL: ADCIEN Mask
Definition at line 740 of file NUC472_442.h.
| #define ADC_CTL_ADCIEN_Pos (1) |
ADC_T::CTL: ADCIEN Position
Definition at line 739 of file NUC472_442.h.
| #define ADC_CTL_DIFFEN_Msk (0x1ul << ADC_CTL_DIFFEN_Pos) |
ADC_T::CTL: DIFFEN Mask
Definition at line 758 of file NUC472_442.h.
| #define ADC_CTL_DIFFEN_Pos (10) |
ADC_T::CTL: DIFFEN Position
Definition at line 757 of file NUC472_442.h.
| #define ADC_CTL_DMOF_Msk (0x1ul << ADC_CTL_DMOF_Pos) |
ADC_T::CTL: DMOF Mask
Definition at line 767 of file NUC472_442.h.
| #define ADC_CTL_DMOF_Pos (31) |
ADC_T::CTL: DMOF Position
Definition at line 766 of file NUC472_442.h.
| #define ADC_CTL_HWTRGCOND_Msk (0x3ul << ADC_CTL_HWTRGCOND_Pos) |
ADC_T::CTL: HWTRGCOND Mask
Definition at line 749 of file NUC472_442.h.
| #define ADC_CTL_HWTRGCOND_Pos (6) |
ADC_T::CTL: HWTRGCOND Position
Definition at line 748 of file NUC472_442.h.
| #define ADC_CTL_HWTRGEN_Msk (0x1ul << ADC_CTL_HWTRGEN_Pos) |
ADC_T::CTL: HWTRGEN Mask
Definition at line 752 of file NUC472_442.h.
| #define ADC_CTL_HWTRGEN_Pos (8) |
ADC_T::CTL: HWTRGEN Position
Definition at line 751 of file NUC472_442.h.
| #define ADC_CTL_HWTRGSEL_Msk (0x3ul << ADC_CTL_HWTRGSEL_Pos) |
ADC_T::CTL: HWTRGSEL Mask
Definition at line 746 of file NUC472_442.h.
| #define ADC_CTL_HWTRGSEL_Pos (4) |
ADC_T::CTL: HWTRGSEL Position
Definition at line 745 of file NUC472_442.h.
| #define ADC_CTL_OPMODE_Msk (0x3ul << ADC_CTL_OPMODE_Pos) |
ADC_T::CTL: OPMODE Mask
Definition at line 743 of file NUC472_442.h.
| #define ADC_CTL_OPMODE_Pos (2) |
ADC_T::CTL: OPMODE Position
Definition at line 742 of file NUC472_442.h.
| #define ADC_CTL_PDMAEN_Msk (0x1ul << ADC_CTL_PDMAEN_Pos) |
ADC_T::CTL: PDMAEN Mask
Definition at line 755 of file NUC472_442.h.
| #define ADC_CTL_PDMAEN_Pos (9) |
ADC_T::CTL: PDMAEN Position
Definition at line 754 of file NUC472_442.h.
| #define ADC_CTL_PWMTRGDLY_Msk (0xfful << ADC_CTL_PWMTRGDLY_Pos) |
ADC_T::CTL: PWMTRGDLY Mask
Definition at line 764 of file NUC472_442.h.
| #define ADC_CTL_PWMTRGDLY_Pos (16) |
ADC_T::CTL: PWMTRGDLY Position
Definition at line 763 of file NUC472_442.h.
| #define ADC_CTL_SWTRG_Msk (0x1ul << ADC_CTL_SWTRG_Pos) |
ADC_T::CTL: SWTRG Mask
Definition at line 761 of file NUC472_442.h.
| #define ADC_CTL_SWTRG_Pos (11) |
ADC_T::CTL: SWTRG Position
Definition at line 760 of file NUC472_442.h.
| #define ADC_CURDAT_CURDAT_Msk (0x3fffful << ADC_CURDAT_CURDAT_Pos) |
ADC_T::CURDAT: CURDAT Mask
Definition at line 836 of file NUC472_442.h.
| #define ADC_CURDAT_CURDAT_Pos (0) |
ADC_T::CURDAT: CURDAT Position
Definition at line 835 of file NUC472_442.h.
| #define ADC_DAT0_OV_Msk (0x1ul << ADC_DAT0_OV_Pos) |
ADC_T::DAT: OV Mask
Definition at line 614 of file NUC472_442.h.
| #define ADC_DAT0_OV_Pos (16) |
ADC_T::DAT: OV Position
Definition at line 613 of file NUC472_442.h.
| #define ADC_DAT0_RESULT_Msk (0xfffful << ADC_DAT0_RESULT_Pos) |
ADC_T::DAT: RESULT Mask
Definition at line 611 of file NUC472_442.h.
| #define ADC_DAT0_RESULT_Pos (0) |
@addtogroup ADC_CONST ADC Bit Field Definition Constant Definitions for ADC Controller
ADC_T::DAT: RESULT Position
Definition at line 610 of file NUC472_442.h.
| #define ADC_DAT0_VALID_Msk (0x1ul << ADC_DAT0_VALID_Pos) |
ADC_T::DAT: VALID Mask
Definition at line 617 of file NUC472_442.h.
| #define ADC_DAT0_VALID_Pos (17) |
ADC_T::DAT: VALID Position
Definition at line 616 of file NUC472_442.h.
| #define ADC_DAT10_OV_Msk (0x1ul << ADC_DAT10_OV_Pos) |
ADC_T::DAT: OV Mask
Definition at line 704 of file NUC472_442.h.
| #define ADC_DAT10_OV_Pos (16) |
ADC_T::DAT: OV Position
Definition at line 703 of file NUC472_442.h.
| #define ADC_DAT10_RESULT_Msk (0xfffful << ADC_DAT10_RESULT_Pos) |
ADC_T::DAT: RESULT Mask
Definition at line 701 of file NUC472_442.h.
| #define ADC_DAT10_RESULT_Pos (0) |
ADC_T::DAT: RESULT Position
Definition at line 700 of file NUC472_442.h.
| #define ADC_DAT10_VALID_Msk (0x1ul << ADC_DAT10_VALID_Pos) |
ADC_T::DAT: VALID Mask
Definition at line 707 of file NUC472_442.h.
| #define ADC_DAT10_VALID_Pos (17) |
ADC_T::DAT: VALID Position
Definition at line 706 of file NUC472_442.h.
| #define ADC_DAT11_OV_Msk (0x1ul << ADC_DAT11_OV_Pos) |
ADC_T::DAT: OV Mask
Definition at line 713 of file NUC472_442.h.
| #define ADC_DAT11_OV_Pos (16) |
ADC_T::DAT: OV Position
Definition at line 712 of file NUC472_442.h.
| #define ADC_DAT11_RESULT_Msk (0xfffful << ADC_DAT11_RESULT_Pos) |
ADC_T::DAT: RESULT Mask
Definition at line 710 of file NUC472_442.h.
| #define ADC_DAT11_RESULT_Pos (0) |
ADC_T::DAT: RESULT Position
Definition at line 709 of file NUC472_442.h.
| #define ADC_DAT11_VALID_Msk (0x1ul << ADC_DAT11_VALID_Pos) |
ADC_T::DAT: VALID Mask
Definition at line 716 of file NUC472_442.h.
| #define ADC_DAT11_VALID_Pos (17) |
ADC_T::DAT: VALID Position
Definition at line 715 of file NUC472_442.h.
| #define ADC_DAT12_OV_Msk (0x1ul << ADC_DAT12_OV_Pos) |
ADC_T::DAT: OV Mask
Definition at line 722 of file NUC472_442.h.
| #define ADC_DAT12_OV_Pos (16) |
ADC_T::DAT: OV Position
Definition at line 721 of file NUC472_442.h.
| #define ADC_DAT12_RESULT_Msk (0xfffful << ADC_DAT12_RESULT_Pos) |
ADC_T::DAT: RESULT Mask
Definition at line 719 of file NUC472_442.h.
| #define ADC_DAT12_RESULT_Pos (0) |
ADC_T::DAT: RESULT Position
Definition at line 718 of file NUC472_442.h.
| #define ADC_DAT12_VALID_Msk (0x1ul << ADC_DAT12_VALID_Pos) |
ADC_T::DAT: VALID Mask
Definition at line 725 of file NUC472_442.h.
| #define ADC_DAT12_VALID_Pos (17) |
ADC_T::DAT: VALID Position
Definition at line 724 of file NUC472_442.h.
| #define ADC_DAT13_OV_Msk (0x1ul << ADC_DAT13_OV_Pos) |
ADC_T::DAT: OV Mask
Definition at line 731 of file NUC472_442.h.
| #define ADC_DAT13_OV_Pos (16) |
ADC_T::DAT: OV Position
Definition at line 730 of file NUC472_442.h.
| #define ADC_DAT13_RESULT_Msk (0xfffful << ADC_DAT13_RESULT_Pos) |
ADC_T::DAT: RESULT Mask
Definition at line 728 of file NUC472_442.h.
| #define ADC_DAT13_RESULT_Pos (0) |
ADC_T::DAT: RESULT Position
Definition at line 727 of file NUC472_442.h.
| #define ADC_DAT13_VALID_Msk (0x1ul << ADC_DAT13_VALID_Pos) |
ADC_T::DAT: VALID Mask
Definition at line 734 of file NUC472_442.h.
| #define ADC_DAT13_VALID_Pos (17) |
ADC_T::DAT: VALID Position
Definition at line 733 of file NUC472_442.h.
| #define ADC_DAT1_OV_Msk (0x1ul << ADC_DAT1_OV_Pos) |
ADC_T::DAT: OV Mask
Definition at line 623 of file NUC472_442.h.
| #define ADC_DAT1_OV_Pos (16) |
ADC_T::DAT: OV Position
Definition at line 622 of file NUC472_442.h.
| #define ADC_DAT1_RESULT_Msk (0xfffful << ADC_DAT1_RESULT_Pos) |
ADC_T::DAT: RESULT Mask
Definition at line 620 of file NUC472_442.h.
| #define ADC_DAT1_RESULT_Pos (0) |
ADC_T::DAT: RESULT Position
Definition at line 619 of file NUC472_442.h.
| #define ADC_DAT1_VALID_Msk (0x1ul << ADC_DAT1_VALID_Pos) |
ADC_T::DAT: VALID Mask
Definition at line 626 of file NUC472_442.h.
| #define ADC_DAT1_VALID_Pos (17) |
ADC_T::DAT: VALID Position
Definition at line 625 of file NUC472_442.h.
| #define ADC_DAT2_OV_Msk (0x1ul << ADC_DAT2_OV_Pos) |
ADC_T::DAT: OV Mask
Definition at line 632 of file NUC472_442.h.
| #define ADC_DAT2_OV_Pos (16) |
ADC_T::DAT: OV Position
Definition at line 631 of file NUC472_442.h.
| #define ADC_DAT2_RESULT_Msk (0xfffful << ADC_DAT2_RESULT_Pos) |
ADC_T::DAT: RESULT Mask
Definition at line 629 of file NUC472_442.h.
| #define ADC_DAT2_RESULT_Pos (0) |
ADC_T::DAT: RESULT Position
Definition at line 628 of file NUC472_442.h.
| #define ADC_DAT2_VALID_Msk (0x1ul << ADC_DAT2_VALID_Pos) |
ADC_T::DAT: VALID Mask
Definition at line 635 of file NUC472_442.h.
| #define ADC_DAT2_VALID_Pos (17) |
ADC_T::DAT: VALID Position
Definition at line 634 of file NUC472_442.h.
| #define ADC_DAT3_OV_Msk (0x1ul << ADC_DAT3_OV_Pos) |
ADC_T::DAT: OV Mask
Definition at line 641 of file NUC472_442.h.
| #define ADC_DAT3_OV_Pos (16) |
ADC_T::DAT: OV Position
Definition at line 640 of file NUC472_442.h.
| #define ADC_DAT3_RESULT_Msk (0xfffful << ADC_DAT3_RESULT_Pos) |
ADC_T::DAT: RESULT Mask
Definition at line 638 of file NUC472_442.h.
| #define ADC_DAT3_RESULT_Pos (0) |
ADC_T::DAT: RESULT Position
Definition at line 637 of file NUC472_442.h.
| #define ADC_DAT3_VALID_Msk (0x1ul << ADC_DAT3_VALID_Pos) |
ADC_T::DAT: VALID Mask
Definition at line 644 of file NUC472_442.h.
| #define ADC_DAT3_VALID_Pos (17) |
ADC_T::DAT: VALID Position
Definition at line 643 of file NUC472_442.h.
| #define ADC_DAT4_OV_Msk (0x1ul << ADC_DAT4_OV_Pos) |
ADC_T::DAT: OV Mask
Definition at line 650 of file NUC472_442.h.
| #define ADC_DAT4_OV_Pos (16) |
ADC_T::DAT: OV Position
Definition at line 649 of file NUC472_442.h.
| #define ADC_DAT4_RESULT_Msk (0xfffful << ADC_DAT4_RESULT_Pos) |
ADC_T::DAT: RESULT Mask
Definition at line 647 of file NUC472_442.h.
| #define ADC_DAT4_RESULT_Pos (0) |
ADC_T::DAT: RESULT Position
Definition at line 646 of file NUC472_442.h.
| #define ADC_DAT4_VALID_Msk (0x1ul << ADC_DAT4_VALID_Pos) |
ADC_T::DAT: VALID Mask
Definition at line 653 of file NUC472_442.h.
| #define ADC_DAT4_VALID_Pos (17) |
ADC_T::DAT: VALID Position
Definition at line 652 of file NUC472_442.h.
| #define ADC_DAT5_OV_Msk (0x1ul << ADC_DAT5_OV_Pos) |
ADC_T::DAT: OV Mask
Definition at line 659 of file NUC472_442.h.
| #define ADC_DAT5_OV_Pos (16) |
ADC_T::DAT: OV Position
Definition at line 658 of file NUC472_442.h.
| #define ADC_DAT5_RESULT_Msk (0xfffful << ADC_DAT5_RESULT_Pos) |
ADC_T::DAT: RESULT Mask
Definition at line 656 of file NUC472_442.h.
| #define ADC_DAT5_RESULT_Pos (0) |
ADC_T::DAT: RESULT Position
Definition at line 655 of file NUC472_442.h.
| #define ADC_DAT5_VALID_Msk (0x1ul << ADC_DAT5_VALID_Pos) |
ADC_T::DAT: VALID Mask
Definition at line 662 of file NUC472_442.h.
| #define ADC_DAT5_VALID_Pos (17) |
ADC_T::DAT: VALID Position
Definition at line 661 of file NUC472_442.h.
| #define ADC_DAT6_OV_Msk (0x1ul << ADC_DAT6_OV_Pos) |
ADC_T::DAT: OV Mask
Definition at line 668 of file NUC472_442.h.
| #define ADC_DAT6_OV_Pos (16) |
ADC_T::DAT: OV Position
Definition at line 667 of file NUC472_442.h.
| #define ADC_DAT6_RESULT_Msk (0xfffful << ADC_DAT6_RESULT_Pos) |
ADC_T::DAT: RESULT Mask
Definition at line 665 of file NUC472_442.h.
| #define ADC_DAT6_RESULT_Pos (0) |
ADC_T::DAT: RESULT Position
Definition at line 664 of file NUC472_442.h.
| #define ADC_DAT6_VALID_Msk (0x1ul << ADC_DAT6_VALID_Pos) |
ADC_T::DAT: VALID Mask
Definition at line 671 of file NUC472_442.h.
| #define ADC_DAT6_VALID_Pos (17) |
ADC_T::DAT: VALID Position
Definition at line 670 of file NUC472_442.h.
| #define ADC_DAT7_OV_Msk (0x1ul << ADC_DAT7_OV_Pos) |
ADC_T::DAT: OV Mask
Definition at line 677 of file NUC472_442.h.
| #define ADC_DAT7_OV_Pos (16) |
ADC_T::DAT: OV Position
Definition at line 676 of file NUC472_442.h.
| #define ADC_DAT7_RESULT_Msk (0xfffful << ADC_DAT7_RESULT_Pos) |
ADC_T::DAT: RESULT Mask
Definition at line 674 of file NUC472_442.h.
| #define ADC_DAT7_RESULT_Pos (0) |
ADC_T::DAT: RESULT Position
Definition at line 673 of file NUC472_442.h.
| #define ADC_DAT7_VALID_Msk (0x1ul << ADC_DAT7_VALID_Pos) |
ADC_T::DAT: VALID Mask
Definition at line 680 of file NUC472_442.h.
| #define ADC_DAT7_VALID_Pos (17) |
ADC_T::DAT: VALID Position
Definition at line 679 of file NUC472_442.h.
| #define ADC_DAT8_OV_Msk (0x1ul << ADC_DAT8_OV_Pos) |
ADC_T::DAT: OV Mask
Definition at line 686 of file NUC472_442.h.
| #define ADC_DAT8_OV_Pos (16) |
ADC_T::DAT: OV Position
Definition at line 685 of file NUC472_442.h.
| #define ADC_DAT8_RESULT_Msk (0xfffful << ADC_DAT8_RESULT_Pos) |
ADC_T::DAT: RESULT Mask
Definition at line 683 of file NUC472_442.h.
| #define ADC_DAT8_RESULT_Pos (0) |
ADC_T::DAT: RESULT Position
Definition at line 682 of file NUC472_442.h.
| #define ADC_DAT8_VALID_Msk (0x1ul << ADC_DAT8_VALID_Pos) |
ADC_T::DAT: VALID Mask
Definition at line 689 of file NUC472_442.h.
| #define ADC_DAT8_VALID_Pos (17) |
ADC_T::DAT: VALID Position
Definition at line 688 of file NUC472_442.h.
| #define ADC_DAT9_OV_Msk (0x1ul << ADC_DAT9_OV_Pos) |
ADC_T::DAT: OV Mask
Definition at line 695 of file NUC472_442.h.
| #define ADC_DAT9_OV_Pos (16) |
ADC_T::DAT: OV Position
Definition at line 694 of file NUC472_442.h.
| #define ADC_DAT9_RESULT_Msk (0xfffful << ADC_DAT9_RESULT_Pos) |
ADC_T::DAT: RESULT Mask
Definition at line 692 of file NUC472_442.h.
| #define ADC_DAT9_RESULT_Pos (0) |
ADC_T::DAT: RESULT Position
Definition at line 691 of file NUC472_442.h.
| #define ADC_DAT9_VALID_Msk (0x1ul << ADC_DAT9_VALID_Pos) |
ADC_T::DAT: VALID Mask
Definition at line 698 of file NUC472_442.h.
| #define ADC_DAT9_VALID_Pos (17) |
ADC_T::DAT: VALID Position
Definition at line 697 of file NUC472_442.h.
| #define ADC_STATUS0_ADCMPF0_Msk (0x1ul << ADC_STATUS0_ADCMPF0_Pos) |
ADC_T::STATUS0: ADCMPF0 Mask
Definition at line 818 of file NUC472_442.h.
| #define ADC_STATUS0_ADCMPF0_Pos (1) |
ADC_T::STATUS0: ADCMPF0 Position
Definition at line 817 of file NUC472_442.h.
| #define ADC_STATUS0_ADCMPF1_Msk (0x1ul << ADC_STATUS0_ADCMPF1_Pos) |
ADC_T::STATUS0: ADCMPF1 Mask
Definition at line 821 of file NUC472_442.h.
| #define ADC_STATUS0_ADCMPF1_Pos (2) |
ADC_T::STATUS0: ADCMPF1 Position
Definition at line 820 of file NUC472_442.h.
| #define ADC_STATUS0_ADIF_Msk (0x1ul << ADC_STATUS0_ADIF_Pos) |
ADC_T::STATUS0: ADIF Mask
Definition at line 815 of file NUC472_442.h.
| #define ADC_STATUS0_ADIF_Pos (0) |
ADC_T::STATUS0: ADIF Position
Definition at line 814 of file NUC472_442.h.
| #define ADC_STATUS0_BUSY_Msk (0x1ul << ADC_STATUS0_BUSY_Pos) |
ADC_T::STATUS0: BUSY Mask
Definition at line 824 of file NUC472_442.h.
| #define ADC_STATUS0_BUSY_Pos (3) |
ADC_T::STATUS0: BUSY Position
Definition at line 823 of file NUC472_442.h.
| #define ADC_STATUS0_CHANNEL_Msk (0xful << ADC_STATUS0_CHANNEL_Pos) |
ADC_T::STATUS0: CHANNEL Mask
Definition at line 827 of file NUC472_442.h.
| #define ADC_STATUS0_CHANNEL_Pos (4) |
ADC_T::STATUS0: CHANNEL Position
Definition at line 826 of file NUC472_442.h.
| #define ADC_STATUS1_OV_Msk (0x3ffful << ADC_STATUS1_OV_Pos) |
ADC_T::STATUS1: OV Mask
Definition at line 833 of file NUC472_442.h.
| #define ADC_STATUS1_OV_Pos (16) |
ADC_T::STATUS1: OV Position
Definition at line 832 of file NUC472_442.h.
| #define ADC_STATUS1_VALID_Msk (0x3ffful << ADC_STATUS1_VALID_Pos) |
ADC_T::STATUS1: VALID Mask
Definition at line 830 of file NUC472_442.h.
| #define ADC_STATUS1_VALID_Pos (0) |
ADC_T::STATUS1: VALID Position
Definition at line 829 of file NUC472_442.h.
| #define CAN_BRPE_BRPE_Msk (0xFul << CAN_BRPE_BRPE_Pos) |
CAN_T::BRPE: BRPE Mask
Definition at line 1528 of file NUC472_442.h.
| #define CAN_BRPE_BRPE_Pos 0 |
CAN_T::BRPE: BRPE Position
Definition at line 1527 of file NUC472_442.h.
| #define CAN_BTIME_BRP_Msk (0x3Ful << CAN_BTIME_BRP_Pos) |
CAN_T::BTIME: BRP Mask
Definition at line 1507 of file NUC472_442.h.
| #define CAN_BTIME_BRP_Pos 0 |
CAN_T::BTIME: BRP Position
Definition at line 1506 of file NUC472_442.h.
| #define CAN_BTIME_SJW_Msk (0x3ul << CAN_BTIME_SJW_Pos) |
CAN_T::BTIME: SJW Mask
Definition at line 1504 of file NUC472_442.h.
| #define CAN_BTIME_SJW_Pos 6 |
CAN_T::BTIME: SJW Position
Definition at line 1503 of file NUC472_442.h.
| #define CAN_BTIME_TSEG1_Msk (0xFul << CAN_BTIME_TSEG1_Pos) |
CAN_T::BTIME: TSEG1 Mask
Definition at line 1501 of file NUC472_442.h.
| #define CAN_BTIME_TSEG1_Pos 8 |
CAN_T::BTIME: TSEG1 Position
Definition at line 1500 of file NUC472_442.h.
| #define CAN_BTIME_TSEG2_Msk (0x7ul << CAN_BTIME_TSEG2_Pos) |
CAN_T::BTIME: TSEG2 Mask
Definition at line 1498 of file NUC472_442.h.
| #define CAN_BTIME_TSEG2_Pos 12 |
CAN_T::BTIME: TSEG2 Position
Definition at line 1497 of file NUC472_442.h.
| #define CAN_CON_CCE_Msk (1ul << CAN_CON_CCE_Pos) |
CAN_T::CON: CCE Mask
Definition at line 1453 of file NUC472_442.h.
| #define CAN_CON_CCE_Pos 6 |
CAN_T::CON: CCE Position
Definition at line 1452 of file NUC472_442.h.
| #define CAN_CON_DAR_Msk (1ul << CAN_CON_DAR_Pos) |
CAN_T::CON: DAR Mask
Definition at line 1456 of file NUC472_442.h.
| #define CAN_CON_DAR_Pos 5 |
CAN_T::CON: DAR Position
Definition at line 1455 of file NUC472_442.h.
| #define CAN_CON_EIE_Msk (1ul << CAN_CON_EIE_Pos) |
CAN_T::CON: EIE Mask
Definition at line 1459 of file NUC472_442.h.
| #define CAN_CON_EIE_Pos 3 |
CAN_T::CON: EIE Position
Definition at line 1458 of file NUC472_442.h.
| #define CAN_CON_IE_Msk (1ul << CAN_CON_IE_Pos) |
CAN_T::CON: IE Mask
Definition at line 1465 of file NUC472_442.h.
| #define CAN_CON_IE_Pos 1 |
CAN_T::CON: IE Position
Definition at line 1464 of file NUC472_442.h.
| #define CAN_CON_INIT_Msk (1ul << CAN_CON_INIT_Pos) |
CAN_T::CON: INIT Mask
Definition at line 1468 of file NUC472_442.h.
| #define CAN_CON_INIT_Pos 0 |
CAN_T::CON: INIT Position
Definition at line 1467 of file NUC472_442.h.
| #define CAN_CON_SIE_Msk (1ul << CAN_CON_SIE_Pos) |
CAN_T::CON: SIE Mask
Definition at line 1462 of file NUC472_442.h.
| #define CAN_CON_SIE_Pos 2 |
CAN_T::CON: SIE Position
Definition at line 1461 of file NUC472_442.h.
| #define CAN_CON_TEST_Msk (1ul << CAN_CON_TEST_Pos) |
CAN_T::CON: TEST Mask
Definition at line 1450 of file NUC472_442.h.
| #define CAN_CON_TEST_Pos 7 |
@addtogroup CAN_CONST CAN Bit Field Definition Constant Definitions for CAN Controller
CAN_T::CON: TEST Position
Definition at line 1449 of file NUC472_442.h.
| #define CAN_ERR_REC_Msk (0x7Ful << CAN_ERR_REC_Pos) |
CAN_T::ERR: REC Mask
Definition at line 1492 of file NUC472_442.h.
| #define CAN_ERR_REC_Pos 8 |
CAN_T::ERR: REC Position
Definition at line 1491 of file NUC472_442.h.
| #define CAN_ERR_RP_Msk (1ul << CAN_ERR_RP_Pos) |
CAN_T::ERR: RP Mask
Definition at line 1489 of file NUC472_442.h.
| #define CAN_ERR_RP_Pos 15 |
CAN_T::ERR: RP Position
Definition at line 1488 of file NUC472_442.h.
| #define CAN_ERR_TEC_Msk (0xFFul << CAN_ERR_TEC_Pos) |
CAN_T::ERR: TEC Mask
Definition at line 1495 of file NUC472_442.h.
| #define CAN_ERR_TEC_Pos 0 |
CAN_T::ERR: TEC Position
Definition at line 1494 of file NUC472_442.h.
| #define CAN_IF_ARB1_ID_Msk (0xFFFFul << CAN_IF_ARB1_ID_Pos) |
CAN_IF_T::ARB1: ID Mask
Definition at line 1573 of file NUC472_442.h.
| #define CAN_IF_ARB1_ID_Pos 0 |
CAN_IF_T::ARB1: ID Position
Definition at line 1572 of file NUC472_442.h.
| #define CAN_IF_ARB2_DIR_Msk (1ul << CAN_IF_ARB2_DIR_Pos) |
CAN_IF_T::ARB2: DIR Mask
Definition at line 1582 of file NUC472_442.h.
| #define CAN_IF_ARB2_DIR_Pos 13 |
CAN_IF_T::ARB2: DIR Position
Definition at line 1581 of file NUC472_442.h.
| #define CAN_IF_ARB2_ID_Msk (0x1FFFul << CAN_IF_ARB2_ID_Pos) |
CAN_IF_T::ARB2: ID Mask
Definition at line 1585 of file NUC472_442.h.
| #define CAN_IF_ARB2_ID_Pos 0 |
CAN_IF_T::ARB2: ID Position
Definition at line 1584 of file NUC472_442.h.
| #define CAN_IF_ARB2_MSGVAL_Msk (1ul << CAN_IF_ARB2_MSGVAL_Pos) |
CAN_IF_T::ARB2: MSGVAL Mask
Definition at line 1576 of file NUC472_442.h.
| #define CAN_IF_ARB2_MSGVAL_Pos 15 |
CAN_IF_T::ARB2: MSGVAL Position
Definition at line 1575 of file NUC472_442.h.
| #define CAN_IF_ARB2_XTD_Msk (1ul << CAN_IF_ARB2_XTD_Pos) |
CAN_IF_T::ARB2: XTD Mask
Definition at line 1579 of file NUC472_442.h.
| #define CAN_IF_ARB2_XTD_Pos 14 |
CAN_IF_T::ARB2: XTD Position
Definition at line 1578 of file NUC472_442.h.
| #define CAN_IF_CMASK_ARB_Msk (1ul << CAN_IF_CMASK_ARB_Pos) |
CAN_IF_T::CMASK: ARB Mask
Definition at line 1543 of file NUC472_442.h.
| #define CAN_IF_CMASK_ARB_Pos 5 |
CAN_IF_T::CMASK: ARB Position
Definition at line 1542 of file NUC472_442.h.
| #define CAN_IF_CMASK_CLRINTPND_Msk (1ul << CAN_IF_CMASK_CLRINTPND_Pos) |
CAN_IF_T::CMASK: CLRINTPND Mask
Definition at line 1549 of file NUC472_442.h.
| #define CAN_IF_CMASK_CLRINTPND_Pos 3 |
CAN_IF_T::CMASK: CLRINTPND Position
Definition at line 1548 of file NUC472_442.h.
| #define CAN_IF_CMASK_CONTROL_Msk (1ul << CAN_IF_CMASK_CONTROL_Pos) |
CAN_IF_T::CMASK: CONTROL Mask
Definition at line 1546 of file NUC472_442.h.
| #define CAN_IF_CMASK_CONTROL_Pos 4 |
CAN_IF_T::CMASK: CONTROL Position
Definition at line 1545 of file NUC472_442.h.
| #define CAN_IF_CMASK_DATAA_Msk (1ul << CAN_IF_CMASK_DATAA_Pos) |
CAN_IF_T::CMASK: DATAA Mask
Definition at line 1555 of file NUC472_442.h.
| #define CAN_IF_CMASK_DATAA_Pos 1 |
CAN_IF_T::CMASK: DATAA Position
Definition at line 1554 of file NUC472_442.h.
| #define CAN_IF_CMASK_DATAB_Msk (1ul << CAN_IF_CMASK_DATAB_Pos) |
CAN_IF_T::CMASK: DATAB Mask
Definition at line 1558 of file NUC472_442.h.
| #define CAN_IF_CMASK_DATAB_Pos 0 |
CAN_IF_T::CMASK: DATAB Position
Definition at line 1557 of file NUC472_442.h.
| #define CAN_IF_CMASK_MASK_Msk (1ul << CAN_IF_CMASK_MASK_Pos) |
CAN_IF_T::CMASK: MASK Mask
Definition at line 1540 of file NUC472_442.h.
| #define CAN_IF_CMASK_MASK_Pos 6 |
CAN_IF_T::CMASK: MASK Position
Definition at line 1539 of file NUC472_442.h.
| #define CAN_IF_CMASK_TXRQSTNEWDAT_Msk (1ul << CAN_IF_CMASK_TXRQSTNEWDAT_Pos) |
CAN_IF_T::CMASK: TXRQSTNEWDAT Mask
Definition at line 1552 of file NUC472_442.h.
| #define CAN_IF_CMASK_TXRQSTNEWDAT_Pos 2 |
CAN_IF_T::CMASK: TXRQSTNEWDAT Position
Definition at line 1551 of file NUC472_442.h.
| #define CAN_IF_CMASK_WRRD_Msk (1ul << CAN_IF_CMASK_WRRD_Pos) |
CAN_IF_T::CMASK: WRRD Mask
Definition at line 1537 of file NUC472_442.h.
| #define CAN_IF_CMASK_WRRD_Pos 7 |
CAN_IF_T::CMASK: WRRD Position
Definition at line 1536 of file NUC472_442.h.
| #define CAN_IF_CREQ_BUSY_Msk (1ul << CAN_IF_CREQ_BUSY_Pos) |
CAN_IF_T::CREQ: BUSY Mask
Definition at line 1531 of file NUC472_442.h.
| #define CAN_IF_CREQ_BUSY_Pos 15 |
CAN_IF_T::CREQ: BUSY Position
Definition at line 1530 of file NUC472_442.h.
| #define CAN_IF_CREQ_MSGNUM_Msk (0x3Ful << CAN_IF_CREQ_MSGNUM_Pos) |
CAN_IF_T::CREQ: MSGNUM Mask
Definition at line 1534 of file NUC472_442.h.
| #define CAN_IF_CREQ_MSGNUM_Pos 0 |
CAN_IF_T::CREQ: MSGNUM Position
Definition at line 1533 of file NUC472_442.h.
| #define CAN_IF_DAT_A1_DATA0_Msk (0xFFul << CAN_IF_DAT_A1_DATA0_Pos) |
CAN_IF_T::DAT_A1: DATA0 Mask
Definition at line 1621 of file NUC472_442.h.
| #define CAN_IF_DAT_A1_DATA0_Pos 0 |
CAN_IF_T::DAT_A1: DATA0 Position
Definition at line 1620 of file NUC472_442.h.
| #define CAN_IF_DAT_A1_DATA1_Msk (0xFFul << CAN_IF_DAT_A1_DATA1_Pos) |
CAN_IF_T::DAT_A1: DATA1 Mask
Definition at line 1618 of file NUC472_442.h.
| #define CAN_IF_DAT_A1_DATA1_Pos 8 |
CAN_IF_T::DAT_A1: DATA1 Position
Definition at line 1617 of file NUC472_442.h.
| #define CAN_IF_DAT_A2_DATA2_Msk (0xFFul << CAN_IF_DAT_A2_DATA2_Pos) |
CAN_IF_T::DAT_A2: DATA2 Mask
Definition at line 1627 of file NUC472_442.h.
| #define CAN_IF_DAT_A2_DATA2_Pos 0 |
CAN_IF_T::DAT_A2: DATA2 Position
Definition at line 1626 of file NUC472_442.h.
| #define CAN_IF_DAT_A2_DATA3_Msk (0xFFul << CAN_IF_DAT_A2_DATA3_Pos) |
CAN_IF_T::DAT_A2: DATA3 Mask
Definition at line 1624 of file NUC472_442.h.
| #define CAN_IF_DAT_A2_DATA3_Pos 8 |
CAN_IF_T::DAT_A2: DATA3 Position
Definition at line 1623 of file NUC472_442.h.
| #define CAN_IF_DAT_B1_DATA4_Msk (0xFFul << CAN_IF_DAT_B1_DATA4_Pos) |
CAN_IF_T::DAT_B1: DATA4 Mask
Definition at line 1633 of file NUC472_442.h.
| #define CAN_IF_DAT_B1_DATA4_Pos 0 |
CAN_IF_T::DAT_B1: DATA4 Position
Definition at line 1632 of file NUC472_442.h.
| #define CAN_IF_DAT_B1_DATA5_Msk (0xFFul << CAN_IF_DAT_B1_DATA5_Pos) |
CAN_IF_T::DAT_B1: DATA5 Mask
Definition at line 1630 of file NUC472_442.h.
| #define CAN_IF_DAT_B1_DATA5_Pos 8 |
CAN_IF_T::DAT_B1: DATA5 Position
Definition at line 1629 of file NUC472_442.h.
| #define CAN_IF_DAT_B2_DATA6_Msk (0xFFul << CAN_IF_DAT_B2_DATA6_Pos) |
CAN_IF_T::DAT_B2: DATA6 Mask
Definition at line 1639 of file NUC472_442.h.
| #define CAN_IF_DAT_B2_DATA6_Pos 0 |
CAN_IF_T::DAT_B2: DATA6 Position
Definition at line 1638 of file NUC472_442.h.
| #define CAN_IF_DAT_B2_DATA7_Msk (0xFFul << CAN_IF_DAT_B2_DATA7_Pos) |
CAN_IF_T::DAT_B2: DATA7 Mask
Definition at line 1636 of file NUC472_442.h.
| #define CAN_IF_DAT_B2_DATA7_Pos 8 |
CAN_IF_T::DAT_B2: DATA7 Position
Definition at line 1635 of file NUC472_442.h.
| #define CAN_IF_IPND1_INTPND_Msk (0xFFFFul << CAN_IF_IPND1_INTPND_Pos) |
CAN_T::IPND1: INTPND Mask
Definition at line 1654 of file NUC472_442.h.
| #define CAN_IF_IPND1_INTPND_Pos 0 |
CAN_T::IPND1: INTPND Position
Definition at line 1653 of file NUC472_442.h.
| #define CAN_IF_IPND2_INTPND_Msk (0xFFFFul << CAN_IF_IPND2_INTPND_Pos) |
CAN_T::IPND2: INTPND Mask
Definition at line 1657 of file NUC472_442.h.
| #define CAN_IF_IPND2_INTPND_Pos 0 |
CAN_T::IPND2: INTPND Position
Definition at line 1656 of file NUC472_442.h.
| #define CAN_IF_MASK1_MSK_Msk (0xFFul << CAN_IF_MASK1_MSK_Pos) |
CAN_IF_T::MASK1: MSK Mask
Definition at line 1561 of file NUC472_442.h.
| #define CAN_IF_MASK1_MSK_Pos 0 |
CAN_IF_T::MASK1: MSK Position
Definition at line 1560 of file NUC472_442.h.
| #define CAN_IF_MASK2_MDIR_Msk (1ul << CAN_IF_MASK2_MDIR_Pos) |
CAN_IF_T::MASK2: MDIR Mask
Definition at line 1567 of file NUC472_442.h.
| #define CAN_IF_MASK2_MDIR_Pos 14 |
CAN_IF_T::MASK2: MDIR Position
Definition at line 1566 of file NUC472_442.h.
| #define CAN_IF_MASK2_MSK_Msk (0x1FFul << CAN_IF_MASK2_MSK_Pos) |
CAN_IF_T::MASK2: MSK Mask
Definition at line 1570 of file NUC472_442.h.
| #define CAN_IF_MASK2_MSK_Pos 0 |
CAN_IF_T::MASK2: MSK Position
Definition at line 1569 of file NUC472_442.h.
| #define CAN_IF_MASK2_MXTD_Msk (1ul << CAN_IF_MASK2_MXTD_Pos) |
CAN_IF_T::MASK2: MXTD Mask
Definition at line 1564 of file NUC472_442.h.
| #define CAN_IF_MASK2_MXTD_Pos 15 |
CAN_IF_T::MASK2: MXTD Position
Definition at line 1563 of file NUC472_442.h.
| #define CAN_IF_MCON_DLC_Msk (0xFul << CAN_IF_MCON_DLC_Pos) |
CAN_IF_T::MCON: DLC Mask
Definition at line 1615 of file NUC472_442.h.
| #define CAN_IF_MCON_DLC_Pos 0 |
CAN_IF_T::MCON: DLC Position
Definition at line 1614 of file NUC472_442.h.
| #define CAN_IF_MCON_EOB_Msk (1ul << CAN_IF_MCON_EOB_Pos) |
CAN_IF_T::MCON: EOB Mask
Definition at line 1612 of file NUC472_442.h.
| #define CAN_IF_MCON_EOB_Pos 7 |
CAN_IF_T::MCON: EOB Position
Definition at line 1611 of file NUC472_442.h.
| #define CAN_IF_MCON_INTPND_Msk (1ul << CAN_IF_MCON_INTPND_Pos) |
CAN_IF_T::MCON: INTPND Mask
Definition at line 1594 of file NUC472_442.h.
| #define CAN_IF_MCON_INTPND_Pos 13 |
CAN_IF_T::MCON: INTPND Position
Definition at line 1593 of file NUC472_442.h.
| #define CAN_IF_MCON_MSGLST_Msk (1ul << CAN_IF_MCON_MSGLST_Pos) |
CAN_IF_T::MCON: MSGLST Mask
Definition at line 1591 of file NUC472_442.h.
| #define CAN_IF_MCON_MSGLST_Pos 14 |
CAN_IF_T::MCON: MSGLST Position
Definition at line 1590 of file NUC472_442.h.
| #define CAN_IF_MCON_NEWDAT_Msk (1ul << CAN_IF_MCON_NEWDAT_Pos) |
CAN_IF_T::MCON: NEWDAT Mask
Definition at line 1588 of file NUC472_442.h.
| #define CAN_IF_MCON_NEWDAT_Pos 15 |
CAN_IF_T::MCON: NEWDAT Position
Definition at line 1587 of file NUC472_442.h.
| #define CAN_IF_MCON_RMTEN_Msk (1ul << CAN_IF_MCON_RMTEN_Pos) |
CAN_IF_T::MCON: RMTEN Mask
Definition at line 1606 of file NUC472_442.h.
| #define CAN_IF_MCON_RMTEN_Pos 9 |
CAN_IF_T::MCON: RMTEN Position
Definition at line 1605 of file NUC472_442.h.
| #define CAN_IF_MCON_RXIE_Msk (1ul << CAN_IF_MCON_RXIE_Pos) |
CAN_IF_T::MCON: RXIE Mask
Definition at line 1603 of file NUC472_442.h.
| #define CAN_IF_MCON_RXIE_Pos 10 |
CAN_IF_T::MCON: RXIE Position
Definition at line 1602 of file NUC472_442.h.
| #define CAN_IF_MCON_TXIE_Msk (1ul << CAN_IF_MCON_TXIE_Pos) |
CAN_IF_T::MCON: TXIE Mask
Definition at line 1600 of file NUC472_442.h.
| #define CAN_IF_MCON_TXIE_Pos 11 |
CAN_IF_T::MCON: TXIE Position
Definition at line 1599 of file NUC472_442.h.
| #define CAN_IF_MCON_TXRQST_Msk (1ul << CAN_IF_MCON_TXRQST_Pos) |
CAN_IF_T::MCON: TXRQST Mask
Definition at line 1609 of file NUC472_442.h.
| #define CAN_IF_MCON_TXRQST_Pos 8 |
CAN_IF_T::MCON: TXRQST Position
Definition at line 1608 of file NUC472_442.h.
| #define CAN_IF_MCON_UMASK_Msk (1ul << CAN_IF_MCON_UMASK_Pos) |
CAN_IF_T::MCON: UMASK Mask
Definition at line 1597 of file NUC472_442.h.
| #define CAN_IF_MCON_UMASK_Pos 12 |
CAN_IF_T::MCON: UMASK Position
Definition at line 1596 of file NUC472_442.h.
| #define CAN_IF_MVLD1_MSGVAL_Msk (0xFFFFul << CAN_IF_MVLD1_MSGVAL_Pos) |
CAN_T::MVLD1: MSGVAL Mask
Definition at line 1660 of file NUC472_442.h.
| #define CAN_IF_MVLD1_MSGVAL_Pos 0 |
CAN_T::MVLD1: MSGVAL Position
Definition at line 1659 of file NUC472_442.h.
| #define CAN_IF_MVLD2_MSGVAL_Msk (0xFFFFul << CAN_IF_MVLD2_MSGVAL_Pos) |
CAN_T::MVLD2: MSGVAL Mask
Definition at line 1663 of file NUC472_442.h.
| #define CAN_IF_MVLD2_MSGVAL_Pos 0 |
CAN_T::MVLD2: MSGVAL Position
Definition at line 1662 of file NUC472_442.h.
| #define CAN_IF_NDAT1_NEWDATA_Msk (0xFFFFul << CAN_IF_NDAT1_NEWDATA_Pos) |
CAN_T::NDAT1: NEWDATA Mask
Definition at line 1648 of file NUC472_442.h.
| #define CAN_IF_NDAT1_NEWDATA_Pos 0 |
CAN_T::NDAT1: NEWDATA Position
Definition at line 1647 of file NUC472_442.h.
| #define CAN_IF_NDAT2_NEWDATA_Msk (0xFFFFul << CAN_IF_NDAT2_NEWDATA_Pos) |
CAN_T::NDAT2: NEWDATA Mask
Definition at line 1651 of file NUC472_442.h.
| #define CAN_IF_NDAT2_NEWDATA_Pos 0 |
CAN_T::NDAT2: NEWDATA Position
Definition at line 1650 of file NUC472_442.h.
| #define CAN_IF_TXRQST1_TXRQST_Msk (0xFFFFul << CAN_IF_TXRQST1_TXRQST_Pos) |
CAN_T::TXRQST1: TXRQST Mask
Definition at line 1642 of file NUC472_442.h.
| #define CAN_IF_TXRQST1_TXRQST_Pos 0 |
CAN_T::TXRQST1: TXRQST Position
Definition at line 1641 of file NUC472_442.h.
| #define CAN_IF_TXRQST2_TXRQST_Msk (0xFFFFul << CAN_IF_TXRQST2_TXRQST_Pos) |
CAN_T::TXRQST2: TXRQST Mask
Definition at line 1645 of file NUC472_442.h.
| #define CAN_IF_TXRQST2_TXRQST_Pos 0 |
CAN_T::TXRQST2: TXRQST Position
Definition at line 1644 of file NUC472_442.h.
| #define CAN_IIDR_INTID_Msk (0xFFFFul << CAN_IIDR_INTID_Pos) |
CAN_T::IIDR: INTID Mask
Definition at line 1510 of file NUC472_442.h.
| #define CAN_IIDR_INTID_Pos 0 |
CAN_T::IIDR: INTID Position
Definition at line 1509 of file NUC472_442.h.
| #define CAN_STATUS_BOFF_Msk (1ul << CAN_STATUS_BOFF_Pos) |
CAN_T::STATUS: BOFF Mask
Definition at line 1471 of file NUC472_442.h.
| #define CAN_STATUS_BOFF_Pos 7 |
CAN_T::STATUS: BOFF Position
Definition at line 1470 of file NUC472_442.h.
| #define CAN_STATUS_EPASS_Msk (1ul << CAN_STATUS_EPASS_Pos) |
CAN_T::STATUS: EPASS Mask
Definition at line 1477 of file NUC472_442.h.
| #define CAN_STATUS_EPASS_Pos 5 |
CAN_T::STATUS: EPASS Position
Definition at line 1476 of file NUC472_442.h.
| #define CAN_STATUS_EWARN_Msk (1ul << CAN_STATUS_EWARN_Pos) |
CAN_T::STATUS: EWARN Mask
Definition at line 1474 of file NUC472_442.h.
| #define CAN_STATUS_EWARN_Pos 6 |
CAN_T::STATUS: EWARN Position
Definition at line 1473 of file NUC472_442.h.
| #define CAN_STATUS_LEC_Msk (0x7ul << CAN_STATUS_LEC_Pos) |
CAN_T::STATUS: LEC Mask
Definition at line 1486 of file NUC472_442.h.
| #define CAN_STATUS_LEC_Pos 0 |
CAN_T::STATUS: LEC Position
Definition at line 1485 of file NUC472_442.h.
| #define CAN_STATUS_RXOK_Msk (1ul << CAN_STATUS_RXOK_Pos) |
CAN_T::STATUS: RXOK Mask
Definition at line 1480 of file NUC472_442.h.
| #define CAN_STATUS_RXOK_Pos 4 |
CAN_T::STATUS: RXOK Position
Definition at line 1479 of file NUC472_442.h.
| #define CAN_STATUS_TXOK_Msk (1ul << CAN_STATUS_TXOK_Pos) |
CAN_T::STATUS: TXOK Mask
Definition at line 1483 of file NUC472_442.h.
| #define CAN_STATUS_TXOK_Pos 3 |
CAN_T::STATUS: TXOK Position
Definition at line 1482 of file NUC472_442.h.
| #define CAN_TEST_BASIC_Msk (1ul << CAN_TEST_BASIC_Pos) |
CAN_T::TEST: Basic Mask
Definition at line 1525 of file NUC472_442.h.
| #define CAN_TEST_BASIC_Pos 2 |
CAN_T::TEST: Basic Position
Definition at line 1524 of file NUC472_442.h.
| #define CAN_TEST_LBACK_Msk (1ul << CAN_TEST_LBACK_Pos) |
CAN_T::TEST: LBACK Mask
Definition at line 1519 of file NUC472_442.h.
| #define CAN_TEST_LBACK_Pos 4 |
CAN_T::TEST: LBACK Position
Definition at line 1518 of file NUC472_442.h.
| #define CAN_TEST_RX_Msk (1ul << CAN_TEST_RX_Pos) |
CAN_T::TEST: RX Mask
Definition at line 1513 of file NUC472_442.h.
| #define CAN_TEST_RX_Pos 7 |
CAN_T::TEST: RX Position
Definition at line 1512 of file NUC472_442.h.
| #define CAN_TEST_SILENT_Msk (1ul << CAN_TEST_SILENT_Pos) |
CAN_T::TEST: Silent Mask
Definition at line 1522 of file NUC472_442.h.
| #define CAN_TEST_SILENT_Pos 3 |
CAN_T::TEST: Silent Position
Definition at line 1521 of file NUC472_442.h.
| #define CAN_TEST_TX_Msk (0x3ul << CAN_TEST_TX_Pos) |
CAN_T::TEST: TX Mask
Definition at line 1516 of file NUC472_442.h.
| #define CAN_TEST_TX_Pos 5 |
CAN_T::TEST: TX Position
Definition at line 1515 of file NUC472_442.h.
| #define CAN_WUEN_WAKUP_EN_Msk (1ul << CAN_WUEN_WAKUP_EN_Pos) |
CAN_T::WU_EN: WAKUP_EN Mask
Definition at line 1666 of file NUC472_442.h.
| #define CAN_WUEN_WAKUP_EN_Pos 0 |
CAN_T::WU_EN: WAKUP_EN Position
Definition at line 1665 of file NUC472_442.h.
| #define CAN_WUSTATUS_WAKUP_STS_Msk (1ul << CAN_WUSTATUS_WAKUP_STS_Pos) |
CAN_T::WU_STATUS: WAKUP_STS Mask
Definition at line 1669 of file NUC472_442.h.
| #define CAN_WUSTATUS_WAKUP_STS_Pos 0 |
CAN_T::WU_STATUS: WAKUP_STS Position
Definition at line 1668 of file NUC472_442.h.
| #define CAP_CMPADDR_CMPADDR_Msk (0xfffffffful << CAP_CMPADDR_CMPADDR_Pos) |
CAP_T::CMPADDR: CMPADDR Mask
Definition at line 2358 of file NUC472_442.h.
| #define CAP_CMPADDR_CMPADDR_Pos (0) |
CAP_T::CMPADDR: CMPADDR Position
Definition at line 2357 of file NUC472_442.h.
| #define CAP_CTL_ADDRSW_Msk (0x1ul << CAP_CTL_ADDRSW_Pos) |
CAP_T::CTL: ADDRSW Mask
Definition at line 2184 of file NUC472_442.h.
| #define CAP_CTL_ADDRSW_Pos (3) |
CAP_T::CTL: ADDRSW Position
Definition at line 2183 of file NUC472_442.h.
| #define CAP_CTL_CAPEN_Msk (0x1ul << CAP_CTL_CAPEN_Pos) |
CAP_T::CTL: CAPEN Mask
Definition at line 2181 of file NUC472_442.h.
| #define CAP_CTL_CAPEN_Pos (0) |
@addtogroup CAP_CONST CAP Bit Field Definition Constant Definitions for CAP Controller
CAP_T::CTL: CAPEN Position
Definition at line 2180 of file NUC472_442.h.
| #define CAP_CTL_PKTEN_Msk (0x1ul << CAP_CTL_PKTEN_Pos) |
CAP_T::CTL: PKTEN Mask
Definition at line 2190 of file NUC472_442.h.
| #define CAP_CTL_PKTEN_Pos (6) |
CAP_T::CTL: PKTEN Position
Definition at line 2189 of file NUC472_442.h.
| #define CAP_CTL_PLNEN_Msk (0x1ul << CAP_CTL_PLNEN_Pos) |
CAP_T::CTL: PLNEN Mask
Definition at line 2187 of file NUC472_442.h.
| #define CAP_CTL_PLNEN_Pos (5) |
CAP_T::CTL: PLNEN Position
Definition at line 2186 of file NUC472_442.h.
| #define CAP_CTL_SHUTTER_Msk (0x1ul << CAP_CTL_SHUTTER_Pos) |
CAP_T::CTL: SHUTTER Mask
Definition at line 2193 of file NUC472_442.h.
| #define CAP_CTL_SHUTTER_Pos (16) |
CAP_T::CTL: SHUTTER Position
Definition at line 2192 of file NUC472_442.h.
| #define CAP_CTL_UPDATE_Msk (0x1ul << CAP_CTL_UPDATE_Pos) |
CAP_T::CTL: UPDATE Mask
Definition at line 2196 of file NUC472_442.h.
| #define CAP_CTL_UPDATE_Pos (20) |
CAP_T::CTL: UPDATE Position
Definition at line 2195 of file NUC472_442.h.
| #define CAP_CTL_VPRST_Msk (0x1ul << CAP_CTL_VPRST_Pos) |
CAP_T::CTL: VPRST Mask
Definition at line 2199 of file NUC472_442.h.
| #define CAP_CTL_VPRST_Pos (24) |
CAP_T::CTL: VPRST Position
Definition at line 2198 of file NUC472_442.h.
| #define CAP_CURADDRP_CURADDR_Msk (0xfffffffful << CAP_CURADDRP_CURADDR_Pos) |
CAP_T::CURADDRP: CURADDR Mask
Definition at line 2385 of file NUC472_442.h.
| #define CAP_CURADDRP_CURADDR_Pos (0) |
CAP_T::CURADDRP: CURADDR Position
Definition at line 2384 of file NUC472_442.h.
| #define CAP_CURADDRU_CURADDR_Msk (0xfffffffful << CAP_CURADDRU_CURADDR_Pos) |
CAP_T::CURADDRU: CURADDR Mask
Definition at line 2391 of file NUC472_442.h.
| #define CAP_CURADDRU_CURADDR_Pos (0) |
CAP_T::CURADDRU: CURADDR Position
Definition at line 2390 of file NUC472_442.h.
| #define CAP_CURADDRY_CURADDR_Msk (0xfffffffful << CAP_CURADDRY_CURADDR_Pos) |
CAP_T::CURADDRY: CURADDR Mask
Definition at line 2388 of file NUC472_442.h.
| #define CAP_CURADDRY_CURADDR_Pos (0) |
CAP_T::CURADDRY: CURADDR Position
Definition at line 2387 of file NUC472_442.h.
| #define CAP_CURVADDR_CURADDR_Msk (0xfffffffful << CAP_CURVADDR_CURADDR_Pos) |
CAP_T::CURVADDR: CURADDR Mask
Definition at line 2394 of file NUC472_442.h.
| #define CAP_CURVADDR_CURADDR_Pos (0) |
CAP_T::CURVADDR: CURADDR Position
Definition at line 2393 of file NUC472_442.h.
| #define CAP_CWS_CWH_Msk (0x7fful << CAP_CWS_CWH_Pos) |
CAP_T::CWS: CIWH Mask
Definition at line 2304 of file NUC472_442.h.
| #define CAP_CWS_CWH_Pos (16) |
CAP_T::CWS: CIWH Position
Definition at line 2303 of file NUC472_442.h.
| #define CAP_CWS_CWW_Msk (0xffful << CAP_CWS_CWW_Pos) |
CAP_T::CWS: CWW Mask
Definition at line 2301 of file NUC472_442.h.
| #define CAP_CWS_CWW_Pos (0) |
CAP_T::CWS: CWW Position
Definition at line 2300 of file NUC472_442.h.
| #define CAP_CWSP_CWSADDRH_Msk (0xffful << CAP_CWSP_CWSADDRH_Pos) |
CAP_T::CWSP: CWSADDRH Mask
Definition at line 2295 of file NUC472_442.h.
| #define CAP_CWSP_CWSADDRH_Pos (0) |
CAP_T::CWSP: CWSADDRH Position
Definition at line 2294 of file NUC472_442.h.
| #define CAP_CWSP_CWSADDRV_Msk (0x7fful << CAP_CWSP_CWSADDRV_Pos) |
CAP_T::CWSP: CWSADDRV Mask
Definition at line 2298 of file NUC472_442.h.
| #define CAP_CWSP_CWSADDRV_Pos (16) |
CAP_T::CWSP: CWSADDRV Position
Definition at line 2297 of file NUC472_442.h.
| #define CAP_FIFOTH_OVF_Msk (0x1ul << CAP_FIFOTH_OVF_Pos) |
CAP_T::FIFOTH: OVF Mask
Definition at line 2355 of file NUC472_442.h.
| #define CAP_FIFOTH_OVF_Pos (31) |
CAP_T::FIFOTH: OVF Position
Definition at line 2354 of file NUC472_442.h.
| #define CAP_FIFOTH_PKTFTH_Msk (0x1ful << CAP_FIFOTH_PKTFTH_Pos) |
CAP_T::FIFOTH: PKTFTH Mask
Definition at line 2352 of file NUC472_442.h.
| #define CAP_FIFOTH_PKTFTH_Pos (24) |
CAP_T::FIFOTH: PKTFTH Position
Definition at line 2351 of file NUC472_442.h.
| #define CAP_FIFOTH_PLNUFTH_Msk (0xful << CAP_FIFOTH_PLNUFTH_Pos) |
CAP_T::FIFOTH: PLNUFTH Mask
Definition at line 2346 of file NUC472_442.h.
| #define CAP_FIFOTH_PLNUFTH_Pos (8) |
CAP_T::FIFOTH: PLNUFTH Position
Definition at line 2345 of file NUC472_442.h.
| #define CAP_FIFOTH_PLNVFTH_Msk (0xful << CAP_FIFOTH_PLNVFTH_Pos) |
CAP_T::FIFOTH: PLNVFTH Mask
Definition at line 2343 of file NUC472_442.h.
| #define CAP_FIFOTH_PLNVFTH_Pos (0) |
CAP_T::FIFOTH: PLNVFTH Position
Definition at line 2342 of file NUC472_442.h.
| #define CAP_FIFOTH_PLNYFTH_Msk (0x1ful << CAP_FIFOTH_PLNYFTH_Pos) |
CAP_T::FIFOTH: PLNYFTH Mask
Definition at line 2349 of file NUC472_442.h.
| #define CAP_FIFOTH_PLNYFTH_Pos (16) |
CAP_T::FIFOTH: PLNYFTH Position
Definition at line 2348 of file NUC472_442.h.
| #define CAP_FRCTL_FRM_Msk (0x3ful << CAP_FRCTL_FRM_Pos) |
CAP_T::FRCTL: FRM Mask
Definition at line 2331 of file NUC472_442.h.
| #define CAP_FRCTL_FRM_Pos (0) |
CAP_T::FRCTL: FRM Position
Definition at line 2330 of file NUC472_442.h.
| #define CAP_FRCTL_FRN_Msk (0x3ful << CAP_FRCTL_FRN_Pos) |
CAP_T::FRCTL: FRN Mask
Definition at line 2334 of file NUC472_442.h.
| #define CAP_FRCTL_FRN_Pos (8) |
CAP_T::FRCTL: FRN Position
Definition at line 2333 of file NUC472_442.h.
| #define CAP_INT_ADDRMIEN_Msk (0x1ul << CAP_INT_ADDRMIEN_Pos) |
CAP_T::INT: ADDRMIEN Mask
Definition at line 2253 of file NUC472_442.h.
| #define CAP_INT_ADDRMIEN_Pos (19) |
CAP_T::INT: ADDRMIEN Position
Definition at line 2252 of file NUC472_442.h.
| #define CAP_INT_ADDRMINTF_Msk (0x1ul << CAP_INT_ADDRMINTF_Pos) |
CAP_T::INT: ADDRMINTF Mask
Definition at line 2241 of file NUC472_442.h.
| #define CAP_INT_ADDRMINTF_Pos (3) |
CAP_T::INT: ADDRMINTF Position
Definition at line 2240 of file NUC472_442.h.
| #define CAP_INT_MDIEN_Msk (0x1ul << CAP_INT_MDIEN_Pos) |
CAP_T::INT: MDIEN Mask
Definition at line 2256 of file NUC472_442.h.
| #define CAP_INT_MDIEN_Pos (20) |
CAP_T::INT: MDIEN Position
Definition at line 2255 of file NUC472_442.h.
| #define CAP_INT_MDINTF_Msk (0x1ul << CAP_INT_MDINTF_Pos) |
CAP_T::INT: MDINTF Mask
Definition at line 2244 of file NUC472_442.h.
| #define CAP_INT_MDINTF_Pos (4) |
CAP_T::INT: MDINTF Position
Definition at line 2243 of file NUC472_442.h.
| #define CAP_INT_MEIEN_Msk (0x1ul << CAP_INT_MEIEN_Pos) |
CAP_T::INT: MEIEN Mask
Definition at line 2250 of file NUC472_442.h.
| #define CAP_INT_MEIEN_Pos (17) |
CAP_T::INT: MEIEN Position
Definition at line 2249 of file NUC472_442.h.
| #define CAP_INT_MEINTF_Msk (0x1ul << CAP_INT_MEINTF_Pos) |
CAP_T::INT: MEINTF Mask
Definition at line 2238 of file NUC472_442.h.
| #define CAP_INT_MEINTF_Pos (1) |
CAP_T::INT: MEINTF Position
Definition at line 2237 of file NUC472_442.h.
| #define CAP_INT_VIEN_Msk (0x1ul << CAP_INT_VIEN_Pos) |
CAP_T::INT: VIEN Mask
Definition at line 2247 of file NUC472_442.h.
| #define CAP_INT_VIEN_Pos (16) |
CAP_T::INT: VIEN Position
Definition at line 2246 of file NUC472_442.h.
| #define CAP_INT_VINTF_Msk (0x1ul << CAP_INT_VINTF_Pos) |
CAP_T::INT: VINTF Mask
Definition at line 2235 of file NUC472_442.h.
| #define CAP_INT_VINTF_Pos (0) |
CAP_T::INT: VINTF Position
Definition at line 2234 of file NUC472_442.h.
| #define CAP_MD_MDBS_Msk (0x1ul << CAP_MD_MDBS_Pos) |
CAP_T::MD: MDBS Mask
Definition at line 2271 of file NUC472_442.h.
| #define CAP_MD_MDBS_Pos (8) |
CAP_T::MD: MDBS Position
Definition at line 2270 of file NUC472_442.h.
| #define CAP_MD_MDDF_Msk (0x3ul << CAP_MD_MDDF_Pos) |
CAP_T::MD: MDDF Mask
Definition at line 2277 of file NUC472_442.h.
| #define CAP_MD_MDDF_Pos (10) |
CAP_T::MD: MDDF Position
Definition at line 2276 of file NUC472_442.h.
| #define CAP_MD_MDEN_Msk (0x1ul << CAP_MD_MDEN_Pos) |
CAP_T::MD: MDEN Mask
Definition at line 2268 of file NUC472_442.h.
| #define CAP_MD_MDEN_Pos (0) |
CAP_T::MD: MDEN Position
Definition at line 2267 of file NUC472_442.h.
| #define CAP_MD_MDSM_Msk (0x1ul << CAP_MD_MDSM_Pos) |
CAP_T::MD: MDSM Mask
Definition at line 2274 of file NUC472_442.h.
| #define CAP_MD_MDSM_Pos (9) |
CAP_T::MD: MDSM Position
Definition at line 2273 of file NUC472_442.h.
| #define CAP_MD_MDTHR_Msk (0x1ful << CAP_MD_MDTHR_Pos) |
CAP_T::MD: MDTHR Mask
Definition at line 2280 of file NUC472_442.h.
| #define CAP_MD_MDTHR_Pos (16) |
CAP_T::MD: MDTHR Position
Definition at line 2279 of file NUC472_442.h.
| #define CAP_MDADDR_MDADDR_Msk (0xfffffffful << CAP_MDADDR_MDADDR_Pos) |
CAP_T::MDADDR: MDADDR Mask
Definition at line 2283 of file NUC472_442.h.
| #define CAP_MDADDR_MDADDR_Pos (0) |
CAP_T::MDADDR: MDADDR Position
Definition at line 2282 of file NUC472_442.h.
| #define CAP_MDYADDR_MDYADDR_Msk (0xfffffffful << CAP_MDYADDR_MDYADDR_Pos) |
CAP_T::MDYADDR: MDYADDR Mask
Definition at line 2286 of file NUC472_442.h.
| #define CAP_MDYADDR_MDYADDR_Pos (0) |
CAP_T::MDYADDR: MDYADDR Position
Definition at line 2285 of file NUC472_442.h.
| #define CAP_PAR_COLORCTL_Msk (0x3ul << CAP_PAR_COLORCTL_Pos) |
CAP_T::PAR: COLORCTL Mask
Definition at line 2229 of file NUC472_442.h.
| #define CAP_PAR_COLORCTL_Pos (11) |
CAP_T::PAR: COLORCTL Position
Definition at line 2228 of file NUC472_442.h.
| #define CAP_PAR_FBB_Msk (0x1ul << CAP_PAR_FBB_Pos) |
CAP_T::PAR: FBB Mask
Definition at line 2232 of file NUC472_442.h.
| #define CAP_PAR_FBB_Pos (18) |
CAP_T::PAR: FBB Position
Definition at line 2231 of file NUC472_442.h.
| #define CAP_PAR_HSP_Msk (0x1ul << CAP_PAR_HSP_Pos) |
CAP_T::PAR: HSP Mask
Definition at line 2223 of file NUC472_442.h.
| #define CAP_PAR_HSP_Pos (9) |
CAP_T::PAR: HSP Position
Definition at line 2222 of file NUC472_442.h.
| #define CAP_PAR_INDATORD_Msk (0x3ul << CAP_PAR_INDATORD_Pos) |
CAP_T::PAR: INDATORD Mask
Definition at line 2208 of file NUC472_442.h.
| #define CAP_PAR_INDATORD_Pos (2) |
CAP_T::PAR: INDATORD Position
Definition at line 2207 of file NUC472_442.h.
| #define CAP_PAR_INFMT_Msk (0x1ul << CAP_PAR_INFMT_Pos) |
CAP_T::PAR: INFMT Mask
Definition at line 2202 of file NUC472_442.h.
| #define CAP_PAR_INFMT_Pos (0) |
CAP_T::PAR: INFMT Position
Definition at line 2201 of file NUC472_442.h.
| #define CAP_PAR_OUTFMT_Msk (0x3ul << CAP_PAR_OUTFMT_Pos) |
CAP_T::PAR: OUTFMT Mask
Definition at line 2211 of file NUC472_442.h.
| #define CAP_PAR_OUTFMT_Pos (4) |
CAP_T::PAR: OUTFMT Position
Definition at line 2210 of file NUC472_442.h.
| #define CAP_PAR_PCLKP_Msk (0x1ul << CAP_PAR_PCLKP_Pos) |
CAP_T::PAR: PCLKP Mask
Definition at line 2220 of file NUC472_442.h.
| #define CAP_PAR_PCLKP_Pos (8) |
CAP_T::PAR: PCLKP Position
Definition at line 2219 of file NUC472_442.h.
| #define CAP_PAR_PLNFMT_Msk (0x1ul << CAP_PAR_PLNFMT_Pos) |
CAP_T::PAR: PLNFMT Mask
Definition at line 2217 of file NUC472_442.h.
| #define CAP_PAR_PLNFMT_Pos (7) |
CAP_T::PAR: PLNFMT Position
Definition at line 2216 of file NUC472_442.h.
| #define CAP_PAR_RANGE_Msk (0x1ul << CAP_PAR_RANGE_Pos) |
CAP_T::PAR: RANGE Mask
Definition at line 2214 of file NUC472_442.h.
| #define CAP_PAR_RANGE_Pos (6) |
CAP_T::PAR: RANGE Position
Definition at line 2213 of file NUC472_442.h.
| #define CAP_PAR_SENTYPE_Msk (0x1ul << CAP_PAR_SENTYPE_Pos) |
CAP_T::PAR: SENTYPE Mask
Definition at line 2205 of file NUC472_442.h.
| #define CAP_PAR_SENTYPE_Pos (1) |
CAP_T::PAR: SENTYPE Position
Definition at line 2204 of file NUC472_442.h.
| #define CAP_PAR_VSP_Msk (0x1ul << CAP_PAR_VSP_Pos) |
CAP_T::PAR: VSP Mask
Definition at line 2226 of file NUC472_442.h.
| #define CAP_PAR_VSP_Pos (10) |
CAP_T::PAR: VSP Position
Definition at line 2225 of file NUC472_442.h.
| #define CAP_PKTBA0_BASEADDR_Msk (0xfffffffful << CAP_PKTBA0_BASEADDR_Pos) |
CAP_T::PKTBA0: BASEADDR Mask
Definition at line 2397 of file NUC472_442.h.
| #define CAP_PKTBA0_BASEADDR_Pos (0) |
CAP_T::PKTBA0: BASEADDR Position
Definition at line 2396 of file NUC472_442.h.
| #define CAP_PKTBA1_BASEADDR_Msk (0xfffffffful << CAP_PKTBA1_BASEADDR_Pos) |
CAP_T::PKTBA1: BASEADDR Mask
Definition at line 2400 of file NUC472_442.h.
| #define CAP_PKTBA1_BASEADDR_Pos (0) |
CAP_T::PKTBA1: BASEADDR Position
Definition at line 2399 of file NUC472_442.h.
| #define CAP_PKTSL_PKTSHML_Msk (0xfful << CAP_PKTSL_PKTSHML_Pos) |
CAP_T::PKTSL: PKTSHML Mask
Definition at line 2307 of file NUC472_442.h.
| #define CAP_PKTSL_PKTSHML_Pos (0) |
CAP_T::PKTSL: PKTSHML Position
Definition at line 2306 of file NUC472_442.h.
| #define CAP_PKTSL_PKTSHNL_Msk (0xfful << CAP_PKTSL_PKTSHNL_Pos) |
CAP_T::PKTSL: PKTSHNL Mask
Definition at line 2310 of file NUC472_442.h.
| #define CAP_PKTSL_PKTSHNL_Pos (8) |
CAP_T::PKTSL: PKTSHNL Position
Definition at line 2309 of file NUC472_442.h.
| #define CAP_PKTSL_PKTSVML_Msk (0xfful << CAP_PKTSL_PKTSVML_Pos) |
CAP_T::PKTSL: PKTSVML Mask
Definition at line 2313 of file NUC472_442.h.
| #define CAP_PKTSL_PKTSVML_Pos (16) |
CAP_T::PKTSL: PKTSVML Position
Definition at line 2312 of file NUC472_442.h.
| #define CAP_PKTSL_PKTSVNL_Msk (0xfful << CAP_PKTSL_PKTSVNL_Pos) |
CAP_T::PKTSL: PKTSVNL Mask
Definition at line 2316 of file NUC472_442.h.
| #define CAP_PKTSL_PKTSVNL_Pos (24) |
CAP_T::PKTSL: PKTSVNL Position
Definition at line 2315 of file NUC472_442.h.
| #define CAP_PKTSM_PKTSHMH_Msk (0xfful << CAP_PKTSM_PKTSHMH_Pos) |
CAP_T::PKTSM: PKTSHMH Mask
Definition at line 2361 of file NUC472_442.h.
| #define CAP_PKTSM_PKTSHMH_Pos (0) |
CAP_T::PKTSM: PKTSHMH Position
Definition at line 2360 of file NUC472_442.h.
| #define CAP_PKTSM_PKTSHNH_Msk (0xfful << CAP_PKTSM_PKTSHNH_Pos) |
CAP_T::PKTSM: PKTSHNH Mask
Definition at line 2364 of file NUC472_442.h.
| #define CAP_PKTSM_PKTSHNH_Pos (8) |
CAP_T::PKTSM: PKTSHNH Position
Definition at line 2363 of file NUC472_442.h.
| #define CAP_PKTSM_PKTSVMH_Msk (0xfful << CAP_PKTSM_PKTSVMH_Pos) |
CAP_T::PKTSM: PKTSVMH Mask
Definition at line 2367 of file NUC472_442.h.
| #define CAP_PKTSM_PKTSVMH_Pos (16) |
CAP_T::PKTSM: PKTSVMH Position
Definition at line 2366 of file NUC472_442.h.
| #define CAP_PKTSM_PKTSVNH_Msk (0xfful << CAP_PKTSM_PKTSVNH_Pos) |
CAP_T::PKTSM: PKTSVNH Mask
Definition at line 2370 of file NUC472_442.h.
| #define CAP_PKTSM_PKTSVNH_Pos (24) |
CAP_T::PKTSM: PKTSVNH Position
Definition at line 2369 of file NUC472_442.h.
| #define CAP_PLNSL_PLNSHML_Msk (0xfful << CAP_PLNSL_PLNSHML_Pos) |
CAP_T::PLNSL: PLNSHML Mask
Definition at line 2319 of file NUC472_442.h.
| #define CAP_PLNSL_PLNSHML_Pos (0) |
CAP_T::PLNSL: PLNSHML Position
Definition at line 2318 of file NUC472_442.h.
| #define CAP_PLNSL_PLNSHNL_Msk (0xfful << CAP_PLNSL_PLNSHNL_Pos) |
CAP_T::PLNSL: PLNSHNL Mask
Definition at line 2322 of file NUC472_442.h.
| #define CAP_PLNSL_PLNSHNL_Pos (8) |
CAP_T::PLNSL: PLNSHNL Position
Definition at line 2321 of file NUC472_442.h.
| #define CAP_PLNSL_PLNSVML_Msk (0xfful << CAP_PLNSL_PLNSVML_Pos) |
CAP_T::PLNSL: PLNSVML Mask
Definition at line 2325 of file NUC472_442.h.
| #define CAP_PLNSL_PLNSVML_Pos (16) |
CAP_T::PLNSL: PLNSVML Position
Definition at line 2324 of file NUC472_442.h.
| #define CAP_PLNSL_PLNSVNL_Msk (0xfful << CAP_PLNSL_PLNSVNL_Pos) |
CAP_T::PLNSL: PLNSVNL Mask
Definition at line 2328 of file NUC472_442.h.
| #define CAP_PLNSL_PLNSVNL_Pos (24) |
CAP_T::PLNSL: PLNSVNL Position
Definition at line 2327 of file NUC472_442.h.
| #define CAP_PLNSM_PLNSHMH_Msk (0xfful << CAP_PLNSM_PLNSHMH_Pos) |
CAP_T::PLNSM: PLNSHMH Mask
Definition at line 2373 of file NUC472_442.h.
| #define CAP_PLNSM_PLNSHMH_Pos (0) |
CAP_T::PLNSM: PLNSHMH Position
Definition at line 2372 of file NUC472_442.h.
| #define CAP_PLNSM_PLNSHNH_Msk (0xfful << CAP_PLNSM_PLNSHNH_Pos) |
CAP_T::PLNSM: PLNSHNH Mask
Definition at line 2376 of file NUC472_442.h.
| #define CAP_PLNSM_PLNSHNH_Pos (8) |
CAP_T::PLNSM: PLNSHNH Position
Definition at line 2375 of file NUC472_442.h.
| #define CAP_PLNSM_PLNSVMH_Msk (0xfful << CAP_PLNSM_PLNSVMH_Pos) |
CAP_T::PLNSM: PLNSVMH Mask
Definition at line 2379 of file NUC472_442.h.
| #define CAP_PLNSM_PLNSVMH_Pos (16) |
CAP_T::PLNSM: PLNSVMH Position
Definition at line 2378 of file NUC472_442.h.
| #define CAP_PLNSM_PLNSVNH_Msk (0xfful << CAP_PLNSM_PLNSVNH_Pos) |
CAP_T::PLNSM: PLNSVNH Mask
Definition at line 2382 of file NUC472_442.h.
| #define CAP_PLNSM_PLNSVNH_Pos (24) |
CAP_T::PLNSM: PLNSVNH Position
Definition at line 2381 of file NUC472_442.h.
| #define CAP_POSTERIZE_UCOMP_Msk (0xfful << CAP_POSTERIZE_UCOMP_Pos) |
CAP_T::POSTERIZE: UCOMP Mask
Definition at line 2262 of file NUC472_442.h.
| #define CAP_POSTERIZE_UCOMP_Pos (8) |
CAP_T::POSTERIZE: UCOMP Position
Definition at line 2261 of file NUC472_442.h.
| #define CAP_POSTERIZE_VCOMP_Msk (0xfful << CAP_POSTERIZE_VCOMP_Pos) |
CAP_T::POSTERIZE: VCOMP Mask
Definition at line 2259 of file NUC472_442.h.
| #define CAP_POSTERIZE_VCOMP_Pos (0) |
CAP_T::POSTERIZE: VCOMP Position
Definition at line 2258 of file NUC472_442.h.
| #define CAP_POSTERIZE_YCOMP_Msk (0xfful << CAP_POSTERIZE_YCOMP_Pos) |
CAP_T::POSTERIZE: YCOMP Mask
Definition at line 2265 of file NUC472_442.h.
| #define CAP_POSTERIZE_YCOMP_Pos (16) |
CAP_T::POSTERIZE: YCOMP Position
Definition at line 2264 of file NUC472_442.h.
| #define CAP_SEPIA_UCOMP_Msk (0xfful << CAP_SEPIA_UCOMP_Pos) |
CAP_T::SEPIA: UCOMP Mask
Definition at line 2292 of file NUC472_442.h.
| #define CAP_SEPIA_UCOMP_Pos (8) |
CAP_T::SEPIA: UCOMP Position
Definition at line 2291 of file NUC472_442.h.
| #define CAP_SEPIA_VCOMP_Msk (0xfful << CAP_SEPIA_VCOMP_Pos) |
CAP_T::SEPIA: VCOMP Mask
Definition at line 2289 of file NUC472_442.h.
| #define CAP_SEPIA_VCOMP_Pos (0) |
CAP_T::SEPIA: VCOMP Position
Definition at line 2288 of file NUC472_442.h.
| #define CAP_STRIDE_PKTSTRIDE_Msk (0x3ffful << CAP_STRIDE_PKTSTRIDE_Pos) |
CAP_T::STRIDE: PKTSTRIDE Mask
Definition at line 2337 of file NUC472_442.h.
| #define CAP_STRIDE_PKTSTRIDE_Pos (0) |
CAP_T::STRIDE: PKTSTRIDE Position
Definition at line 2336 of file NUC472_442.h.
| #define CAP_STRIDE_PLNSTRIDE_Msk (0x3ffful << CAP_STRIDE_PLNSTRIDE_Pos) |
CAP_T::STRIDE: PLNSTRIDE Mask
Definition at line 2340 of file NUC472_442.h.
| #define CAP_STRIDE_PLNSTRIDE_Pos (16) |
CAP_T::STRIDE: PLNSTRIDE Position
Definition at line 2339 of file NUC472_442.h.
| #define CAP_UBA_BASEADDR_Msk (0xfffffffful << CAP_UBA_BASEADDR_Pos) |
CAP_T::UBA: BASEADDR Mask
Definition at line 2406 of file NUC472_442.h.
| #define CAP_UBA_BASEADDR_Pos (0) |
CAP_T::UBA: BASEADDR Position
Definition at line 2405 of file NUC472_442.h.
| #define CAP_VBA_BASEADDR_Msk (0xfffffffful << CAP_VBA_BASEADDR_Pos) |
CAP_T::VBA: BASEADDR Mask
Definition at line 2409 of file NUC472_442.h.
| #define CAP_VBA_BASEADDR_Pos (0) |
CAP_T::VBA: BASEADDR Position
Definition at line 2408 of file NUC472_442.h.
| #define CAP_YBA_BASEADDR_Msk (0xfffffffful << CAP_YBA_BASEADDR_Pos) |
CAP_T::YBA: BASEADDR Mask
Definition at line 2403 of file NUC472_442.h.
| #define CAP_YBA_BASEADDR_Pos (0) |
CAP_T::YBA: BASEADDR Position
Definition at line 2402 of file NUC472_442.h.
| #define CLK_AHBCLK_CAPCKEN_Msk (0x1ul << CLK_AHBCLK_CAPCKEN_Pos) |
CLK_T::AHBCLK: CAPCKEN Mask
Definition at line 3598 of file NUC472_442.h.
| #define CLK_AHBCLK_CAPCKEN_Pos (8) |
CLK_T::AHBCLK: CAPCKEN Position
Definition at line 3597 of file NUC472_442.h.
| #define CLK_AHBCLK_CRCCKEN_Msk (0x1ul << CLK_AHBCLK_CRCCKEN_Pos) |
CLK_T::AHBCLK: CRCCKEN Mask
Definition at line 3595 of file NUC472_442.h.
| #define CLK_AHBCLK_CRCCKEN_Pos (7) |
CLK_T::AHBCLK: CRCCKEN Position
Definition at line 3594 of file NUC472_442.h.
| #define CLK_AHBCLK_CRPTCKEN_Msk (0x1ul << CLK_AHBCLK_CRPTCKEN_Pos) |
CLK_T::AHBCLK: CRPTCKEN Mask
Definition at line 3607 of file NUC472_442.h.
| #define CLK_AHBCLK_CRPTCKEN_Pos (12) |
CLK_T::AHBCLK: CRPTCKEN Position
Definition at line 3606 of file NUC472_442.h.
| #define CLK_AHBCLK_EBICKEN_Msk (0x1ul << CLK_AHBCLK_EBICKEN_Pos) |
CLK_T::AHBCLK: EBICKEN Mask
Definition at line 3583 of file NUC472_442.h.
| #define CLK_AHBCLK_EBICKEN_Pos (3) |
CLK_T::AHBCLK: EBICKEN Position
Definition at line 3582 of file NUC472_442.h.
| #define CLK_AHBCLK_EMACCKEN_Msk (0x1ul << CLK_AHBCLK_EMACCKEN_Pos) |
CLK_T::AHBCLK: EMACCKEN Mask
Definition at line 3589 of file NUC472_442.h.
| #define CLK_AHBCLK_EMACCKEN_Pos (5) |
CLK_T::AHBCLK: EMACCKEN Position
Definition at line 3588 of file NUC472_442.h.
| #define CLK_AHBCLK_ISPCKEN_Msk (0x1ul << CLK_AHBCLK_ISPCKEN_Pos) |
CLK_T::AHBCLK: ISPCKEN Mask
Definition at line 3580 of file NUC472_442.h.
| #define CLK_AHBCLK_ISPCKEN_Pos (2) |
CLK_T::AHBCLK: ISPCKEN Position
Definition at line 3579 of file NUC472_442.h.
| #define CLK_AHBCLK_PDMACKEN_Msk (0x1ul << CLK_AHBCLK_PDMACKEN_Pos) |
CLK_T::AHBCLK: PDMACKEN Mask
Definition at line 3577 of file NUC472_442.h.
| #define CLK_AHBCLK_PDMACKEN_Pos (1) |
CLK_T::AHBCLK: PDMACKEN Position
Definition at line 3576 of file NUC472_442.h.
| #define CLK_AHBCLK_SDHCKEN_Msk (0x1ul << CLK_AHBCLK_SDHCKEN_Pos) |
CLK_T::AHBCLK: SDHCKEN Mask
Definition at line 3592 of file NUC472_442.h.
| #define CLK_AHBCLK_SDHCKEN_Pos (6) |
CLK_T::AHBCLK: SDHCKEN Position
Definition at line 3591 of file NUC472_442.h.
| #define CLK_AHBCLK_SENCKEN_Msk (0x1ul << CLK_AHBCLK_SENCKEN_Pos) |
CLK_T::AHBCLK: SENCKEN Mask
Definition at line 3601 of file NUC472_442.h.
| #define CLK_AHBCLK_SENCKEN_Pos (9) |
CLK_T::AHBCLK: SENCKEN Position
Definition at line 3600 of file NUC472_442.h.
| #define CLK_AHBCLK_USBDCKEN_Msk (0x1ul << CLK_AHBCLK_USBDCKEN_Pos) |
CLK_T::AHBCLK: USBDCKEN Mask
Definition at line 3604 of file NUC472_442.h.
| #define CLK_AHBCLK_USBDCKEN_Pos (10) |
CLK_T::AHBCLK: USBDCKEN Position
Definition at line 3603 of file NUC472_442.h.
| #define CLK_AHBCLK_USBHCKEN_Msk (0x1ul << CLK_AHBCLK_USBHCKEN_Pos) |
CLK_T::AHBCLK: USBHCKEN Mask
Definition at line 3586 of file NUC472_442.h.
| #define CLK_AHBCLK_USBHCKEN_Pos (4) |
CLK_T::AHBCLK: USBHCKEN Position
Definition at line 3585 of file NUC472_442.h.
| #define CLK_APBCLK0_ACMPCKEN_Msk (0x1ul << CLK_APBCLK0_ACMPCKEN_Pos) |
CLK_T::APBCLK0: ACMPCKEN Mask
Definition at line 3631 of file NUC472_442.h.
| #define CLK_APBCLK0_ACMPCKEN_Pos (7) |
CLK_T::APBCLK0: ACMPCKEN Position
Definition at line 3630 of file NUC472_442.h.
| #define CLK_APBCLK0_ADCCKEN_Msk (0x1ul << CLK_APBCLK0_ADCCKEN_Pos) |
CLK_T::APBCLK0: ADCCKEN Mask
Definition at line 3685 of file NUC472_442.h.
| #define CLK_APBCLK0_ADCCKEN_Pos (28) |
CLK_T::APBCLK0: ADCCKEN Position
Definition at line 3684 of file NUC472_442.h.
| #define CLK_APBCLK0_CAN0CKEN_Msk (0x1ul << CLK_APBCLK0_CAN0CKEN_Pos) |
CLK_T::APBCLK0: CAN0CKEN Mask
Definition at line 3676 of file NUC472_442.h.
| #define CLK_APBCLK0_CAN0CKEN_Pos (24) |
CLK_T::APBCLK0: CAN0CKEN Position
Definition at line 3675 of file NUC472_442.h.
| #define CLK_APBCLK0_CAN1CKEN_Msk (0x1ul << CLK_APBCLK0_CAN1CKEN_Pos) |
CLK_T::APBCLK0: CAN1CKEN Mask
Definition at line 3679 of file NUC472_442.h.
| #define CLK_APBCLK0_CAN1CKEN_Pos (25) |
CLK_T::APBCLK0: CAN1CKEN Position
Definition at line 3678 of file NUC472_442.h.
| #define CLK_APBCLK0_CLKOCKEN_Msk (0x1ul << CLK_APBCLK0_CLKOCKEN_Pos) |
CLK_T::APBCLK0: CLKOCKEN Mask
Definition at line 3628 of file NUC472_442.h.
| #define CLK_APBCLK0_CLKOCKEN_Pos (6) |
CLK_T::APBCLK0: CLKOCKEN Position
Definition at line 3627 of file NUC472_442.h.
| #define CLK_APBCLK0_I2C0CKEN_Msk (0x1ul << CLK_APBCLK0_I2C0CKEN_Pos) |
CLK_T::APBCLK0: I2C0CKEN Mask
Definition at line 3634 of file NUC472_442.h.
| #define CLK_APBCLK0_I2C0CKEN_Pos (8) |
CLK_T::APBCLK0: I2C0CKEN Position
Definition at line 3633 of file NUC472_442.h.
| #define CLK_APBCLK0_I2C1CKEN_Msk (0x1ul << CLK_APBCLK0_I2C1CKEN_Pos) |
CLK_T::APBCLK0: I2C1CKEN Mask
Definition at line 3637 of file NUC472_442.h.
| #define CLK_APBCLK0_I2C1CKEN_Pos (9) |
CLK_T::APBCLK0: I2C1CKEN Position
Definition at line 3636 of file NUC472_442.h.
| #define CLK_APBCLK0_I2C2CKEN_Msk (0x1ul << CLK_APBCLK0_I2C2CKEN_Pos) |
CLK_T::APBCLK0: I2C2CKEN Mask
Definition at line 3640 of file NUC472_442.h.
| #define CLK_APBCLK0_I2C2CKEN_Pos (10) |
CLK_T::APBCLK0: I2C2CKEN Position
Definition at line 3639 of file NUC472_442.h.
| #define CLK_APBCLK0_I2C3CKEN_Msk (0x1ul << CLK_APBCLK0_I2C3CKEN_Pos) |
CLK_T::APBCLK0: I2C3CKEN Mask
Definition at line 3643 of file NUC472_442.h.
| #define CLK_APBCLK0_I2C3CKEN_Pos (11) |
CLK_T::APBCLK0: I2C3CKEN Position
Definition at line 3642 of file NUC472_442.h.
| #define CLK_APBCLK0_I2S0CKEN_Msk (0x1ul << CLK_APBCLK0_I2S0CKEN_Pos) |
CLK_T::APBCLK0: I2S0CKEN Mask
Definition at line 3688 of file NUC472_442.h.
| #define CLK_APBCLK0_I2S0CKEN_Pos (29) |
CLK_T::APBCLK0: I2S0CKEN Position
Definition at line 3687 of file NUC472_442.h.
| #define CLK_APBCLK0_I2S1CKEN_Msk (0x1ul << CLK_APBCLK0_I2S1CKEN_Pos) |
CLK_T::APBCLK0: I2S1CKEN Mask
Definition at line 3691 of file NUC472_442.h.
| #define CLK_APBCLK0_I2S1CKEN_Pos (30) |
CLK_T::APBCLK0: I2S1CKEN Position
Definition at line 3690 of file NUC472_442.h.
| #define CLK_APBCLK0_OTGCKEN_Msk (0x1ul << CLK_APBCLK0_OTGCKEN_Pos) |
CLK_T::APBCLK0: OTGCKEN Mask
Definition at line 3682 of file NUC472_442.h.
| #define CLK_APBCLK0_OTGCKEN_Pos (26) |
CLK_T::APBCLK0: OTGCKEN Position
Definition at line 3681 of file NUC472_442.h.
| #define CLK_APBCLK0_PS2CKEN_Msk (0x1ul << CLK_APBCLK0_PS2CKEN_Pos) |
CLK_T::APBCLK0: PS2CKEN Mask
Definition at line 3694 of file NUC472_442.h.
| #define CLK_APBCLK0_PS2CKEN_Pos (31) |
CLK_T::APBCLK0: PS2CKEN Position
Definition at line 3693 of file NUC472_442.h.
| #define CLK_APBCLK0_RTCCKEN_Msk (0x1ul << CLK_APBCLK0_RTCCKEN_Pos) |
CLK_T::APBCLK0: RTCCKEN Mask
Definition at line 3613 of file NUC472_442.h.
| #define CLK_APBCLK0_RTCCKEN_Pos (1) |
CLK_T::APBCLK0: RTCCKEN Position
Definition at line 3612 of file NUC472_442.h.
| #define CLK_APBCLK0_SPI0CKEN_Msk (0x1ul << CLK_APBCLK0_SPI0CKEN_Pos) |
CLK_T::APBCLK0: SPI0CKEN Mask
Definition at line 3646 of file NUC472_442.h.
| #define CLK_APBCLK0_SPI0CKEN_Pos (12) |
CLK_T::APBCLK0: SPI0CKEN Position
Definition at line 3645 of file NUC472_442.h.
| #define CLK_APBCLK0_SPI1CKEN_Msk (0x1ul << CLK_APBCLK0_SPI1CKEN_Pos) |
CLK_T::APBCLK0: SPI1CKEN Mask
Definition at line 3649 of file NUC472_442.h.
| #define CLK_APBCLK0_SPI1CKEN_Pos (13) |
CLK_T::APBCLK0: SPI1CKEN Position
Definition at line 3648 of file NUC472_442.h.
| #define CLK_APBCLK0_SPI2CKEN_Msk (0x1ul << CLK_APBCLK0_SPI2CKEN_Pos) |
CLK_T::APBCLK0: SPI2CKEN Mask
Definition at line 3652 of file NUC472_442.h.
| #define CLK_APBCLK0_SPI2CKEN_Pos (14) |
CLK_T::APBCLK0: SPI2CKEN Position
Definition at line 3651 of file NUC472_442.h.
| #define CLK_APBCLK0_SPI3CKEN_Msk (0x1ul << CLK_APBCLK0_SPI3CKEN_Pos) |
CLK_T::APBCLK0: SPI3CKEN Mask
Definition at line 3655 of file NUC472_442.h.
| #define CLK_APBCLK0_SPI3CKEN_Pos (15) |
CLK_T::APBCLK0: SPI3CKEN Position
Definition at line 3654 of file NUC472_442.h.
| #define CLK_APBCLK0_TMR0CKEN_Msk (0x1ul << CLK_APBCLK0_TMR0CKEN_Pos) |
CLK_T::APBCLK0: TMR0CKEN Mask
Definition at line 3616 of file NUC472_442.h.
| #define CLK_APBCLK0_TMR0CKEN_Pos (2) |
CLK_T::APBCLK0: TMR0CKEN Position
Definition at line 3615 of file NUC472_442.h.
| #define CLK_APBCLK0_TMR1CKEN_Msk (0x1ul << CLK_APBCLK0_TMR1CKEN_Pos) |
CLK_T::APBCLK0: TMR1CKEN Mask
Definition at line 3619 of file NUC472_442.h.
| #define CLK_APBCLK0_TMR1CKEN_Pos (3) |
CLK_T::APBCLK0: TMR1CKEN Position
Definition at line 3618 of file NUC472_442.h.
| #define CLK_APBCLK0_TMR2CKEN_Msk (0x1ul << CLK_APBCLK0_TMR2CKEN_Pos) |
CLK_T::APBCLK0: TMR2CKEN Mask
Definition at line 3622 of file NUC472_442.h.
| #define CLK_APBCLK0_TMR2CKEN_Pos (4) |
CLK_T::APBCLK0: TMR2CKEN Position
Definition at line 3621 of file NUC472_442.h.
| #define CLK_APBCLK0_TMR3CKEN_Msk (0x1ul << CLK_APBCLK0_TMR3CKEN_Pos) |
CLK_T::APBCLK0: TMR3CKEN Mask
Definition at line 3625 of file NUC472_442.h.
| #define CLK_APBCLK0_TMR3CKEN_Pos (5) |
CLK_T::APBCLK0: TMR3CKEN Position
Definition at line 3624 of file NUC472_442.h.
| #define CLK_APBCLK0_UART0CKEN_Msk (0x1ul << CLK_APBCLK0_UART0CKEN_Pos) |
CLK_T::APBCLK0: UART0CKEN Mask
Definition at line 3658 of file NUC472_442.h.
| #define CLK_APBCLK0_UART0CKEN_Pos (16) |
CLK_T::APBCLK0: UART0CKEN Position
Definition at line 3657 of file NUC472_442.h.
| #define CLK_APBCLK0_UART1CKEN_Msk (0x1ul << CLK_APBCLK0_UART1CKEN_Pos) |
CLK_T::APBCLK0: UART1CKEN Mask
Definition at line 3661 of file NUC472_442.h.
| #define CLK_APBCLK0_UART1CKEN_Pos (17) |
CLK_T::APBCLK0: UART1CKEN Position
Definition at line 3660 of file NUC472_442.h.
| #define CLK_APBCLK0_UART2CKEN_Msk (0x1ul << CLK_APBCLK0_UART2CKEN_Pos) |
CLK_T::APBCLK0: UART2CKEN Mask
Definition at line 3664 of file NUC472_442.h.
| #define CLK_APBCLK0_UART2CKEN_Pos (18) |
CLK_T::APBCLK0: UART2CKEN Position
Definition at line 3663 of file NUC472_442.h.
| #define CLK_APBCLK0_UART3CKEN_Msk (0x1ul << CLK_APBCLK0_UART3CKEN_Pos) |
CLK_T::APBCLK0: UART3CKEN Mask
Definition at line 3667 of file NUC472_442.h.
| #define CLK_APBCLK0_UART3CKEN_Pos (19) |
CLK_T::APBCLK0: UART3CKEN Position
Definition at line 3666 of file NUC472_442.h.
| #define CLK_APBCLK0_UART4CKEN_Msk (0x1ul << CLK_APBCLK0_UART4CKEN_Pos) |
CLK_T::APBCLK0: UART4CKEN Mask
Definition at line 3670 of file NUC472_442.h.
| #define CLK_APBCLK0_UART4CKEN_Pos (20) |
CLK_T::APBCLK0: UART4CKEN Position
Definition at line 3669 of file NUC472_442.h.
| #define CLK_APBCLK0_UART5CKEN_Msk (0x1ul << CLK_APBCLK0_UART5CKEN_Pos) |
CLK_T::APBCLK0: UART5CKEN Mask
Definition at line 3673 of file NUC472_442.h.
| #define CLK_APBCLK0_UART5CKEN_Pos (21) |
CLK_T::APBCLK0: UART5CKEN Position
Definition at line 3672 of file NUC472_442.h.
| #define CLK_APBCLK0_WDTCKEN_Msk (0x1ul << CLK_APBCLK0_WDTCKEN_Pos) |
CLK_T::APBCLK0: WDTCKEN Mask
Definition at line 3610 of file NUC472_442.h.
| #define CLK_APBCLK0_WDTCKEN_Pos (0) |
CLK_T::APBCLK0: WDTCKEN Position
Definition at line 3609 of file NUC472_442.h.
| #define CLK_APBCLK1_EADCCKEN_Msk (0x1ul << CLK_APBCLK1_EADCCKEN_Pos) |
CLK_T::APBCLK1: EADCCKEN Mask
Definition at line 3757 of file NUC472_442.h.
| #define CLK_APBCLK1_EADCCKEN_Pos (31) |
CLK_T::APBCLK1: EADCCKEN Position
Definition at line 3756 of file NUC472_442.h.
| #define CLK_APBCLK1_ECAP0CKEN_Msk (0x1ul << CLK_APBCLK1_ECAP0CKEN_Pos) |
CLK_T::APBCLK1: ECAP0CKEN Mask
Definition at line 3742 of file NUC472_442.h.
| #define CLK_APBCLK1_ECAP0CKEN_Pos (26) |
CLK_T::APBCLK1: ECAP0CKEN Position
Definition at line 3741 of file NUC472_442.h.
| #define CLK_APBCLK1_ECAP1CKEN_Msk (0x1ul << CLK_APBCLK1_ECAP1CKEN_Pos) |
CLK_T::APBCLK1: ECAP1CKEN Mask
Definition at line 3745 of file NUC472_442.h.
| #define CLK_APBCLK1_ECAP1CKEN_Pos (27) |
CLK_T::APBCLK1: ECAP1CKEN Position
Definition at line 3744 of file NUC472_442.h.
| #define CLK_APBCLK1_EPWM0CKEN_Msk (0x1ul << CLK_APBCLK1_EPWM0CKEN_Pos) |
CLK_T::APBCLK1: EPWM0CKEN Mask
Definition at line 3748 of file NUC472_442.h.
| #define CLK_APBCLK1_EPWM0CKEN_Pos (28) |
CLK_T::APBCLK1: EPWM0CKEN Position
Definition at line 3747 of file NUC472_442.h.
| #define CLK_APBCLK1_EPWM1CKEN_Msk (0x1ul << CLK_APBCLK1_EPWM1CKEN_Pos) |
CLK_T::APBCLK1: EPWM1CKEN Mask
Definition at line 3751 of file NUC472_442.h.
| #define CLK_APBCLK1_EPWM1CKEN_Pos (29) |
CLK_T::APBCLK1: EPWM1CKEN Position
Definition at line 3750 of file NUC472_442.h.
| #define CLK_APBCLK1_I2C4CKEN_Msk (0x1ul << CLK_APBCLK1_I2C4CKEN_Pos) |
CLK_T::APBCLK1: I2C4CKEN Mask
Definition at line 3715 of file NUC472_442.h.
| #define CLK_APBCLK1_I2C4CKEN_Pos (8) |
CLK_T::APBCLK1: I2C4CKEN Position
Definition at line 3714 of file NUC472_442.h.
| #define CLK_APBCLK1_OPACKEN_Msk (0x1ul << CLK_APBCLK1_OPACKEN_Pos) |
CLK_T::APBCLK1: OPACKEN Mask
Definition at line 3754 of file NUC472_442.h.
| #define CLK_APBCLK1_OPACKEN_Pos (30) |
CLK_T::APBCLK1: OPACKEN Position
Definition at line 3753 of file NUC472_442.h.
| #define CLK_APBCLK1_PWM0CH01CKEN_Msk (0x1ul << CLK_APBCLK1_PWM0CH01CKEN_Pos) |
CLK_T::APBCLK1: PWM0CH01CKEN Mask
Definition at line 3718 of file NUC472_442.h.
| #define CLK_APBCLK1_PWM0CH01CKEN_Pos (16) |
CLK_T::APBCLK1: PWM0CH01CKEN Position
Definition at line 3717 of file NUC472_442.h.
| #define CLK_APBCLK1_PWM0CH23CKEN_Msk (0x1ul << CLK_APBCLK1_PWM0CH23CKEN_Pos) |
CLK_T::APBCLK1: PWM0CH23CKEN Mask
Definition at line 3721 of file NUC472_442.h.
| #define CLK_APBCLK1_PWM0CH23CKEN_Pos (17) |
CLK_T::APBCLK1: PWM0CH23CKEN Position
Definition at line 3720 of file NUC472_442.h.
| #define CLK_APBCLK1_PWM0CH45CKEN_Msk (0x1ul << CLK_APBCLK1_PWM0CH45CKEN_Pos) |
CLK_T::APBCLK1: PWM0CH45CKEN Mask
Definition at line 3724 of file NUC472_442.h.
| #define CLK_APBCLK1_PWM0CH45CKEN_Pos (18) |
CLK_T::APBCLK1: PWM0CH45CKEN Position
Definition at line 3723 of file NUC472_442.h.
| #define CLK_APBCLK1_PWM1CH01CKEN_Msk (0x1ul << CLK_APBCLK1_PWM1CH01CKEN_Pos) |
CLK_T::APBCLK1: PWM1CH01CKEN Mask
Definition at line 3727 of file NUC472_442.h.
| #define CLK_APBCLK1_PWM1CH01CKEN_Pos (19) |
CLK_T::APBCLK1: PWM1CH01CKEN Position
Definition at line 3726 of file NUC472_442.h.
| #define CLK_APBCLK1_PWM1CH23CKEN_Msk (0x3ul << CLK_APBCLK1_PWM1CH23CKEN_Pos) |
CLK_T::APBCLK1: PWM1CH23CKEN Mask
Definition at line 3730 of file NUC472_442.h.
| #define CLK_APBCLK1_PWM1CH23CKEN_Pos (20) |
CLK_T::APBCLK1: PWM1CH23CKEN Position
Definition at line 3729 of file NUC472_442.h.
| #define CLK_APBCLK1_PWM1CH45CKEN_Msk (0x1ul << CLK_APBCLK1_PWM1CH45CKEN_Pos) |
CLK_T::APBCLK1: PWM1CH45CKEN Mask
Definition at line 3733 of file NUC472_442.h.
| #define CLK_APBCLK1_PWM1CH45CKEN_Pos (21) |
CLK_T::APBCLK1: PWM1CH45CKEN Position
Definition at line 3732 of file NUC472_442.h.
| #define CLK_APBCLK1_QEI0CKEN_Msk (0x1ul << CLK_APBCLK1_QEI0CKEN_Pos) |
CLK_T::APBCLK1: QEI0CKEN Mask
Definition at line 3736 of file NUC472_442.h.
| #define CLK_APBCLK1_QEI0CKEN_Pos (22) |
CLK_T::APBCLK1: QEI0CKEN Position
Definition at line 3735 of file NUC472_442.h.
| #define CLK_APBCLK1_QEI1CKEN_Msk (0x1ul << CLK_APBCLK1_QEI1CKEN_Pos) |
CLK_T::APBCLK1: QEI1CKEN Mask
Definition at line 3739 of file NUC472_442.h.
| #define CLK_APBCLK1_QEI1CKEN_Pos (23) |
CLK_T::APBCLK1: QEI1CKEN Position
Definition at line 3738 of file NUC472_442.h.
| #define CLK_APBCLK1_SC0CKEN_Msk (0x1ul << CLK_APBCLK1_SC0CKEN_Pos) |
CLK_T::APBCLK1: SC0CKEN Mask
Definition at line 3697 of file NUC472_442.h.
| #define CLK_APBCLK1_SC0CKEN_Pos (0) |
CLK_T::APBCLK1: SC0CKEN Position
Definition at line 3696 of file NUC472_442.h.
| #define CLK_APBCLK1_SC1CKEN_Msk (0x1ul << CLK_APBCLK1_SC1CKEN_Pos) |
CLK_T::APBCLK1: SC1CKEN Mask
Definition at line 3700 of file NUC472_442.h.
| #define CLK_APBCLK1_SC1CKEN_Pos (1) |
CLK_T::APBCLK1: SC1CKEN Position
Definition at line 3699 of file NUC472_442.h.
| #define CLK_APBCLK1_SC2CKEN_Msk (0x1ul << CLK_APBCLK1_SC2CKEN_Pos) |
CLK_T::APBCLK1: SC2CKEN Mask
Definition at line 3703 of file NUC472_442.h.
| #define CLK_APBCLK1_SC2CKEN_Pos (2) |
CLK_T::APBCLK1: SC2CKEN Position
Definition at line 3702 of file NUC472_442.h.
| #define CLK_APBCLK1_SC3CKEN_Msk (0x1ul << CLK_APBCLK1_SC3CKEN_Pos) |
CLK_T::APBCLK1: SC3CKEN Mask
Definition at line 3706 of file NUC472_442.h.
| #define CLK_APBCLK1_SC3CKEN_Pos (3) |
CLK_T::APBCLK1: SC3CKEN Position
Definition at line 3705 of file NUC472_442.h.
| #define CLK_APBCLK1_SC4CKEN_Msk (0x1ul << CLK_APBCLK1_SC4CKEN_Pos) |
CLK_T::APBCLK1: SC4CKEN Mask
Definition at line 3709 of file NUC472_442.h.
| #define CLK_APBCLK1_SC4CKEN_Pos (4) |
CLK_T::APBCLK1: SC4CKEN Position
Definition at line 3708 of file NUC472_442.h.
| #define CLK_APBCLK1_SC5CKEN_Msk (0x1ul << CLK_APBCLK1_SC5CKEN_Pos) |
CLK_T::APBCLK1: SC5CKEN Mask
Definition at line 3712 of file NUC472_442.h.
| #define CLK_APBCLK1_SC5CKEN_Pos (5) |
CLK_T::APBCLK1: SC5CKEN Position
Definition at line 3711 of file NUC472_442.h.
| #define CLK_CLKDCTL_IRCDEN_Msk (0x1ul << CLK_CLKDCTL_IRCDEN_Pos) |
CLK_T::CLKDCTL: IRCDEN Mask
Definition at line 3970 of file NUC472_442.h.
| #define CLK_CLKDCTL_IRCDEN_Pos (8) |
CLK_T::CLKDCTL: IRCDEN Position
Definition at line 3969 of file NUC472_442.h.
| #define CLK_CLKDCTL_IRCFIEN_Msk (0x1ul << CLK_CLKDCTL_IRCFIEN_Pos) |
CLK_T::CLKDCTL: IRCFIEN Mask
Definition at line 3973 of file NUC472_442.h.
| #define CLK_CLKDCTL_IRCFIEN_Pos (9) |
CLK_T::CLKDCTL: IRCFIEN Position
Definition at line 3972 of file NUC472_442.h.
| #define CLK_CLKDCTL_IRCFIF_Msk (0x1ul << CLK_CLKDCTL_IRCFIF_Pos) |
CLK_T::CLKDCTL: IRCFIF Mask
Definition at line 3976 of file NUC472_442.h.
| #define CLK_CLKDCTL_IRCFIF_Pos (10) |
CLK_T::CLKDCTL: IRCFIF Position
Definition at line 3975 of file NUC472_442.h.
| #define CLK_CLKDCTL_SYSFDEN_Msk (0x1ul << CLK_CLKDCTL_SYSFDEN_Pos) |
CLK_T::CLKDCTL: SYSFDEN Mask
Definition at line 3961 of file NUC472_442.h.
| #define CLK_CLKDCTL_SYSFDEN_Pos (0) |
CLK_T::CLKDCTL: SYSFDEN Position
Definition at line 3960 of file NUC472_442.h.
| #define CLK_CLKDCTL_SYSFIEN_Msk (0x1ul << CLK_CLKDCTL_SYSFIEN_Pos) |
CLK_T::CLKDCTL: SYSFIEN Mask
Definition at line 3964 of file NUC472_442.h.
| #define CLK_CLKDCTL_SYSFIEN_Pos (1) |
CLK_T::CLKDCTL: SYSFIEN Position
Definition at line 3963 of file NUC472_442.h.
| #define CLK_CLKDCTL_SYSFIF_Msk (0x1ul << CLK_CLKDCTL_SYSFIF_Pos) |
CLK_T::CLKDCTL: SYSFIF Mask
Definition at line 3967 of file NUC472_442.h.
| #define CLK_CLKDCTL_SYSFIF_Pos (2) |
CLK_T::CLKDCTL: SYSFIF Position
Definition at line 3966 of file NUC472_442.h.
| #define CLK_CLKDIV0_ADCDIV_Msk (0xfful << CLK_CLKDIV0_ADCDIV_Pos) |
CLK_T::CLKDIV0: ADCDIV Mask
Definition at line 3868 of file NUC472_442.h.
| #define CLK_CLKDIV0_ADCDIV_Pos (16) |
CLK_T::CLKDIV0: ADCDIV Position
Definition at line 3867 of file NUC472_442.h.
| #define CLK_CLKDIV0_HCLKDIV_Msk (0xful << CLK_CLKDIV0_HCLKDIV_Pos) |
CLK_T::CLKDIV0: HCLKDIV Mask
Definition at line 3859 of file NUC472_442.h.
| #define CLK_CLKDIV0_HCLKDIV_Pos (0) |
CLK_T::CLKDIV0: HCLKDIV Position
Definition at line 3858 of file NUC472_442.h.
| #define CLK_CLKDIV0_SDHDIV_Msk (0xfful << CLK_CLKDIV0_SDHDIV_Pos) |
CLK_T::CLKDIV0: SDHDIV Mask
Definition at line 3871 of file NUC472_442.h.
| #define CLK_CLKDIV0_SDHDIV_Pos (24) |
CLK_T::CLKDIV0: SDHDIV Position
Definition at line 3870 of file NUC472_442.h.
| #define CLK_CLKDIV0_UARTDIV_Msk (0xful << CLK_CLKDIV0_UARTDIV_Pos) |
CLK_T::CLKDIV0: UARTDIV Mask
Definition at line 3865 of file NUC472_442.h.
| #define CLK_CLKDIV0_UARTDIV_Pos (8) |
CLK_T::CLKDIV0: UARTDIV Position
Definition at line 3864 of file NUC472_442.h.
| #define CLK_CLKDIV0_USBHDIV_Msk (0xful << CLK_CLKDIV0_USBHDIV_Pos) |
CLK_T::CLKDIV0: USBHDIV Mask
Definition at line 3862 of file NUC472_442.h.
| #define CLK_CLKDIV0_USBHDIV_Pos (4) |
CLK_T::CLKDIV0: USBHDIV Position
Definition at line 3861 of file NUC472_442.h.
| #define CLK_CLKDIV1_SC0DIV_Msk (0xfful << CLK_CLKDIV1_SC0DIV_Pos) |
CLK_T::CLKDIV1: SC0DIV Mask
Definition at line 3874 of file NUC472_442.h.
| #define CLK_CLKDIV1_SC0DIV_Pos (0) |
CLK_T::CLKDIV1: SC0DIV Position
Definition at line 3873 of file NUC472_442.h.
| #define CLK_CLKDIV1_SC1DIV_Msk (0xfful << CLK_CLKDIV1_SC1DIV_Pos) |
CLK_T::CLKDIV1: SC1DIV Mask
Definition at line 3877 of file NUC472_442.h.
| #define CLK_CLKDIV1_SC1DIV_Pos (8) |
CLK_T::CLKDIV1: SC1DIV Position
Definition at line 3876 of file NUC472_442.h.
| #define CLK_CLKDIV1_SC2DIV_Msk (0xfful << CLK_CLKDIV1_SC2DIV_Pos) |
CLK_T::CLKDIV1: SC2DIV Mask
Definition at line 3880 of file NUC472_442.h.
| #define CLK_CLKDIV1_SC2DIV_Pos (16) |
CLK_T::CLKDIV1: SC2DIV Position
Definition at line 3879 of file NUC472_442.h.
| #define CLK_CLKDIV1_SC3DIV_Msk (0xfful << CLK_CLKDIV1_SC3DIV_Pos) |
CLK_T::CLKDIV1: SC3DIV Mask
Definition at line 3883 of file NUC472_442.h.
| #define CLK_CLKDIV1_SC3DIV_Pos (24) |
CLK_T::CLKDIV1: SC3DIV Position
Definition at line 3882 of file NUC472_442.h.
| #define CLK_CLKDIV2_SC4DIV_Msk (0xfful << CLK_CLKDIV2_SC4DIV_Pos) |
CLK_T::CLKDIV2: SC4DIV Mask
Definition at line 3886 of file NUC472_442.h.
| #define CLK_CLKDIV2_SC4DIV_Pos (0) |
CLK_T::CLKDIV2: SC4DIV Position
Definition at line 3885 of file NUC472_442.h.
| #define CLK_CLKDIV2_SC5DIV_Msk (0xfful << CLK_CLKDIV2_SC5DIV_Pos) |
CLK_T::CLKDIV2: SC5DIV Mask
Definition at line 3889 of file NUC472_442.h.
| #define CLK_CLKDIV2_SC5DIV_Pos (8) |
CLK_T::CLKDIV2: SC5DIV Position
Definition at line 3888 of file NUC472_442.h.
| #define CLK_CLKDIV3_CAPDIV_Msk (0xfful << CLK_CLKDIV3_CAPDIV_Pos) |
CLK_T::CLKDIV3: CAPDIV Mask
Definition at line 3892 of file NUC472_442.h.
| #define CLK_CLKDIV3_CAPDIV_Pos (0) |
CLK_T::CLKDIV3: CAPDIV Position
Definition at line 3891 of file NUC472_442.h.
| #define CLK_CLKDIV3_EMACDIV_Msk (0xfful << CLK_CLKDIV3_EMACDIV_Pos) |
CLK_T::CLKDIV3: EMACDIV Mask
Definition at line 3898 of file NUC472_442.h.
| #define CLK_CLKDIV3_EMACDIV_Pos (16) |
CLK_T::CLKDIV3: EMACDIV Position
Definition at line 3897 of file NUC472_442.h.
| #define CLK_CLKDIV3_VSENSEDIV_Msk (0xfful << CLK_CLKDIV3_VSENSEDIV_Pos) |
CLK_T::CLKDIV3: VSENSEDIV Mask
Definition at line 3895 of file NUC472_442.h.
| #define CLK_CLKDIV3_VSENSEDIV_Pos (8) |
CLK_T::CLKDIV3: VSENSEDIV Position
Definition at line 3894 of file NUC472_442.h.
| #define CLK_CLKOCTL_CLKOEN_Msk (0x1ul << CLK_CLKOCTL_CLKOEN_Pos) |
CLK_T::CLKOCTL: CLKOEN Mask
Definition at line 3955 of file NUC472_442.h.
| #define CLK_CLKOCTL_CLKOEN_Pos (4) |
CLK_T::CLKOCTL: CLKOEN Position
Definition at line 3954 of file NUC472_442.h.
| #define CLK_CLKOCTL_DIV1EN_Msk (0x1ul << CLK_CLKOCTL_DIV1EN_Pos) |
CLK_T::CLKOCTL: DIV1EN Mask
Definition at line 3958 of file NUC472_442.h.
| #define CLK_CLKOCTL_DIV1EN_Pos (5) |
CLK_T::CLKOCTL: DIV1EN Position
Definition at line 3957 of file NUC472_442.h.
| #define CLK_CLKOCTL_FSEL_Msk (0xful << CLK_CLKOCTL_FSEL_Pos) |
CLK_T::CLKOCTL: FSEL Mask
Definition at line 3952 of file NUC472_442.h.
| #define CLK_CLKOCTL_FSEL_Pos (0) |
CLK_T::CLKOCTL: FSEL Position
Definition at line 3951 of file NUC472_442.h.
| #define CLK_CLKSEL0_CAPSEL_Msk (0x3ul << CLK_CLKSEL0_CAPSEL_Pos) |
CLK_T::CLKSEL0: CAPSEL Mask
Definition at line 3772 of file NUC472_442.h.
| #define CLK_CLKSEL0_CAPSEL_Pos (16) |
CLK_T::CLKSEL0: CAPSEL Position
Definition at line 3771 of file NUC472_442.h.
| #define CLK_CLKSEL0_HCLKSEL_Msk (0x7ul << CLK_CLKSEL0_HCLKSEL_Pos) |
CLK_T::CLKSEL0: HCLKSEL Mask
Definition at line 3760 of file NUC472_442.h.
| #define CLK_CLKSEL0_HCLKSEL_Pos (0) |
CLK_T::CLKSEL0: HCLKSEL Position
Definition at line 3759 of file NUC472_442.h.
| #define CLK_CLKSEL0_PCLKSEL_Msk (0x1ul << CLK_CLKSEL0_PCLKSEL_Pos) |
CLK_T::CLKSEL0: PCLKSEL Mask
Definition at line 3766 of file NUC472_442.h.
| #define CLK_CLKSEL0_PCLKSEL_Pos (6) |
CLK_T::CLKSEL0: PCLKSEL Position
Definition at line 3765 of file NUC472_442.h.
| #define CLK_CLKSEL0_SDHSEL_Msk (0x3ul << CLK_CLKSEL0_SDHSEL_Pos) |
CLK_T::CLKSEL0: SDHSEL Mask
Definition at line 3775 of file NUC472_442.h.
| #define CLK_CLKSEL0_SDHSEL_Pos (20) |
CLK_T::CLKSEL0: SDHSEL Position
Definition at line 3774 of file NUC472_442.h.
| #define CLK_CLKSEL0_STCLKSEL_Msk (0x7ul << CLK_CLKSEL0_STCLKSEL_Pos) |
CLK_T::CLKSEL0: STCLKSEL Mask
Definition at line 3763 of file NUC472_442.h.
| #define CLK_CLKSEL0_STCLKSEL_Pos (3) |
CLK_T::CLKSEL0: STCLKSEL Position
Definition at line 3762 of file NUC472_442.h.
| #define CLK_CLKSEL0_USBHSEL_Msk (0x1ul << CLK_CLKSEL0_USBHSEL_Pos) |
CLK_T::CLKSEL0: USBHSEL Mask
Definition at line 3769 of file NUC472_442.h.
| #define CLK_CLKSEL0_USBHSEL_Pos (8) |
CLK_T::CLKSEL0: USBHSEL Position
Definition at line 3768 of file NUC472_442.h.
| #define CLK_CLKSEL1_ADCSEL_Msk (0x3ul << CLK_CLKSEL1_ADCSEL_Pos) |
CLK_T::CLKSEL1: ADCSEL Mask
Definition at line 3781 of file NUC472_442.h.
| #define CLK_CLKSEL1_ADCSEL_Pos (2) |
CLK_T::CLKSEL1: ADCSEL Position
Definition at line 3780 of file NUC472_442.h.
| #define CLK_CLKSEL1_CLKOSEL_Msk (0x3ul << CLK_CLKSEL1_CLKOSEL_Pos) |
CLK_T::CLKSEL1: CLKOSEL Mask
Definition at line 3811 of file NUC472_442.h.
| #define CLK_CLKSEL1_CLKOSEL_Pos (28) |
CLK_T::CLKSEL1: CLKOSEL Position
Definition at line 3810 of file NUC472_442.h.
| #define CLK_CLKSEL1_SPI0SEL_Msk (0x1ul << CLK_CLKSEL1_SPI0SEL_Pos) |
CLK_T::CLKSEL1: SPI0SEL Mask
Definition at line 3784 of file NUC472_442.h.
| #define CLK_CLKSEL1_SPI0SEL_Pos (4) |
CLK_T::CLKSEL1: SPI0SEL Position
Definition at line 3783 of file NUC472_442.h.
| #define CLK_CLKSEL1_SPI1SEL_Msk (0x1ul << CLK_CLKSEL1_SPI1SEL_Pos) |
CLK_T::CLKSEL1: SPI1SEL Mask
Definition at line 3787 of file NUC472_442.h.
| #define CLK_CLKSEL1_SPI1SEL_Pos (5) |
CLK_T::CLKSEL1: SPI1SEL Position
Definition at line 3786 of file NUC472_442.h.
| #define CLK_CLKSEL1_SPI2SEL_Msk (0x1ul << CLK_CLKSEL1_SPI2SEL_Pos) |
CLK_T::CLKSEL1: SPI2SEL Mask
Definition at line 3790 of file NUC472_442.h.
| #define CLK_CLKSEL1_SPI2SEL_Pos (6) |
CLK_T::CLKSEL1: SPI2SEL Position
Definition at line 3789 of file NUC472_442.h.
| #define CLK_CLKSEL1_SPI3SEL_Msk (0x1ul << CLK_CLKSEL1_SPI3SEL_Pos) |
CLK_T::CLKSEL1: SPI3SEL Mask
Definition at line 3793 of file NUC472_442.h.
| #define CLK_CLKSEL1_SPI3SEL_Pos (7) |
CLK_T::CLKSEL1: SPI3SEL Position
Definition at line 3792 of file NUC472_442.h.
| #define CLK_CLKSEL1_TMR0SEL_Msk (0x7ul << CLK_CLKSEL1_TMR0SEL_Pos) |
CLK_T::CLKSEL1: TMR0SEL Mask
Definition at line 3796 of file NUC472_442.h.
| #define CLK_CLKSEL1_TMR0SEL_Pos (8) |
CLK_T::CLKSEL1: TMR0SEL Position
Definition at line 3795 of file NUC472_442.h.
| #define CLK_CLKSEL1_TMR1SEL_Msk (0x7ul << CLK_CLKSEL1_TMR1SEL_Pos) |
CLK_T::CLKSEL1: TMR1SEL Mask
Definition at line 3799 of file NUC472_442.h.
| #define CLK_CLKSEL1_TMR1SEL_Pos (12) |
CLK_T::CLKSEL1: TMR1SEL Position
Definition at line 3798 of file NUC472_442.h.
| #define CLK_CLKSEL1_TMR2SEL_Msk (0x7ul << CLK_CLKSEL1_TMR2SEL_Pos) |
CLK_T::CLKSEL1: TMR2SEL Mask
Definition at line 3802 of file NUC472_442.h.
| #define CLK_CLKSEL1_TMR2SEL_Pos (16) |
CLK_T::CLKSEL1: TMR2SEL Position
Definition at line 3801 of file NUC472_442.h.
| #define CLK_CLKSEL1_TMR3SEL_Msk (0x7ul << CLK_CLKSEL1_TMR3SEL_Pos) |
CLK_T::CLKSEL1: TMR3SEL Mask
Definition at line 3805 of file NUC472_442.h.
| #define CLK_CLKSEL1_TMR3SEL_Pos (20) |
CLK_T::CLKSEL1: TMR3SEL Position
Definition at line 3804 of file NUC472_442.h.
| #define CLK_CLKSEL1_UARTSEL_Msk (0x3ul << CLK_CLKSEL1_UARTSEL_Pos) |
CLK_T::CLKSEL1: UARTSEL Mask
Definition at line 3808 of file NUC472_442.h.
| #define CLK_CLKSEL1_UARTSEL_Pos (24) |
CLK_T::CLKSEL1: UARTSEL Position
Definition at line 3807 of file NUC472_442.h.
| #define CLK_CLKSEL1_WDTSEL_Msk (0x3ul << CLK_CLKSEL1_WDTSEL_Pos) |
CLK_T::CLKSEL1: WDTSEL Mask
Definition at line 3778 of file NUC472_442.h.
| #define CLK_CLKSEL1_WDTSEL_Pos (0) |
CLK_T::CLKSEL1: WDTSEL Position
Definition at line 3777 of file NUC472_442.h.
| #define CLK_CLKSEL1_WWDTSEL_Msk (0x3ul << CLK_CLKSEL1_WWDTSEL_Pos) |
CLK_T::CLKSEL1: WWDTSEL Mask
Definition at line 3814 of file NUC472_442.h.
| #define CLK_CLKSEL1_WWDTSEL_Pos (30) |
CLK_T::CLKSEL1: WWDTSEL Position
Definition at line 3813 of file NUC472_442.h.
| #define CLK_CLKSEL2_PWM0CH01SEL_Msk (0x7ul << CLK_CLKSEL2_PWM0CH01SEL_Pos) |
CLK_T::CLKSEL2: PWM0CH01SEL Mask
Definition at line 3817 of file NUC472_442.h.
| #define CLK_CLKSEL2_PWM0CH01SEL_Pos (0) |
CLK_T::CLKSEL2: PWM0CH01SEL Position
Definition at line 3816 of file NUC472_442.h.
| #define CLK_CLKSEL2_PWM0CH23SEL_Msk (0x7ul << CLK_CLKSEL2_PWM0CH23SEL_Pos) |
CLK_T::CLKSEL2: PWM0CH23SEL Mask
Definition at line 3820 of file NUC472_442.h.
| #define CLK_CLKSEL2_PWM0CH23SEL_Pos (4) |
CLK_T::CLKSEL2: PWM0CH23SEL Position
Definition at line 3819 of file NUC472_442.h.
| #define CLK_CLKSEL2_PWM0CH45SEL_Msk (0x7ul << CLK_CLKSEL2_PWM0CH45SEL_Pos) |
CLK_T::CLKSEL2: PWM0CH45SEL Mask
Definition at line 3823 of file NUC472_442.h.
| #define CLK_CLKSEL2_PWM0CH45SEL_Pos (8) |
CLK_T::CLKSEL2: PWM0CH45SEL Position
Definition at line 3822 of file NUC472_442.h.
| #define CLK_CLKSEL2_PWM1CH01SEL_Msk (0x7ul << CLK_CLKSEL2_PWM1CH01SEL_Pos) |
CLK_T::CLKSEL2: PWM1CH01SEL Mask
Definition at line 3826 of file NUC472_442.h.
| #define CLK_CLKSEL2_PWM1CH01SEL_Pos (12) |
CLK_T::CLKSEL2: PWM1CH01SEL Position
Definition at line 3825 of file NUC472_442.h.
| #define CLK_CLKSEL2_PWM1CH23SEL_Msk (0x7ul << CLK_CLKSEL2_PWM1CH23SEL_Pos) |
CLK_T::CLKSEL2: PWM1CH23SEL Mask
Definition at line 3829 of file NUC472_442.h.
| #define CLK_CLKSEL2_PWM1CH23SEL_Pos (16) |
CLK_T::CLKSEL2: PWM1CH23SEL Position
Definition at line 3828 of file NUC472_442.h.
| #define CLK_CLKSEL2_PWM1CH45SEL_Msk (0x7ul << CLK_CLKSEL2_PWM1CH45SEL_Pos) |
CLK_T::CLKSEL2: PWM1CH45SEL Mask
Definition at line 3832 of file NUC472_442.h.
| #define CLK_CLKSEL2_PWM1CH45SEL_Pos (20) |
CLK_T::CLKSEL2: PWM1CH45SEL Position
Definition at line 3831 of file NUC472_442.h.
| #define CLK_CLKSEL3_I2S0SEL_Msk (0x3ul << CLK_CLKSEL3_I2S0SEL_Pos) |
CLK_T::CLKSEL3: I2S0SEL Mask
Definition at line 3853 of file NUC472_442.h.
| #define CLK_CLKSEL3_I2S0SEL_Pos (16) |
CLK_T::CLKSEL3: I2S0SEL Position
Definition at line 3852 of file NUC472_442.h.
| #define CLK_CLKSEL3_I2S1SEL_Msk (0x3ul << CLK_CLKSEL3_I2S1SEL_Pos) |
CLK_T::CLKSEL3: I2S1SEL Mask
Definition at line 3856 of file NUC472_442.h.
| #define CLK_CLKSEL3_I2S1SEL_Pos (18) |
CLK_T::CLKSEL3: I2S1SEL Position
Definition at line 3855 of file NUC472_442.h.
| #define CLK_CLKSEL3_SC0SEL_Msk (0x3ul << CLK_CLKSEL3_SC0SEL_Pos) |
CLK_T::CLKSEL3: SC0SEL Mask
Definition at line 3835 of file NUC472_442.h.
| #define CLK_CLKSEL3_SC0SEL_Pos (0) |
CLK_T::CLKSEL3: SC0SEL Position
Definition at line 3834 of file NUC472_442.h.
| #define CLK_CLKSEL3_SC1SEL_Msk (0x3ul << CLK_CLKSEL3_SC1SEL_Pos) |
CLK_T::CLKSEL3: SC1SEL Mask
Definition at line 3838 of file NUC472_442.h.
| #define CLK_CLKSEL3_SC1SEL_Pos (2) |
CLK_T::CLKSEL3: SC1SEL Position
Definition at line 3837 of file NUC472_442.h.
| #define CLK_CLKSEL3_SC2SEL_Msk (0x3ul << CLK_CLKSEL3_SC2SEL_Pos) |
CLK_T::CLKSEL3: SC2SEL Mask
Definition at line 3841 of file NUC472_442.h.
| #define CLK_CLKSEL3_SC2SEL_Pos (4) |
CLK_T::CLKSEL3: SC2SEL Position
Definition at line 3840 of file NUC472_442.h.
| #define CLK_CLKSEL3_SC3SEL_Msk (0x3ul << CLK_CLKSEL3_SC3SEL_Pos) |
CLK_T::CLKSEL3: SC3SEL Mask
Definition at line 3844 of file NUC472_442.h.
| #define CLK_CLKSEL3_SC3SEL_Pos (6) |
CLK_T::CLKSEL3: SC3SEL Position
Definition at line 3843 of file NUC472_442.h.
| #define CLK_CLKSEL3_SC4SEL_Msk (0x3ul << CLK_CLKSEL3_SC4SEL_Pos) |
CLK_T::CLKSEL3: SC4SEL Mask
Definition at line 3847 of file NUC472_442.h.
| #define CLK_CLKSEL3_SC4SEL_Pos (8) |
CLK_T::CLKSEL3: SC4SEL Position
Definition at line 3846 of file NUC472_442.h.
| #define CLK_CLKSEL3_SC5SEL_Msk (0x3ul << CLK_CLKSEL3_SC5SEL_Pos) |
CLK_T::CLKSEL3: SC5SEL Mask
Definition at line 3850 of file NUC472_442.h.
| #define CLK_CLKSEL3_SC5SEL_Pos (10) |
CLK_T::CLKSEL3: SC5SEL Position
Definition at line 3849 of file NUC472_442.h.
| #define CLK_PLL2CTL_PLL2CKEN_Msk (0x1ul << CLK_PLL2CTL_PLL2CKEN_Pos) |
CLK_T::PLL2CTL: PLL2CKEN Mask
Definition at line 3928 of file NUC472_442.h.
| #define CLK_PLL2CTL_PLL2CKEN_Pos (8) |
CLK_T::PLL2CTL: PLL2CKEN Position
Definition at line 3927 of file NUC472_442.h.
| #define CLK_PLL2CTL_PLL2DIV_Msk (0xfful << CLK_PLL2CTL_PLL2DIV_Pos) |
CLK_T::PLL2CTL: PLL2DIV Mask
Definition at line 3925 of file NUC472_442.h.
| #define CLK_PLL2CTL_PLL2DIV_Pos (0) |
CLK_T::PLL2CTL: PLL2DIV Position
Definition at line 3924 of file NUC472_442.h.
| #define CLK_PLLCTL_BP_Msk (0x1ul << CLK_PLLCTL_BP_Pos) |
CLK_T::PLLCTL: BP Mask
Definition at line 3913 of file NUC472_442.h.
| #define CLK_PLLCTL_BP_Pos (17) |
CLK_T::PLLCTL: BP Position
Definition at line 3912 of file NUC472_442.h.
| #define CLK_PLLCTL_FBDIV_Msk (0x1fful << CLK_PLLCTL_FBDIV_Pos) |
CLK_T::PLLCTL: FBDIV Mask
Definition at line 3901 of file NUC472_442.h.
| #define CLK_PLLCTL_FBDIV_Pos (0) |
CLK_T::PLLCTL: FBDIV Position
Definition at line 3900 of file NUC472_442.h.
| #define CLK_PLLCTL_INDIV_Msk (0x1ful << CLK_PLLCTL_INDIV_Pos) |
CLK_T::PLLCTL: INDIV Mask
Definition at line 3904 of file NUC472_442.h.
| #define CLK_PLLCTL_INDIV_Pos (9) |
CLK_T::PLLCTL: INDIV Position
Definition at line 3903 of file NUC472_442.h.
| #define CLK_PLLCTL_OE_Msk (0x1ul << CLK_PLLCTL_OE_Pos) |
CLK_T::PLLCTL: OE Mask
Definition at line 3916 of file NUC472_442.h.
| #define CLK_PLLCTL_OE_Pos (18) |
CLK_T::PLLCTL: OE Position
Definition at line 3915 of file NUC472_442.h.
| #define CLK_PLLCTL_OUTDV_Msk (0x3ul << CLK_PLLCTL_OUTDV_Pos) |
CLK_T::PLLCTL: OUTDV Mask
Definition at line 3907 of file NUC472_442.h.
| #define CLK_PLLCTL_OUTDV_Pos (14) |
CLK_T::PLLCTL: OUTDV Position
Definition at line 3906 of file NUC472_442.h.
| #define CLK_PLLCTL_PD_Msk (0x1ul << CLK_PLLCTL_PD_Pos) |
CLK_T::PLLCTL: PD Mask
Definition at line 3910 of file NUC472_442.h.
| #define CLK_PLLCTL_PD_Pos (16) |
CLK_T::PLLCTL: PD Position
Definition at line 3909 of file NUC472_442.h.
| #define CLK_PLLCTL_PLLREMAP_Msk (0x1ul << CLK_PLLCTL_PLLREMAP_Pos) |
CLK_T::PLLCTL: PLLREMAP Mask
Definition at line 3922 of file NUC472_442.h.
| #define CLK_PLLCTL_PLLREMAP_Pos (20) |
CLK_T::PLLCTL: PLLREMAP Position
Definition at line 3921 of file NUC472_442.h.
| #define CLK_PLLCTL_PLLSRC_Msk (0x1ul << CLK_PLLCTL_PLLSRC_Pos) |
CLK_T::PLLCTL: PLLSRC Mask
Definition at line 3919 of file NUC472_442.h.
| #define CLK_PLLCTL_PLLSRC_Pos (19) |
CLK_T::PLLCTL: PLLSRC Position
Definition at line 3918 of file NUC472_442.h.
| #define CLK_PWRCTL_DBPDEN_Msk (0x1ul << CLK_PWRCTL_DBPDEN_Pos) |
CLK_T::PWRCTL: DBPDEN Mask
Definition at line 3574 of file NUC472_442.h.
| #define CLK_PWRCTL_DBPDEN_Pos (9) |
CLK_T::PWRCTL: DBPDEN Position
Definition at line 3573 of file NUC472_442.h.
| #define CLK_PWRCTL_HIRCEN_Msk (0x1ul << CLK_PWRCTL_HIRCEN_Pos) |
CLK_T::PWRCTL: HIRCEN Mask
Definition at line 3553 of file NUC472_442.h.
| #define CLK_PWRCTL_HIRCEN_Pos (2) |
CLK_T::PWRCTL: HIRCEN Position
Definition at line 3552 of file NUC472_442.h.
| #define CLK_PWRCTL_HXTEN_Msk (0x1ul << CLK_PWRCTL_HXTEN_Pos) |
CLK_T::PWRCTL: HXTEN Mask
Definition at line 3547 of file NUC472_442.h.
| #define CLK_PWRCTL_HXTEN_Pos (0) |
@addtogroup CLK_CONST CLK Bit Field Definition Constant Definitions for CLK Controller
CLK_T::PWRCTL: HXTEN Position
Definition at line 3546 of file NUC472_442.h.
| #define CLK_PWRCTL_LIRCEN_Msk (0x1ul << CLK_PWRCTL_LIRCEN_Pos) |
CLK_T::PWRCTL: LIRCEN Mask
Definition at line 3556 of file NUC472_442.h.
| #define CLK_PWRCTL_LIRCEN_Pos (3) |
CLK_T::PWRCTL: LIRCEN Position
Definition at line 3555 of file NUC472_442.h.
| #define CLK_PWRCTL_LXTEN_Msk (0x1ul << CLK_PWRCTL_LXTEN_Pos) |
CLK_T::PWRCTL: LXTEN Mask
Definition at line 3550 of file NUC472_442.h.
| #define CLK_PWRCTL_LXTEN_Pos (1) |
CLK_T::PWRCTL: LXTEN Position
Definition at line 3549 of file NUC472_442.h.
| #define CLK_PWRCTL_PDEN_Msk (0x1ul << CLK_PWRCTL_PDEN_Pos) |
CLK_T::PWRCTL: PDEN Mask
Definition at line 3568 of file NUC472_442.h.
| #define CLK_PWRCTL_PDEN_Pos (7) |
CLK_T::PWRCTL: PDEN Position
Definition at line 3567 of file NUC472_442.h.
| #define CLK_PWRCTL_PDWKDLY_Msk (0x1ul << CLK_PWRCTL_PDWKDLY_Pos) |
CLK_T::PWRCTL: PDWKDLY Mask
Definition at line 3559 of file NUC472_442.h.
| #define CLK_PWRCTL_PDWKDLY_Pos (4) |
CLK_T::PWRCTL: PDWKDLY Position
Definition at line 3558 of file NUC472_442.h.
| #define CLK_PWRCTL_PDWKIEN_Msk (0x1ul << CLK_PWRCTL_PDWKIEN_Pos) |
CLK_T::PWRCTL: PDWKIEN Mask
Definition at line 3562 of file NUC472_442.h.
| #define CLK_PWRCTL_PDWKIEN_Pos (5) |
CLK_T::PWRCTL: PDWKIEN Position
Definition at line 3561 of file NUC472_442.h.
| #define CLK_PWRCTL_PDWKIF_Msk (0x1ul << CLK_PWRCTL_PDWKIF_Pos) |
CLK_T::PWRCTL: PDWKIF Mask
Definition at line 3565 of file NUC472_442.h.
| #define CLK_PWRCTL_PDWKIF_Pos (6) |
CLK_T::PWRCTL: PDWKIF Position
Definition at line 3564 of file NUC472_442.h.
| #define CLK_PWRCTL_PDWTCPU_Msk (0x1ul << CLK_PWRCTL_PDWTCPU_Pos) |
CLK_T::PWRCTL: PDWTCPU Mask
Definition at line 3571 of file NUC472_442.h.
| #define CLK_PWRCTL_PDWTCPU_Pos (8) |
CLK_T::PWRCTL: PDWTCPU Position
Definition at line 3570 of file NUC472_442.h.
| #define CLK_STATUS_CLKSFAIL_Msk (0x1ul << CLK_STATUS_CLKSFAIL_Pos) |
CLK_T::STATUS: CLKSFAIL Mask
Definition at line 3949 of file NUC472_442.h.
| #define CLK_STATUS_CLKSFAIL_Pos (7) |
CLK_T::STATUS: CLKSFAIL Position
Definition at line 3948 of file NUC472_442.h.
| #define CLK_STATUS_HIRCSTB_Msk (0x1ul << CLK_STATUS_HIRCSTB_Pos) |
CLK_T::STATUS: HIRCSTB Mask
Definition at line 3943 of file NUC472_442.h.
| #define CLK_STATUS_HIRCSTB_Pos (4) |
CLK_T::STATUS: HIRCSTB Position
Definition at line 3942 of file NUC472_442.h.
| #define CLK_STATUS_HXTSTB_Msk (0x1ul << CLK_STATUS_HXTSTB_Pos) |
CLK_T::STATUS: HXTSTB Mask
Definition at line 3931 of file NUC472_442.h.
| #define CLK_STATUS_HXTSTB_Pos (0) |
CLK_T::STATUS: HXTSTB Position
Definition at line 3930 of file NUC472_442.h.
| #define CLK_STATUS_LIRCSTB_Msk (0x1ul << CLK_STATUS_LIRCSTB_Pos) |
CLK_T::STATUS: LIRCSTB Mask
Definition at line 3940 of file NUC472_442.h.
| #define CLK_STATUS_LIRCSTB_Pos (3) |
CLK_T::STATUS: LIRCSTB Position
Definition at line 3939 of file NUC472_442.h.
| #define CLK_STATUS_LXTSTB_Msk (0x1ul << CLK_STATUS_LXTSTB_Pos) |
CLK_T::STATUS: LXTSTB Mask
Definition at line 3934 of file NUC472_442.h.
| #define CLK_STATUS_LXTSTB_Pos (1) |
CLK_T::STATUS: LXTSTB Position
Definition at line 3933 of file NUC472_442.h.
| #define CLK_STATUS_PLL2STB_Msk (0x1ul << CLK_STATUS_PLL2STB_Pos) |
CLK_T::STATUS: PLL2STB Mask
Definition at line 3946 of file NUC472_442.h.
| #define CLK_STATUS_PLL2STB_Pos (5) |
CLK_T::STATUS: PLL2STB Position
Definition at line 3945 of file NUC472_442.h.
| #define CLK_STATUS_PLLSTB_Msk (0x1ul << CLK_STATUS_PLLSTB_Pos) |
CLK_T::STATUS: PLLSTB Mask
Definition at line 3937 of file NUC472_442.h.
| #define CLK_STATUS_PLLSTB_Pos (2) |
CLK_T::STATUS: PLLSTB Position
Definition at line 3936 of file NUC472_442.h.
| #define CRC_CHECKSUM_CHECKSUM_Msk (0xfffffffful << CRC_CHECKSUM_CHECKSUM_Pos) |
CRC_T::CHECKSUM: CHECKSUM Mask
Definition at line 4110 of file NUC472_442.h.
| #define CRC_CHECKSUM_CHECKSUM_Pos (0) |
CRC_T::CHECKSUM: CHECKSUM Position
Definition at line 4109 of file NUC472_442.h.
| #define CRC_CTL_CHKSFMT_Msk (0x1ul << CRC_CTL_CHKSFMT_Pos) |
CRC_T::CTL: CHKSFMT Mask
Definition at line 4095 of file NUC472_442.h.
| #define CRC_CTL_CHKSFMT_Pos (27) |
CRC_T::CTL: CHKSFMT Position
Definition at line 4094 of file NUC472_442.h.
| #define CRC_CTL_CHKSREV_Msk (0x1ul << CRC_CTL_CHKSREV_Pos) |
CRC_T::CTL: CHKSREV Mask
Definition at line 4089 of file NUC472_442.h.
| #define CRC_CTL_CHKSREV_Pos (25) |
CRC_T::CTL: CHKSREV Position
Definition at line 4088 of file NUC472_442.h.
| #define CRC_CTL_CRCEN_Msk (0x1ul << CRC_CTL_CRCEN_Pos) |
CRC_T::CTL: CRCEN Mask
Definition at line 4080 of file NUC472_442.h.
| #define CRC_CTL_CRCEN_Pos (0) |
@addtogroup CRC_CONST CRC Bit Field Definition Constant Definitions for CRC Controller
CRC_T::CTL: CRCEN Position
Definition at line 4079 of file NUC472_442.h.
| #define CRC_CTL_CRCMODE_Msk (0x3ul << CRC_CTL_CRCMODE_Pos) |
CRC_T::CTL: CRCMODE Mask
Definition at line 4101 of file NUC472_442.h.
| #define CRC_CTL_CRCMODE_Pos (30) |
CRC_T::CTL: CRCMODE Position
Definition at line 4100 of file NUC472_442.h.
| #define CRC_CTL_CRCRST_Msk (0x1ul << CRC_CTL_CRCRST_Pos) |
CRC_T::CTL: CRCRST Mask
Definition at line 4083 of file NUC472_442.h.
| #define CRC_CTL_CRCRST_Pos (1) |
CRC_T::CTL: CRCRST Position
Definition at line 4082 of file NUC472_442.h.
| #define CRC_CTL_DATFMT_Msk (0x1ul << CRC_CTL_DATFMT_Pos) |
CRC_T::CTL: DATFMT Mask
Definition at line 4092 of file NUC472_442.h.
| #define CRC_CTL_DATFMT_Pos (26) |
CRC_T::CTL: DATFMT Position
Definition at line 4091 of file NUC472_442.h.
| #define CRC_CTL_DATLEN_Msk (0x3ul << CRC_CTL_DATLEN_Pos) |
CRC_T::CTL: DATLEN Mask
Definition at line 4098 of file NUC472_442.h.
| #define CRC_CTL_DATLEN_Pos (28) |
CRC_T::CTL: DATLEN Position
Definition at line 4097 of file NUC472_442.h.
| #define CRC_CTL_DATREV_Msk (0x1ul << CRC_CTL_DATREV_Pos) |
CRC_T::CTL: DATREV Mask
Definition at line 4086 of file NUC472_442.h.
| #define CRC_CTL_DATREV_Pos (24) |
CRC_T::CTL: DATREV Position
Definition at line 4085 of file NUC472_442.h.
| #define CRC_DAT_DATA_Msk (0xfffffffful << CRC_DAT_DATA_Pos) |
CRC_T::DAT: DATA Mask
Definition at line 4104 of file NUC472_442.h.
| #define CRC_DAT_DATA_Pos (0) |
CRC_T::DAT: DATA Position
Definition at line 4103 of file NUC472_442.h.
| #define CRC_SEED_SEED_Msk (0xfffffffful << CRC_SEED_SEED_Pos) |
CRC_T::SEED: SEED Mask
Definition at line 4107 of file NUC472_442.h.
| #define CRC_SEED_SEED_Pos (0) |
CRC_T::SEED: SEED Position
Definition at line 4106 of file NUC472_442.h.
| #define CRPT_AES0_CNT_CNT_Msk (0xfffffffful << CRPT_AES0_CNT_CNT_Pos) |
CRPT_T::AES0_CNT: CNT Mask
Definition at line 6993 of file NUC472_442.h.
| #define CRPT_AES0_CNT_CNT_Pos (0) |
CRPT_T::AES0_CNT: CNT Position
Definition at line 6992 of file NUC472_442.h.
| #define CRPT_AES0_DADDR_DADDR_Msk (0xfffffffful << CRPT_AES0_DADDR_DADDR_Pos) |
CRPT_T::AES0_DADDR: DADDR Mask
Definition at line 6990 of file NUC472_442.h.
| #define CRPT_AES0_DADDR_DADDR_Pos (0) |
CRPT_T::AES0_DADDR: DADDR Position
Definition at line 6989 of file NUC472_442.h.
| #define CRPT_AES0_IV0_IV_Msk (0xfffffffful << CRPT_AES0_IV0_IV_Pos) |
CRPT_T::AES0_IV0: IV Mask
Definition at line 6975 of file NUC472_442.h.
| #define CRPT_AES0_IV0_IV_Pos (0) |
CRPT_T::AES0_IV0: IV Position
Definition at line 6974 of file NUC472_442.h.
| #define CRPT_AES0_IV1_IV_Msk (0xfffffffful << CRPT_AES0_IV1_IV_Pos) |
CRPT_T::AES0_IV1: IV Mask
Definition at line 6978 of file NUC472_442.h.
| #define CRPT_AES0_IV1_IV_Pos (0) |
CRPT_T::AES0_IV1: IV Position
Definition at line 6977 of file NUC472_442.h.
| #define CRPT_AES0_IV2_IV_Msk (0xfffffffful << CRPT_AES0_IV2_IV_Pos) |
CRPT_T::AES0_IV2: IV Mask
Definition at line 6981 of file NUC472_442.h.
| #define CRPT_AES0_IV2_IV_Pos (0) |
CRPT_T::AES0_IV2: IV Position
Definition at line 6980 of file NUC472_442.h.
| #define CRPT_AES0_IV3_IV_Msk (0xfffffffful << CRPT_AES0_IV3_IV_Pos) |
CRPT_T::AES0_IV3: IV Mask
Definition at line 6984 of file NUC472_442.h.
| #define CRPT_AES0_IV3_IV_Pos (0) |
CRPT_T::AES0_IV3: IV Position
Definition at line 6983 of file NUC472_442.h.
| #define CRPT_AES0_KEY0_KEY_Msk (0xfffffffful << CRPT_AES0_KEY0_KEY_Pos) |
CRPT_T::AES0_KEY0: KEY Mask
Definition at line 6951 of file NUC472_442.h.
| #define CRPT_AES0_KEY0_KEY_Pos (0) |
CRPT_T::AES0_KEY0: KEY Position
Definition at line 6950 of file NUC472_442.h.
| #define CRPT_AES0_KEY1_KEY_Msk (0xfffffffful << CRPT_AES0_KEY1_KEY_Pos) |
CRPT_T::AES0_KEY1: KEY Mask
Definition at line 6954 of file NUC472_442.h.
| #define CRPT_AES0_KEY1_KEY_Pos (0) |
CRPT_T::AES0_KEY1: KEY Position
Definition at line 6953 of file NUC472_442.h.
| #define CRPT_AES0_KEY2_KEY_Msk (0xfffffffful << CRPT_AES0_KEY2_KEY_Pos) |
CRPT_T::AES0_KEY2: KEY Mask
Definition at line 6957 of file NUC472_442.h.
| #define CRPT_AES0_KEY2_KEY_Pos (0) |
CRPT_T::AES0_KEY2: KEY Position
Definition at line 6956 of file NUC472_442.h.
| #define CRPT_AES0_KEY3_KEY_Msk (0xfffffffful << CRPT_AES0_KEY3_KEY_Pos) |
CRPT_T::AES0_KEY3: KEY Mask
Definition at line 6960 of file NUC472_442.h.
| #define CRPT_AES0_KEY3_KEY_Pos (0) |
CRPT_T::AES0_KEY3: KEY Position
Definition at line 6959 of file NUC472_442.h.
| #define CRPT_AES0_KEY4_KEY_Msk (0xfffffffful << CRPT_AES0_KEY4_KEY_Pos) |
CRPT_T::AES0_KEY4: KEY Mask
Definition at line 6963 of file NUC472_442.h.
| #define CRPT_AES0_KEY4_KEY_Pos (0) |
CRPT_T::AES0_KEY4: KEY Position
Definition at line 6962 of file NUC472_442.h.
| #define CRPT_AES0_KEY5_KEY_Msk (0xfffffffful << CRPT_AES0_KEY5_KEY_Pos) |
CRPT_T::AES0_KEY5: KEY Mask
Definition at line 6966 of file NUC472_442.h.
| #define CRPT_AES0_KEY5_KEY_Pos (0) |
CRPT_T::AES0_KEY5: KEY Position
Definition at line 6965 of file NUC472_442.h.
| #define CRPT_AES0_KEY6_KEY_Msk (0xfffffffful << CRPT_AES0_KEY6_KEY_Pos) |
CRPT_T::AES0_KEY6: KEY Mask
Definition at line 6969 of file NUC472_442.h.
| #define CRPT_AES0_KEY6_KEY_Pos (0) |
CRPT_T::AES0_KEY6: KEY Position
Definition at line 6968 of file NUC472_442.h.
| #define CRPT_AES0_KEY7_KEY_Msk (0xfffffffful << CRPT_AES0_KEY7_KEY_Pos) |
CRPT_T::AES0_KEY7: KEY Mask
Definition at line 6972 of file NUC472_442.h.
| #define CRPT_AES0_KEY7_KEY_Pos (0) |
CRPT_T::AES0_KEY7: KEY Position
Definition at line 6971 of file NUC472_442.h.
| #define CRPT_AES0_SADDR_SADDR_Msk (0xfffffffful << CRPT_AES0_SADDR_SADDR_Pos) |
CRPT_T::AES0_SADDR: SADDR Mask
Definition at line 6987 of file NUC472_442.h.
| #define CRPT_AES0_SADDR_SADDR_Pos (0) |
CRPT_T::AES0_SADDR: SADDR Position
Definition at line 6986 of file NUC472_442.h.
| #define CRPT_AES1_CNT_CNT_Msk (0xfffffffful << CRPT_AES1_CNT_CNT_Pos) |
CRPT_T::AES1_CNT: CNT Mask
Definition at line 7038 of file NUC472_442.h.
| #define CRPT_AES1_CNT_CNT_Pos (0) |
CRPT_T::AES1_CNT: CNT Position
Definition at line 7037 of file NUC472_442.h.
| #define CRPT_AES1_DADDR_DADDR_Msk (0xfffffffful << CRPT_AES1_DADDR_DADDR_Pos) |
CRPT_T::AES1_DADDR: DADDR Mask
Definition at line 7035 of file NUC472_442.h.
| #define CRPT_AES1_DADDR_DADDR_Pos (0) |
CRPT_T::AES1_DADDR: DADDR Position
Definition at line 7034 of file NUC472_442.h.
| #define CRPT_AES1_IV0_IV_Msk (0xfffffffful << CRPT_AES1_IV0_IV_Pos) |
CRPT_T::AES1_IV0: IV Mask
Definition at line 7020 of file NUC472_442.h.
| #define CRPT_AES1_IV0_IV_Pos (0) |
CRPT_T::AES1_IV0: IV Position
Definition at line 7019 of file NUC472_442.h.
| #define CRPT_AES1_IV1_IV_Msk (0xfffffffful << CRPT_AES1_IV1_IV_Pos) |
CRPT_T::AES1_IV1: IV Mask
Definition at line 7023 of file NUC472_442.h.
| #define CRPT_AES1_IV1_IV_Pos (0) |
CRPT_T::AES1_IV1: IV Position
Definition at line 7022 of file NUC472_442.h.
| #define CRPT_AES1_IV2_IV_Msk (0xfffffffful << CRPT_AES1_IV2_IV_Pos) |
CRPT_T::AES1_IV2: IV Mask
Definition at line 7026 of file NUC472_442.h.
| #define CRPT_AES1_IV2_IV_Pos (0) |
CRPT_T::AES1_IV2: IV Position
Definition at line 7025 of file NUC472_442.h.
| #define CRPT_AES1_IV3_IV_Msk (0xfffffffful << CRPT_AES1_IV3_IV_Pos) |
CRPT_T::AES1_IV3: IV Mask
Definition at line 7029 of file NUC472_442.h.
| #define CRPT_AES1_IV3_IV_Pos (0) |
CRPT_T::AES1_IV3: IV Position
Definition at line 7028 of file NUC472_442.h.
| #define CRPT_AES1_KEY0_KEY_Msk (0xfffffffful << CRPT_AES1_KEY0_KEY_Pos) |
CRPT_T::AES1_KEY0: KEY Mask
Definition at line 6996 of file NUC472_442.h.
| #define CRPT_AES1_KEY0_KEY_Pos (0) |
CRPT_T::AES1_KEY0: KEY Position
Definition at line 6995 of file NUC472_442.h.
| #define CRPT_AES1_KEY1_KEY_Msk (0xfffffffful << CRPT_AES1_KEY1_KEY_Pos) |
CRPT_T::AES1_KEY1: KEY Mask
Definition at line 6999 of file NUC472_442.h.
| #define CRPT_AES1_KEY1_KEY_Pos (0) |
CRPT_T::AES1_KEY1: KEY Position
Definition at line 6998 of file NUC472_442.h.
| #define CRPT_AES1_KEY2_KEY_Msk (0xfffffffful << CRPT_AES1_KEY2_KEY_Pos) |
CRPT_T::AES1_KEY2: KEY Mask
Definition at line 7002 of file NUC472_442.h.
| #define CRPT_AES1_KEY2_KEY_Pos (0) |
CRPT_T::AES1_KEY2: KEY Position
Definition at line 7001 of file NUC472_442.h.
| #define CRPT_AES1_KEY3_KEY_Msk (0xfffffffful << CRPT_AES1_KEY3_KEY_Pos) |
CRPT_T::AES1_KEY3: KEY Mask
Definition at line 7005 of file NUC472_442.h.
| #define CRPT_AES1_KEY3_KEY_Pos (0) |
CRPT_T::AES1_KEY3: KEY Position
Definition at line 7004 of file NUC472_442.h.
| #define CRPT_AES1_KEY4_KEY_Msk (0xfffffffful << CRPT_AES1_KEY4_KEY_Pos) |
CRPT_T::AES1_KEY4: KEY Mask
Definition at line 7008 of file NUC472_442.h.
| #define CRPT_AES1_KEY4_KEY_Pos (0) |
CRPT_T::AES1_KEY4: KEY Position
Definition at line 7007 of file NUC472_442.h.
| #define CRPT_AES1_KEY5_KEY_Msk (0xfffffffful << CRPT_AES1_KEY5_KEY_Pos) |
CRPT_T::AES1_KEY5: KEY Mask
Definition at line 7011 of file NUC472_442.h.
| #define CRPT_AES1_KEY5_KEY_Pos (0) |
CRPT_T::AES1_KEY5: KEY Position
Definition at line 7010 of file NUC472_442.h.
| #define CRPT_AES1_KEY6_KEY_Msk (0xfffffffful << CRPT_AES1_KEY6_KEY_Pos) |
CRPT_T::AES1_KEY6: KEY Mask
Definition at line 7014 of file NUC472_442.h.
| #define CRPT_AES1_KEY6_KEY_Pos (0) |
CRPT_T::AES1_KEY6: KEY Position
Definition at line 7013 of file NUC472_442.h.
| #define CRPT_AES1_KEY7_KEY_Msk (0xfffffffful << CRPT_AES1_KEY7_KEY_Pos) |
CRPT_T::AES1_KEY7: KEY Mask
Definition at line 7017 of file NUC472_442.h.
| #define CRPT_AES1_KEY7_KEY_Pos (0) |
CRPT_T::AES1_KEY7: KEY Position
Definition at line 7016 of file NUC472_442.h.
| #define CRPT_AES1_SADDR_SADDR_Msk (0xfffffffful << CRPT_AES1_SADDR_SADDR_Pos) |
CRPT_T::AES1_SADDR: SADDR Mask
Definition at line 7032 of file NUC472_442.h.
| #define CRPT_AES1_SADDR_SADDR_Pos (0) |
CRPT_T::AES1_SADDR: SADDR Position
Definition at line 7031 of file NUC472_442.h.
| #define CRPT_AES2_CNT_CNT_Msk (0xfffffffful << CRPT_AES2_CNT_CNT_Pos) |
CRPT_T::AES2_CNT: CNT Mask
Definition at line 7083 of file NUC472_442.h.
| #define CRPT_AES2_CNT_CNT_Pos (0) |
CRPT_T::AES2_CNT: CNT Position
Definition at line 7082 of file NUC472_442.h.
| #define CRPT_AES2_DADDR_DADDR_Msk (0xfffffffful << CRPT_AES2_DADDR_DADDR_Pos) |
CRPT_T::AES2_DADDR: DADDR Mask
Definition at line 7080 of file NUC472_442.h.
| #define CRPT_AES2_DADDR_DADDR_Pos (0) |
CRPT_T::AES2_DADDR: DADDR Position
Definition at line 7079 of file NUC472_442.h.
| #define CRPT_AES2_IV0_IV_Msk (0xfffffffful << CRPT_AES2_IV0_IV_Pos) |
CRPT_T::AES2_IV0: IV Mask
Definition at line 7065 of file NUC472_442.h.
| #define CRPT_AES2_IV0_IV_Pos (0) |
CRPT_T::AES2_IV0: IV Position
Definition at line 7064 of file NUC472_442.h.
| #define CRPT_AES2_IV1_IV_Msk (0xfffffffful << CRPT_AES2_IV1_IV_Pos) |
CRPT_T::AES2_IV1: IV Mask
Definition at line 7068 of file NUC472_442.h.
| #define CRPT_AES2_IV1_IV_Pos (0) |
CRPT_T::AES2_IV1: IV Position
Definition at line 7067 of file NUC472_442.h.
| #define CRPT_AES2_IV2_IV_Msk (0xfffffffful << CRPT_AES2_IV2_IV_Pos) |
CRPT_T::AES2_IV2: IV Mask
Definition at line 7071 of file NUC472_442.h.
| #define CRPT_AES2_IV2_IV_Pos (0) |
CRPT_T::AES2_IV2: IV Position
Definition at line 7070 of file NUC472_442.h.
| #define CRPT_AES2_IV3_IV_Msk (0xfffffffful << CRPT_AES2_IV3_IV_Pos) |
CRPT_T::AES2_IV3: IV Mask
Definition at line 7074 of file NUC472_442.h.
| #define CRPT_AES2_IV3_IV_Pos (0) |
CRPT_T::AES2_IV3: IV Position
Definition at line 7073 of file NUC472_442.h.
| #define CRPT_AES2_KEY0_KEY_Msk (0xfffffffful << CRPT_AES2_KEY0_KEY_Pos) |
CRPT_T::AES2_KEY0: KEY Mask
Definition at line 7041 of file NUC472_442.h.
| #define CRPT_AES2_KEY0_KEY_Pos (0) |
CRPT_T::AES2_KEY0: KEY Position
Definition at line 7040 of file NUC472_442.h.
| #define CRPT_AES2_KEY1_KEY_Msk (0xfffffffful << CRPT_AES2_KEY1_KEY_Pos) |
CRPT_T::AES2_KEY1: KEY Mask
Definition at line 7044 of file NUC472_442.h.
| #define CRPT_AES2_KEY1_KEY_Pos (0) |
CRPT_T::AES2_KEY1: KEY Position
Definition at line 7043 of file NUC472_442.h.
| #define CRPT_AES2_KEY2_KEY_Msk (0xfffffffful << CRPT_AES2_KEY2_KEY_Pos) |
CRPT_T::AES2_KEY2: KEY Mask
Definition at line 7047 of file NUC472_442.h.
| #define CRPT_AES2_KEY2_KEY_Pos (0) |
CRPT_T::AES2_KEY2: KEY Position
Definition at line 7046 of file NUC472_442.h.
| #define CRPT_AES2_KEY3_KEY_Msk (0xfffffffful << CRPT_AES2_KEY3_KEY_Pos) |
CRPT_T::AES2_KEY3: KEY Mask
Definition at line 7050 of file NUC472_442.h.
| #define CRPT_AES2_KEY3_KEY_Pos (0) |
CRPT_T::AES2_KEY3: KEY Position
Definition at line 7049 of file NUC472_442.h.
| #define CRPT_AES2_KEY4_KEY_Msk (0xfffffffful << CRPT_AES2_KEY4_KEY_Pos) |
CRPT_T::AES2_KEY4: KEY Mask
Definition at line 7053 of file NUC472_442.h.
| #define CRPT_AES2_KEY4_KEY_Pos (0) |
CRPT_T::AES2_KEY4: KEY Position
Definition at line 7052 of file NUC472_442.h.
| #define CRPT_AES2_KEY5_KEY_Msk (0xfffffffful << CRPT_AES2_KEY5_KEY_Pos) |
CRPT_T::AES2_KEY5: KEY Mask
Definition at line 7056 of file NUC472_442.h.
| #define CRPT_AES2_KEY5_KEY_Pos (0) |
CRPT_T::AES2_KEY5: KEY Position
Definition at line 7055 of file NUC472_442.h.
| #define CRPT_AES2_KEY6_KEY_Msk (0xfffffffful << CRPT_AES2_KEY6_KEY_Pos) |
CRPT_T::AES2_KEY6: KEY Mask
Definition at line 7059 of file NUC472_442.h.
| #define CRPT_AES2_KEY6_KEY_Pos (0) |
CRPT_T::AES2_KEY6: KEY Position
Definition at line 7058 of file NUC472_442.h.
| #define CRPT_AES2_KEY7_KEY_Msk (0xfffffffful << CRPT_AES2_KEY7_KEY_Pos) |
CRPT_T::AES2_KEY7: KEY Mask
Definition at line 7062 of file NUC472_442.h.
| #define CRPT_AES2_KEY7_KEY_Pos (0) |
CRPT_T::AES2_KEY7: KEY Position
Definition at line 7061 of file NUC472_442.h.
| #define CRPT_AES2_SADDR_SADDR_Msk (0xfffffffful << CRPT_AES2_SADDR_SADDR_Pos) |
CRPT_T::AES2_SADDR: SADDR Mask
Definition at line 7077 of file NUC472_442.h.
| #define CRPT_AES2_SADDR_SADDR_Pos (0) |
CRPT_T::AES2_SADDR: SADDR Position
Definition at line 7076 of file NUC472_442.h.
| #define CRPT_AES3_CNT_CNT_Msk (0xfffffffful << CRPT_AES3_CNT_CNT_Pos) |
CRPT_T::AES3_CNT: CNT Mask
Definition at line 7128 of file NUC472_442.h.
| #define CRPT_AES3_CNT_CNT_Pos (0) |
CRPT_T::AES3_CNT: CNT Position
Definition at line 7127 of file NUC472_442.h.
| #define CRPT_AES3_DADDR_DADDR_Msk (0xfffffffful << CRPT_AES3_DADDR_DADDR_Pos) |
CRPT_T::AES3_DADDR: DADDR Mask
Definition at line 7125 of file NUC472_442.h.
| #define CRPT_AES3_DADDR_DADDR_Pos (0) |
CRPT_T::AES3_DADDR: DADDR Position
Definition at line 7124 of file NUC472_442.h.
| #define CRPT_AES3_IV0_IV_Msk (0xfffffffful << CRPT_AES3_IV0_IV_Pos) |
CRPT_T::AES3_IV0: IV Mask
Definition at line 7110 of file NUC472_442.h.
| #define CRPT_AES3_IV0_IV_Pos (0) |
CRPT_T::AES3_IV0: IV Position
Definition at line 7109 of file NUC472_442.h.
| #define CRPT_AES3_IV1_IV_Msk (0xfffffffful << CRPT_AES3_IV1_IV_Pos) |
CRPT_T::AES3_IV1: IV Mask
Definition at line 7113 of file NUC472_442.h.
| #define CRPT_AES3_IV1_IV_Pos (0) |
CRPT_T::AES3_IV1: IV Position
Definition at line 7112 of file NUC472_442.h.
| #define CRPT_AES3_IV2_IV_Msk (0xfffffffful << CRPT_AES3_IV2_IV_Pos) |
CRPT_T::AES3_IV2: IV Mask
Definition at line 7116 of file NUC472_442.h.
| #define CRPT_AES3_IV2_IV_Pos (0) |
CRPT_T::AES3_IV2: IV Position
Definition at line 7115 of file NUC472_442.h.
| #define CRPT_AES3_IV3_IV_Msk (0xfffffffful << CRPT_AES3_IV3_IV_Pos) |
CRPT_T::AES3_IV3: IV Mask
Definition at line 7119 of file NUC472_442.h.
| #define CRPT_AES3_IV3_IV_Pos (0) |
CRPT_T::AES3_IV3: IV Position
Definition at line 7118 of file NUC472_442.h.
| #define CRPT_AES3_KEY0_KEY_Msk (0xfffffffful << CRPT_AES3_KEY0_KEY_Pos) |
CRPT_T::AES3_KEY0: KEY Mask
Definition at line 7086 of file NUC472_442.h.
| #define CRPT_AES3_KEY0_KEY_Pos (0) |
CRPT_T::AES3_KEY0: KEY Position
Definition at line 7085 of file NUC472_442.h.
| #define CRPT_AES3_KEY1_KEY_Msk (0xfffffffful << CRPT_AES3_KEY1_KEY_Pos) |
CRPT_T::AES3_KEY1: KEY Mask
Definition at line 7089 of file NUC472_442.h.
| #define CRPT_AES3_KEY1_KEY_Pos (0) |
CRPT_T::AES3_KEY1: KEY Position
Definition at line 7088 of file NUC472_442.h.
| #define CRPT_AES3_KEY2_KEY_Msk (0xfffffffful << CRPT_AES3_KEY2_KEY_Pos) |
CRPT_T::AES3_KEY2: KEY Mask
Definition at line 7092 of file NUC472_442.h.
| #define CRPT_AES3_KEY2_KEY_Pos (0) |
CRPT_T::AES3_KEY2: KEY Position
Definition at line 7091 of file NUC472_442.h.
| #define CRPT_AES3_KEY3_KEY_Msk (0xfffffffful << CRPT_AES3_KEY3_KEY_Pos) |
CRPT_T::AES3_KEY3: KEY Mask
Definition at line 7095 of file NUC472_442.h.
| #define CRPT_AES3_KEY3_KEY_Pos (0) |
CRPT_T::AES3_KEY3: KEY Position
Definition at line 7094 of file NUC472_442.h.
| #define CRPT_AES3_KEY4_KEY_Msk (0xfffffffful << CRPT_AES3_KEY4_KEY_Pos) |
CRPT_T::AES3_KEY4: KEY Mask
Definition at line 7098 of file NUC472_442.h.
| #define CRPT_AES3_KEY4_KEY_Pos (0) |
CRPT_T::AES3_KEY4: KEY Position
Definition at line 7097 of file NUC472_442.h.
| #define CRPT_AES3_KEY5_KEY_Msk (0xfffffffful << CRPT_AES3_KEY5_KEY_Pos) |
CRPT_T::AES3_KEY5: KEY Mask
Definition at line 7101 of file NUC472_442.h.
| #define CRPT_AES3_KEY5_KEY_Pos (0) |
CRPT_T::AES3_KEY5: KEY Position
Definition at line 7100 of file NUC472_442.h.
| #define CRPT_AES3_KEY6_KEY_Msk (0xfffffffful << CRPT_AES3_KEY6_KEY_Pos) |
CRPT_T::AES3_KEY6: KEY Mask
Definition at line 7104 of file NUC472_442.h.
| #define CRPT_AES3_KEY6_KEY_Pos (0) |
CRPT_T::AES3_KEY6: KEY Position
Definition at line 7103 of file NUC472_442.h.
| #define CRPT_AES3_KEY7_KEY_Msk (0xfffffffful << CRPT_AES3_KEY7_KEY_Pos) |
CRPT_T::AES3_KEY7: KEY Mask
Definition at line 7107 of file NUC472_442.h.
| #define CRPT_AES3_KEY7_KEY_Pos (0) |
CRPT_T::AES3_KEY7: KEY Position
Definition at line 7106 of file NUC472_442.h.
| #define CRPT_AES3_SADDR_SADDR_Msk (0xfffffffful << CRPT_AES3_SADDR_SADDR_Pos) |
CRPT_T::AES3_SADDR: SADDR Mask
Definition at line 7122 of file NUC472_442.h.
| #define CRPT_AES3_SADDR_SADDR_Pos (0) |
CRPT_T::AES3_SADDR: SADDR Position
Definition at line 7121 of file NUC472_442.h.
| #define CRPT_AES_CTL_CHANNEL_Msk (0x3ul << CRPT_AES_CTL_CHANNEL_Pos) |
CRPT_T::AES_CTL: CHANNEL Mask
Definition at line 6909 of file NUC472_442.h.
| #define CRPT_AES_CTL_CHANNEL_Pos (24) |
CRPT_T::AES_CTL: CHANNEL Position
Definition at line 6908 of file NUC472_442.h.
| #define CRPT_AES_CTL_DMACSCAD_Msk (0x1ul << CRPT_AES_CTL_DMACSCAD_Pos) |
CRPT_T::AES_CTL: DMACSCAD Mask
Definition at line 6891 of file NUC472_442.h.
| #define CRPT_AES_CTL_DMACSCAD_Pos (6) |
CRPT_T::AES_CTL: DMACSCAD Position
Definition at line 6890 of file NUC472_442.h.
| #define CRPT_AES_CTL_DMAEN_Msk (0x1ul << CRPT_AES_CTL_DMAEN_Pos) |
CRPT_T::AES_CTL: DMAEN Mask
Definition at line 6894 of file NUC472_442.h.
| #define CRPT_AES_CTL_DMAEN_Pos (7) |
CRPT_T::AES_CTL: DMAEN Position
Definition at line 6893 of file NUC472_442.h.
| #define CRPT_AES_CTL_DMALAST_Msk (0x1ul << CRPT_AES_CTL_DMALAST_Pos) |
CRPT_T::AES_CTL: DMALAST Mask
Definition at line 6888 of file NUC472_442.h.
| #define CRPT_AES_CTL_DMALAST_Pos (5) |
CRPT_T::AES_CTL: DMALAST Position
Definition at line 6887 of file NUC472_442.h.
| #define CRPT_AES_CTL_ENCRPT_Msk (0x1ul << CRPT_AES_CTL_ENCRPT_Pos) |
CRPT_T::AES_CTL: ENCRPT Mask
Definition at line 6900 of file NUC472_442.h.
| #define CRPT_AES_CTL_ENCRPT_Pos (16) |
CRPT_T::AES_CTL: ENCRPT Position
Definition at line 6899 of file NUC472_442.h.
| #define CRPT_AES_CTL_INSWAP_Msk (0x1ul << CRPT_AES_CTL_INSWAP_Pos) |
CRPT_T::AES_CTL: INSWAP Mask
Definition at line 6906 of file NUC472_442.h.
| #define CRPT_AES_CTL_INSWAP_Pos (23) |
CRPT_T::AES_CTL: INSWAP Position
Definition at line 6905 of file NUC472_442.h.
| #define CRPT_AES_CTL_KEYPRT_Msk (0x1ul << CRPT_AES_CTL_KEYPRT_Pos) |
CRPT_T::AES_CTL: KEYPRT Mask
Definition at line 6915 of file NUC472_442.h.
| #define CRPT_AES_CTL_KEYPRT_Pos (31) |
CRPT_T::AES_CTL: KEYPRT Position
Definition at line 6914 of file NUC472_442.h.
| #define CRPT_AES_CTL_KEYSZ_Msk (0x3ul << CRPT_AES_CTL_KEYSZ_Pos) |
CRPT_T::AES_CTL: KEYSZ Mask
Definition at line 6885 of file NUC472_442.h.
| #define CRPT_AES_CTL_KEYSZ_Pos (2) |
CRPT_T::AES_CTL: KEYSZ Position
Definition at line 6884 of file NUC472_442.h.
| #define CRPT_AES_CTL_KEYUNPRT_Msk (0x1ful << CRPT_AES_CTL_KEYUNPRT_Pos) |
CRPT_T::AES_CTL: KEYUNPRT Mask
Definition at line 6912 of file NUC472_442.h.
| #define CRPT_AES_CTL_KEYUNPRT_Pos (26) |
CRPT_T::AES_CTL: KEYUNPRT Position
Definition at line 6911 of file NUC472_442.h.
| #define CRPT_AES_CTL_OPMODE_Msk (0xfful << CRPT_AES_CTL_OPMODE_Pos) |
CRPT_T::AES_CTL: OPMODE Mask
Definition at line 6897 of file NUC472_442.h.
| #define CRPT_AES_CTL_OPMODE_Pos (8) |
CRPT_T::AES_CTL: OPMODE Position
Definition at line 6896 of file NUC472_442.h.
| #define CRPT_AES_CTL_OUTSWAP_Msk (0x1ul << CRPT_AES_CTL_OUTSWAP_Pos) |
CRPT_T::AES_CTL: OUTSWAP Mask
Definition at line 6903 of file NUC472_442.h.
| #define CRPT_AES_CTL_OUTSWAP_Pos (22) |
CRPT_T::AES_CTL: OUTSWAP Position
Definition at line 6902 of file NUC472_442.h.
| #define CRPT_AES_CTL_START_Msk (0x1ul << CRPT_AES_CTL_START_Pos) |
CRPT_T::AES_CTL: START Mask
Definition at line 6879 of file NUC472_442.h.
| #define CRPT_AES_CTL_START_Pos (0) |
CRPT_T::AES_CTL: START Position
Definition at line 6878 of file NUC472_442.h.
| #define CRPT_AES_CTL_STOP_Msk (0x1ul << CRPT_AES_CTL_STOP_Pos) |
CRPT_T::AES_CTL: STOP Mask
Definition at line 6882 of file NUC472_442.h.
| #define CRPT_AES_CTL_STOP_Pos (1) |
CRPT_T::AES_CTL: STOP Position
Definition at line 6881 of file NUC472_442.h.
| #define CRPT_AES_DATIN_DATIN_Msk (0xfffffffful << CRPT_AES_DATIN_DATIN_Pos) |
CRPT_T::AES_DATIN: DATIN Mask
Definition at line 6945 of file NUC472_442.h.
| #define CRPT_AES_DATIN_DATIN_Pos (0) |
CRPT_T::AES_DATIN: DATIN Position
Definition at line 6944 of file NUC472_442.h.
| #define CRPT_AES_DATOUT_DATOUT_Msk (0xfffffffful << CRPT_AES_DATOUT_DATOUT_Pos) |
CRPT_T::AES_DATOUT: DATOUT Mask
Definition at line 6948 of file NUC472_442.h.
| #define CRPT_AES_DATOUT_DATOUT_Pos (0) |
CRPT_T::AES_DATOUT: DATOUT Position
Definition at line 6947 of file NUC472_442.h.
| #define CRPT_AES_FDBCK0_FDBCK_Msk (0xfffffffful << CRPT_AES_FDBCK0_FDBCK_Pos) |
CRPT_T::AES_FDBCK0: FDBCK Mask
Definition at line 6861 of file NUC472_442.h.
| #define CRPT_AES_FDBCK0_FDBCK_Pos (0) |
CRPT_T::AES_FDBCK0: FDBCK Position
Definition at line 6860 of file NUC472_442.h.
| #define CRPT_AES_FDBCK1_FDBCK_Msk (0xfffffffful << CRPT_AES_FDBCK1_FDBCK_Pos) |
CRPT_T::AES_FDBCK1: FDBCK Mask
Definition at line 6864 of file NUC472_442.h.
| #define CRPT_AES_FDBCK1_FDBCK_Pos (0) |
CRPT_T::AES_FDBCK1: FDBCK Position
Definition at line 6863 of file NUC472_442.h.
| #define CRPT_AES_FDBCK2_FDBCK_Msk (0xfffffffful << CRPT_AES_FDBCK2_FDBCK_Pos) |
CRPT_T::AES_FDBCK2: FDBCK Mask
Definition at line 6867 of file NUC472_442.h.
| #define CRPT_AES_FDBCK2_FDBCK_Pos (0) |
CRPT_T::AES_FDBCK2: FDBCK Position
Definition at line 6866 of file NUC472_442.h.
| #define CRPT_AES_FDBCK3_FDBCK_Msk (0xfffffffful << CRPT_AES_FDBCK3_FDBCK_Pos) |
CRPT_T::AES_FDBCK3: FDBCK Mask
Definition at line 6870 of file NUC472_442.h.
| #define CRPT_AES_FDBCK3_FDBCK_Pos (0) |
CRPT_T::AES_FDBCK3: FDBCK Position
Definition at line 6869 of file NUC472_442.h.
| #define CRPT_AES_STS_BUSERR_Msk (0x1ul << CRPT_AES_STS_BUSERR_Pos) |
CRPT_T::AES_STS: BUSERR Mask
Definition at line 6942 of file NUC472_442.h.
| #define CRPT_AES_STS_BUSERR_Pos (20) |
CRPT_T::AES_STS: BUSERR Position
Definition at line 6941 of file NUC472_442.h.
| #define CRPT_AES_STS_BUSY_Msk (0x1ul << CRPT_AES_STS_BUSY_Pos) |
CRPT_T::AES_STS: BUSY Mask
Definition at line 6918 of file NUC472_442.h.
| #define CRPT_AES_STS_BUSY_Pos (0) |
CRPT_T::AES_STS: BUSY Position
Definition at line 6917 of file NUC472_442.h.
| #define CRPT_AES_STS_CNTERR_Msk (0x1ul << CRPT_AES_STS_CNTERR_Pos) |
CRPT_T::AES_STS: CNTERR Mask
Definition at line 6930 of file NUC472_442.h.
| #define CRPT_AES_STS_CNTERR_Pos (12) |
CRPT_T::AES_STS: CNTERR Position
Definition at line 6929 of file NUC472_442.h.
| #define CRPT_AES_STS_INBUFEMPTY_Msk (0x1ul << CRPT_AES_STS_INBUFEMPTY_Pos) |
CRPT_T::AES_STS: INBUFEMPTY Mask
Definition at line 6921 of file NUC472_442.h.
| #define CRPT_AES_STS_INBUFEMPTY_Pos (8) |
CRPT_T::AES_STS: INBUFEMPTY Position
Definition at line 6920 of file NUC472_442.h.
| #define CRPT_AES_STS_INBUFERR_Msk (0x1ul << CRPT_AES_STS_INBUFERR_Pos) |
CRPT_T::AES_STS: INBUFERR Mask
Definition at line 6927 of file NUC472_442.h.
| #define CRPT_AES_STS_INBUFERR_Pos (10) |
CRPT_T::AES_STS: INBUFERR Position
Definition at line 6926 of file NUC472_442.h.
| #define CRPT_AES_STS_INBUFFULL_Msk (0x1ul << CRPT_AES_STS_INBUFFULL_Pos) |
CRPT_T::AES_STS: INBUFFULL Mask
Definition at line 6924 of file NUC472_442.h.
| #define CRPT_AES_STS_INBUFFULL_Pos (9) |
CRPT_T::AES_STS: INBUFFULL Position
Definition at line 6923 of file NUC472_442.h.
| #define CRPT_AES_STS_OUTBUFEMPTY_Msk (0x1ul << CRPT_AES_STS_OUTBUFEMPTY_Pos) |
CRPT_T::AES_STS: OUTBUFEMPTY Mask
Definition at line 6933 of file NUC472_442.h.
| #define CRPT_AES_STS_OUTBUFEMPTY_Pos (16) |
CRPT_T::AES_STS: OUTBUFEMPTY Position
Definition at line 6932 of file NUC472_442.h.
| #define CRPT_AES_STS_OUTBUFERR_Msk (0x1ul << CRPT_AES_STS_OUTBUFERR_Pos) |
CRPT_T::AES_STS: OUTBUFERR Mask
Definition at line 6939 of file NUC472_442.h.
| #define CRPT_AES_STS_OUTBUFERR_Pos (18) |
CRPT_T::AES_STS: OUTBUFERR Position
Definition at line 6938 of file NUC472_442.h.
| #define CRPT_AES_STS_OUTBUFFULL_Msk (0x1ul << CRPT_AES_STS_OUTBUFFULL_Pos) |
CRPT_T::AES_STS: OUTBUFFULL Mask
Definition at line 6936 of file NUC472_442.h.
| #define CRPT_AES_STS_OUTBUFFULL_Pos (17) |
CRPT_T::AES_STS: OUTBUFFULL Position
Definition at line 6935 of file NUC472_442.h.
| #define CRPT_INTEN_AESERRIEN_Msk (0x1ul << CRPT_INTEN_AESERRIEN_Pos) |
CRPT_T::INTEN: AESERRIEN Mask
Definition at line 6783 of file NUC472_442.h.
| #define CRPT_INTEN_AESERRIEN_Pos (1) |
CRPT_T::INTEN: AESERRIEN Position
Definition at line 6782 of file NUC472_442.h.
| #define CRPT_INTEN_AESIEN_Msk (0x1ul << CRPT_INTEN_AESIEN_Pos) |
CRPT_T::INTEN: AESIEN Mask
Definition at line 6780 of file NUC472_442.h.
| #define CRPT_INTEN_AESIEN_Pos (0) |
@addtogroup CRPT_CONST CRPT Bit Field Definition Constant Definitions for CRPT Controller
CRPT_T::INTEN: AESIEN Position
Definition at line 6779 of file NUC472_442.h.
| #define CRPT_INTEN_PRNGIEN_Msk (0x1ul << CRPT_INTEN_PRNGIEN_Pos) |
CRPT_T::INTEN: PRNGIEN Mask
Definition at line 6792 of file NUC472_442.h.
| #define CRPT_INTEN_PRNGIEN_Pos (16) |
CRPT_T::INTEN: PRNGIEN Position
Definition at line 6791 of file NUC472_442.h.
| #define CRPT_INTEN_SHAERRIEN_Msk (0x1ul << CRPT_INTEN_SHAERRIEN_Pos) |
CRPT_T::INTEN: SHAERRIEN Mask
Definition at line 6798 of file NUC472_442.h.
| #define CRPT_INTEN_SHAERRIEN_Pos (25) |
CRPT_T::INTEN: SHAERRIEN Position
Definition at line 6797 of file NUC472_442.h.
| #define CRPT_INTEN_SHAIEN_Msk (0x1ul << CRPT_INTEN_SHAIEN_Pos) |
CRPT_T::INTEN: SHAIEN Mask
Definition at line 6795 of file NUC472_442.h.
| #define CRPT_INTEN_SHAIEN_Pos (24) |
CRPT_T::INTEN: SHAIEN Position
Definition at line 6794 of file NUC472_442.h.
| #define CRPT_INTEN_TDESERRIEN_Msk (0x1ul << CRPT_INTEN_TDESERRIEN_Pos) |
CRPT_T::INTEN: TDESERRIEN Mask
Definition at line 6789 of file NUC472_442.h.
| #define CRPT_INTEN_TDESERRIEN_Pos (9) |
CRPT_T::INTEN: TDESERRIEN Position
Definition at line 6788 of file NUC472_442.h.
| #define CRPT_INTEN_TDESIEN_Msk (0x1ul << CRPT_INTEN_TDESIEN_Pos) |
CRPT_T::INTEN: TDESIEN Mask
Definition at line 6786 of file NUC472_442.h.
| #define CRPT_INTEN_TDESIEN_Pos (8) |
CRPT_T::INTEN: TDESIEN Position
Definition at line 6785 of file NUC472_442.h.
| #define CRPT_INTSTS_AESERRIF_Msk (0x1ul << CRPT_INTSTS_AESERRIF_Pos) |
CRPT_T::INTSTS: AESERRIF Mask
Definition at line 6804 of file NUC472_442.h.
| #define CRPT_INTSTS_AESERRIF_Pos (1) |
CRPT_T::INTSTS: AESERRIF Position
Definition at line 6803 of file NUC472_442.h.
| #define CRPT_INTSTS_AESIF_Msk (0x1ul << CRPT_INTSTS_AESIF_Pos) |
CRPT_T::INTSTS: AESIF Mask
Definition at line 6801 of file NUC472_442.h.
| #define CRPT_INTSTS_AESIF_Pos (0) |
CRPT_T::INTSTS: AESIF Position
Definition at line 6800 of file NUC472_442.h.
| #define CRPT_INTSTS_PRNGIF_Msk (0x1ul << CRPT_INTSTS_PRNGIF_Pos) |
CRPT_T::INTSTS: PRNGIF Mask
Definition at line 6813 of file NUC472_442.h.
| #define CRPT_INTSTS_PRNGIF_Pos (16) |
CRPT_T::INTSTS: PRNGIF Position
Definition at line 6812 of file NUC472_442.h.
| #define CRPT_INTSTS_SHAERRIF_Msk (0x1ul << CRPT_INTSTS_SHAERRIF_Pos) |
CRPT_T::INTSTS: SHAERRIF Mask
Definition at line 6819 of file NUC472_442.h.
| #define CRPT_INTSTS_SHAERRIF_Pos (25) |
CRPT_T::INTSTS: SHAERRIF Position
Definition at line 6818 of file NUC472_442.h.
| #define CRPT_INTSTS_SHAIF_Msk (0x1ul << CRPT_INTSTS_SHAIF_Pos) |
CRPT_T::INTSTS: SHAIF Mask
Definition at line 6816 of file NUC472_442.h.
| #define CRPT_INTSTS_SHAIF_Pos (24) |
CRPT_T::INTSTS: SHAIF Position
Definition at line 6815 of file NUC472_442.h.
| #define CRPT_INTSTS_TDESERRIF_Msk (0x1ul << CRPT_INTSTS_TDESERRIF_Pos) |
CRPT_T::INTSTS: TDESERRIF Mask
Definition at line 6810 of file NUC472_442.h.
| #define CRPT_INTSTS_TDESERRIF_Pos (9) |
CRPT_T::INTSTS: TDESERRIF Position
Definition at line 6809 of file NUC472_442.h.
| #define CRPT_INTSTS_TDESIF_Msk (0x1ul << CRPT_INTSTS_TDESIF_Pos) |
CRPT_T::INTSTS: TDESIF Mask
Definition at line 6807 of file NUC472_442.h.
| #define CRPT_INTSTS_TDESIF_Pos (8) |
CRPT_T::INTSTS: TDESIF Position
Definition at line 6806 of file NUC472_442.h.
| #define CRPT_PRNG_CTL_BUSY_Msk (0x1ul << CRPT_PRNG_CTL_BUSY_Pos) |
CRPT_T::PRNG_CTL: BUSY Mask
Definition at line 6831 of file NUC472_442.h.
| #define CRPT_PRNG_CTL_BUSY_Pos (8) |
CRPT_T::PRNG_CTL: BUSY Position
Definition at line 6830 of file NUC472_442.h.
| #define CRPT_PRNG_CTL_KEYSZ_Msk (0x3ul << CRPT_PRNG_CTL_KEYSZ_Pos) |
CRPT_T::PRNG_CTL: KEYSZ Mask
Definition at line 6828 of file NUC472_442.h.
| #define CRPT_PRNG_CTL_KEYSZ_Pos (2) |
CRPT_T::PRNG_CTL: KEYSZ Position
Definition at line 6827 of file NUC472_442.h.
| #define CRPT_PRNG_CTL_SEEDRLD_Msk (0x1ul << CRPT_PRNG_CTL_SEEDRLD_Pos) |
CRPT_T::PRNG_CTL: SEEDRLD Mask
Definition at line 6825 of file NUC472_442.h.
| #define CRPT_PRNG_CTL_SEEDRLD_Pos (1) |
CRPT_T::PRNG_CTL: SEEDRLD Position
Definition at line 6824 of file NUC472_442.h.
| #define CRPT_PRNG_CTL_START_Msk (0x1ul << CRPT_PRNG_CTL_START_Pos) |
CRPT_T::PRNG_CTL: START Mask
Definition at line 6822 of file NUC472_442.h.
| #define CRPT_PRNG_CTL_START_Pos (0) |
CRPT_T::PRNG_CTL: START Position
Definition at line 6821 of file NUC472_442.h.
| #define CRPT_PRNG_KEY0_KEY_Msk (0xfffffffful << CRPT_PRNG_KEY0_KEY_Pos) |
CRPT_T::PRNG_KEY0: KEY Mask
Definition at line 6837 of file NUC472_442.h.
| #define CRPT_PRNG_KEY0_KEY_Pos (0) |
CRPT_T::PRNG_KEY0: KEY Position
Definition at line 6836 of file NUC472_442.h.
| #define CRPT_PRNG_KEY1_KEY_Msk (0xfffffffful << CRPT_PRNG_KEY1_KEY_Pos) |
CRPT_T::PRNG_KEY1: KEY Mask
Definition at line 6840 of file NUC472_442.h.
| #define CRPT_PRNG_KEY1_KEY_Pos (0) |
CRPT_T::PRNG_KEY1: KEY Position
Definition at line 6839 of file NUC472_442.h.
| #define CRPT_PRNG_KEY2_KEY_Msk (0xfffffffful << CRPT_PRNG_KEY2_KEY_Pos) |
CRPT_T::PRNG_KEY2: KEY Mask
Definition at line 6843 of file NUC472_442.h.
| #define CRPT_PRNG_KEY2_KEY_Pos (0) |
CRPT_T::PRNG_KEY2: KEY Position
Definition at line 6842 of file NUC472_442.h.
| #define CRPT_PRNG_KEY3_KEY_Msk (0xfffffffful << CRPT_PRNG_KEY3_KEY_Pos) |
CRPT_T::PRNG_KEY3: KEY Mask
Definition at line 6846 of file NUC472_442.h.
| #define CRPT_PRNG_KEY3_KEY_Pos (0) |
CRPT_T::PRNG_KEY3: KEY Position
Definition at line 6845 of file NUC472_442.h.
| #define CRPT_PRNG_KEY4_KEY_Msk (0xfffffffful << CRPT_PRNG_KEY4_KEY_Pos) |
CRPT_T::PRNG_KEY4: KEY Mask
Definition at line 6849 of file NUC472_442.h.
| #define CRPT_PRNG_KEY4_KEY_Pos (0) |
CRPT_T::PRNG_KEY4: KEY Position
Definition at line 6848 of file NUC472_442.h.
| #define CRPT_PRNG_KEY5_KEY_Msk (0xfffffffful << CRPT_PRNG_KEY5_KEY_Pos) |
CRPT_T::PRNG_KEY5: KEY Mask
Definition at line 6852 of file NUC472_442.h.
| #define CRPT_PRNG_KEY5_KEY_Pos (0) |
CRPT_T::PRNG_KEY5: KEY Position
Definition at line 6851 of file NUC472_442.h.
| #define CRPT_PRNG_KEY6_KEY_Msk (0xfffffffful << CRPT_PRNG_KEY6_KEY_Pos) |
CRPT_T::PRNG_KEY6: KEY Mask
Definition at line 6855 of file NUC472_442.h.
| #define CRPT_PRNG_KEY6_KEY_Pos (0) |
CRPT_T::PRNG_KEY6: KEY Position
Definition at line 6854 of file NUC472_442.h.
| #define CRPT_PRNG_KEY7_KEY_Msk (0xfffffffful << CRPT_PRNG_KEY7_KEY_Pos) |
CRPT_T::PRNG_KEY7: KEY Mask
Definition at line 6858 of file NUC472_442.h.
| #define CRPT_PRNG_KEY7_KEY_Pos (0) |
CRPT_T::PRNG_KEY7: KEY Position
Definition at line 6857 of file NUC472_442.h.
| #define CRPT_PRNG_SEED_SEED_Msk (0xfffffffful << CRPT_PRNG_SEED_SEED_Pos) |
CRPT_T::PRNG_SEED: SEED Mask
Definition at line 6834 of file NUC472_442.h.
| #define CRPT_PRNG_SEED_SEED_Pos (0) |
CRPT_T::PRNG_SEED: SEED Position
Definition at line 6833 of file NUC472_442.h.
| #define CRPT_SHA_CTL_DMAEN_Msk (0x1ul << CRPT_SHA_CTL_DMAEN_Pos) |
CRPT_T::SHA_CTL: DMAEN Mask
Definition at line 7347 of file NUC472_442.h.
| #define CRPT_SHA_CTL_DMAEN_Pos (7) |
CRPT_T::SHA_CTL: DMAEN Position
Definition at line 7346 of file NUC472_442.h.
| #define CRPT_SHA_CTL_DMALAST_Msk (0x1ul << CRPT_SHA_CTL_DMALAST_Pos) |
CRPT_T::SHA_CTL: DMALAST Mask
Definition at line 7344 of file NUC472_442.h.
| #define CRPT_SHA_CTL_DMALAST_Pos (5) |
CRPT_T::SHA_CTL: DMALAST Position
Definition at line 7343 of file NUC472_442.h.
| #define CRPT_SHA_CTL_INSWAP_Msk (0x1ul << CRPT_SHA_CTL_INSWAP_Pos) |
CRPT_T::SHA_CTL: INSWAP Mask
Definition at line 7356 of file NUC472_442.h.
| #define CRPT_SHA_CTL_INSWAP_Pos (23) |
CRPT_T::SHA_CTL: INSWAP Position
Definition at line 7355 of file NUC472_442.h.
| #define CRPT_SHA_CTL_OPMODE_Msk (0x7ul << CRPT_SHA_CTL_OPMODE_Pos) |
CRPT_T::SHA_CTL: OPMODE Mask
Definition at line 7350 of file NUC472_442.h.
| #define CRPT_SHA_CTL_OPMODE_Pos (8) |
CRPT_T::SHA_CTL: OPMODE Position
Definition at line 7349 of file NUC472_442.h.
| #define CRPT_SHA_CTL_OUTSWAP_Msk (0x1ul << CRPT_SHA_CTL_OUTSWAP_Pos) |
CRPT_T::SHA_CTL: OUTSWAP Mask
Definition at line 7353 of file NUC472_442.h.
| #define CRPT_SHA_CTL_OUTSWAP_Pos (22) |
CRPT_T::SHA_CTL: OUTSWAP Position
Definition at line 7352 of file NUC472_442.h.
| #define CRPT_SHA_CTL_START_Msk (0x1ul << CRPT_SHA_CTL_START_Pos) |
CRPT_T::SHA_CTL: START Mask
Definition at line 7338 of file NUC472_442.h.
| #define CRPT_SHA_CTL_START_Pos (0) |
CRPT_T::SHA_CTL: START Position
Definition at line 7337 of file NUC472_442.h.
| #define CRPT_SHA_CTL_STOP_Msk (0x1ul << CRPT_SHA_CTL_STOP_Pos) |
CRPT_T::SHA_CTL: STOP Mask
Definition at line 7341 of file NUC472_442.h.
| #define CRPT_SHA_CTL_STOP_Pos (1) |
CRPT_T::SHA_CTL: STOP Position
Definition at line 7340 of file NUC472_442.h.
| #define CRPT_SHA_DATIN_DATIN_Msk (0xfffffffful << CRPT_SHA_DATIN_DATIN_Pos) |
CRPT_T::SHA_DATIN: DATIN Mask
Definition at line 7404 of file NUC472_442.h.
| #define CRPT_SHA_DATIN_DATIN_Pos (0) |
CRPT_T::SHA_DATIN: DATIN Position
Definition at line 7403 of file NUC472_442.h.
| #define CRPT_SHA_DGST0_DGST_Msk (0xfffffffful << CRPT_SHA_DGST0_DGST_Pos) |
CRPT_T::SHA_DGST0: DGST Mask
Definition at line 7371 of file NUC472_442.h.
| #define CRPT_SHA_DGST0_DGST_Pos (0) |
CRPT_T::SHA_DGST0: DGST Position
Definition at line 7370 of file NUC472_442.h.
| #define CRPT_SHA_DGST1_DGST_Msk (0xfffffffful << CRPT_SHA_DGST1_DGST_Pos) |
CRPT_T::SHA_DGST1: DGST Mask
Definition at line 7374 of file NUC472_442.h.
| #define CRPT_SHA_DGST1_DGST_Pos (0) |
CRPT_T::SHA_DGST1: DGST Position
Definition at line 7373 of file NUC472_442.h.
| #define CRPT_SHA_DGST2_DGST_Msk (0xfffffffful << CRPT_SHA_DGST2_DGST_Pos) |
CRPT_T::SHA_DGST2: DGST Mask
Definition at line 7377 of file NUC472_442.h.
| #define CRPT_SHA_DGST2_DGST_Pos (0) |
CRPT_T::SHA_DGST2: DGST Position
Definition at line 7376 of file NUC472_442.h.
| #define CRPT_SHA_DGST3_DGST_Msk (0xfffffffful << CRPT_SHA_DGST3_DGST_Pos) |
CRPT_T::SHA_DGST3: DGST Mask
Definition at line 7380 of file NUC472_442.h.
| #define CRPT_SHA_DGST3_DGST_Pos (0) |
CRPT_T::SHA_DGST3: DGST Position
Definition at line 7379 of file NUC472_442.h.
| #define CRPT_SHA_DGST4_DGST_Msk (0xfffffffful << CRPT_SHA_DGST4_DGST_Pos) |
CRPT_T::SHA_DGST4: DGST Mask
Definition at line 7383 of file NUC472_442.h.
| #define CRPT_SHA_DGST4_DGST_Pos (0) |
CRPT_T::SHA_DGST4: DGST Position
Definition at line 7382 of file NUC472_442.h.
| #define CRPT_SHA_DGST5_DGST_Msk (0xfffffffful << CRPT_SHA_DGST5_DGST_Pos) |
CRPT_T::SHA_DGST5: DGST Mask
Definition at line 7386 of file NUC472_442.h.
| #define CRPT_SHA_DGST5_DGST_Pos (0) |
CRPT_T::SHA_DGST5: DGST Position
Definition at line 7385 of file NUC472_442.h.
| #define CRPT_SHA_DGST6_DGST_Msk (0xfffffffful << CRPT_SHA_DGST6_DGST_Pos) |
CRPT_T::SHA_DGST6: DGST Mask
Definition at line 7389 of file NUC472_442.h.
| #define CRPT_SHA_DGST6_DGST_Pos (0) |
CRPT_T::SHA_DGST6: DGST Position
Definition at line 7388 of file NUC472_442.h.
| #define CRPT_SHA_DGST7_DGST_Msk (0xfffffffful << CRPT_SHA_DGST7_DGST_Pos) |
CRPT_T::SHA_DGST7: DGST Mask
Definition at line 7392 of file NUC472_442.h.
| #define CRPT_SHA_DGST7_DGST_Pos (0) |
CRPT_T::SHA_DGST7: DGST Position
Definition at line 7391 of file NUC472_442.h.
| #define CRPT_SHA_DMACNT_DMACNT_Msk (0xfffffffful << CRPT_SHA_DMACNT_DMACNT_Pos) |
CRPT_T::SHA_DMACNT: DMACNT Mask
Definition at line 7401 of file NUC472_442.h.
| #define CRPT_SHA_DMACNT_DMACNT_Pos (0) |
CRPT_T::SHA_DMACNT: DMACNT Position
Definition at line 7400 of file NUC472_442.h.
| #define CRPT_SHA_KEYCNT_KEYCNT_Msk (0xfffffffful << CRPT_SHA_KEYCNT_KEYCNT_Pos) |
CRPT_T::SHA_KEYCNT: KEYCNT Mask
Definition at line 7395 of file NUC472_442.h.
| #define CRPT_SHA_KEYCNT_KEYCNT_Pos (0) |
CRPT_T::SHA_KEYCNT: KEYCNT Position
Definition at line 7394 of file NUC472_442.h.
| #define CRPT_SHA_SADDR_SADDR_Msk (0xfffffffful << CRPT_SHA_SADDR_SADDR_Pos) |
CRPT_T::SHA_SADDR: SADDR Mask
Definition at line 7398 of file NUC472_442.h.
| #define CRPT_SHA_SADDR_SADDR_Pos (0) |
CRPT_T::SHA_SADDR: SADDR Position
Definition at line 7397 of file NUC472_442.h.
| #define CRPT_SHA_STS_BUSY_Msk (0x1ul << CRPT_SHA_STS_BUSY_Pos) |
CRPT_T::SHA_STS: BUSY Mask
Definition at line 7359 of file NUC472_442.h.
| #define CRPT_SHA_STS_BUSY_Pos (0) |
CRPT_T::SHA_STS: BUSY Position
Definition at line 7358 of file NUC472_442.h.
| #define CRPT_SHA_STS_DATINREQ_Msk (0x1ul << CRPT_SHA_STS_DATINREQ_Pos) |
CRPT_T::SHA_STS: DATINREQ Mask
Definition at line 7368 of file NUC472_442.h.
| #define CRPT_SHA_STS_DATINREQ_Pos (16) |
CRPT_T::SHA_STS: DATINREQ Position
Definition at line 7367 of file NUC472_442.h.
| #define CRPT_SHA_STS_DMABUSY_Msk (0x1ul << CRPT_SHA_STS_DMABUSY_Pos) |
CRPT_T::SHA_STS: DMABUSY Mask
Definition at line 7362 of file NUC472_442.h.
| #define CRPT_SHA_STS_DMABUSY_Pos (1) |
CRPT_T::SHA_STS: DMABUSY Position
Definition at line 7361 of file NUC472_442.h.
| #define CRPT_SHA_STS_DMAERR_Msk (0x1ul << CRPT_SHA_STS_DMAERR_Pos) |
CRPT_T::SHA_STS: DMAERR Mask
Definition at line 7365 of file NUC472_442.h.
| #define CRPT_SHA_STS_DMAERR_Pos (8) |
CRPT_T::SHA_STS: DMAERR Position
Definition at line 7364 of file NUC472_442.h.
| #define CRPT_TDES0_CNT_CNT_Msk (0xfffffffful << CRPT_TDES0_CNT_CNT_Pos) |
CRPT_T::TDES0_CNT: CNT Mask
Definition at line 7230 of file NUC472_442.h.
| #define CRPT_TDES0_CNT_CNT_Pos (0) |
CRPT_T::TDES0_CNT: CNT Position
Definition at line 7229 of file NUC472_442.h.
| #define CRPT_TDES0_DADDR_DADDR_Msk (0xfffffffful << CRPT_TDES0_DADDR_DADDR_Pos) |
CRPT_T::TDES0_DADDR: DADDR Mask
Definition at line 7227 of file NUC472_442.h.
| #define CRPT_TDES0_DADDR_DADDR_Pos (0) |
CRPT_T::TDES0_DADDR: DADDR Position
Definition at line 7226 of file NUC472_442.h.
| #define CRPT_TDES0_IVH_IV_Msk (0xfffffffful << CRPT_TDES0_IVH_IV_Pos) |
CRPT_T::TDES0_IVH: IV Mask
Definition at line 7218 of file NUC472_442.h.
| #define CRPT_TDES0_IVH_IV_Pos (0) |
CRPT_T::TDES0_IVH: IV Position
Definition at line 7217 of file NUC472_442.h.
| #define CRPT_TDES0_IVL_IV_Msk (0xfffffffful << CRPT_TDES0_IVL_IV_Pos) |
CRPT_T::TDES0_IVL: IV Mask
Definition at line 7221 of file NUC472_442.h.
| #define CRPT_TDES0_IVL_IV_Pos (0) |
CRPT_T::TDES0_IVL: IV Position
Definition at line 7220 of file NUC472_442.h.
| #define CRPT_TDES0_KEY1H_KEY_Msk (0xfffffffful << CRPT_TDES0_KEY1H_KEY_Pos) |
CRPT_T::TDES0_KEY1H: KEY Mask
Definition at line 7200 of file NUC472_442.h.
| #define CRPT_TDES0_KEY1H_KEY_Pos (0) |
CRPT_T::TDES0_KEY1H: KEY Position
Definition at line 7199 of file NUC472_442.h.
| #define CRPT_TDES0_KEY1L_KEY_Msk (0xfffffffful << CRPT_TDES0_KEY1L_KEY_Pos) |
CRPT_T::TDES0_KEY1L: KEY Mask
Definition at line 7203 of file NUC472_442.h.
| #define CRPT_TDES0_KEY1L_KEY_Pos (0) |
CRPT_T::TDES0_KEY1L: KEY Position
Definition at line 7202 of file NUC472_442.h.
| #define CRPT_TDES0_KEY2H_KEY_Msk (0xfffffffful << CRPT_TDES0_KEY2H_KEY_Pos) |
CRPT_T::TDES0_KEY2H: KEY Mask
Definition at line 7206 of file NUC472_442.h.
| #define CRPT_TDES0_KEY2H_KEY_Pos (0) |
CRPT_T::TDES0_KEY2H: KEY Position
Definition at line 7205 of file NUC472_442.h.
| #define CRPT_TDES0_KEY2L_KEY_Msk (0xfffffffful << CRPT_TDES0_KEY2L_KEY_Pos) |
CRPT_T::TDES0_KEY2L: KEY Mask
Definition at line 7209 of file NUC472_442.h.
| #define CRPT_TDES0_KEY2L_KEY_Pos (0) |
CRPT_T::TDES0_KEY2L: KEY Position
Definition at line 7208 of file NUC472_442.h.
| #define CRPT_TDES0_KEY3H_KEY_Msk (0xfffffffful << CRPT_TDES0_KEY3H_KEY_Pos) |
CRPT_T::TDES0_KEY3H: KEY Mask
Definition at line 7212 of file NUC472_442.h.
| #define CRPT_TDES0_KEY3H_KEY_Pos (0) |
CRPT_T::TDES0_KEY3H: KEY Position
Definition at line 7211 of file NUC472_442.h.
| #define CRPT_TDES0_KEY3L_KEY_Msk (0xfffffffful << CRPT_TDES0_KEY3L_KEY_Pos) |
CRPT_T::TDES0_KEY3L: KEY Mask
Definition at line 7215 of file NUC472_442.h.
| #define CRPT_TDES0_KEY3L_KEY_Pos (0) |
CRPT_T::TDES0_KEY3L: KEY Position
Definition at line 7214 of file NUC472_442.h.
| #define CRPT_TDES0_SADDR_SADDR_Msk (0xfffffffful << CRPT_TDES0_SADDR_SADDR_Pos) |
CRPT_T::TDES0_SADDR: SADDR Mask
Definition at line 7224 of file NUC472_442.h.
| #define CRPT_TDES0_SADDR_SADDR_Pos (0) |
CRPT_T::TDES0_SADDR: SADDR Position
Definition at line 7223 of file NUC472_442.h.
| #define CRPT_TDES1_CNT_CNT_Msk (0xfffffffful << CRPT_TDES1_CNT_CNT_Pos) |
CRPT_T::TDES1_CNT: CNT Mask
Definition at line 7269 of file NUC472_442.h.
| #define CRPT_TDES1_CNT_CNT_Pos (0) |
CRPT_T::TDES1_CNT: CNT Position
Definition at line 7268 of file NUC472_442.h.
| #define CRPT_TDES1_DADDR_DADDR_Msk (0xfffffffful << CRPT_TDES1_DADDR_DADDR_Pos) |
CRPT_T::TDES1_DADDR: DADDR Mask
Definition at line 7266 of file NUC472_442.h.
| #define CRPT_TDES1_DADDR_DADDR_Pos (0) |
CRPT_T::TDES1_DADDR: DADDR Position
Definition at line 7265 of file NUC472_442.h.
| #define CRPT_TDES1_IVH_IV_Msk (0xfffffffful << CRPT_TDES1_IVH_IV_Pos) |
CRPT_T::TDES1_IVH: IV Mask
Definition at line 7257 of file NUC472_442.h.
| #define CRPT_TDES1_IVH_IV_Pos (0) |
CRPT_T::TDES1_IVH: IV Position
Definition at line 7256 of file NUC472_442.h.
| #define CRPT_TDES1_IVL_IV_Msk (0xfffffffful << CRPT_TDES1_IVL_IV_Pos) |
CRPT_T::TDES1_IVL: IV Mask
Definition at line 7260 of file NUC472_442.h.
| #define CRPT_TDES1_IVL_IV_Pos (0) |
CRPT_T::TDES1_IVL: IV Position
Definition at line 7259 of file NUC472_442.h.
| #define CRPT_TDES1_KEY1H_KEY_Msk (0xfffffffful << CRPT_TDES1_KEY1H_KEY_Pos) |
CRPT_T::TDES1_KEY1H: KEY Mask
Definition at line 7239 of file NUC472_442.h.
| #define CRPT_TDES1_KEY1H_KEY_Pos (0) |
CRPT_T::TDES1_KEY1H: KEY Position
Definition at line 7238 of file NUC472_442.h.
| #define CRPT_TDES1_KEY1L_KEY_Msk (0xfffffffful << CRPT_TDES1_KEY1L_KEY_Pos) |
CRPT_T::TDES1_KEY1L: KEY Mask
Definition at line 7242 of file NUC472_442.h.
| #define CRPT_TDES1_KEY1L_KEYL_Pos (0) |
CRPT_T::TDES1_KEY1L: KEY Position
Definition at line 7241 of file NUC472_442.h.
| #define CRPT_TDES1_KEY2H_KEY_Msk (0xfffffffful << CRPT_TDES1_KEY2H_KEY_Pos) |
CRPT_T::TDES1_KEY2H: KEY Mask
Definition at line 7245 of file NUC472_442.h.
| #define CRPT_TDES1_KEY2H_KEY_Pos (0) |
CRPT_T::TDES1_KEY2H: KEY Position
Definition at line 7244 of file NUC472_442.h.
| #define CRPT_TDES1_KEY2L_KEY_Msk (0xfffffffful << CRPT_TDES1_KEY2L_KEY_Pos) |
CRPT_T::TDES1_KEY2L: KEY Mask
Definition at line 7248 of file NUC472_442.h.
| #define CRPT_TDES1_KEY2L_KEY_Pos (0) |
CRPT_T::TDES1_KEY2L: KEY Position
Definition at line 7247 of file NUC472_442.h.
| #define CRPT_TDES1_KEY3H_KEY_Msk (0xfffffffful << CRPT_TDES1_KEY3H_KEY_Pos) |
CRPT_T::TDES1_KEY3H: KEY Mask
Definition at line 7251 of file NUC472_442.h.
| #define CRPT_TDES1_KEY3H_KEY_Pos (0) |
CRPT_T::TDES1_KEY3H: KEY Position
Definition at line 7250 of file NUC472_442.h.
| #define CRPT_TDES1_KEY3L_KEY_Msk (0xfffffffful << CRPT_TDES1_KEY3L_KEY_Pos) |
CRPT_T::TDES1_KEY3L: KEY Mask
Definition at line 7254 of file NUC472_442.h.
| #define CRPT_TDES1_KEY3L_KEY_Pos (0) |
CRPT_T::TDES1_KEY3L: KEY Position
Definition at line 7253 of file NUC472_442.h.
| #define CRPT_TDES1_SADDR_SADDR_Msk (0xfffffffful << CRPT_TDES1_SADDR_SADDR_Pos) |
CRPT_T::TDES1_SADDR: SADDR Mask
Definition at line 7263 of file NUC472_442.h.
| #define CRPT_TDES1_SADDR_SADDR_Pos (0) |
CRPT_T::TDES1_SADDR: SADDR Position
Definition at line 7262 of file NUC472_442.h.
| #define CRPT_TDES2_CNT_CNT_Msk (0xfffffffful << CRPT_TDES2_CNT_CNT_Pos) |
CRPT_T::TDES2_CNT: CNT Mask
Definition at line 7302 of file NUC472_442.h.
| #define CRPT_TDES2_CNT_CNT_Pos (0) |
CRPT_T::TDES2_CNT: CNT Position
Definition at line 7301 of file NUC472_442.h.
| #define CRPT_TDES2_DADDR_DADDR_Msk (0xfffffffful << CRPT_TDES2_DADDR_DADDR_Pos) |
CRPT_T::TDES2_DADDR: DADDR Mask
Definition at line 7299 of file NUC472_442.h.
| #define CRPT_TDES2_DADDR_DADDR_Pos (0) |
CRPT_T::TDES2_DADDR: DADDR Position
Definition at line 7298 of file NUC472_442.h.
| #define CRPT_TDES2_IVH_IV_Msk (0xfffffffful << CRPT_TDES2_IVH_IV_Pos) |
CRPT_T::TDES2_IVH: IV Mask
Definition at line 7290 of file NUC472_442.h.
| #define CRPT_TDES2_IVH_IV_Pos (0) |
CRPT_T::TDES2_IVH: IV Position
Definition at line 7289 of file NUC472_442.h.
| #define CRPT_TDES2_IVL_IV_Msk (0xfffffffful << CRPT_TDES2_IVL_IV_Pos) |
CRPT_T::TDES2_IVL: IV Mask
Definition at line 7293 of file NUC472_442.h.
| #define CRPT_TDES2_IVL_IV_Pos (0) |
CRPT_T::TDES2_IVL: IV Position
Definition at line 7292 of file NUC472_442.h.
| #define CRPT_TDES2_KEY1H_KEY_Msk (0xfffffffful << CRPT_TDES2_KEY1H_KEY_Pos) |
CRPT_T::TDES2_KEY1H: KEY Mask
Definition at line 7272 of file NUC472_442.h.
| #define CRPT_TDES2_KEY1H_KEY_Pos (0) |
CRPT_T::TDES2_KEY1H: KEY Position
Definition at line 7271 of file NUC472_442.h.
| #define CRPT_TDES2_KEY1L_KEY_Msk (0xfffffffful << CRPT_TDES2_KEY1L_KEY_Pos) |
CRPT_T::TDES2_KEY1L: KEY Mask
Definition at line 7275 of file NUC472_442.h.
| #define CRPT_TDES2_KEY1L_KEY_Pos (0) |
CRPT_T::TDES2_KEY1L: KEY Position
Definition at line 7274 of file NUC472_442.h.
| #define CRPT_TDES2_KEY2H_KEY_Msk (0xfffffffful << CRPT_TDES2_KEY2H_KEY_Pos) |
CRPT_T::TDES2_KEY2H: KEY Mask
Definition at line 7278 of file NUC472_442.h.
| #define CRPT_TDES2_KEY2H_KEY_Pos (0) |
CRPT_T::TDES2_KEY2H: KEY Position
Definition at line 7277 of file NUC472_442.h.
| #define CRPT_TDES2_KEY2L_KEY_Msk (0xfffffffful << CRPT_TDES2_KEY2L_KEY_Pos) |
CRPT_T::TDES2_KEY2L: KEY Mask
Definition at line 7281 of file NUC472_442.h.
| #define CRPT_TDES2_KEY2L_KEY_Pos (0) |
CRPT_T::TDES2_KEY2L: KEY Position
Definition at line 7280 of file NUC472_442.h.
| #define CRPT_TDES2_KEY3H_KEY_Msk (0xfffffffful << CRPT_TDES2_KEY3H_KEY_Pos) |
CRPT_T::TDES2_KEY3H: KEY Mask
Definition at line 7284 of file NUC472_442.h.
| #define CRPT_TDES2_KEY3H_KEY_Pos (0) |
CRPT_T::TDES2_KEY3H: KEY Position
Definition at line 7283 of file NUC472_442.h.
| #define CRPT_TDES2_KEY3L_KEY_Msk (0xfffffffful << CRPT_TDES2_KEY3L_KEY_Pos) |
CRPT_T::TDES2_KEY3L: KEY Mask
Definition at line 7287 of file NUC472_442.h.
| #define CRPT_TDES2_KEY3L_KEY_Pos (0) |
CRPT_T::TDES2_KEY3L: KEY Position
Definition at line 7286 of file NUC472_442.h.
| #define CRPT_TDES2_SADDR_SADDR_Msk (0xfffffffful << CRPT_TDES2_SADDR_SADDR_Pos) |
CRPT_T::TDES2_SADDR: SADDR Mask
Definition at line 7296 of file NUC472_442.h.
| #define CRPT_TDES2_SADDR_SADDR_Pos (0) |
CRPT_T::TDES2_SADDR: SADDR Position
Definition at line 7295 of file NUC472_442.h.
| #define CRPT_TDES3_CNT_CNT_Msk (0xfffffffful << CRPT_TDES3_CNT_CNT_Pos) |
CRPT_T::TDES3_CNT: CNT Mask
Definition at line 7335 of file NUC472_442.h.
| #define CRPT_TDES3_CNT_CNT_Pos (0) |
CRPT_T::TDES3_CNT: CNT Position
Definition at line 7334 of file NUC472_442.h.
| #define CRPT_TDES3_DADDR_DADDR_Msk (0xfffffffful << CRPT_TDES3_DADDR_DADDR_Pos) |
CRPT_T::TDES3_DADDR: DADDR Mask
Definition at line 7332 of file NUC472_442.h.
| #define CRPT_TDES3_DADDR_DADDR_Pos (0) |
CRPT_T::TDES3_DADDR: DADDR Position
Definition at line 7331 of file NUC472_442.h.
| #define CRPT_TDES3_IVH_IV_Msk (0xfffffffful << CRPT_TDES3_IVH_IV_Pos) |
CRPT_T::TDES3_IVH: IV Mask
Definition at line 7323 of file NUC472_442.h.
| #define CRPT_TDES3_IVH_IV_Pos (0) |
CRPT_T::TDES3_IVH: IV Position
Definition at line 7322 of file NUC472_442.h.
| #define CRPT_TDES3_IVL_IV_Msk (0xfffffffful << CRPT_TDES3_IVL_IV_Pos) |
CRPT_T::TDES3_IVL: IV Mask
Definition at line 7326 of file NUC472_442.h.
| #define CRPT_TDES3_IVL_IV_Pos (0) |
CRPT_T::TDES3_IVL: IV Position
Definition at line 7325 of file NUC472_442.h.
| #define CRPT_TDES3_KEY1H_KEY_Msk (0xfffffffful << CRPT_TDES3_KEY1H_KEY_Pos) |
CRPT_T::TDES3_KEY1H: KEY Mask
Definition at line 7305 of file NUC472_442.h.
| #define CRPT_TDES3_KEY1H_KEY_Pos (0) |
CRPT_T::TDES3_KEY1H: KEY Position
Definition at line 7304 of file NUC472_442.h.
| #define CRPT_TDES3_KEY1L_KEY_Msk (0xfffffffful << CRPT_TDES3_KEY1L_KEY_Pos) |
CRPT_T::TDES3_KEY1L: KEY Mask
Definition at line 7308 of file NUC472_442.h.
| #define CRPT_TDES3_KEY1L_KEY_Pos (0) |
CRPT_T::TDES3_KEY1L: KEY Position
Definition at line 7307 of file NUC472_442.h.
| #define CRPT_TDES3_KEY2H_KEY_Msk (0xfffffffful << CRPT_TDES3_KEY2H_KEY_Pos) |
CRPT_T::TDES3_KEY2H: KEY Mask
Definition at line 7311 of file NUC472_442.h.
| #define CRPT_TDES3_KEY2H_KEY_Pos (0) |
CRPT_T::TDES3_KEY2H: KEY Position
Definition at line 7310 of file NUC472_442.h.
| #define CRPT_TDES3_KEY2L_KEY_Msk (0xfffffffful << CRPT_TDES3_KEY2L_KEY_Pos) |
CRPT_T::TDES3_KEY2L: KEY Mask
Definition at line 7314 of file NUC472_442.h.
| #define CRPT_TDES3_KEY2L_KEY_Pos (0) |
CRPT_T::TDES3_KEY2L: KEY Position
Definition at line 7313 of file NUC472_442.h.
| #define CRPT_TDES3_KEY3H_KEY_Msk (0xfffffffful << CRPT_TDES3_KEY3H_KEY_Pos) |
CRPT_T::TDES3_KEY3H: KEY Mask
Definition at line 7317 of file NUC472_442.h.
| #define CRPT_TDES3_KEY3H_KEY_Pos (0) |
CRPT_T::TDES3_KEY3H: KEY Position
Definition at line 7316 of file NUC472_442.h.
| #define CRPT_TDES3_KEY3L_KEY_Msk (0xfffffffful << CRPT_TDES3_KEY3L_KEY_Pos) |
CRPT_T::TDES3_KEY3L: KEY Mask
Definition at line 7320 of file NUC472_442.h.
| #define CRPT_TDES3_KEY3L_KEY_Pos (0) |
CRPT_T::TDES3_KEY3L: KEY Position
Definition at line 7319 of file NUC472_442.h.
| #define CRPT_TDES3_SADDR_SADDR_Msk (0xfffffffful << CRPT_TDES3_SADDR_SADDR_Pos) |
CRPT_T::TDES3_SADDR: SADDR Mask
Definition at line 7329 of file NUC472_442.h.
| #define CRPT_TDES3_SADDR_SADDR_Pos (0) |
CRPT_T::TDES3_SADDR: SADDR Position
Definition at line 7328 of file NUC472_442.h.
| #define CRPT_TDES_CTL_3KEYS_Msk (0x1ul << CRPT_TDES_CTL_3KEYS_Pos) |
CRPT_T::TDES_CTL: 3KEYS Mask
Definition at line 7140 of file NUC472_442.h.
| #define CRPT_TDES_CTL_3KEYS_Pos (3) |
CRPT_T::TDES_CTL: 3KEYS Position
Definition at line 7139 of file NUC472_442.h.
| #define CRPT_TDES_CTL_BLKSWAP_Msk (0x1ul << CRPT_TDES_CTL_BLKSWAP_Pos) |
CRPT_T::TDES_CTL: BLKSWAP Mask
Definition at line 7158 of file NUC472_442.h.
| #define CRPT_TDES_CTL_BLKSWAP_Pos (21) |
CRPT_T::TDES_CTL: BLKSWAP Position
Definition at line 7157 of file NUC472_442.h.
| #define CRPT_TDES_CTL_CHANNEL_Msk (0x3ul << CRPT_TDES_CTL_CHANNEL_Pos) |
CRPT_T::TDES_CTL: CHANNEL Mask
Definition at line 7167 of file NUC472_442.h.
| #define CRPT_TDES_CTL_CHANNEL_Pos (24) |
CRPT_T::TDES_CTL: CHANNEL Position
Definition at line 7166 of file NUC472_442.h.
| #define CRPT_TDES_CTL_DMACSCAD_Msk (0x1ul << CRPT_TDES_CTL_DMACSCAD_Pos) |
CRPT_T::TDES_CTL: DMACSCAD Mask
Definition at line 7146 of file NUC472_442.h.
| #define CRPT_TDES_CTL_DMACSCAD_Pos (6) |
CRPT_T::TDES_CTL: DMACSCAD Position
Definition at line 7145 of file NUC472_442.h.
| #define CRPT_TDES_CTL_DMAEN_Msk (0x1ul << CRPT_TDES_CTL_DMAEN_Pos) |
CRPT_T::TDES_CTL: DMAEN Mask
Definition at line 7149 of file NUC472_442.h.
| #define CRPT_TDES_CTL_DMAEN_Pos (7) |
CRPT_T::TDES_CTL: DMAEN Position
Definition at line 7148 of file NUC472_442.h.
| #define CRPT_TDES_CTL_DMALAST_Msk (0x1ul << CRPT_TDES_CTL_DMALAST_Pos) |
CRPT_T::TDES_CTL: DMALAST Mask
Definition at line 7143 of file NUC472_442.h.
| #define CRPT_TDES_CTL_DMALAST_Pos (5) |
CRPT_T::TDES_CTL: DMALAST Position
Definition at line 7142 of file NUC472_442.h.
| #define CRPT_TDES_CTL_ENCRPT_Msk (0x1ul << CRPT_TDES_CTL_ENCRPT_Pos) |
CRPT_T::TDES_CTL: ENCRPT Mask
Definition at line 7155 of file NUC472_442.h.
| #define CRPT_TDES_CTL_ENCRPT_Pos (16) |
CRPT_T::TDES_CTL: ENCRPT Position
Definition at line 7154 of file NUC472_442.h.
| #define CRPT_TDES_CTL_INSWAP_Msk (0x1ul << CRPT_TDES_CTL_INSWAP_Pos) |
CRPT_T::TDES_CTL: INSWAP Mask
Definition at line 7164 of file NUC472_442.h.
| #define CRPT_TDES_CTL_INSWAP_Pos (23) |
CRPT_T::TDES_CTL: INSWAP Position
Definition at line 7163 of file NUC472_442.h.
| #define CRPT_TDES_CTL_KEYPRT_Msk (0x1ul << CRPT_TDES_CTL_KEYPRT_Pos) |
CRPT_T::TDES_CTL: KEYPRT Mask
Definition at line 7173 of file NUC472_442.h.
| #define CRPT_TDES_CTL_KEYPRT_Pos (31) |
CRPT_T::TDES_CTL: KEYPRT Position
Definition at line 7172 of file NUC472_442.h.
| #define CRPT_TDES_CTL_KEYUNPRT_Msk (0x1ful << CRPT_TDES_CTL_KEYUNPRT_Pos) |
CRPT_T::TDES_CTL: KEYUNPRT Mask
Definition at line 7170 of file NUC472_442.h.
| #define CRPT_TDES_CTL_KEYUNPRT_Pos (26) |
CRPT_T::TDES_CTL: KEYUNPRT Position
Definition at line 7169 of file NUC472_442.h.
| #define CRPT_TDES_CTL_OPMODE_Msk (0x7ul << CRPT_TDES_CTL_OPMODE_Pos) |
CRPT_T::TDES_CTL: OPMODE Mask
Definition at line 7152 of file NUC472_442.h.
| #define CRPT_TDES_CTL_OPMODE_Pos (8) |
CRPT_T::TDES_CTL: OPMODE Position
Definition at line 7151 of file NUC472_442.h.
| #define CRPT_TDES_CTL_OUTSWAP_Msk (0x1ul << CRPT_TDES_CTL_OUTSWAP_Pos) |
CRPT_T::TDES_CTL: OUTSWAP Mask
Definition at line 7161 of file NUC472_442.h.
| #define CRPT_TDES_CTL_OUTSWAP_Pos (22) |
CRPT_T::TDES_CTL: OUTSWAP Position
Definition at line 7160 of file NUC472_442.h.
| #define CRPT_TDES_CTL_START_Msk (0x1ul << CRPT_TDES_CTL_START_Pos) |
CRPT_T::TDES_CTL: START Mask
Definition at line 7131 of file NUC472_442.h.
| #define CRPT_TDES_CTL_START_Pos (0) |
CRPT_T::TDES_CTL: START Position
Definition at line 7130 of file NUC472_442.h.
| #define CRPT_TDES_CTL_STOP_Msk (0x1ul << CRPT_TDES_CTL_STOP_Pos) |
CRPT_T::TDES_CTL: STOP Mask
Definition at line 7134 of file NUC472_442.h.
| #define CRPT_TDES_CTL_STOP_Pos (1) |
CRPT_T::TDES_CTL: STOP Position
Definition at line 7133 of file NUC472_442.h.
| #define CRPT_TDES_CTL_TMODE_Msk (0x1ul << CRPT_TDES_CTL_TMODE_Pos) |
CRPT_T::TDES_CTL: TMODE Mask
Definition at line 7137 of file NUC472_442.h.
| #define CRPT_TDES_CTL_TMODE_Pos (2) |
CRPT_T::TDES_CTL: TMODE Position
Definition at line 7136 of file NUC472_442.h.
| #define CRPT_TDES_DATIN_DATIN_Msk (0xfffffffful << CRPT_TDES_DATIN_DATIN_Pos) |
CRPT_T::TDES_DATIN: DATIN Mask
Definition at line 7233 of file NUC472_442.h.
| #define CRPT_TDES_DATIN_DATIN_Pos (0) |
CRPT_T::TDES_DATIN: DATIN Position
Definition at line 7232 of file NUC472_442.h.
| #define CRPT_TDES_DATOUT_DATOUT_Msk (0xfffffffful << CRPT_TDES_DATOUT_DATOUT_Pos) |
CRPT_T::TDES_DATOUT: DATOUT Mask
Definition at line 7236 of file NUC472_442.h.
| #define CRPT_TDES_DATOUT_DATOUT_Pos (0) |
CRPT_T::TDES_DATOUT: DATOUT Position
Definition at line 7235 of file NUC472_442.h.
| #define CRPT_TDES_FDBCKH_FDBCK_Msk (0xfffffffful << CRPT_TDES_FDBCKH_FDBCK_Pos) |
CRPT_T::TDES_FDBCKH: FDBCK Mask
Definition at line 6873 of file NUC472_442.h.
| #define CRPT_TDES_FDBCKH_FDBCK_Pos (0) |
CRPT_T::TDES_FDBCKH: FDBCK Position
Definition at line 6872 of file NUC472_442.h.
| #define CRPT_TDES_FDBCKL_FDBCK_Msk (0xfffffffful << CRPT_TDES_FDBCKL_FDBCK_Pos) |
CRPT_T::TDES_FDBCKL: FDBCK Mask
Definition at line 6876 of file NUC472_442.h.
| #define CRPT_TDES_FDBCKL_FDBCK_Pos (0) |
CRPT_T::TDES_FDBCKL: FDBCK Position
Definition at line 6875 of file NUC472_442.h.
| #define CRPT_TDES_STS_BUSERR_Msk (0x1ul << CRPT_TDES_STS_BUSERR_Pos) |
CRPT_T::TDES_STS: BUSERR Mask
Definition at line 7197 of file NUC472_442.h.
| #define CRPT_TDES_STS_BUSERR_Pos (20) |
CRPT_T::TDES_STS: BUSERR Position
Definition at line 7196 of file NUC472_442.h.
| #define CRPT_TDES_STS_BUSY_Msk (0x1ul << CRPT_TDES_STS_BUSY_Pos) |
CRPT_T::TDES_STS: BUSY Mask
Definition at line 7176 of file NUC472_442.h.
| #define CRPT_TDES_STS_BUSY_Pos (0) |
CRPT_T::TDES_STS: BUSY Position
Definition at line 7175 of file NUC472_442.h.
| #define CRPT_TDES_STS_INBUFEMPTY_Msk (0x1ul << CRPT_TDES_STS_INBUFEMPTY_Pos) |
CRPT_T::TDES_STS: INBUFEMPTY Mask
Definition at line 7179 of file NUC472_442.h.
| #define CRPT_TDES_STS_INBUFEMPTY_Pos (8) |
CRPT_T::TDES_STS: INBUFEMPTY Position
Definition at line 7178 of file NUC472_442.h.
| #define CRPT_TDES_STS_INBUFERR_Msk (0x1ul << CRPT_TDES_STS_INBUFERR_Pos) |
CRPT_T::TDES_STS: INBUFERR Mask
Definition at line 7185 of file NUC472_442.h.
| #define CRPT_TDES_STS_INBUFERR_Pos (10) |
CRPT_T::TDES_STS: INBUFERR Position
Definition at line 7184 of file NUC472_442.h.
| #define CRPT_TDES_STS_INBUFFULL_Msk (0x1ul << CRPT_TDES_STS_INBUFFULL_Pos) |
CRPT_T::TDES_STS: INBUFFULL Mask
Definition at line 7182 of file NUC472_442.h.
| #define CRPT_TDES_STS_INBUFFULL_Pos (9) |
CRPT_T::TDES_STS: INBUFFULL Position
Definition at line 7181 of file NUC472_442.h.
| #define CRPT_TDES_STS_OUTBUFEMPTY_Msk (0x1ul << CRPT_TDES_STS_OUTBUFEMPTY_Pos) |
CRPT_T::TDES_STS: OUTBUFEMPTY Mask
Definition at line 7188 of file NUC472_442.h.
| #define CRPT_TDES_STS_OUTBUFEMPTY_Pos (16) |
CRPT_T::TDES_STS: OUTBUFEMPTY Position
Definition at line 7187 of file NUC472_442.h.
| #define CRPT_TDES_STS_OUTBUFERR_Msk (0x1ul << CRPT_TDES_STS_OUTBUFERR_Pos) |
CRPT_T::TDES_STS: OUTBUFERR Mask
Definition at line 7194 of file NUC472_442.h.
| #define CRPT_TDES_STS_OUTBUFERR_Pos (18) |
CRPT_T::TDES_STS: OUTBUFERR Position
Definition at line 7193 of file NUC472_442.h.
| #define CRPT_TDES_STS_OUTBUFFULL_Msk (0x1ul << CRPT_TDES_STS_OUTBUFFULL_Pos) |
CRPT_T::TDES_STS: OUTBUFFULL Mask
Definition at line 7191 of file NUC472_442.h.
| #define CRPT_TDES_STS_OUTBUFFULL_Pos (17) |
CRPT_T::TDES_STS: OUTBUFFULL Position
Definition at line 7190 of file NUC472_442.h.
| #define EADC_AD0DAT0_OV_Msk (0x1ul << EADC_AD0DAT0_OV_Pos) |
EADC_T::AD0DAT0: OV Mask
Definition at line 9978 of file NUC472_442.h.
| #define EADC_AD0DAT0_OV_Pos (16) |
EADC_T::AD0DAT0: OV Position
Definition at line 9977 of file NUC472_442.h.
| #define EADC_AD0DAT0_RESULT_Msk (0xffful << EADC_AD0DAT0_RESULT_Pos) |
EADC_T::AD0DAT0: RESULT Mask
Definition at line 9975 of file NUC472_442.h.
| #define EADC_AD0DAT0_RESULT_Pos (0) |
@addtogroup EADC_CONST EADC Bit Field Definition Constant Definitions for EADC Controller
EADC_T::AD0DAT0: RESULT Position
Definition at line 9974 of file NUC472_442.h.
| #define EADC_AD0DAT0_VALID_Msk (0x1ul << EADC_AD0DAT0_VALID_Pos) |
EADC_T::AD0DAT0: VALID Mask
Definition at line 9981 of file NUC472_442.h.
| #define EADC_AD0DAT0_VALID_Pos (17) |
EADC_T::AD0DAT0: VALID Position
Definition at line 9980 of file NUC472_442.h.
| #define EADC_AD0DAT1_OV_Msk (0x1ul << EADC_AD0DAT1_OV_Pos) |
EADC_T::AD0DAT1: OV Mask
Definition at line 9987 of file NUC472_442.h.
| #define EADC_AD0DAT1_OV_Pos (16) |
EADC_T::AD0DAT1: OV Position
Definition at line 9986 of file NUC472_442.h.
| #define EADC_AD0DAT1_RESULT_Msk (0xffful << EADC_AD0DAT1_RESULT_Pos) |
EADC_T::AD0DAT1: RESULT Mask
Definition at line 9984 of file NUC472_442.h.
| #define EADC_AD0DAT1_RESULT_Pos (0) |
EADC_T::AD0DAT1: RESULT Position
Definition at line 9983 of file NUC472_442.h.
| #define EADC_AD0DAT1_VALID_Msk (0x1ul << EADC_AD0DAT1_VALID_Pos) |
EADC_T::AD0DAT1: VALID Mask
Definition at line 9990 of file NUC472_442.h.
| #define EADC_AD0DAT1_VALID_Pos (17) |
EADC_T::AD0DAT1: VALID Position
Definition at line 9989 of file NUC472_442.h.
| #define EADC_AD0DAT2_OV_Msk (0x1ul << EADC_AD0DAT2_OV_Pos) |
EADC_T::AD0DAT2: OV Mask
Definition at line 9996 of file NUC472_442.h.
| #define EADC_AD0DAT2_OV_Pos (16) |
EADC_T::AD0DAT2: OV Position
Definition at line 9995 of file NUC472_442.h.
| #define EADC_AD0DAT2_RESULT_Msk (0xffful << EADC_AD0DAT2_RESULT_Pos) |
EADC_T::AD0DAT2: RESULT Mask
Definition at line 9993 of file NUC472_442.h.
| #define EADC_AD0DAT2_RESULT_Pos (0) |
EADC_T::AD0DAT2: RESULT Position
Definition at line 9992 of file NUC472_442.h.
| #define EADC_AD0DAT2_VALID_Msk (0x1ul << EADC_AD0DAT2_VALID_Pos) |
EADC_T::AD0DAT2: VALID Mask
Definition at line 9999 of file NUC472_442.h.
| #define EADC_AD0DAT2_VALID_Pos (17) |
EADC_T::AD0DAT2: VALID Position
Definition at line 9998 of file NUC472_442.h.
| #define EADC_AD0DAT3_OV_Msk (0x1ul << EADC_AD0DAT3_OV_Pos) |
EADC_T::AD0DAT3: OV Mask
Definition at line 10005 of file NUC472_442.h.
| #define EADC_AD0DAT3_OV_Pos (16) |
EADC_T::AD0DAT3: OV Position
Definition at line 10004 of file NUC472_442.h.
| #define EADC_AD0DAT3_RESULT_Msk (0xffful << EADC_AD0DAT3_RESULT_Pos) |
EADC_T::AD0DAT3: RESULT Mask
Definition at line 10002 of file NUC472_442.h.
| #define EADC_AD0DAT3_RESULT_Pos (0) |
EADC_T::AD0DAT3: RESULT Position
Definition at line 10001 of file NUC472_442.h.
| #define EADC_AD0DAT3_VALID_Msk (0x1ul << EADC_AD0DAT3_VALID_Pos) |
EADC_T::AD0DAT3: VALID Mask
Definition at line 10008 of file NUC472_442.h.
| #define EADC_AD0DAT3_VALID_Pos (17) |
EADC_T::AD0DAT3: VALID Position
Definition at line 10007 of file NUC472_442.h.
| #define EADC_AD0DAT4_OV_Msk (0x1ul << EADC_AD0DAT4_OV_Pos) |
EADC_T::AD0DAT4: OV Mask
Definition at line 10014 of file NUC472_442.h.
| #define EADC_AD0DAT4_OV_Pos (16) |
EADC_T::AD0DAT4: OV Position
Definition at line 10013 of file NUC472_442.h.
| #define EADC_AD0DAT4_RESULT_Msk (0xffful << EADC_AD0DAT4_RESULT_Pos) |
EADC_T::AD0DAT4: RESULT Mask
Definition at line 10011 of file NUC472_442.h.
| #define EADC_AD0DAT4_RESULT_Pos (0) |
EADC_T::AD0DAT4: RESULT Position
Definition at line 10010 of file NUC472_442.h.
| #define EADC_AD0DAT4_VALID_Msk (0x1ul << EADC_AD0DAT4_VALID_Pos) |
EADC_T::AD0DAT4: VALID Mask
Definition at line 10017 of file NUC472_442.h.
| #define EADC_AD0DAT4_VALID_Pos (17) |
EADC_T::AD0DAT4: VALID Position
Definition at line 10016 of file NUC472_442.h.
| #define EADC_AD0DAT5_OV_Msk (0x1ul << EADC_AD0DAT5_OV_Pos) |
EADC_T::AD0DAT5: OV Mask
Definition at line 10023 of file NUC472_442.h.
| #define EADC_AD0DAT5_OV_Pos (16) |
EADC_T::AD0DAT5: OV Position
Definition at line 10022 of file NUC472_442.h.
| #define EADC_AD0DAT5_RESULT_Msk (0xffful << EADC_AD0DAT5_RESULT_Pos) |
EADC_T::AD0DAT5: RESULT Mask
Definition at line 10020 of file NUC472_442.h.
| #define EADC_AD0DAT5_RESULT_Pos (0) |
EADC_T::AD0DAT5: RESULT Position
Definition at line 10019 of file NUC472_442.h.
| #define EADC_AD0DAT5_VALID_Msk (0x1ul << EADC_AD0DAT5_VALID_Pos) |
EADC_T::AD0DAT5: VALID Mask
Definition at line 10026 of file NUC472_442.h.
| #define EADC_AD0DAT5_VALID_Pos (17) |
EADC_T::AD0DAT5: VALID Position
Definition at line 10025 of file NUC472_442.h.
| #define EADC_AD0DAT6_OV_Msk (0x1ul << EADC_AD0DAT6_OV_Pos) |
EADC_T::AD0DAT6: OV Mask
Definition at line 10032 of file NUC472_442.h.
| #define EADC_AD0DAT6_OV_Pos (16) |
EADC_T::AD0DAT6: OV Position
Definition at line 10031 of file NUC472_442.h.
| #define EADC_AD0DAT6_RESULT_Msk (0xffful << EADC_AD0DAT6_RESULT_Pos) |
EADC_T::AD0DAT6: RESULT Mask
Definition at line 10029 of file NUC472_442.h.
| #define EADC_AD0DAT6_RESULT_Pos (0) |
EADC_T::AD0DAT6: RESULT Position
Definition at line 10028 of file NUC472_442.h.
| #define EADC_AD0DAT6_VALID_Msk (0x1ul << EADC_AD0DAT6_VALID_Pos) |
EADC_T::AD0DAT6: VALID Mask
Definition at line 10035 of file NUC472_442.h.
| #define EADC_AD0DAT6_VALID_Pos (17) |
EADC_T::AD0DAT6: VALID Position
Definition at line 10034 of file NUC472_442.h.
| #define EADC_AD0DAT7_OV_Msk (0x1ul << EADC_AD0DAT7_OV_Pos) |
EADC_T::AD0DAT7: OV Mask
Definition at line 10041 of file NUC472_442.h.
| #define EADC_AD0DAT7_OV_Pos (16) |
EADC_T::AD0DAT7: OV Position
Definition at line 10040 of file NUC472_442.h.
| #define EADC_AD0DAT7_RESULT_Msk (0xffful << EADC_AD0DAT7_RESULT_Pos) |
EADC_T::AD0DAT7: RESULT Mask
Definition at line 10038 of file NUC472_442.h.
| #define EADC_AD0DAT7_RESULT_Pos (0) |
EADC_T::AD0DAT7: RESULT Position
Definition at line 10037 of file NUC472_442.h.
| #define EADC_AD0DAT7_VALID_Msk (0x1ul << EADC_AD0DAT7_VALID_Pos) |
EADC_T::AD0DAT7: VALID Mask
Definition at line 10044 of file NUC472_442.h.
| #define EADC_AD0DAT7_VALID_Pos (17) |
EADC_T::AD0DAT7: VALID Position
Definition at line 10043 of file NUC472_442.h.
| #define EADC_AD0DDAT0_RESULT_Msk (0xffful << EADC_AD0DDAT0_RESULT_Pos) |
EADC_T::AD0DDAT0: RESULT Mask
Definition at line 10527 of file NUC472_442.h.
| #define EADC_AD0DDAT0_RESULT_Pos (0) |
EADC_T::AD0DDAT0: RESULT Position
Definition at line 10526 of file NUC472_442.h.
| #define EADC_AD0DDAT0_VALID_Msk (0x1ul << EADC_AD0DDAT0_VALID_Pos) |
EADC_T::AD0DDAT0: VALID Mask
Definition at line 10530 of file NUC472_442.h.
| #define EADC_AD0DDAT0_VALID_Pos (16) |
EADC_T::AD0DDAT0: VALID Position
Definition at line 10529 of file NUC472_442.h.
| #define EADC_AD0DDAT1_RESULT_Msk (0xffful << EADC_AD0DDAT1_RESULT_Pos) |
EADC_T::AD0DDAT1: RESULT Mask
Definition at line 10533 of file NUC472_442.h.
| #define EADC_AD0DDAT1_RESULT_Pos (0) |
EADC_T::AD0DDAT1: RESULT Position
Definition at line 10532 of file NUC472_442.h.
| #define EADC_AD0DDAT1_VALID_Msk (0x1ul << EADC_AD0DDAT1_VALID_Pos) |
EADC_T::AD0DDAT1: VALID Mask
Definition at line 10536 of file NUC472_442.h.
| #define EADC_AD0DDAT1_VALID_Pos (16) |
EADC_T::AD0DDAT1: VALID Position
Definition at line 10535 of file NUC472_442.h.
| #define EADC_AD0DDAT2_RESULT_Msk (0xffful << EADC_AD0DDAT2_RESULT_Pos) |
EADC_T::AD0DDAT2: RESULT Mask
Definition at line 10539 of file NUC472_442.h.
| #define EADC_AD0DDAT2_RESULT_Pos (0) |
EADC_T::AD0DDAT2: RESULT Position
Definition at line 10538 of file NUC472_442.h.
| #define EADC_AD0DDAT2_VALID_Msk (0x1ul << EADC_AD0DDAT2_VALID_Pos) |
EADC_T::AD0DDAT2: VALID Mask
Definition at line 10542 of file NUC472_442.h.
| #define EADC_AD0DDAT2_VALID_Pos (16) |
EADC_T::AD0DDAT2: VALID Position
Definition at line 10541 of file NUC472_442.h.
| #define EADC_AD0DDAT3_RESULT_Msk (0xffful << EADC_AD0DDAT3_RESULT_Pos) |
EADC_T::AD0DDAT3: RESULT Mask
Definition at line 10545 of file NUC472_442.h.
| #define EADC_AD0DDAT3_RESULT_Pos (0) |
EADC_T::AD0DDAT3: RESULT Position
Definition at line 10544 of file NUC472_442.h.
| #define EADC_AD0DDAT3_VALID_Msk (0x1ul << EADC_AD0DDAT3_VALID_Pos) |
EADC_T::AD0DDAT3: VALID Mask
Definition at line 10548 of file NUC472_442.h.
| #define EADC_AD0DDAT3_VALID_Pos (16) |
EADC_T::AD0DDAT3: VALID Position
Definition at line 10547 of file NUC472_442.h.
| #define EADC_AD0SPCTL0_CHSEL_Msk (0xful << EADC_AD0SPCTL0_CHSEL_Pos) |
EADC_T::AD0SPCTL0: CHSEL Mask
Definition at line 10167 of file NUC472_442.h.
| #define EADC_AD0SPCTL0_CHSEL_Pos (0) |
EADC_T::AD0SPCTL0: CHSEL Position
Definition at line 10166 of file NUC472_442.h.
| #define EADC_AD0SPCTL0_EXTFEN_Msk (0x1ul << EADC_AD0SPCTL0_EXTFEN_Pos) |
EADC_T::AD0SPCTL0: EXTFEN Mask
Definition at line 10182 of file NUC472_442.h.
| #define EADC_AD0SPCTL0_EXTFEN_Pos (21) |
EADC_T::AD0SPCTL0: EXTFEN Position
Definition at line 10181 of file NUC472_442.h.
| #define EADC_AD0SPCTL0_EXTREN_Msk (0x1ul << EADC_AD0SPCTL0_EXTREN_Pos) |
EADC_T::AD0SPCTL0: EXTREN Mask
Definition at line 10179 of file NUC472_442.h.
| #define EADC_AD0SPCTL0_EXTREN_Pos (20) |
EADC_T::AD0SPCTL0: EXTREN Position
Definition at line 10178 of file NUC472_442.h.
| #define EADC_AD0SPCTL0_TRGDLYCNT_Msk (0xfful << EADC_AD0SPCTL0_TRGDLYCNT_Pos) |
EADC_T::AD0SPCTL0: TRGDLYCNT Mask
Definition at line 10173 of file NUC472_442.h.
| #define EADC_AD0SPCTL0_TRGDLYCNT_Pos (8) |
EADC_T::AD0SPCTL0: TRGDLYCNT Position
Definition at line 10172 of file NUC472_442.h.
| #define EADC_AD0SPCTL0_TRGDLYDIV_Msk (0x3ul << EADC_AD0SPCTL0_TRGDLYDIV_Pos) |
EADC_T::AD0SPCTL0: TRGDLYDIV Mask
Definition at line 10176 of file NUC472_442.h.
| #define EADC_AD0SPCTL0_TRGDLYDIV_Pos (16) |
EADC_T::AD0SPCTL0: TRGDLYDIV Position
Definition at line 10175 of file NUC472_442.h.
| #define EADC_AD0SPCTL0_TRGSEL_Msk (0xful << EADC_AD0SPCTL0_TRGSEL_Pos) |
EADC_T::AD0SPCTL0: TRGSEL Mask
Definition at line 10170 of file NUC472_442.h.
| #define EADC_AD0SPCTL0_TRGSEL_Pos (4) |
EADC_T::AD0SPCTL0: TRGSEL Position
Definition at line 10169 of file NUC472_442.h.
| #define EADC_AD0SPCTL1_CHSEL_Msk (0xful << EADC_AD0SPCTL1_CHSEL_Pos) |
EADC_T::AD0SPCTL1: CHSEL Mask
Definition at line 10185 of file NUC472_442.h.
| #define EADC_AD0SPCTL1_CHSEL_Pos (0) |
EADC_T::AD0SPCTL1: CHSEL Position
Definition at line 10184 of file NUC472_442.h.
| #define EADC_AD0SPCTL1_EXTFEN_Msk (0x1ul << EADC_AD0SPCTL1_EXTFEN_Pos) |
EADC_T::AD0SPCTL1: EXTFEN Mask
Definition at line 10200 of file NUC472_442.h.
| #define EADC_AD0SPCTL1_EXTFEN_Pos (21) |
EADC_T::AD0SPCTL1: EXTFEN Position
Definition at line 10199 of file NUC472_442.h.
| #define EADC_AD0SPCTL1_EXTREN_Msk (0x1ul << EADC_AD0SPCTL1_EXTREN_Pos) |
EADC_T::AD0SPCTL1: EXTREN Mask
Definition at line 10197 of file NUC472_442.h.
| #define EADC_AD0SPCTL1_EXTREN_Pos (20) |
EADC_T::AD0SPCTL1: EXTREN Position
Definition at line 10196 of file NUC472_442.h.
| #define EADC_AD0SPCTL1_TRGDLYCNT_Msk (0xfful << EADC_AD0SPCTL1_TRGDLYCNT_Pos) |
EADC_T::AD0SPCTL1: TRGDLYCNT Mask
Definition at line 10191 of file NUC472_442.h.
| #define EADC_AD0SPCTL1_TRGDLYCNT_Pos (8) |
EADC_T::AD0SPCTL1: TRGDLYCNT Position
Definition at line 10190 of file NUC472_442.h.
| #define EADC_AD0SPCTL1_TRGDLYDIV_Msk (0x3ul << EADC_AD0SPCTL1_TRGDLYDIV_Pos) |
EADC_T::AD0SPCTL1: TRGDLYDIV Mask
Definition at line 10194 of file NUC472_442.h.
| #define EADC_AD0SPCTL1_TRGDLYDIV_Pos (16) |
EADC_T::AD0SPCTL1: TRGDLYDIV Position
Definition at line 10193 of file NUC472_442.h.
| #define EADC_AD0SPCTL1_TRGSEL_Msk (0xful << EADC_AD0SPCTL1_TRGSEL_Pos) |
EADC_T::AD0SPCTL1: TRGSEL Mask
Definition at line 10188 of file NUC472_442.h.
| #define EADC_AD0SPCTL1_TRGSEL_Pos (4) |
EADC_T::AD0SPCTL1: TRGSEL Position
Definition at line 10187 of file NUC472_442.h.
| #define EADC_AD0SPCTL2_CHSEL_Msk (0xful << EADC_AD0SPCTL2_CHSEL_Pos) |
EADC_T::AD0SPCTL2: CHSEL Mask
Definition at line 10203 of file NUC472_442.h.
| #define EADC_AD0SPCTL2_CHSEL_Pos (0) |
EADC_T::AD0SPCTL2: CHSEL Position
Definition at line 10202 of file NUC472_442.h.
| #define EADC_AD0SPCTL2_EXTFEN_Msk (0x1ul << EADC_AD0SPCTL2_EXTFEN_Pos) |
EADC_T::AD0SPCTL2: EXTFEN Mask
Definition at line 10218 of file NUC472_442.h.
| #define EADC_AD0SPCTL2_EXTFEN_Pos (21) |
EADC_T::AD0SPCTL2: EXTFEN Position
Definition at line 10217 of file NUC472_442.h.
| #define EADC_AD0SPCTL2_EXTREN_Msk (0x1ul << EADC_AD0SPCTL2_EXTREN_Pos) |
EADC_T::AD0SPCTL2: EXTREN Mask
Definition at line 10215 of file NUC472_442.h.
| #define EADC_AD0SPCTL2_EXTREN_Pos (20) |
EADC_T::AD0SPCTL2: EXTREN Position
Definition at line 10214 of file NUC472_442.h.
| #define EADC_AD0SPCTL2_TRGDLYCNT_Msk (0xfful << EADC_AD0SPCTL2_TRGDLYCNT_Pos) |
EADC_T::AD0SPCTL2: TRGDLYCNT Mask
Definition at line 10209 of file NUC472_442.h.
| #define EADC_AD0SPCTL2_TRGDLYCNT_Pos (8) |
EADC_T::AD0SPCTL2: TRGDLYCNT Position
Definition at line 10208 of file NUC472_442.h.
| #define EADC_AD0SPCTL2_TRGDLYDIV_Msk (0x3ul << EADC_AD0SPCTL2_TRGDLYDIV_Pos) |
EADC_T::AD0SPCTL2: TRGDLYDIV Mask
Definition at line 10212 of file NUC472_442.h.
| #define EADC_AD0SPCTL2_TRGDLYDIV_Pos (16) |
EADC_T::AD0SPCTL2: TRGDLYDIV Position
Definition at line 10211 of file NUC472_442.h.
| #define EADC_AD0SPCTL2_TRGSEL_Msk (0xful << EADC_AD0SPCTL2_TRGSEL_Pos) |
EADC_T::AD0SPCTL2: TRGSEL Mask
Definition at line 10206 of file NUC472_442.h.
| #define EADC_AD0SPCTL2_TRGSEL_Pos (4) |
EADC_T::AD0SPCTL2: TRGSEL Position
Definition at line 10205 of file NUC472_442.h.
| #define EADC_AD0SPCTL3_CHSEL_Msk (0xful << EADC_AD0SPCTL3_CHSEL_Pos) |
EADC_T::AD0SPCTL3: CHSEL Mask
Definition at line 10221 of file NUC472_442.h.
| #define EADC_AD0SPCTL3_CHSEL_Pos (0) |
EADC_T::AD0SPCTL3: CHSEL Position
Definition at line 10220 of file NUC472_442.h.
| #define EADC_AD0SPCTL3_EXTFEN_Msk (0x1ul << EADC_AD0SPCTL3_EXTFEN_Pos) |
EADC_T::AD0SPCTL3: EXTFEN Mask
Definition at line 10236 of file NUC472_442.h.
| #define EADC_AD0SPCTL3_EXTFEN_Pos (21) |
EADC_T::AD0SPCTL3: EXTFEN Position
Definition at line 10235 of file NUC472_442.h.
| #define EADC_AD0SPCTL3_EXTREN_Msk (0x1ul << EADC_AD0SPCTL3_EXTREN_Pos) |
EADC_T::AD0SPCTL3: EXTREN Mask
Definition at line 10233 of file NUC472_442.h.
| #define EADC_AD0SPCTL3_EXTREN_Pos (20) |
EADC_T::AD0SPCTL3: EXTREN Position
Definition at line 10232 of file NUC472_442.h.
| #define EADC_AD0SPCTL3_TRGDLYCNT_Msk (0xfful << EADC_AD0SPCTL3_TRGDLYCNT_Pos) |
EADC_T::AD0SPCTL3: TRGDLYCNT Mask
Definition at line 10227 of file NUC472_442.h.
| #define EADC_AD0SPCTL3_TRGDLYCNT_Pos (8) |
EADC_T::AD0SPCTL3: TRGDLYCNT Position
Definition at line 10226 of file NUC472_442.h.
| #define EADC_AD0SPCTL3_TRGDLYDIV_Msk (0x3ul << EADC_AD0SPCTL3_TRGDLYDIV_Pos) |
EADC_T::AD0SPCTL3: TRGDLYDIV Mask
Definition at line 10230 of file NUC472_442.h.
| #define EADC_AD0SPCTL3_TRGDLYDIV_Pos (16) |
EADC_T::AD0SPCTL3: TRGDLYDIV Position
Definition at line 10229 of file NUC472_442.h.
| #define EADC_AD0SPCTL3_TRGSEL_Msk (0xful << EADC_AD0SPCTL3_TRGSEL_Pos) |
EADC_T::AD0SPCTL3: TRGSEL Mask
Definition at line 10224 of file NUC472_442.h.
| #define EADC_AD0SPCTL3_TRGSEL_Pos (4) |
EADC_T::AD0SPCTL3: TRGSEL Position
Definition at line 10223 of file NUC472_442.h.
| #define EADC_AD0SPCTL4_CHSEL_Msk (0xful << EADC_AD0SPCTL4_CHSEL_Pos) |
EADC_T::AD0SPCTL4: CHSEL Mask
Definition at line 10239 of file NUC472_442.h.
| #define EADC_AD0SPCTL4_CHSEL_Pos (0) |
EADC_T::AD0SPCTL4: CHSEL Position
Definition at line 10238 of file NUC472_442.h.
| #define EADC_AD0SPCTL4_EXTFEN_Msk (0x1ul << EADC_AD0SPCTL4_EXTFEN_Pos) |
EADC_T::AD0SPCTL4: EXTFEN Mask
Definition at line 10248 of file NUC472_442.h.
| #define EADC_AD0SPCTL4_EXTFEN_Pos (21) |
EADC_T::AD0SPCTL4: EXTFEN Position
Definition at line 10247 of file NUC472_442.h.
| #define EADC_AD0SPCTL4_EXTREN_Msk (0x1ul << EADC_AD0SPCTL4_EXTREN_Pos) |
EADC_T::AD0SPCTL4: EXTREN Mask
Definition at line 10245 of file NUC472_442.h.
| #define EADC_AD0SPCTL4_EXTREN_Pos (20) |
EADC_T::AD0SPCTL4: EXTREN Position
Definition at line 10244 of file NUC472_442.h.
| #define EADC_AD0SPCTL4_TRGSEL_Msk (0x7ul << EADC_AD0SPCTL4_TRGSEL_Pos) |
EADC_T::AD0SPCTL4: TRGSEL Mask
Definition at line 10242 of file NUC472_442.h.
| #define EADC_AD0SPCTL4_TRGSEL_Pos (4) |
EADC_T::AD0SPCTL4: TRGSEL Position
Definition at line 10241 of file NUC472_442.h.
| #define EADC_AD0SPCTL5_CHSEL_Msk (0xful << EADC_AD0SPCTL5_CHSEL_Pos) |
EADC_T::AD0SPCTL5: CHSEL Mask
Definition at line 10251 of file NUC472_442.h.
| #define EADC_AD0SPCTL5_CHSEL_Pos (0) |
EADC_T::AD0SPCTL5: CHSEL Position
Definition at line 10250 of file NUC472_442.h.
| #define EADC_AD0SPCTL5_EXTFEN_Msk (0x1ul << EADC_AD0SPCTL5_EXTFEN_Pos) |
EADC_T::AD0SPCTL5: EXTFEN Mask
Definition at line 10260 of file NUC472_442.h.
| #define EADC_AD0SPCTL5_EXTFEN_Pos (21) |
EADC_T::AD0SPCTL5: EXTFEN Position
Definition at line 10259 of file NUC472_442.h.
| #define EADC_AD0SPCTL5_EXTREN_Msk (0x1ul << EADC_AD0SPCTL5_EXTREN_Pos) |
EADC_T::AD0SPCTL5: EXTREN Mask
Definition at line 10257 of file NUC472_442.h.
| #define EADC_AD0SPCTL5_EXTREN_Pos (20) |
EADC_T::AD0SPCTL5: EXTREN Position
Definition at line 10256 of file NUC472_442.h.
| #define EADC_AD0SPCTL5_TRGSEL_Msk (0x7ul << EADC_AD0SPCTL5_TRGSEL_Pos) |
EADC_T::AD0SPCTL5: TRGSEL Mask
Definition at line 10254 of file NUC472_442.h.
| #define EADC_AD0SPCTL5_TRGSEL_Pos (4) |
EADC_T::AD0SPCTL5: TRGSEL Position
Definition at line 10253 of file NUC472_442.h.
| #define EADC_AD0SPCTL6_CHSEL_Msk (0xful << EADC_AD0SPCTL6_CHSEL_Pos) |
EADC_T::AD0SPCTL6: CHSEL Mask
Definition at line 10263 of file NUC472_442.h.
| #define EADC_AD0SPCTL6_CHSEL_Pos (0) |
EADC_T::AD0SPCTL6: CHSEL Position
Definition at line 10262 of file NUC472_442.h.
| #define EADC_AD0SPCTL6_EXTFEN_Msk (0x1ul << EADC_AD0SPCTL6_EXTFEN_Pos) |
EADC_T::AD0SPCTL6: EXTFEN Mask
Definition at line 10272 of file NUC472_442.h.
| #define EADC_AD0SPCTL6_EXTFEN_Pos (21) |
EADC_T::AD0SPCTL6: EXTFEN Position
Definition at line 10271 of file NUC472_442.h.
| #define EADC_AD0SPCTL6_EXTREN_Msk (0x1ul << EADC_AD0SPCTL6_EXTREN_Pos) |
EADC_T::AD0SPCTL6: EXTREN Mask
Definition at line 10269 of file NUC472_442.h.
| #define EADC_AD0SPCTL6_EXTREN_Pos (20) |
EADC_T::AD0SPCTL6: EXTREN Position
Definition at line 10268 of file NUC472_442.h.
| #define EADC_AD0SPCTL6_TRGSEL_Msk (0x7ul << EADC_AD0SPCTL6_TRGSEL_Pos) |
EADC_T::AD0SPCTL6: TRGSEL Mask
Definition at line 10266 of file NUC472_442.h.
| #define EADC_AD0SPCTL6_TRGSEL_Pos (4) |
EADC_T::AD0SPCTL6: TRGSEL Position
Definition at line 10265 of file NUC472_442.h.
| #define EADC_AD0SPCTL7_CHSEL_Msk (0xful << EADC_AD0SPCTL7_CHSEL_Pos) |
EADC_T::AD0SPCTL7: CHSEL Mask
Definition at line 10275 of file NUC472_442.h.
| #define EADC_AD0SPCTL7_CHSEL_Pos (0) |
EADC_T::AD0SPCTL7: CHSEL Position
Definition at line 10274 of file NUC472_442.h.
| #define EADC_AD0SPCTL7_EXTFEN_Msk (0x1ul << EADC_AD0SPCTL7_EXTFEN_Pos) |
EADC_T::AD0SPCTL7: EXTFEN Mask
Definition at line 10284 of file NUC472_442.h.
| #define EADC_AD0SPCTL7_EXTFEN_Pos (21) |
EADC_T::AD0SPCTL7: EXTFEN Position
Definition at line 10283 of file NUC472_442.h.
| #define EADC_AD0SPCTL7_EXTREN_Msk (0x1ul << EADC_AD0SPCTL7_EXTREN_Pos) |
EADC_T::AD0SPCTL7: EXTREN Mask
Definition at line 10281 of file NUC472_442.h.
| #define EADC_AD0SPCTL7_EXTREN_Pos (20) |
EADC_T::AD0SPCTL7: EXTREN Position
Definition at line 10280 of file NUC472_442.h.
| #define EADC_AD0SPCTL7_TRGSEL_Msk (0x7ul << EADC_AD0SPCTL7_TRGSEL_Pos) |
EADC_T::AD0SPCTL7: TRGSEL Mask
Definition at line 10278 of file NUC472_442.h.
| #define EADC_AD0SPCTL7_TRGSEL_Pos (4) |
EADC_T::AD0SPCTL7: TRGSEL Position
Definition at line 10277 of file NUC472_442.h.
| #define EADC_AD0TRGEN0_EPWM00CEN_Msk (0x1ul << EADC_AD0TRGEN0_EPWM00CEN_Pos) |
EADC_T::AD0TRGEN0: EPWM00CEN Mask
Definition at line 10800 of file NUC472_442.h.
| #define EADC_AD0TRGEN0_EPWM00CEN_Pos (3) |
EADC_T::AD0TRGEN0: EPWM00CEN Position
Definition at line 10799 of file NUC472_442.h.
| #define EADC_AD0TRGEN0_EPWM00FEN_Msk (0x1ul << EADC_AD0TRGEN0_EPWM00FEN_Pos) |
EADC_T::AD0TRGEN0: EPWM00FEN Mask
Definition at line 10794 of file NUC472_442.h.
| #define EADC_AD0TRGEN0_EPWM00FEN_Pos (1) |
EADC_T::AD0TRGEN0: EPWM00FEN Position
Definition at line 10793 of file NUC472_442.h.
| #define EADC_AD0TRGEN0_EPWM00PEN_Msk (0x1ul << EADC_AD0TRGEN0_EPWM00PEN_Pos) |
EADC_T::AD0TRGEN0: EPWM00PEN Mask
Definition at line 10797 of file NUC472_442.h.
| #define EADC_AD0TRGEN0_EPWM00PEN_Pos (2) |
EADC_T::AD0TRGEN0: EPWM00PEN Position
Definition at line 10796 of file NUC472_442.h.
| #define EADC_AD0TRGEN0_EPWM00REN_Msk (0x1ul << EADC_AD0TRGEN0_EPWM00REN_Pos) |
EADC_T::AD0TRGEN0: EPWM00REN Mask
Definition at line 10791 of file NUC472_442.h.
| #define EADC_AD0TRGEN0_EPWM00REN_Pos (0) |
EADC_T::AD0TRGEN0: EPWM00REN Position
Definition at line 10790 of file NUC472_442.h.
| #define EADC_AD0TRGEN0_EPWM02CEN_Msk (0x1ul << EADC_AD0TRGEN0_EPWM02CEN_Pos) |
EADC_T::AD0TRGEN0: EPWM02CEN Mask
Definition at line 10812 of file NUC472_442.h.
| #define EADC_AD0TRGEN0_EPWM02CEN_Pos (7) |
EADC_T::AD0TRGEN0: EPWM02CEN Position
Definition at line 10811 of file NUC472_442.h.
| #define EADC_AD0TRGEN0_EPWM02FEN_Msk (0x1ul << EADC_AD0TRGEN0_EPWM02FEN_Pos) |
EADC_T::AD0TRGEN0: EPWM02FEN Mask
Definition at line 10806 of file NUC472_442.h.
| #define EADC_AD0TRGEN0_EPWM02FEN_Pos (5) |
EADC_T::AD0TRGEN0: EPWM02FEN Position
Definition at line 10805 of file NUC472_442.h.
| #define EADC_AD0TRGEN0_EPWM02PEN_Msk (0x1ul << EADC_AD0TRGEN0_EPWM02PEN_Pos) |
EADC_T::AD0TRGEN0: EPWM02PEN Mask
Definition at line 10809 of file NUC472_442.h.
| #define EADC_AD0TRGEN0_EPWM02PEN_Pos (6) |
EADC_T::AD0TRGEN0: EPWM02PEN Position
Definition at line 10808 of file NUC472_442.h.
| #define EADC_AD0TRGEN0_EPWM02REN_Msk (0x1ul << EADC_AD0TRGEN0_EPWM02REN_Pos) |
EADC_T::AD0TRGEN0: EPWM02REN Mask
Definition at line 10803 of file NUC472_442.h.
| #define EADC_AD0TRGEN0_EPWM02REN_Pos (4) |
EADC_T::AD0TRGEN0: EPWM02REN Position
Definition at line 10802 of file NUC472_442.h.
| #define EADC_AD0TRGEN0_EPWM04CEN_Msk (0x1ul << EADC_AD0TRGEN0_EPWM04CEN_Pos) |
EADC_T::AD0TRGEN0: EPWM04CEN Mask
Definition at line 10824 of file NUC472_442.h.
| #define EADC_AD0TRGEN0_EPWM04CEN_Pos (11) |
EADC_T::AD0TRGEN0: EPWM04CEN Position
Definition at line 10823 of file NUC472_442.h.
| #define EADC_AD0TRGEN0_EPWM04FEN_Msk (0x1ul << EADC_AD0TRGEN0_EPWM04FEN_Pos) |
EADC_T::AD0TRGEN0: EPWM04FEN Mask
Definition at line 10818 of file NUC472_442.h.
| #define EADC_AD0TRGEN0_EPWM04FEN_Pos (9) |
EADC_T::AD0TRGEN0: EPWM04FEN Position
Definition at line 10817 of file NUC472_442.h.
| #define EADC_AD0TRGEN0_EPWM04PEN_Msk (0x1ul << EADC_AD0TRGEN0_EPWM04PEN_Pos) |
EADC_T::AD0TRGEN0: EPWM04PEN Mask
Definition at line 10821 of file NUC472_442.h.
| #define EADC_AD0TRGEN0_EPWM04PEN_Pos (10) |
EADC_T::AD0TRGEN0: EPWM04PEN Position
Definition at line 10820 of file NUC472_442.h.
| #define EADC_AD0TRGEN0_EPWM04REN_Msk (0x1ul << EADC_AD0TRGEN0_EPWM04REN_Pos) |
EADC_T::AD0TRGEN0: EPWM04REN Mask
Definition at line 10815 of file NUC472_442.h.
| #define EADC_AD0TRGEN0_EPWM04REN_Pos (8) |
EADC_T::AD0TRGEN0: EPWM04REN Position
Definition at line 10814 of file NUC472_442.h.
| #define EADC_AD0TRGEN0_EPWM10CEN_Msk (0x1ul << EADC_AD0TRGEN0_EPWM10CEN_Pos) |
EADC_T::AD0TRGEN0: EPWM10CEN Mask
Definition at line 10836 of file NUC472_442.h.
| #define EADC_AD0TRGEN0_EPWM10CEN_Pos (15) |
EADC_T::AD0TRGEN0: EPWM10CEN Position
Definition at line 10835 of file NUC472_442.h.
| #define EADC_AD0TRGEN0_EPWM10FEN_Msk (0x1ul << EADC_AD0TRGEN0_EPWM10FEN_Pos) |
EADC_T::AD0TRGEN0: EPWM10FEN Mask
Definition at line 10830 of file NUC472_442.h.
| #define EADC_AD0TRGEN0_EPWM10FEN_Pos (13) |
EADC_T::AD0TRGEN0: EPWM10FEN Position
Definition at line 10829 of file NUC472_442.h.
| #define EADC_AD0TRGEN0_EPWM10PEN_Msk (0x1ul << EADC_AD0TRGEN0_EPWM10PEN_Pos) |
EADC_T::AD0TRGEN0: EPWM10PEN Mask
Definition at line 10833 of file NUC472_442.h.
| #define EADC_AD0TRGEN0_EPWM10PEN_Pos (14) |
EADC_T::AD0TRGEN0: EPWM10PEN Position
Definition at line 10832 of file NUC472_442.h.
| #define EADC_AD0TRGEN0_EPWM10REN_Msk (0x1ul << EADC_AD0TRGEN0_EPWM10REN_Pos) |
EADC_T::AD0TRGEN0: EPWM10REN Mask
Definition at line 10827 of file NUC472_442.h.
| #define EADC_AD0TRGEN0_EPWM10REN_Pos (12) |
EADC_T::AD0TRGEN0: EPWM10REN Position
Definition at line 10826 of file NUC472_442.h.
| #define EADC_AD0TRGEN0_EPWM120FEN_Msk (0x1ul << EADC_AD0TRGEN0_EPWM120FEN_Pos) |
EADC_T::AD0TRGEN0: EPWM120FEN Mask
Definition at line 10842 of file NUC472_442.h.
| #define EADC_AD0TRGEN0_EPWM120FEN_Pos (17) |
EADC_T::AD0TRGEN0: EPWM120FEN Position
Definition at line 10841 of file NUC472_442.h.
| #define EADC_AD0TRGEN0_EPWM12CEN_Msk (0x1ul << EADC_AD0TRGEN0_EPWM12CEN_Pos) |
EADC_T::AD0TRGEN0: EPWM12CEN Mask
Definition at line 10848 of file NUC472_442.h.
| #define EADC_AD0TRGEN0_EPWM12CEN_Pos (19) |
EADC_T::AD0TRGEN0: EPWM12CEN Position
Definition at line 10847 of file NUC472_442.h.
| #define EADC_AD0TRGEN0_EPWM12PEN_Msk (0x1ul << EADC_AD0TRGEN0_EPWM12PEN_Pos) |
EADC_T::AD0TRGEN0: EPWM12PEN Mask
Definition at line 10845 of file NUC472_442.h.
| #define EADC_AD0TRGEN0_EPWM12PEN_Pos (18) |
EADC_T::AD0TRGEN0: EPWM12PEN Position
Definition at line 10844 of file NUC472_442.h.
| #define EADC_AD0TRGEN0_EPWM12REN_Msk (0x1ul << EADC_AD0TRGEN0_EPWM12REN_Pos) |
EADC_T::AD0TRGEN0: EPWM12REN Mask
Definition at line 10839 of file NUC472_442.h.
| #define EADC_AD0TRGEN0_EPWM12REN_Pos (16) |
EADC_T::AD0TRGEN0: EPWM12REN Position
Definition at line 10838 of file NUC472_442.h.
| #define EADC_AD0TRGEN0_EPWM14CEN_Msk (0x1ul << EADC_AD0TRGEN0_EPWM14CEN_Pos) |
EADC_T::AD0TRGEN0: EPWM14CEN Mask
Definition at line 10860 of file NUC472_442.h.
| #define EADC_AD0TRGEN0_EPWM14CEN_Pos (23) |
EADC_T::AD0TRGEN0: EPWM14CEN Position
Definition at line 10859 of file NUC472_442.h.
| #define EADC_AD0TRGEN0_EPWM14FEN_Msk (0x1ul << EADC_AD0TRGEN0_EPWM14FEN_Pos) |
EADC_T::AD0TRGEN0: EPWM14FEN Mask
Definition at line 10854 of file NUC472_442.h.
| #define EADC_AD0TRGEN0_EPWM14FEN_Pos (21) |
EADC_T::AD0TRGEN0: EPWM14FEN Position
Definition at line 10853 of file NUC472_442.h.
| #define EADC_AD0TRGEN0_EPWM14PEN_Msk (0x1ul << EADC_AD0TRGEN0_EPWM14PEN_Pos) |
EADC_T::AD0TRGEN0: EPWM14PEN Mask
Definition at line 10857 of file NUC472_442.h.
| #define EADC_AD0TRGEN0_EPWM14PEN_Pos (22) |
EADC_T::AD0TRGEN0: EPWM14PEN Position
Definition at line 10856 of file NUC472_442.h.
| #define EADC_AD0TRGEN0_EPWM14REN_Msk (0x1ul << EADC_AD0TRGEN0_EPWM14REN_Pos) |
EADC_T::AD0TRGEN0: EPWM14REN Mask
Definition at line 10851 of file NUC472_442.h.
| #define EADC_AD0TRGEN0_EPWM14REN_Pos (20) |
EADC_T::AD0TRGEN0: EPWM14REN Position
Definition at line 10850 of file NUC472_442.h.
| #define EADC_AD0TRGEN0_PWM00CEN_Msk (0x1ul << EADC_AD0TRGEN0_PWM00CEN_Pos) |
EADC_T::AD0TRGEN0: PWM00CEN Mask
Definition at line 10872 of file NUC472_442.h.
| #define EADC_AD0TRGEN0_PWM00CEN_Pos (27) |
EADC_T::AD0TRGEN0: PWM00CEN Position
Definition at line 10871 of file NUC472_442.h.
| #define EADC_AD0TRGEN0_PWM00FEN_Msk (0x1ul << EADC_AD0TRGEN0_PWM00FEN_Pos) |
EADC_T::AD0TRGEN0: PWM00FEN Mask
Definition at line 10866 of file NUC472_442.h.
| #define EADC_AD0TRGEN0_PWM00FEN_Pos (25) |
EADC_T::AD0TRGEN0: PWM00FEN Position
Definition at line 10865 of file NUC472_442.h.
| #define EADC_AD0TRGEN0_PWM00PEN_Msk (0x1ul << EADC_AD0TRGEN0_PWM00PEN_Pos) |
EADC_T::AD0TRGEN0: PWM00PEN Mask
Definition at line 10869 of file NUC472_442.h.
| #define EADC_AD0TRGEN0_PWM00PEN_Pos (26) |
EADC_T::AD0TRGEN0: PWM00PEN Position
Definition at line 10868 of file NUC472_442.h.
| #define EADC_AD0TRGEN0_PWM00REN_Msk (0x1ul << EADC_AD0TRGEN0_PWM00REN_Pos) |
EADC_T::AD0TRGEN0: PWM00REN Mask
Definition at line 10863 of file NUC472_442.h.
| #define EADC_AD0TRGEN0_PWM00REN_Pos (24) |
EADC_T::AD0TRGEN0: PWM00REN Position
Definition at line 10862 of file NUC472_442.h.
| #define EADC_AD0TRGEN0_PWM01CEN_Msk (0x1ul << EADC_AD0TRGEN0_PWM01CEN_Pos) |
EADC_T::AD0TRGEN0: PWM01CEN Mask
Definition at line 10884 of file NUC472_442.h.
| #define EADC_AD0TRGEN0_PWM01CEN_Pos (31) |
EADC_T::AD0TRGEN0: PWM01CEN Position
Definition at line 10883 of file NUC472_442.h.
| #define EADC_AD0TRGEN0_PWM01FEN_Msk (0x1ul << EADC_AD0TRGEN0_PWM01FEN_Pos) |
EADC_T::AD0TRGEN0: PWM01FEN Mask
Definition at line 10878 of file NUC472_442.h.
| #define EADC_AD0TRGEN0_PWM01FEN_Pos (29) |
EADC_T::AD0TRGEN0: PWM01FEN Position
Definition at line 10877 of file NUC472_442.h.
| #define EADC_AD0TRGEN0_PWM01PEN_Msk (0x1ul << EADC_AD0TRGEN0_PWM01PEN_Pos) |
EADC_T::AD0TRGEN0: PWM01PEN Mask
Definition at line 10881 of file NUC472_442.h.
| #define EADC_AD0TRGEN0_PWM01PEN_Pos (30) |
EADC_T::AD0TRGEN0: PWM01PEN Position
Definition at line 10880 of file NUC472_442.h.
| #define EADC_AD0TRGEN0_PWM01REN_Msk (0x1ul << EADC_AD0TRGEN0_PWM01REN_Pos) |
EADC_T::AD0TRGEN0: PWM01REN Mask
Definition at line 10875 of file NUC472_442.h.
| #define EADC_AD0TRGEN0_PWM01REN_Pos (28) |
EADC_T::AD0TRGEN0: PWM01REN Position
Definition at line 10874 of file NUC472_442.h.
| #define EADC_AD0TRGEN1_EPWM00CEN_Msk (0x1ul << EADC_AD0TRGEN1_EPWM00CEN_Pos) |
EADC_T::AD0TRGEN1: EPWM00CEN Mask
Definition at line 10896 of file NUC472_442.h.
| #define EADC_AD0TRGEN1_EPWM00CEN_Pos (3) |
EADC_T::AD0TRGEN1: EPWM00CEN Position
Definition at line 10895 of file NUC472_442.h.
| #define EADC_AD0TRGEN1_EPWM00FEN_Msk (0x1ul << EADC_AD0TRGEN1_EPWM00FEN_Pos) |
EADC_T::AD0TRGEN1: EPWM00FEN Mask
Definition at line 10890 of file NUC472_442.h.
| #define EADC_AD0TRGEN1_EPWM00FEN_Pos (1) |
EADC_T::AD0TRGEN1: EPWM00FEN Position
Definition at line 10889 of file NUC472_442.h.
| #define EADC_AD0TRGEN1_EPWM00PEN_Msk (0x1ul << EADC_AD0TRGEN1_EPWM00PEN_Pos) |
EADC_T::AD0TRGEN1: EPWM00PEN Mask
Definition at line 10893 of file NUC472_442.h.
| #define EADC_AD0TRGEN1_EPWM00PEN_Pos (2) |
EADC_T::AD0TRGEN1: EPWM00PEN Position
Definition at line 10892 of file NUC472_442.h.
| #define EADC_AD0TRGEN1_EPWM00REN_Msk (0x1ul << EADC_AD0TRGEN1_EPWM00REN_Pos) |
EADC_T::AD0TRGEN1: EPWM00REN Mask
Definition at line 10887 of file NUC472_442.h.
| #define EADC_AD0TRGEN1_EPWM00REN_Pos (0) |
EADC_T::AD0TRGEN1: EPWM00REN Position
Definition at line 10886 of file NUC472_442.h.
| #define EADC_AD0TRGEN1_EPWM02CEN_Msk (0x1ul << EADC_AD0TRGEN1_EPWM02CEN_Pos) |
EADC_T::AD0TRGEN1: EPWM02CEN Mask
Definition at line 10908 of file NUC472_442.h.
| #define EADC_AD0TRGEN1_EPWM02CEN_Pos (7) |
EADC_T::AD0TRGEN1: EPWM02CEN Position
Definition at line 10907 of file NUC472_442.h.
| #define EADC_AD0TRGEN1_EPWM02FEN_Msk (0x1ul << EADC_AD0TRGEN1_EPWM02FEN_Pos) |
EADC_T::AD0TRGEN1: EPWM02FEN Mask
Definition at line 10902 of file NUC472_442.h.
| #define EADC_AD0TRGEN1_EPWM02FEN_Pos (5) |
EADC_T::AD0TRGEN1: EPWM02FEN Position
Definition at line 10901 of file NUC472_442.h.
| #define EADC_AD0TRGEN1_EPWM02PEN_Msk (0x1ul << EADC_AD0TRGEN1_EPWM02PEN_Pos) |
EADC_T::AD0TRGEN1: EPWM02PEN Mask
Definition at line 10905 of file NUC472_442.h.
| #define EADC_AD0TRGEN1_EPWM02PEN_Pos (6) |
EADC_T::AD0TRGEN1: EPWM02PEN Position
Definition at line 10904 of file NUC472_442.h.
| #define EADC_AD0TRGEN1_EPWM02REN_Msk (0x1ul << EADC_AD0TRGEN1_EPWM02REN_Pos) |
EADC_T::AD0TRGEN1: EPWM02REN Mask
Definition at line 10899 of file NUC472_442.h.
| #define EADC_AD0TRGEN1_EPWM02REN_Pos (4) |
EADC_T::AD0TRGEN1: EPWM02REN Position
Definition at line 10898 of file NUC472_442.h.
| #define EADC_AD0TRGEN1_EPWM04CEN_Msk (0x1ul << EADC_AD0TRGEN1_EPWM04CEN_Pos) |
EADC_T::AD0TRGEN1: EPWM04CEN Mask
Definition at line 10920 of file NUC472_442.h.
| #define EADC_AD0TRGEN1_EPWM04CEN_Pos (11) |
EADC_T::AD0TRGEN1: EPWM04CEN Position
Definition at line 10919 of file NUC472_442.h.
| #define EADC_AD0TRGEN1_EPWM04FEN_Msk (0x1ul << EADC_AD0TRGEN1_EPWM04FEN_Pos) |
EADC_T::AD0TRGEN1: EPWM04FEN Mask
Definition at line 10914 of file NUC472_442.h.
| #define EADC_AD0TRGEN1_EPWM04FEN_Pos (9) |
EADC_T::AD0TRGEN1: EPWM04FEN Position
Definition at line 10913 of file NUC472_442.h.
| #define EADC_AD0TRGEN1_EPWM04PEN_Msk (0x1ul << EADC_AD0TRGEN1_EPWM04PEN_Pos) |
EADC_T::AD0TRGEN1: EPWM04PEN Mask
Definition at line 10917 of file NUC472_442.h.
| #define EADC_AD0TRGEN1_EPWM04PEN_Pos (10) |
EADC_T::AD0TRGEN1: EPWM04PEN Position
Definition at line 10916 of file NUC472_442.h.
| #define EADC_AD0TRGEN1_EPWM04REN_Msk (0x1ul << EADC_AD0TRGEN1_EPWM04REN_Pos) |
EADC_T::AD0TRGEN1: EPWM04REN Mask
Definition at line 10911 of file NUC472_442.h.
| #define EADC_AD0TRGEN1_EPWM04REN_Pos (8) |
EADC_T::AD0TRGEN1: EPWM04REN Position
Definition at line 10910 of file NUC472_442.h.
| #define EADC_AD0TRGEN1_EPWM10CEN_Msk (0x1ul << EADC_AD0TRGEN1_EPWM10CEN_Pos) |
EADC_T::AD0TRGEN1: EPWM10CEN Mask
Definition at line 10932 of file NUC472_442.h.
| #define EADC_AD0TRGEN1_EPWM10CEN_Pos (15) |
EADC_T::AD0TRGEN1: EPWM10CEN Position
Definition at line 10931 of file NUC472_442.h.
| #define EADC_AD0TRGEN1_EPWM10FEN_Msk (0x1ul << EADC_AD0TRGEN1_EPWM10FEN_Pos) |
EADC_T::AD0TRGEN1: EPWM10FEN Mask
Definition at line 10926 of file NUC472_442.h.
| #define EADC_AD0TRGEN1_EPWM10FEN_Pos (13) |
EADC_T::AD0TRGEN1: EPWM10FEN Position
Definition at line 10925 of file NUC472_442.h.
| #define EADC_AD0TRGEN1_EPWM10PEN_Msk (0x1ul << EADC_AD0TRGEN1_EPWM10PEN_Pos) |
EADC_T::AD0TRGEN1: EPWM10PEN Mask
Definition at line 10929 of file NUC472_442.h.
| #define EADC_AD0TRGEN1_EPWM10PEN_Pos (14) |
EADC_T::AD0TRGEN1: EPWM10PEN Position
Definition at line 10928 of file NUC472_442.h.
| #define EADC_AD0TRGEN1_EPWM10REN_Msk (0x1ul << EADC_AD0TRGEN1_EPWM10REN_Pos) |
EADC_T::AD0TRGEN1: EPWM10REN Mask
Definition at line 10923 of file NUC472_442.h.
| #define EADC_AD0TRGEN1_EPWM10REN_Pos (12) |
EADC_T::AD0TRGEN1: EPWM10REN Position
Definition at line 10922 of file NUC472_442.h.
| #define EADC_AD0TRGEN1_EPWM120FEN_Msk (0x1ul << EADC_AD0TRGEN1_EPWM120FEN_Pos) |
EADC_T::AD0TRGEN1: EPWM120FEN Mask
Definition at line 10938 of file NUC472_442.h.
| #define EADC_AD0TRGEN1_EPWM120FEN_Pos (17) |
EADC_T::AD0TRGEN1: EPWM120FEN Position
Definition at line 10937 of file NUC472_442.h.
| #define EADC_AD0TRGEN1_EPWM12CEN_Msk (0x1ul << EADC_AD0TRGEN1_EPWM12CEN_Pos) |
EADC_T::AD0TRGEN1: EPWM12CEN Mask
Definition at line 10944 of file NUC472_442.h.
| #define EADC_AD0TRGEN1_EPWM12CEN_Pos (19) |
EADC_T::AD0TRGEN1: EPWM12CEN Position
Definition at line 10943 of file NUC472_442.h.
| #define EADC_AD0TRGEN1_EPWM12PEN_Msk (0x1ul << EADC_AD0TRGEN1_EPWM12PEN_Pos) |
EADC_T::AD0TRGEN1: EPWM12PEN Mask
Definition at line 10941 of file NUC472_442.h.
| #define EADC_AD0TRGEN1_EPWM12PEN_Pos (18) |
EADC_T::AD0TRGEN1: EPWM12PEN Position
Definition at line 10940 of file NUC472_442.h.
| #define EADC_AD0TRGEN1_EPWM12REN_Msk (0x1ul << EADC_AD0TRGEN1_EPWM12REN_Pos) |
EADC_T::AD0TRGEN1: EPWM12REN Mask
Definition at line 10935 of file NUC472_442.h.
| #define EADC_AD0TRGEN1_EPWM12REN_Pos (16) |
EADC_T::AD0TRGEN1: EPWM12REN Position
Definition at line 10934 of file NUC472_442.h.
| #define EADC_AD0TRGEN1_EPWM14CEN_Msk (0x1ul << EADC_AD0TRGEN1_EPWM14CEN_Pos) |
EADC_T::AD0TRGEN1: EPWM14CEN Mask
Definition at line 10956 of file NUC472_442.h.
| #define EADC_AD0TRGEN1_EPWM14CEN_Pos (23) |
EADC_T::AD0TRGEN1: EPWM14CEN Position
Definition at line 10955 of file NUC472_442.h.
| #define EADC_AD0TRGEN1_EPWM14FEN_Msk (0x1ul << EADC_AD0TRGEN1_EPWM14FEN_Pos) |
EADC_T::AD0TRGEN1: EPWM14FEN Mask
Definition at line 10950 of file NUC472_442.h.
| #define EADC_AD0TRGEN1_EPWM14FEN_Pos (21) |
EADC_T::AD0TRGEN1: EPWM14FEN Position
Definition at line 10949 of file NUC472_442.h.
| #define EADC_AD0TRGEN1_EPWM14PEN_Msk (0x1ul << EADC_AD0TRGEN1_EPWM14PEN_Pos) |
EADC_T::AD0TRGEN1: EPWM14PEN Mask
Definition at line 10953 of file NUC472_442.h.
| #define EADC_AD0TRGEN1_EPWM14PEN_Pos (22) |
EADC_T::AD0TRGEN1: EPWM14PEN Position
Definition at line 10952 of file NUC472_442.h.
| #define EADC_AD0TRGEN1_EPWM14REN_Msk (0x1ul << EADC_AD0TRGEN1_EPWM14REN_Pos) |
EADC_T::AD0TRGEN1: EPWM14REN Mask
Definition at line 10947 of file NUC472_442.h.
| #define EADC_AD0TRGEN1_EPWM14REN_Pos (20) |
EADC_T::AD0TRGEN1: EPWM14REN Position
Definition at line 10946 of file NUC472_442.h.
| #define EADC_AD0TRGEN1_PWM00CEN_Msk (0x1ul << EADC_AD0TRGEN1_PWM00CEN_Pos) |
EADC_T::AD0TRGEN1: PWM00CEN Mask
Definition at line 10968 of file NUC472_442.h.
| #define EADC_AD0TRGEN1_PWM00CEN_Pos (27) |
EADC_T::AD0TRGEN1: PWM00CEN Position
Definition at line 10967 of file NUC472_442.h.
| #define EADC_AD0TRGEN1_PWM00FEN_Msk (0x1ul << EADC_AD0TRGEN1_PWM00FEN_Pos) |
EADC_T::AD0TRGEN1: PWM00FEN Mask
Definition at line 10962 of file NUC472_442.h.
| #define EADC_AD0TRGEN1_PWM00FEN_Pos (25) |
EADC_T::AD0TRGEN1: PWM00FEN Position
Definition at line 10961 of file NUC472_442.h.
| #define EADC_AD0TRGEN1_PWM00PEN_Msk (0x1ul << EADC_AD0TRGEN1_PWM00PEN_Pos) |
EADC_T::AD0TRGEN1: PWM00PEN Mask
Definition at line 10965 of file NUC472_442.h.
| #define EADC_AD0TRGEN1_PWM00PEN_Pos (26) |
EADC_T::AD0TRGEN1: PWM00PEN Position
Definition at line 10964 of file NUC472_442.h.
| #define EADC_AD0TRGEN1_PWM00REN_Msk (0x1ul << EADC_AD0TRGEN1_PWM00REN_Pos) |
EADC_T::AD0TRGEN1: PWM00REN Mask
Definition at line 10959 of file NUC472_442.h.
| #define EADC_AD0TRGEN1_PWM00REN_Pos (24) |
EADC_T::AD0TRGEN1: PWM00REN Position
Definition at line 10958 of file NUC472_442.h.
| #define EADC_AD0TRGEN1_PWM01CEN_Msk (0x1ul << EADC_AD0TRGEN1_PWM01CEN_Pos) |
EADC_T::AD0TRGEN1: PWM01CEN Mask
Definition at line 10980 of file NUC472_442.h.
| #define EADC_AD0TRGEN1_PWM01CEN_Pos (31) |
EADC_T::AD0TRGEN1: PWM01CEN Position
Definition at line 10979 of file NUC472_442.h.
| #define EADC_AD0TRGEN1_PWM01FEN_Msk (0x1ul << EADC_AD0TRGEN1_PWM01FEN_Pos) |
EADC_T::AD0TRGEN1: PWM01FEN Mask
Definition at line 10974 of file NUC472_442.h.
| #define EADC_AD0TRGEN1_PWM01FEN_Pos (29) |
EADC_T::AD0TRGEN1: PWM01FEN Position
Definition at line 10973 of file NUC472_442.h.
| #define EADC_AD0TRGEN1_PWM01PEN_Msk (0x1ul << EADC_AD0TRGEN1_PWM01PEN_Pos) |
EADC_T::AD0TRGEN1: PWM01PEN Mask
Definition at line 10977 of file NUC472_442.h.
| #define EADC_AD0TRGEN1_PWM01PEN_Pos (30) |
EADC_T::AD0TRGEN1: PWM01PEN Position
Definition at line 10976 of file NUC472_442.h.
| #define EADC_AD0TRGEN1_PWM01REN_Msk (0x1ul << EADC_AD0TRGEN1_PWM01REN_Pos) |
EADC_T::AD0TRGEN1: PWM01REN Mask
Definition at line 10971 of file NUC472_442.h.
| #define EADC_AD0TRGEN1_PWM01REN_Pos (28) |
EADC_T::AD0TRGEN1: PWM01REN Position
Definition at line 10970 of file NUC472_442.h.
| #define EADC_AD0TRGEN2_EPWM00CEN_Msk (0x1ul << EADC_AD0TRGEN2_EPWM00CEN_Pos) |
EADC_T::AD0TRGEN2: EPWM00CEN Mask
Definition at line 10992 of file NUC472_442.h.
| #define EADC_AD0TRGEN2_EPWM00CEN_Pos (3) |
EADC_T::AD0TRGEN2: EPWM00CEN Position
Definition at line 10991 of file NUC472_442.h.
| #define EADC_AD0TRGEN2_EPWM00FEN_Msk (0x1ul << EADC_AD0TRGEN2_EPWM00FEN_Pos) |
EADC_T::AD0TRGEN2: EPWM00FEN Mask
Definition at line 10986 of file NUC472_442.h.
| #define EADC_AD0TRGEN2_EPWM00FEN_Pos (1) |
EADC_T::AD0TRGEN2: EPWM00FEN Position
Definition at line 10985 of file NUC472_442.h.
| #define EADC_AD0TRGEN2_EPWM00PEN_Msk (0x1ul << EADC_AD0TRGEN2_EPWM00PEN_Pos) |
EADC_T::AD0TRGEN2: EPWM00PEN Mask
Definition at line 10989 of file NUC472_442.h.
| #define EADC_AD0TRGEN2_EPWM00PEN_Pos (2) |
EADC_T::AD0TRGEN2: EPWM00PEN Position
Definition at line 10988 of file NUC472_442.h.
| #define EADC_AD0TRGEN2_EPWM00REN_Msk (0x1ul << EADC_AD0TRGEN2_EPWM00REN_Pos) |
EADC_T::AD0TRGEN2: EPWM00REN Mask
Definition at line 10983 of file NUC472_442.h.
| #define EADC_AD0TRGEN2_EPWM00REN_Pos (0) |
EADC_T::AD0TRGEN2: EPWM00REN Position
Definition at line 10982 of file NUC472_442.h.
| #define EADC_AD0TRGEN2_EPWM02CEN_Msk (0x1ul << EADC_AD0TRGEN2_EPWM02CEN_Pos) |
EADC_T::AD0TRGEN2: EPWM02CEN Mask
Definition at line 11004 of file NUC472_442.h.
| #define EADC_AD0TRGEN2_EPWM02CEN_Pos (7) |
EADC_T::AD0TRGEN2: EPWM02CEN Position
Definition at line 11003 of file NUC472_442.h.
| #define EADC_AD0TRGEN2_EPWM02FEN_Msk (0x1ul << EADC_AD0TRGEN2_EPWM02FEN_Pos) |
EADC_T::AD0TRGEN2: EPWM02FEN Mask
Definition at line 10998 of file NUC472_442.h.
| #define EADC_AD0TRGEN2_EPWM02FEN_Pos (5) |
EADC_T::AD0TRGEN2: EPWM02FEN Position
Definition at line 10997 of file NUC472_442.h.
| #define EADC_AD0TRGEN2_EPWM02PEN_Msk (0x1ul << EADC_AD0TRGEN2_EPWM02PEN_Pos) |
EADC_T::AD0TRGEN2: EPWM02PEN Mask
Definition at line 11001 of file NUC472_442.h.
| #define EADC_AD0TRGEN2_EPWM02PEN_Pos (6) |
EADC_T::AD0TRGEN2: EPWM02PEN Position
Definition at line 11000 of file NUC472_442.h.
| #define EADC_AD0TRGEN2_EPWM02REN_Msk (0x1ul << EADC_AD0TRGEN2_EPWM02REN_Pos) |
EADC_T::AD0TRGEN2: EPWM02REN Mask
Definition at line 10995 of file NUC472_442.h.
| #define EADC_AD0TRGEN2_EPWM02REN_Pos (4) |
EADC_T::AD0TRGEN2: EPWM02REN Position
Definition at line 10994 of file NUC472_442.h.
| #define EADC_AD0TRGEN2_EPWM04CEN_Msk (0x1ul << EADC_AD0TRGEN2_EPWM04CEN_Pos) |
EADC_T::AD0TRGEN2: EPWM04CEN Mask
Definition at line 11016 of file NUC472_442.h.
| #define EADC_AD0TRGEN2_EPWM04CEN_Pos (11) |
EADC_T::AD0TRGEN2: EPWM04CEN Position
Definition at line 11015 of file NUC472_442.h.
| #define EADC_AD0TRGEN2_EPWM04FEN_Msk (0x1ul << EADC_AD0TRGEN2_EPWM04FEN_Pos) |
EADC_T::AD0TRGEN2: EPWM04FEN Mask
Definition at line 11010 of file NUC472_442.h.
| #define EADC_AD0TRGEN2_EPWM04FEN_Pos (9) |
EADC_T::AD0TRGEN2: EPWM04FEN Position
Definition at line 11009 of file NUC472_442.h.
| #define EADC_AD0TRGEN2_EPWM04PEN_Msk (0x1ul << EADC_AD0TRGEN2_EPWM04PEN_Pos) |
EADC_T::AD0TRGEN2: EPWM04PEN Mask
Definition at line 11013 of file NUC472_442.h.
| #define EADC_AD0TRGEN2_EPWM04PEN_Pos (10) |
EADC_T::AD0TRGEN2: EPWM04PEN Position
Definition at line 11012 of file NUC472_442.h.
| #define EADC_AD0TRGEN2_EPWM04REN_Msk (0x1ul << EADC_AD0TRGEN2_EPWM04REN_Pos) |
EADC_T::AD0TRGEN2: EPWM04REN Mask
Definition at line 11007 of file NUC472_442.h.
| #define EADC_AD0TRGEN2_EPWM04REN_Pos (8) |
EADC_T::AD0TRGEN2: EPWM04REN Position
Definition at line 11006 of file NUC472_442.h.
| #define EADC_AD0TRGEN2_EPWM10CEN_Msk (0x1ul << EADC_AD0TRGEN2_EPWM10CEN_Pos) |
EADC_T::AD0TRGEN2: EPWM10CEN Mask
Definition at line 11028 of file NUC472_442.h.
| #define EADC_AD0TRGEN2_EPWM10CEN_Pos (15) |
EADC_T::AD0TRGEN2: EPWM10CEN Position
Definition at line 11027 of file NUC472_442.h.
| #define EADC_AD0TRGEN2_EPWM10FEN_Msk (0x1ul << EADC_AD0TRGEN2_EPWM10FEN_Pos) |
EADC_T::AD0TRGEN2: EPWM10FEN Mask
Definition at line 11022 of file NUC472_442.h.
| #define EADC_AD0TRGEN2_EPWM10FEN_Pos (13) |
EADC_T::AD0TRGEN2: EPWM10FEN Position
Definition at line 11021 of file NUC472_442.h.
| #define EADC_AD0TRGEN2_EPWM10PEN_Msk (0x1ul << EADC_AD0TRGEN2_EPWM10PEN_Pos) |
EADC_T::AD0TRGEN2: EPWM10PEN Mask
Definition at line 11025 of file NUC472_442.h.
| #define EADC_AD0TRGEN2_EPWM10PEN_Pos (14) |
EADC_T::AD0TRGEN2: EPWM10PEN Position
Definition at line 11024 of file NUC472_442.h.
| #define EADC_AD0TRGEN2_EPWM10REN_Msk (0x1ul << EADC_AD0TRGEN2_EPWM10REN_Pos) |
EADC_T::AD0TRGEN2: EPWM10REN Mask
Definition at line 11019 of file NUC472_442.h.
| #define EADC_AD0TRGEN2_EPWM10REN_Pos (12) |
EADC_T::AD0TRGEN2: EPWM10REN Position
Definition at line 11018 of file NUC472_442.h.
| #define EADC_AD0TRGEN2_EPWM120FEN_Msk (0x1ul << EADC_AD0TRGEN2_EPWM120FEN_Pos) |
EADC_T::AD0TRGEN2: EPWM120FEN Mask
Definition at line 11034 of file NUC472_442.h.
| #define EADC_AD0TRGEN2_EPWM120FEN_Pos (17) |
EADC_T::AD0TRGEN2: EPWM120FEN Position
Definition at line 11033 of file NUC472_442.h.
| #define EADC_AD0TRGEN2_EPWM12CEN_Msk (0x1ul << EADC_AD0TRGEN2_EPWM12CEN_Pos) |
EADC_T::AD0TRGEN2: EPWM12CEN Mask
Definition at line 11040 of file NUC472_442.h.
| #define EADC_AD0TRGEN2_EPWM12CEN_Pos (19) |
EADC_T::AD0TRGEN2: EPWM12CEN Position
Definition at line 11039 of file NUC472_442.h.
| #define EADC_AD0TRGEN2_EPWM12PEN_Msk (0x1ul << EADC_AD0TRGEN2_EPWM12PEN_Pos) |
EADC_T::AD0TRGEN2: EPWM12PEN Mask
Definition at line 11037 of file NUC472_442.h.
| #define EADC_AD0TRGEN2_EPWM12PEN_Pos (18) |
EADC_T::AD0TRGEN2: EPWM12PEN Position
Definition at line 11036 of file NUC472_442.h.
| #define EADC_AD0TRGEN2_EPWM12REN_Msk (0x1ul << EADC_AD0TRGEN2_EPWM12REN_Pos) |
EADC_T::AD0TRGEN2: EPWM12REN Mask
Definition at line 11031 of file NUC472_442.h.
| #define EADC_AD0TRGEN2_EPWM12REN_Pos (16) |
EADC_T::AD0TRGEN2: EPWM12REN Position
Definition at line 11030 of file NUC472_442.h.
| #define EADC_AD0TRGEN2_EPWM14CEN_Msk (0x1ul << EADC_AD0TRGEN2_EPWM14CEN_Pos) |
EADC_T::AD0TRGEN2: EPWM14CEN Mask
Definition at line 11052 of file NUC472_442.h.
| #define EADC_AD0TRGEN2_EPWM14CEN_Pos (23) |
EADC_T::AD0TRGEN2: EPWM14CEN Position
Definition at line 11051 of file NUC472_442.h.
| #define EADC_AD0TRGEN2_EPWM14FEN_Msk (0x1ul << EADC_AD0TRGEN2_EPWM14FEN_Pos) |
EADC_T::AD0TRGEN2: EPWM14FEN Mask
Definition at line 11046 of file NUC472_442.h.
| #define EADC_AD0TRGEN2_EPWM14FEN_Pos (21) |
EADC_T::AD0TRGEN2: EPWM14FEN Position
Definition at line 11045 of file NUC472_442.h.
| #define EADC_AD0TRGEN2_EPWM14PEN_Msk (0x1ul << EADC_AD0TRGEN2_EPWM14PEN_Pos) |
EADC_T::AD0TRGEN2: EPWM14PEN Mask
Definition at line 11049 of file NUC472_442.h.
| #define EADC_AD0TRGEN2_EPWM14PEN_Pos (22) |
EADC_T::AD0TRGEN2: EPWM14PEN Position
Definition at line 11048 of file NUC472_442.h.
| #define EADC_AD0TRGEN2_EPWM14REN_Msk (0x1ul << EADC_AD0TRGEN2_EPWM14REN_Pos) |
EADC_T::AD0TRGEN2: EPWM14REN Mask
Definition at line 11043 of file NUC472_442.h.
| #define EADC_AD0TRGEN2_EPWM14REN_Pos (20) |
EADC_T::AD0TRGEN2: EPWM14REN Position
Definition at line 11042 of file NUC472_442.h.
| #define EADC_AD0TRGEN2_PWM00CEN_Msk (0x1ul << EADC_AD0TRGEN2_PWM00CEN_Pos) |
EADC_T::AD0TRGEN2: PWM00CEN Mask
Definition at line 11064 of file NUC472_442.h.
| #define EADC_AD0TRGEN2_PWM00CEN_Pos (27) |
EADC_T::AD0TRGEN2: PWM00CEN Position
Definition at line 11063 of file NUC472_442.h.
| #define EADC_AD0TRGEN2_PWM00FEN_Msk (0x1ul << EADC_AD0TRGEN2_PWM00FEN_Pos) |
EADC_T::AD0TRGEN2: PWM00FEN Mask
Definition at line 11058 of file NUC472_442.h.
| #define EADC_AD0TRGEN2_PWM00FEN_Pos (25) |
EADC_T::AD0TRGEN2: PWM00FEN Position
Definition at line 11057 of file NUC472_442.h.
| #define EADC_AD0TRGEN2_PWM00PEN_Msk (0x1ul << EADC_AD0TRGEN2_PWM00PEN_Pos) |
EADC_T::AD0TRGEN2: PWM00PEN Mask
Definition at line 11061 of file NUC472_442.h.
| #define EADC_AD0TRGEN2_PWM00PEN_Pos (26) |
EADC_T::AD0TRGEN2: PWM00PEN Position
Definition at line 11060 of file NUC472_442.h.
| #define EADC_AD0TRGEN2_PWM00REN_Msk (0x1ul << EADC_AD0TRGEN2_PWM00REN_Pos) |
EADC_T::AD0TRGEN2: PWM00REN Mask
Definition at line 11055 of file NUC472_442.h.
| #define EADC_AD0TRGEN2_PWM00REN_Pos (24) |
EADC_T::AD0TRGEN2: PWM00REN Position
Definition at line 11054 of file NUC472_442.h.
| #define EADC_AD0TRGEN2_PWM01CEN_Msk (0x1ul << EADC_AD0TRGEN2_PWM01CEN_Pos) |
EADC_T::AD0TRGEN2: PWM01CEN Mask
Definition at line 11076 of file NUC472_442.h.
| #define EADC_AD0TRGEN2_PWM01CEN_Pos (31) |
EADC_T::AD0TRGEN2: PWM01CEN Position
Definition at line 11075 of file NUC472_442.h.
| #define EADC_AD0TRGEN2_PWM01FEN_Msk (0x1ul << EADC_AD0TRGEN2_PWM01FEN_Pos) |
EADC_T::AD0TRGEN2: PWM01FEN Mask
Definition at line 11070 of file NUC472_442.h.
| #define EADC_AD0TRGEN2_PWM01FEN_Pos (29) |
EADC_T::AD0TRGEN2: PWM01FEN Position
Definition at line 11069 of file NUC472_442.h.
| #define EADC_AD0TRGEN2_PWM01PEN_Msk (0x1ul << EADC_AD0TRGEN2_PWM01PEN_Pos) |
EADC_T::AD0TRGEN2: PWM01PEN Mask
Definition at line 11073 of file NUC472_442.h.
| #define EADC_AD0TRGEN2_PWM01PEN_Pos (30) |
EADC_T::AD0TRGEN2: PWM01PEN Position
Definition at line 11072 of file NUC472_442.h.
| #define EADC_AD0TRGEN2_PWM01REN_Msk (0x1ul << EADC_AD0TRGEN2_PWM01REN_Pos) |
EADC_T::AD0TRGEN2: PWM01REN Mask
Definition at line 11067 of file NUC472_442.h.
| #define EADC_AD0TRGEN2_PWM01REN_Pos (28) |
EADC_T::AD0TRGEN2: PWM01REN Position
Definition at line 11066 of file NUC472_442.h.
| #define EADC_AD0TRGEN3_EPWM00CEN_Msk (0x1ul << EADC_AD0TRGEN3_EPWM00CEN_Pos) |
EADC_T::AD0TRGEN3: EPWM00CEN Mask
Definition at line 11088 of file NUC472_442.h.
| #define EADC_AD0TRGEN3_EPWM00CEN_Pos (3) |
EADC_T::AD0TRGEN3: EPWM00CEN Position
Definition at line 11087 of file NUC472_442.h.
| #define EADC_AD0TRGEN3_EPWM00FEN_Msk (0x1ul << EADC_AD0TRGEN3_EPWM00FEN_Pos) |
EADC_T::AD0TRGEN3: EPWM00FEN Mask
Definition at line 11082 of file NUC472_442.h.
| #define EADC_AD0TRGEN3_EPWM00FEN_Pos (1) |
EADC_T::AD0TRGEN3: EPWM00FEN Position
Definition at line 11081 of file NUC472_442.h.
| #define EADC_AD0TRGEN3_EPWM00PEN_Msk (0x1ul << EADC_AD0TRGEN3_EPWM00PEN_Pos) |
EADC_T::AD0TRGEN3: EPWM00PEN Mask
Definition at line 11085 of file NUC472_442.h.
| #define EADC_AD0TRGEN3_EPWM00PEN_Pos (2) |
EADC_T::AD0TRGEN3: EPWM00PEN Position
Definition at line 11084 of file NUC472_442.h.
| #define EADC_AD0TRGEN3_EPWM00REN_Msk (0x1ul << EADC_AD0TRGEN3_EPWM00REN_Pos) |
EADC_T::AD0TRGEN3: EPWM00REN Mask
Definition at line 11079 of file NUC472_442.h.
| #define EADC_AD0TRGEN3_EPWM00REN_Pos (0) |
EADC_T::AD0TRGEN3: EPWM00REN Position
Definition at line 11078 of file NUC472_442.h.
| #define EADC_AD0TRGEN3_EPWM02CEN_Msk (0x1ul << EADC_AD0TRGEN3_EPWM02CEN_Pos) |
EADC_T::AD0TRGEN3: EPWM02CEN Mask
Definition at line 11100 of file NUC472_442.h.
| #define EADC_AD0TRGEN3_EPWM02CEN_Pos (7) |
EADC_T::AD0TRGEN3: EPWM02CEN Position
Definition at line 11099 of file NUC472_442.h.
| #define EADC_AD0TRGEN3_EPWM02FEN_Msk (0x1ul << EADC_AD0TRGEN3_EPWM02FEN_Pos) |
EADC_T::AD0TRGEN3: EPWM02FEN Mask
Definition at line 11094 of file NUC472_442.h.
| #define EADC_AD0TRGEN3_EPWM02FEN_Pos (5) |
EADC_T::AD0TRGEN3: EPWM02FEN Position
Definition at line 11093 of file NUC472_442.h.
| #define EADC_AD0TRGEN3_EPWM02PEN_Msk (0x1ul << EADC_AD0TRGEN3_EPWM02PEN_Pos) |
EADC_T::AD0TRGEN3: EPWM02PEN Mask
Definition at line 11097 of file NUC472_442.h.
| #define EADC_AD0TRGEN3_EPWM02PEN_Pos (6) |
EADC_T::AD0TRGEN3: EPWM02PEN Position
Definition at line 11096 of file NUC472_442.h.
| #define EADC_AD0TRGEN3_EPWM02REN_Msk (0x1ul << EADC_AD0TRGEN3_EPWM02REN_Pos) |
EADC_T::AD0TRGEN3: EPWM02REN Mask
Definition at line 11091 of file NUC472_442.h.
| #define EADC_AD0TRGEN3_EPWM02REN_Pos (4) |
EADC_T::AD0TRGEN3: EPWM02REN Position
Definition at line 11090 of file NUC472_442.h.
| #define EADC_AD0TRGEN3_EPWM04CEN_Msk (0x1ul << EADC_AD0TRGEN3_EPWM04CEN_Pos) |
EADC_T::AD0TRGEN3: EPWM04CEN Mask
Definition at line 11112 of file NUC472_442.h.
| #define EADC_AD0TRGEN3_EPWM04CEN_Pos (11) |
EADC_T::AD0TRGEN3: EPWM04CEN Position
Definition at line 11111 of file NUC472_442.h.
| #define EADC_AD0TRGEN3_EPWM04FEN_Msk (0x1ul << EADC_AD0TRGEN3_EPWM04FEN_Pos) |
EADC_T::AD0TRGEN3: EPWM04FEN Mask
Definition at line 11106 of file NUC472_442.h.
| #define EADC_AD0TRGEN3_EPWM04FEN_Pos (9) |
EADC_T::AD0TRGEN3: EPWM04FEN Position
Definition at line 11105 of file NUC472_442.h.
| #define EADC_AD0TRGEN3_EPWM04PEN_Msk (0x1ul << EADC_AD0TRGEN3_EPWM04PEN_Pos) |
EADC_T::AD0TRGEN3: EPWM04PEN Mask
Definition at line 11109 of file NUC472_442.h.
| #define EADC_AD0TRGEN3_EPWM04PEN_Pos (10) |
EADC_T::AD0TRGEN3: EPWM04PEN Position
Definition at line 11108 of file NUC472_442.h.
| #define EADC_AD0TRGEN3_EPWM04REN_Msk (0x1ul << EADC_AD0TRGEN3_EPWM04REN_Pos) |
EADC_T::AD0TRGEN3: EPWM04REN Mask
Definition at line 11103 of file NUC472_442.h.
| #define EADC_AD0TRGEN3_EPWM04REN_Pos (8) |
EADC_T::AD0TRGEN3: EPWM04REN Position
Definition at line 11102 of file NUC472_442.h.
| #define EADC_AD0TRGEN3_EPWM10CEN_Msk (0x1ul << EADC_AD0TRGEN3_EPWM10CEN_Pos) |
EADC_T::AD0TRGEN3: EPWM10CEN Mask
Definition at line 11124 of file NUC472_442.h.
| #define EADC_AD0TRGEN3_EPWM10CEN_Pos (15) |
EADC_T::AD0TRGEN3: EPWM10CEN Position
Definition at line 11123 of file NUC472_442.h.
| #define EADC_AD0TRGEN3_EPWM10FEN_Msk (0x1ul << EADC_AD0TRGEN3_EPWM10FEN_Pos) |
EADC_T::AD0TRGEN3: EPWM10FEN Mask
Definition at line 11118 of file NUC472_442.h.
| #define EADC_AD0TRGEN3_EPWM10FEN_Pos (13) |
EADC_T::AD0TRGEN3: EPWM10FEN Position
Definition at line 11117 of file NUC472_442.h.
| #define EADC_AD0TRGEN3_EPWM10PEN_Msk (0x1ul << EADC_AD0TRGEN3_EPWM10PEN_Pos) |
EADC_T::AD0TRGEN3: EPWM10PEN Mask
Definition at line 11121 of file NUC472_442.h.
| #define EADC_AD0TRGEN3_EPWM10PEN_Pos (14) |
EADC_T::AD0TRGEN3: EPWM10PEN Position
Definition at line 11120 of file NUC472_442.h.
| #define EADC_AD0TRGEN3_EPWM10REN_Msk (0x1ul << EADC_AD0TRGEN3_EPWM10REN_Pos) |
EADC_T::AD0TRGEN3: EPWM10REN Mask
Definition at line 11115 of file NUC472_442.h.
| #define EADC_AD0TRGEN3_EPWM10REN_Pos (12) |
EADC_T::AD0TRGEN3: EPWM10REN Position
Definition at line 11114 of file NUC472_442.h.
| #define EADC_AD0TRGEN3_EPWM120FEN_Msk (0x1ul << EADC_AD0TRGEN3_EPWM120FEN_Pos) |
EADC_T::AD0TRGEN3: EPWM120FEN Mask
Definition at line 11130 of file NUC472_442.h.
| #define EADC_AD0TRGEN3_EPWM120FEN_Pos (17) |
EADC_T::AD0TRGEN3: EPWM120FEN Position
Definition at line 11129 of file NUC472_442.h.
| #define EADC_AD0TRGEN3_EPWM12CEN_Msk (0x1ul << EADC_AD0TRGEN3_EPWM12CEN_Pos) |
EADC_T::AD0TRGEN3: EPWM12CEN Mask
Definition at line 11136 of file NUC472_442.h.
| #define EADC_AD0TRGEN3_EPWM12CEN_Pos (19) |
EADC_T::AD0TRGEN3: EPWM12CEN Position
Definition at line 11135 of file NUC472_442.h.
| #define EADC_AD0TRGEN3_EPWM12PEN_Msk (0x1ul << EADC_AD0TRGEN3_EPWM12PEN_Pos) |
EADC_T::AD0TRGEN3: EPWM12PEN Mask
Definition at line 11133 of file NUC472_442.h.
| #define EADC_AD0TRGEN3_EPWM12PEN_Pos (18) |
EADC_T::AD0TRGEN3: EPWM12PEN Position
Definition at line 11132 of file NUC472_442.h.
| #define EADC_AD0TRGEN3_EPWM12REN_Msk (0x1ul << EADC_AD0TRGEN3_EPWM12REN_Pos) |
EADC_T::AD0TRGEN3: EPWM12REN Mask
Definition at line 11127 of file NUC472_442.h.
| #define EADC_AD0TRGEN3_EPWM12REN_Pos (16) |
EADC_T::AD0TRGEN3: EPWM12REN Position
Definition at line 11126 of file NUC472_442.h.
| #define EADC_AD0TRGEN3_EPWM14CEN_Msk (0x1ul << EADC_AD0TRGEN3_EPWM14CEN_Pos) |
EADC_T::AD0TRGEN3: EPWM14CEN Mask
Definition at line 11148 of file NUC472_442.h.
| #define EADC_AD0TRGEN3_EPWM14CEN_Pos (23) |
EADC_T::AD0TRGEN3: EPWM14CEN Position
Definition at line 11147 of file NUC472_442.h.
| #define EADC_AD0TRGEN3_EPWM14FEN_Msk (0x1ul << EADC_AD0TRGEN3_EPWM14FEN_Pos) |
EADC_T::AD0TRGEN3: EPWM14FEN Mask
Definition at line 11142 of file NUC472_442.h.
| #define EADC_AD0TRGEN3_EPWM14FEN_Pos (21) |
EADC_T::AD0TRGEN3: EPWM14FEN Position
Definition at line 11141 of file NUC472_442.h.
| #define EADC_AD0TRGEN3_EPWM14PEN_Msk (0x1ul << EADC_AD0TRGEN3_EPWM14PEN_Pos) |
EADC_T::AD0TRGEN3: EPWM14PEN Mask
Definition at line 11145 of file NUC472_442.h.
| #define EADC_AD0TRGEN3_EPWM14PEN_Pos (22) |
EADC_T::AD0TRGEN3: EPWM14PEN Position
Definition at line 11144 of file NUC472_442.h.
| #define EADC_AD0TRGEN3_EPWM14REN_Msk (0x1ul << EADC_AD0TRGEN3_EPWM14REN_Pos) |
EADC_T::AD0TRGEN3: EPWM14REN Mask
Definition at line 11139 of file NUC472_442.h.
| #define EADC_AD0TRGEN3_EPWM14REN_Pos (20) |
EADC_T::AD0TRGEN3: EPWM14REN Position
Definition at line 11138 of file NUC472_442.h.
| #define EADC_AD0TRGEN3_PWM00CEN_Msk (0x1ul << EADC_AD0TRGEN3_PWM00CEN_Pos) |
EADC_T::AD0TRGEN3: PWM00CEN Mask
Definition at line 11160 of file NUC472_442.h.
| #define EADC_AD0TRGEN3_PWM00CEN_Pos (27) |
EADC_T::AD0TRGEN3: PWM00CEN Position
Definition at line 11159 of file NUC472_442.h.
| #define EADC_AD0TRGEN3_PWM00FEN_Msk (0x1ul << EADC_AD0TRGEN3_PWM00FEN_Pos) |
EADC_T::AD0TRGEN3: PWM00FEN Mask
Definition at line 11154 of file NUC472_442.h.
| #define EADC_AD0TRGEN3_PWM00FEN_Pos (25) |
EADC_T::AD0TRGEN3: PWM00FEN Position
Definition at line 11153 of file NUC472_442.h.
| #define EADC_AD0TRGEN3_PWM00PEN_Msk (0x1ul << EADC_AD0TRGEN3_PWM00PEN_Pos) |
EADC_T::AD0TRGEN3: PWM00PEN Mask
Definition at line 11157 of file NUC472_442.h.
| #define EADC_AD0TRGEN3_PWM00PEN_Pos (26) |
EADC_T::AD0TRGEN3: PWM00PEN Position
Definition at line 11156 of file NUC472_442.h.
| #define EADC_AD0TRGEN3_PWM00REN_Msk (0x1ul << EADC_AD0TRGEN3_PWM00REN_Pos) |
EADC_T::AD0TRGEN3: PWM00REN Mask
Definition at line 11151 of file NUC472_442.h.
| #define EADC_AD0TRGEN3_PWM00REN_Pos (24) |
EADC_T::AD0TRGEN3: PWM00REN Position
Definition at line 11150 of file NUC472_442.h.
| #define EADC_AD0TRGEN3_PWM01CEN_Msk (0x1ul << EADC_AD0TRGEN3_PWM01CEN_Pos) |
EADC_T::AD0TRGEN3: PWM01CEN Mask
Definition at line 11172 of file NUC472_442.h.
| #define EADC_AD0TRGEN3_PWM01CEN_Pos (31) |
EADC_T::AD0TRGEN3: PWM01CEN Position
Definition at line 11171 of file NUC472_442.h.
| #define EADC_AD0TRGEN3_PWM01FEN_Msk (0x1ul << EADC_AD0TRGEN3_PWM01FEN_Pos) |
EADC_T::AD0TRGEN3: PWM01FEN Mask
Definition at line 11166 of file NUC472_442.h.
| #define EADC_AD0TRGEN3_PWM01FEN_Pos (29) |
EADC_T::AD0TRGEN3: PWM01FEN Position
Definition at line 11165 of file NUC472_442.h.
| #define EADC_AD0TRGEN3_PWM01PEN_Msk (0x1ul << EADC_AD0TRGEN3_PWM01PEN_Pos) |
EADC_T::AD0TRGEN3: PWM01PEN Mask
Definition at line 11169 of file NUC472_442.h.
| #define EADC_AD0TRGEN3_PWM01PEN_Pos (30) |
EADC_T::AD0TRGEN3: PWM01PEN Position
Definition at line 11168 of file NUC472_442.h.
| #define EADC_AD0TRGEN3_PWM01REN_Msk (0x1ul << EADC_AD0TRGEN3_PWM01REN_Pos) |
EADC_T::AD0TRGEN3: PWM01REN Mask
Definition at line 11163 of file NUC472_442.h.
| #define EADC_AD0TRGEN3_PWM01REN_Pos (28) |
EADC_T::AD0TRGEN3: PWM01REN Position
Definition at line 11162 of file NUC472_442.h.
| #define EADC_AD1DAT0_OV_Msk (0x1ul << EADC_AD1DAT0_OV_Pos) |
EADC_T::AD1DAT0: OV Mask
Definition at line 10050 of file NUC472_442.h.
| #define EADC_AD1DAT0_OV_Pos (16) |
EADC_T::AD1DAT0: OV Position
Definition at line 10049 of file NUC472_442.h.
| #define EADC_AD1DAT0_RESULT_Msk (0xffful << EADC_AD1DAT0_RESULT_Pos) |
EADC_T::AD1DAT0: RESULT Mask
Definition at line 10047 of file NUC472_442.h.
| #define EADC_AD1DAT0_RESULT_Pos (0) |
EADC_T::AD1DAT0: RESULT Position
Definition at line 10046 of file NUC472_442.h.
| #define EADC_AD1DAT0_VALID_Msk (0x1ul << EADC_AD1DAT0_VALID_Pos) |
EADC_T::AD1DAT0: VALID Mask
Definition at line 10053 of file NUC472_442.h.
| #define EADC_AD1DAT0_VALID_Pos (17) |
EADC_T::AD1DAT0: VALID Position
Definition at line 10052 of file NUC472_442.h.
| #define EADC_AD1DAT1_OV_Msk (0x1ul << EADC_AD1DAT1_OV_Pos) |
EADC_T::AD1DAT1: OV Mask
Definition at line 10059 of file NUC472_442.h.
| #define EADC_AD1DAT1_OV_Pos (16) |
EADC_T::AD1DAT1: OV Position
Definition at line 10058 of file NUC472_442.h.
| #define EADC_AD1DAT1_RESULT_Msk (0xffful << EADC_AD1DAT1_RESULT_Pos) |
EADC_T::AD1DAT1: RESULT Mask
Definition at line 10056 of file NUC472_442.h.
| #define EADC_AD1DAT1_RESULT_Pos (0) |
EADC_T::AD1DAT1: RESULT Position
Definition at line 10055 of file NUC472_442.h.
| #define EADC_AD1DAT1_VALID_Msk (0x1ul << EADC_AD1DAT1_VALID_Pos) |
EADC_T::AD1DAT1: VALID Mask
Definition at line 10062 of file NUC472_442.h.
| #define EADC_AD1DAT1_VALID_Pos (17) |
EADC_T::AD1DAT1: VALID Position
Definition at line 10061 of file NUC472_442.h.
| #define EADC_AD1DAT2_OV_Msk (0x1ul << EADC_AD1DAT2_OV_Pos) |
EADC_T::AD1DAT2: OV Mask
Definition at line 10068 of file NUC472_442.h.
| #define EADC_AD1DAT2_OV_Pos (16) |
EADC_T::AD1DAT2: OV Position
Definition at line 10067 of file NUC472_442.h.
| #define EADC_AD1DAT2_RESULT_Msk (0xffful << EADC_AD1DAT2_RESULT_Pos) |
EADC_T::AD1DAT2: RESULT Mask
Definition at line 10065 of file NUC472_442.h.
| #define EADC_AD1DAT2_RESULT_Pos (0) |
EADC_T::AD1DAT2: RESULT Position
Definition at line 10064 of file NUC472_442.h.
| #define EADC_AD1DAT2_VALID_Msk (0x1ul << EADC_AD1DAT2_VALID_Pos) |
EADC_T::AD1DAT2: VALID Mask
Definition at line 10071 of file NUC472_442.h.
| #define EADC_AD1DAT2_VALID_Pos (17) |
EADC_T::AD1DAT2: VALID Position
Definition at line 10070 of file NUC472_442.h.
| #define EADC_AD1DAT3_OV_Msk (0x1ul << EADC_AD1DAT3_OV_Pos) |
EADC_T::AD1DAT3: OV Mask
Definition at line 10077 of file NUC472_442.h.
| #define EADC_AD1DAT3_OV_Pos (16) |
EADC_T::AD1DAT3: OV Position
Definition at line 10076 of file NUC472_442.h.
| #define EADC_AD1DAT3_RESULT_Msk (0xffful << EADC_AD1DAT3_RESULT_Pos) |
EADC_T::AD1DAT3: RESULT Mask
Definition at line 10074 of file NUC472_442.h.
| #define EADC_AD1DAT3_RESULT_Pos (0) |
EADC_T::AD1DAT3: RESULT Position
Definition at line 10073 of file NUC472_442.h.
| #define EADC_AD1DAT3_VALID_Msk (0x1ul << EADC_AD1DAT3_VALID_Pos) |
EADC_T::AD1DAT3: VALID Mask
Definition at line 10080 of file NUC472_442.h.
| #define EADC_AD1DAT3_VALID_Pos (17) |
EADC_T::AD1DAT3: VALID Position
Definition at line 10079 of file NUC472_442.h.
| #define EADC_AD1DAT4_OV_Msk (0x1ul << EADC_AD1DAT4_OV_Pos) |
EADC_T::AD1DAT4: OV Mask
Definition at line 10086 of file NUC472_442.h.
| #define EADC_AD1DAT4_OV_Pos (16) |
EADC_T::AD1DAT4: OV Position
Definition at line 10085 of file NUC472_442.h.
| #define EADC_AD1DAT4_RESULT_Msk (0xffful << EADC_AD1DAT4_RESULT_Pos) |
EADC_T::AD1DAT4: RESULT Mask
Definition at line 10083 of file NUC472_442.h.
| #define EADC_AD1DAT4_RESULT_Pos (0) |
EADC_T::AD1DAT4: RESULT Position
Definition at line 10082 of file NUC472_442.h.
| #define EADC_AD1DAT4_VALID_Msk (0x1ul << EADC_AD1DAT4_VALID_Pos) |
EADC_T::AD1DAT4: VALID Mask
Definition at line 10089 of file NUC472_442.h.
| #define EADC_AD1DAT4_VALID_Pos (17) |
EADC_T::AD1DAT4: VALID Position
Definition at line 10088 of file NUC472_442.h.
| #define EADC_AD1DAT5_OV_Msk (0x1ul << EADC_AD1DAT5_OV_Pos) |
EADC_T::AD1DAT5: OV Mask
Definition at line 10095 of file NUC472_442.h.
| #define EADC_AD1DAT5_OV_Pos (16) |
EADC_T::AD1DAT5: OV Position
Definition at line 10094 of file NUC472_442.h.
| #define EADC_AD1DAT5_RESULT_Msk (0xffful << EADC_AD1DAT5_RESULT_Pos) |
EADC_T::AD1DAT5: RESULT Mask
Definition at line 10092 of file NUC472_442.h.
| #define EADC_AD1DAT5_RESULT_Pos (0) |
EADC_T::AD1DAT5: RESULT Position
Definition at line 10091 of file NUC472_442.h.
| #define EADC_AD1DAT5_VALID_Msk (0x1ul << EADC_AD1DAT5_VALID_Pos) |
EADC_T::AD1DAT5: VALID Mask
Definition at line 10098 of file NUC472_442.h.
| #define EADC_AD1DAT5_VALID_Pos (17) |
EADC_T::AD1DAT5: VALID Position
Definition at line 10097 of file NUC472_442.h.
| #define EADC_AD1DAT6_OV_Msk (0x1ul << EADC_AD1DAT6_OV_Pos) |
EADC_T::AD1DAT6: OV Mask
Definition at line 10104 of file NUC472_442.h.
| #define EADC_AD1DAT6_OV_Pos (16) |
EADC_T::AD1DAT6: OV Position
Definition at line 10103 of file NUC472_442.h.
| #define EADC_AD1DAT6_RESULT_Msk (0xffful << EADC_AD1DAT6_RESULT_Pos) |
EADC_T::AD1DAT6: RESULT Mask
Definition at line 10101 of file NUC472_442.h.
| #define EADC_AD1DAT6_RESULT_Pos (0) |
EADC_T::AD1DAT6: RESULT Position
Definition at line 10100 of file NUC472_442.h.
| #define EADC_AD1DAT6_VALID_Msk (0x1ul << EADC_AD1DAT6_VALID_Pos) |
EADC_T::AD1DAT6: VALID Mask
Definition at line 10107 of file NUC472_442.h.
| #define EADC_AD1DAT6_VALID_Pos (17) |
EADC_T::AD1DAT6: VALID Position
Definition at line 10106 of file NUC472_442.h.
| #define EADC_AD1DAT7_OV_Msk (0x1ul << EADC_AD1DAT7_OV_Pos) |
EADC_T::AD1DAT7: OV Mask
Definition at line 10113 of file NUC472_442.h.
| #define EADC_AD1DAT7_OV_Pos (16) |
EADC_T::AD1DAT7: OV Position
Definition at line 10112 of file NUC472_442.h.
| #define EADC_AD1DAT7_RESULT_Msk (0xffful << EADC_AD1DAT7_RESULT_Pos) |
EADC_T::AD1DAT7: RESULT Mask
Definition at line 10110 of file NUC472_442.h.
| #define EADC_AD1DAT7_RESULT_Pos (0) |
EADC_T::AD1DAT7: RESULT Position
Definition at line 10109 of file NUC472_442.h.
| #define EADC_AD1DAT7_VALID_Msk (0x1ul << EADC_AD1DAT7_VALID_Pos) |
EADC_T::AD1DAT7: VALID Mask
Definition at line 10116 of file NUC472_442.h.
| #define EADC_AD1DAT7_VALID_Pos (17) |
EADC_T::AD1DAT7: VALID Position
Definition at line 10115 of file NUC472_442.h.
| #define EADC_AD1DDAT0_RESULT_Msk (0xffful << EADC_AD1DDAT0_RESULT_Pos) |
EADC_T::AD1DDAT0: RESULT Mask
Definition at line 10551 of file NUC472_442.h.
| #define EADC_AD1DDAT0_RESULT_Pos (0) |
EADC_T::AD1DDAT0: RESULT Position
Definition at line 10550 of file NUC472_442.h.
| #define EADC_AD1DDAT0_VALID_Msk (0x1ul << EADC_AD1DDAT0_VALID_Pos) |
EADC_T::AD1DDAT0: VALID Mask
Definition at line 10554 of file NUC472_442.h.
| #define EADC_AD1DDAT0_VALID_Pos (16) |
EADC_T::AD1DDAT0: VALID Position
Definition at line 10553 of file NUC472_442.h.
| #define EADC_AD1DDAT1_RESULT_Msk (0xffful << EADC_AD1DDAT1_RESULT_Pos) |
EADC_T::AD1DDAT1: RESULT Mask
Definition at line 10557 of file NUC472_442.h.
| #define EADC_AD1DDAT1_RESULT_Pos (0) |
EADC_T::AD1DDAT1: RESULT Position
Definition at line 10556 of file NUC472_442.h.
| #define EADC_AD1DDAT1_VALID_Msk (0x1ul << EADC_AD1DDAT1_VALID_Pos) |
EADC_T::AD1DDAT1: VALID Mask
Definition at line 10560 of file NUC472_442.h.
| #define EADC_AD1DDAT1_VALID_Pos (16) |
EADC_T::AD1DDAT1: VALID Position
Definition at line 10559 of file NUC472_442.h.
| #define EADC_AD1DDAT2_RESULT_Msk (0xffful << EADC_AD1DDAT2_RESULT_Pos) |
EADC_T::AD1DDAT2: RESULT Mask
Definition at line 10563 of file NUC472_442.h.
| #define EADC_AD1DDAT2_RESULT_Pos (0) |
EADC_T::AD1DDAT2: RESULT Position
Definition at line 10562 of file NUC472_442.h.
| #define EADC_AD1DDAT2_VALID_Msk (0x1ul << EADC_AD1DDAT2_VALID_Pos) |
EADC_T::AD1DDAT2: VALID Mask
Definition at line 10566 of file NUC472_442.h.
| #define EADC_AD1DDAT2_VALID_Pos (16) |
EADC_T::AD1DDAT2: VALID Position
Definition at line 10565 of file NUC472_442.h.
| #define EADC_AD1DDAT3_RESULT_Msk (0xffful << EADC_AD1DDAT3_RESULT_Pos) |
EADC_T::AD1DDAT3: RESULT Mask
Definition at line 10569 of file NUC472_442.h.
| #define EADC_AD1DDAT3_RESULT_Pos (0) |
EADC_T::AD1DDAT3: RESULT Position
Definition at line 10568 of file NUC472_442.h.
| #define EADC_AD1DDAT3_VALID_Msk (0x1ul << EADC_AD1DDAT3_VALID_Pos) |
EADC_T::AD1DDAT3: VALID Mask
Definition at line 10572 of file NUC472_442.h.
| #define EADC_AD1DDAT3_VALID_Pos (16) |
EADC_T::AD1DDAT3: VALID Position
Definition at line 10571 of file NUC472_442.h.
| #define EADC_AD1SPCTL0_CHSEL_Msk (0xful << EADC_AD1SPCTL0_CHSEL_Pos) |
EADC_T::AD1SPCTL0: CHSEL Mask
Definition at line 10287 of file NUC472_442.h.
| #define EADC_AD1SPCTL0_CHSEL_Pos (0) |
EADC_T::AD1SPCTL0: CHSEL Position
Definition at line 10286 of file NUC472_442.h.
| #define EADC_AD1SPCTL0_EXTFEN_Msk (0x1ul << EADC_AD1SPCTL0_EXTFEN_Pos) |
EADC_T::AD1SPCTL0: EXTFEN Mask
Definition at line 10302 of file NUC472_442.h.
| #define EADC_AD1SPCTL0_EXTFEN_Pos (21) |
EADC_T::AD1SPCTL0: EXTFEN Position
Definition at line 10301 of file NUC472_442.h.
| #define EADC_AD1SPCTL0_EXTREN_Msk (0x1ul << EADC_AD1SPCTL0_EXTREN_Pos) |
EADC_T::AD1SPCTL0: EXTREN Mask
Definition at line 10299 of file NUC472_442.h.
| #define EADC_AD1SPCTL0_EXTREN_Pos (20) |
EADC_T::AD1SPCTL0: EXTREN Position
Definition at line 10298 of file NUC472_442.h.
| #define EADC_AD1SPCTL0_TRGDLYCNT_Msk (0xfful << EADC_AD1SPCTL0_TRGDLYCNT_Pos) |
EADC_T::AD1SPCTL0: TRGDLYCNT Mask
Definition at line 10293 of file NUC472_442.h.
| #define EADC_AD1SPCTL0_TRGDLYCNT_Pos (8) |
EADC_T::AD1SPCTL0: TRGDLYCNT Position
Definition at line 10292 of file NUC472_442.h.
| #define EADC_AD1SPCTL0_TRGDLYDIV_Msk (0x3ul << EADC_AD1SPCTL0_TRGDLYDIV_Pos) |
EADC_T::AD1SPCTL0: TRGDLYDIV Mask
Definition at line 10296 of file NUC472_442.h.
| #define EADC_AD1SPCTL0_TRGDLYDIV_Pos (16) |
EADC_T::AD1SPCTL0: TRGDLYDIV Position
Definition at line 10295 of file NUC472_442.h.
| #define EADC_AD1SPCTL0_TRGSEL_Msk (0xful << EADC_AD1SPCTL0_TRGSEL_Pos) |
EADC_T::AD1SPCTL0: TRGSEL Mask
Definition at line 10290 of file NUC472_442.h.
| #define EADC_AD1SPCTL0_TRGSEL_Pos (4) |
EADC_T::AD1SPCTL0: TRGSEL Position
Definition at line 10289 of file NUC472_442.h.
| #define EADC_AD1SPCTL1_CHSEL_Msk (0xful << EADC_AD1SPCTL1_CHSEL_Pos) |
EADC_T::AD1SPCTL1: CHSEL Mask
Definition at line 10305 of file NUC472_442.h.
| #define EADC_AD1SPCTL1_CHSEL_Pos (0) |
EADC_T::AD1SPCTL1: CHSEL Position
Definition at line 10304 of file NUC472_442.h.
| #define EADC_AD1SPCTL1_EXTFEN_Msk (0x1ul << EADC_AD1SPCTL1_EXTFEN_Pos) |
EADC_T::AD1SPCTL1: EXTFEN Mask
Definition at line 10320 of file NUC472_442.h.
| #define EADC_AD1SPCTL1_EXTFEN_Pos (21) |
EADC_T::AD1SPCTL1: EXTFEN Position
Definition at line 10319 of file NUC472_442.h.
| #define EADC_AD1SPCTL1_EXTREN_Msk (0x1ul << EADC_AD1SPCTL1_EXTREN_Pos) |
EADC_T::AD1SPCTL1: EXTREN Mask
Definition at line 10317 of file NUC472_442.h.
| #define EADC_AD1SPCTL1_EXTREN_Pos (20) |
EADC_T::AD1SPCTL1: EXTREN Position
Definition at line 10316 of file NUC472_442.h.
| #define EADC_AD1SPCTL1_TRGDLYCNT_Msk (0xfful << EADC_AD1SPCTL1_TRGDLYCNT_Pos) |
EADC_T::AD1SPCTL1: TRGDLYCNT Mask
Definition at line 10311 of file NUC472_442.h.
| #define EADC_AD1SPCTL1_TRGDLYCNT_Pos (8) |
EADC_T::AD1SPCTL1: TRGDLYCNT Position
Definition at line 10310 of file NUC472_442.h.
| #define EADC_AD1SPCTL1_TRGDLYDIV_Msk (0x3ul << EADC_AD1SPCTL1_TRGDLYDIV_Pos) |
EADC_T::AD1SPCTL1: TRGDLYDIV Mask
Definition at line 10314 of file NUC472_442.h.
| #define EADC_AD1SPCTL1_TRGDLYDIV_Pos (16) |
EADC_T::AD1SPCTL1: TRGDLYDIV Position
Definition at line 10313 of file NUC472_442.h.
| #define EADC_AD1SPCTL1_TRGSEL_Msk (0xful << EADC_AD1SPCTL1_TRGSEL_Pos) |
EADC_T::AD1SPCTL1: TRGSEL Mask
Definition at line 10308 of file NUC472_442.h.
| #define EADC_AD1SPCTL1_TRGSEL_Pos (4) |
EADC_T::AD1SPCTL1: TRGSEL Position
Definition at line 10307 of file NUC472_442.h.
| #define EADC_AD1SPCTL2_CHSEL_Msk (0xful << EADC_AD1SPCTL2_CHSEL_Pos) |
EADC_T::AD1SPCTL2: CHSEL Mask
Definition at line 10323 of file NUC472_442.h.
| #define EADC_AD1SPCTL2_CHSEL_Pos (0) |
EADC_T::AD1SPCTL2: CHSEL Position
Definition at line 10322 of file NUC472_442.h.
| #define EADC_AD1SPCTL2_EXTFEN_Msk (0x1ul << EADC_AD1SPCTL2_EXTFEN_Pos) |
EADC_T::AD1SPCTL2: EXTFEN Mask
Definition at line 10338 of file NUC472_442.h.
| #define EADC_AD1SPCTL2_EXTFEN_Pos (21) |
EADC_T::AD1SPCTL2: EXTFEN Position
Definition at line 10337 of file NUC472_442.h.
| #define EADC_AD1SPCTL2_EXTREN_Msk (0x1ul << EADC_AD1SPCTL2_EXTREN_Pos) |
EADC_T::AD1SPCTL2: EXTREN Mask
Definition at line 10335 of file NUC472_442.h.
| #define EADC_AD1SPCTL2_EXTREN_Pos (20) |
EADC_T::AD1SPCTL2: EXTREN Position
Definition at line 10334 of file NUC472_442.h.
| #define EADC_AD1SPCTL2_TRGDLYCNT_Msk (0xfful << EADC_AD1SPCTL2_TRGDLYCNT_Pos) |
EADC_T::AD1SPCTL2: TRGDLYCNT Mask
Definition at line 10329 of file NUC472_442.h.
| #define EADC_AD1SPCTL2_TRGDLYCNT_Pos (8) |
EADC_T::AD1SPCTL2: TRGDLYCNT Position
Definition at line 10328 of file NUC472_442.h.
| #define EADC_AD1SPCTL2_TRGDLYDIV_Msk (0x3ul << EADC_AD1SPCTL2_TRGDLYDIV_Pos) |
EADC_T::AD1SPCTL2: TRGDLYDIV Mask
Definition at line 10332 of file NUC472_442.h.
| #define EADC_AD1SPCTL2_TRGDLYDIV_Pos (16) |
EADC_T::AD1SPCTL2: TRGDLYDIV Position
Definition at line 10331 of file NUC472_442.h.
| #define EADC_AD1SPCTL2_TRGSEL_Msk (0xful << EADC_AD1SPCTL2_TRGSEL_Pos) |
EADC_T::AD1SPCTL2: TRGSEL Mask
Definition at line 10326 of file NUC472_442.h.
| #define EADC_AD1SPCTL2_TRGSEL_Pos (4) |
EADC_T::AD1SPCTL2: TRGSEL Position
Definition at line 10325 of file NUC472_442.h.
| #define EADC_AD1SPCTL3_CHSEL_Msk (0xful << EADC_AD1SPCTL3_CHSEL_Pos) |
EADC_T::AD1SPCTL3: CHSEL Mask
Definition at line 10341 of file NUC472_442.h.
| #define EADC_AD1SPCTL3_CHSEL_Pos (0) |
EADC_T::AD1SPCTL3: CHSEL Position
Definition at line 10340 of file NUC472_442.h.
| #define EADC_AD1SPCTL3_EXTFEN_Msk (0x1ul << EADC_AD1SPCTL3_EXTFEN_Pos) |
EADC_T::AD1SPCTL3: EXTFEN Mask
Definition at line 10356 of file NUC472_442.h.
| #define EADC_AD1SPCTL3_EXTFEN_Pos (21) |
EADC_T::AD1SPCTL3: EXTFEN Position
Definition at line 10355 of file NUC472_442.h.
| #define EADC_AD1SPCTL3_EXTREN_Msk (0x1ul << EADC_AD1SPCTL3_EXTREN_Pos) |
EADC_T::AD1SPCTL3: EXTREN Mask
Definition at line 10353 of file NUC472_442.h.
| #define EADC_AD1SPCTL3_EXTREN_Pos (20) |
EADC_T::AD1SPCTL3: EXTREN Position
Definition at line 10352 of file NUC472_442.h.
| #define EADC_AD1SPCTL3_TRGDLYCNT_Msk (0xfful << EADC_AD1SPCTL3_TRGDLYCNT_Pos) |
EADC_T::AD1SPCTL3: TRGDLYCNT Mask
Definition at line 10347 of file NUC472_442.h.
| #define EADC_AD1SPCTL3_TRGDLYCNT_Pos (8) |
EADC_T::AD1SPCTL3: TRGDLYCNT Position
Definition at line 10346 of file NUC472_442.h.
| #define EADC_AD1SPCTL3_TRGDLYDIV_Msk (0x3ul << EADC_AD1SPCTL3_TRGDLYDIV_Pos) |
EADC_T::AD1SPCTL3: TRGDLYDIV Mask
Definition at line 10350 of file NUC472_442.h.
| #define EADC_AD1SPCTL3_TRGDLYDIV_Pos (16) |
EADC_T::AD1SPCTL3: TRGDLYDIV Position
Definition at line 10349 of file NUC472_442.h.
| #define EADC_AD1SPCTL3_TRGSEL_Msk (0xful << EADC_AD1SPCTL3_TRGSEL_Pos) |
EADC_T::AD1SPCTL3: TRGSEL Mask
Definition at line 10344 of file NUC472_442.h.
| #define EADC_AD1SPCTL3_TRGSEL_Pos (4) |
EADC_T::AD1SPCTL3: TRGSEL Position
Definition at line 10343 of file NUC472_442.h.
| #define EADC_AD1SPCTL4_CHSEL_Msk (0xful << EADC_AD1SPCTL4_CHSEL_Pos) |
EADC_T::AD1SPCTL4: CHSEL Mask
Definition at line 10359 of file NUC472_442.h.
| #define EADC_AD1SPCTL4_CHSEL_Pos (0) |
EADC_T::AD1SPCTL4: CHSEL Position
Definition at line 10358 of file NUC472_442.h.
| #define EADC_AD1SPCTL4_EXTFEN_Msk (0x1ul << EADC_AD1SPCTL4_EXTFEN_Pos) |
EADC_T::AD1SPCTL4: EXTFEN Mask
Definition at line 10368 of file NUC472_442.h.
| #define EADC_AD1SPCTL4_EXTFEN_Pos (21) |
EADC_T::AD1SPCTL4: EXTFEN Position
Definition at line 10367 of file NUC472_442.h.
| #define EADC_AD1SPCTL4_EXTREN_Msk (0x1ul << EADC_AD1SPCTL4_EXTREN_Pos) |
EADC_T::AD1SPCTL4: EXTREN Mask
Definition at line 10365 of file NUC472_442.h.
| #define EADC_AD1SPCTL4_EXTREN_Pos (20) |
EADC_T::AD1SPCTL4: EXTREN Position
Definition at line 10364 of file NUC472_442.h.
| #define EADC_AD1SPCTL4_TRGSEL_Msk (0x7ul << EADC_AD1SPCTL4_TRGSEL_Pos) |
EADC_T::AD1SPCTL4: TRGSEL Mask
Definition at line 10362 of file NUC472_442.h.
| #define EADC_AD1SPCTL4_TRGSEL_Pos (4) |
EADC_T::AD1SPCTL4: TRGSEL Position
Definition at line 10361 of file NUC472_442.h.
| #define EADC_AD1SPCTL5_CHSEL_Msk (0xful << EADC_AD1SPCTL5_CHSEL_Pos) |
EADC_T::AD1SPCTL5: CHSEL Mask
Definition at line 10371 of file NUC472_442.h.
| #define EADC_AD1SPCTL5_CHSEL_Pos (0) |
EADC_T::AD1SPCTL5: CHSEL Position
Definition at line 10370 of file NUC472_442.h.
| #define EADC_AD1SPCTL5_EXTFEN_Msk (0x1ul << EADC_AD1SPCTL5_EXTFEN_Pos) |
EADC_T::AD1SPCTL5: EXTFEN Mask
Definition at line 10380 of file NUC472_442.h.
| #define EADC_AD1SPCTL5_EXTFEN_Pos (21) |
EADC_T::AD1SPCTL5: EXTFEN Position
Definition at line 10379 of file NUC472_442.h.
| #define EADC_AD1SPCTL5_EXTREN_Msk (0x1ul << EADC_AD1SPCTL5_EXTREN_Pos) |
EADC_T::AD1SPCTL5: EXTREN Mask
Definition at line 10377 of file NUC472_442.h.
| #define EADC_AD1SPCTL5_EXTREN_Pos (20) |
EADC_T::AD1SPCTL5: EXTREN Position
Definition at line 10376 of file NUC472_442.h.
| #define EADC_AD1SPCTL5_TRGSEL_Msk (0x7ul << EADC_AD1SPCTL5_TRGSEL_Pos) |
EADC_T::AD1SPCTL5: TRGSEL Mask
Definition at line 10374 of file NUC472_442.h.
| #define EADC_AD1SPCTL5_TRGSEL_Pos (4) |
EADC_T::AD1SPCTL5: TRGSEL Position
Definition at line 10373 of file NUC472_442.h.
| #define EADC_AD1SPCTL6_CHSEL_Msk (0xful << EADC_AD1SPCTL6_CHSEL_Pos) |
EADC_T::AD1SPCTL6: CHSEL Mask
Definition at line 10383 of file NUC472_442.h.
| #define EADC_AD1SPCTL6_CHSEL_Pos (0) |
EADC_T::AD1SPCTL6: CHSEL Position
Definition at line 10382 of file NUC472_442.h.
| #define EADC_AD1SPCTL6_EXTFEN_Msk (0x1ul << EADC_AD1SPCTL6_EXTFEN_Pos) |
EADC_T::AD1SPCTL6: EXTFEN Mask
Definition at line 10392 of file NUC472_442.h.
| #define EADC_AD1SPCTL6_EXTFEN_Pos (21) |
EADC_T::AD1SPCTL6: EXTFEN Position
Definition at line 10391 of file NUC472_442.h.
| #define EADC_AD1SPCTL6_EXTREN_Msk (0x1ul << EADC_AD1SPCTL6_EXTREN_Pos) |
EADC_T::AD1SPCTL6: EXTREN Mask
Definition at line 10389 of file NUC472_442.h.
| #define EADC_AD1SPCTL6_EXTREN_Pos (20) |
EADC_T::AD1SPCTL6: EXTREN Position
Definition at line 10388 of file NUC472_442.h.
| #define EADC_AD1SPCTL6_TRGSEL_Msk (0x7ul << EADC_AD1SPCTL6_TRGSEL_Pos) |
EADC_T::AD1SPCTL6: TRGSEL Mask
Definition at line 10386 of file NUC472_442.h.
| #define EADC_AD1SPCTL6_TRGSEL_Pos (4) |
EADC_T::AD1SPCTL6: TRGSEL Position
Definition at line 10385 of file NUC472_442.h.
| #define EADC_AD1SPCTL7_CHSEL_Msk (0xful << EADC_AD1SPCTL7_CHSEL_Pos) |
EADC_T::AD1SPCTL7: CHSEL Mask
Definition at line 10395 of file NUC472_442.h.
| #define EADC_AD1SPCTL7_CHSEL_Pos (0) |
EADC_T::AD1SPCTL7: CHSEL Position
Definition at line 10394 of file NUC472_442.h.
| #define EADC_AD1SPCTL7_EXTFEN_Msk (0x1ul << EADC_AD1SPCTL7_EXTFEN_Pos) |
EADC_T::AD1SPCTL7: EXTFEN Mask
Definition at line 10404 of file NUC472_442.h.
| #define EADC_AD1SPCTL7_EXTFEN_Pos (21) |
EADC_T::AD1SPCTL7: EXTFEN Position
Definition at line 10403 of file NUC472_442.h.
| #define EADC_AD1SPCTL7_EXTREN_Msk (0x1ul << EADC_AD1SPCTL7_EXTREN_Pos) |
EADC_T::AD1SPCTL7: EXTREN Mask
Definition at line 10401 of file NUC472_442.h.
| #define EADC_AD1SPCTL7_EXTREN_Pos (20) |
EADC_T::AD1SPCTL7: EXTREN Position
Definition at line 10400 of file NUC472_442.h.
| #define EADC_AD1SPCTL7_TRGSEL_Msk (0x7ul << EADC_AD1SPCTL7_TRGSEL_Pos) |
EADC_T::AD1SPCTL7: TRGSEL Mask
Definition at line 10398 of file NUC472_442.h.
| #define EADC_AD1SPCTL7_TRGSEL_Pos (4) |
EADC_T::AD1SPCTL7: TRGSEL Position
Definition at line 10397 of file NUC472_442.h.
| #define EADC_AD1TRGEN0_EPWM00CEN_Msk (0x1ul << EADC_AD1TRGEN0_EPWM00CEN_Pos) |
EADC_T::AD1TRGEN0: EPWM00CEN Mask
Definition at line 11184 of file NUC472_442.h.
| #define EADC_AD1TRGEN0_EPWM00CEN_Pos (3) |
EADC_T::AD1TRGEN0: EPWM00CEN Position
Definition at line 11183 of file NUC472_442.h.
| #define EADC_AD1TRGEN0_EPWM00FEN_Msk (0x1ul << EADC_AD1TRGEN0_EPWM00FEN_Pos) |
EADC_T::AD1TRGEN0: EPWM00FEN Mask
Definition at line 11178 of file NUC472_442.h.
| #define EADC_AD1TRGEN0_EPWM00FEN_Pos (1) |
EADC_T::AD1TRGEN0: EPWM00FEN Position
Definition at line 11177 of file NUC472_442.h.
| #define EADC_AD1TRGEN0_EPWM00PEN_Msk (0x1ul << EADC_AD1TRGEN0_EPWM00PEN_Pos) |
EADC_T::AD1TRGEN0: EPWM00PEN Mask
Definition at line 11181 of file NUC472_442.h.
| #define EADC_AD1TRGEN0_EPWM00PEN_Pos (2) |
EADC_T::AD1TRGEN0: EPWM00PEN Position
Definition at line 11180 of file NUC472_442.h.
| #define EADC_AD1TRGEN0_EPWM00REN_Msk (0x1ul << EADC_AD1TRGEN0_EPWM00REN_Pos) |
EADC_T::AD1TRGEN0: EPWM00REN Mask
Definition at line 11175 of file NUC472_442.h.
| #define EADC_AD1TRGEN0_EPWM00REN_Pos (0) |
EADC_T::AD1TRGEN0: EPWM00REN Position
Definition at line 11174 of file NUC472_442.h.
| #define EADC_AD1TRGEN0_EPWM02CEN_Msk (0x1ul << EADC_AD1TRGEN0_EPWM02CEN_Pos) |
EADC_T::AD1TRGEN0: EPWM02CEN Mask
Definition at line 11196 of file NUC472_442.h.
| #define EADC_AD1TRGEN0_EPWM02CEN_Pos (7) |
EADC_T::AD1TRGEN0: EPWM02CEN Position
Definition at line 11195 of file NUC472_442.h.
| #define EADC_AD1TRGEN0_EPWM02FEN_Msk (0x1ul << EADC_AD1TRGEN0_EPWM02FEN_Pos) |
EADC_T::AD1TRGEN0: EPWM02FEN Mask
Definition at line 11190 of file NUC472_442.h.
| #define EADC_AD1TRGEN0_EPWM02FEN_Pos (5) |
EADC_T::AD1TRGEN0: EPWM02FEN Position
Definition at line 11189 of file NUC472_442.h.
| #define EADC_AD1TRGEN0_EPWM02PEN_Msk (0x1ul << EADC_AD1TRGEN0_EPWM02PEN_Pos) |
EADC_T::AD1TRGEN0: EPWM02PEN Mask
Definition at line 11193 of file NUC472_442.h.
| #define EADC_AD1TRGEN0_EPWM02PEN_Pos (6) |
EADC_T::AD1TRGEN0: EPWM02PEN Position
Definition at line 11192 of file NUC472_442.h.
| #define EADC_AD1TRGEN0_EPWM02REN_Msk (0x1ul << EADC_AD1TRGEN0_EPWM02REN_Pos) |
EADC_T::AD1TRGEN0: EPWM02REN Mask
Definition at line 11187 of file NUC472_442.h.
| #define EADC_AD1TRGEN0_EPWM02REN_Pos (4) |
EADC_T::AD1TRGEN0: EPWM02REN Position
Definition at line 11186 of file NUC472_442.h.
| #define EADC_AD1TRGEN0_EPWM04CEN_Msk (0x1ul << EADC_AD1TRGEN0_EPWM04CEN_Pos) |
EADC_T::AD1TRGEN0: EPWM04CEN Mask
Definition at line 11208 of file NUC472_442.h.
| #define EADC_AD1TRGEN0_EPWM04CEN_Pos (11) |
EADC_T::AD1TRGEN0: EPWM04CEN Position
Definition at line 11207 of file NUC472_442.h.
| #define EADC_AD1TRGEN0_EPWM04FEN_Msk (0x1ul << EADC_AD1TRGEN0_EPWM04FEN_Pos) |
EADC_T::AD1TRGEN0: EPWM04FEN Mask
Definition at line 11202 of file NUC472_442.h.
| #define EADC_AD1TRGEN0_EPWM04FEN_Pos (9) |
EADC_T::AD1TRGEN0: EPWM04FEN Position
Definition at line 11201 of file NUC472_442.h.
| #define EADC_AD1TRGEN0_EPWM04PEN_Msk (0x1ul << EADC_AD1TRGEN0_EPWM04PEN_Pos) |
EADC_T::AD1TRGEN0: EPWM04PEN Mask
Definition at line 11205 of file NUC472_442.h.
| #define EADC_AD1TRGEN0_EPWM04PEN_Pos (10) |
EADC_T::AD1TRGEN0: EPWM04PEN Position
Definition at line 11204 of file NUC472_442.h.
| #define EADC_AD1TRGEN0_EPWM04REN_Msk (0x1ul << EADC_AD1TRGEN0_EPWM04REN_Pos) |
EADC_T::AD1TRGEN0: EPWM04REN Mask
Definition at line 11199 of file NUC472_442.h.
| #define EADC_AD1TRGEN0_EPWM04REN_Pos (8) |
EADC_T::AD1TRGEN0: EPWM04REN Position
Definition at line 11198 of file NUC472_442.h.
| #define EADC_AD1TRGEN0_EPWM10CEN_Msk (0x1ul << EADC_AD1TRGEN0_EPWM10CEN_Pos) |
EADC_T::AD1TRGEN0: EPWM10CEN Mask
Definition at line 11220 of file NUC472_442.h.
| #define EADC_AD1TRGEN0_EPWM10CEN_Pos (15) |
EADC_T::AD1TRGEN0: EPWM10CEN Position
Definition at line 11219 of file NUC472_442.h.
| #define EADC_AD1TRGEN0_EPWM10FEN_Msk (0x1ul << EADC_AD1TRGEN0_EPWM10FEN_Pos) |
EADC_T::AD1TRGEN0: EPWM10FEN Mask
Definition at line 11214 of file NUC472_442.h.
| #define EADC_AD1TRGEN0_EPWM10FEN_Pos (13) |
EADC_T::AD1TRGEN0: EPWM10FEN Position
Definition at line 11213 of file NUC472_442.h.
| #define EADC_AD1TRGEN0_EPWM10PEN_Msk (0x1ul << EADC_AD1TRGEN0_EPWM10PEN_Pos) |
EADC_T::AD1TRGEN0: EPWM10PEN Mask
Definition at line 11217 of file NUC472_442.h.
| #define EADC_AD1TRGEN0_EPWM10PEN_Pos (14) |
EADC_T::AD1TRGEN0: EPWM10PEN Position
Definition at line 11216 of file NUC472_442.h.
| #define EADC_AD1TRGEN0_EPWM10REN_Msk (0x1ul << EADC_AD1TRGEN0_EPWM10REN_Pos) |
EADC_T::AD1TRGEN0: EPWM10REN Mask
Definition at line 11211 of file NUC472_442.h.
| #define EADC_AD1TRGEN0_EPWM10REN_Pos (12) |
EADC_T::AD1TRGEN0: EPWM10REN Position
Definition at line 11210 of file NUC472_442.h.
| #define EADC_AD1TRGEN0_EPWM120FEN_Msk (0x1ul << EADC_AD1TRGEN0_EPWM120FEN_Pos) |
EADC_T::AD1TRGEN0: EPWM120FEN Mask
Definition at line 11226 of file NUC472_442.h.
| #define EADC_AD1TRGEN0_EPWM120FEN_Pos (17) |
EADC_T::AD1TRGEN0: EPWM120FEN Position
Definition at line 11225 of file NUC472_442.h.
| #define EADC_AD1TRGEN0_EPWM12CEN_Msk (0x1ul << EADC_AD1TRGEN0_EPWM12CEN_Pos) |
EADC_T::AD1TRGEN0: EPWM12CEN Mask
Definition at line 11232 of file NUC472_442.h.
| #define EADC_AD1TRGEN0_EPWM12CEN_Pos (19) |
EADC_T::AD1TRGEN0: EPWM12CEN Position
Definition at line 11231 of file NUC472_442.h.
| #define EADC_AD1TRGEN0_EPWM12PEN_Msk (0x1ul << EADC_AD1TRGEN0_EPWM12PEN_Pos) |
EADC_T::AD1TRGEN0: EPWM12PEN Mask
Definition at line 11229 of file NUC472_442.h.
| #define EADC_AD1TRGEN0_EPWM12PEN_Pos (18) |
EADC_T::AD1TRGEN0: EPWM12PEN Position
Definition at line 11228 of file NUC472_442.h.
| #define EADC_AD1TRGEN0_EPWM12REN_Msk (0x1ul << EADC_AD1TRGEN0_EPWM12REN_Pos) |
EADC_T::AD1TRGEN0: EPWM12REN Mask
Definition at line 11223 of file NUC472_442.h.
| #define EADC_AD1TRGEN0_EPWM12REN_Pos (16) |
EADC_T::AD1TRGEN0: EPWM12REN Position
Definition at line 11222 of file NUC472_442.h.
| #define EADC_AD1TRGEN0_EPWM14CEN_Msk (0x1ul << EADC_AD1TRGEN0_EPWM14CEN_Pos) |
EADC_T::AD1TRGEN0: EPWM14CEN Mask
Definition at line 11244 of file NUC472_442.h.
| #define EADC_AD1TRGEN0_EPWM14CEN_Pos (23) |
EADC_T::AD1TRGEN0: EPWM14CEN Position
Definition at line 11243 of file NUC472_442.h.
| #define EADC_AD1TRGEN0_EPWM14FEN_Msk (0x1ul << EADC_AD1TRGEN0_EPWM14FEN_Pos) |
EADC_T::AD1TRGEN0: EPWM14FEN Mask
Definition at line 11238 of file NUC472_442.h.
| #define EADC_AD1TRGEN0_EPWM14FEN_Pos (21) |
EADC_T::AD1TRGEN0: EPWM14FEN Position
Definition at line 11237 of file NUC472_442.h.
| #define EADC_AD1TRGEN0_EPWM14PEN_Msk (0x1ul << EADC_AD1TRGEN0_EPWM14PEN_Pos) |
EADC_T::AD1TRGEN0: EPWM14PEN Mask
Definition at line 11241 of file NUC472_442.h.
| #define EADC_AD1TRGEN0_EPWM14PEN_Pos (22) |
EADC_T::AD1TRGEN0: EPWM14PEN Position
Definition at line 11240 of file NUC472_442.h.
| #define EADC_AD1TRGEN0_EPWM14REN_Msk (0x1ul << EADC_AD1TRGEN0_EPWM14REN_Pos) |
EADC_T::AD1TRGEN0: EPWM14REN Mask
Definition at line 11235 of file NUC472_442.h.
| #define EADC_AD1TRGEN0_EPWM14REN_Pos (20) |
EADC_T::AD1TRGEN0: EPWM14REN Position
Definition at line 11234 of file NUC472_442.h.
| #define EADC_AD1TRGEN0_PWM00CEN_Msk (0x1ul << EADC_AD1TRGEN0_PWM00CEN_Pos) |
EADC_T::AD1TRGEN0: PWM00CEN Mask
Definition at line 11256 of file NUC472_442.h.
| #define EADC_AD1TRGEN0_PWM00CEN_Pos (27) |
EADC_T::AD1TRGEN0: PWM00CEN Position
Definition at line 11255 of file NUC472_442.h.
| #define EADC_AD1TRGEN0_PWM00FEN_Msk (0x1ul << EADC_AD1TRGEN0_PWM00FEN_Pos) |
EADC_T::AD1TRGEN0: PWM00FEN Mask
Definition at line 11250 of file NUC472_442.h.
| #define EADC_AD1TRGEN0_PWM00FEN_Pos (25) |
EADC_T::AD1TRGEN0: PWM00FEN Position
Definition at line 11249 of file NUC472_442.h.
| #define EADC_AD1TRGEN0_PWM00PEN_Msk (0x1ul << EADC_AD1TRGEN0_PWM00PEN_Pos) |
EADC_T::AD1TRGEN0: PWM00PEN Mask
Definition at line 11253 of file NUC472_442.h.
| #define EADC_AD1TRGEN0_PWM00PEN_Pos (26) |
EADC_T::AD1TRGEN0: PWM00PEN Position
Definition at line 11252 of file NUC472_442.h.
| #define EADC_AD1TRGEN0_PWM00REN_Msk (0x1ul << EADC_AD1TRGEN0_PWM00REN_Pos) |
EADC_T::AD1TRGEN0: PWM00REN Mask
Definition at line 11247 of file NUC472_442.h.
| #define EADC_AD1TRGEN0_PWM00REN_Pos (24) |
EADC_T::AD1TRGEN0: PWM00REN Position
Definition at line 11246 of file NUC472_442.h.
| #define EADC_AD1TRGEN0_PWM01CEN_Msk (0x1ul << EADC_AD1TRGEN0_PWM01CEN_Pos) |
EADC_T::AD1TRGEN0: PWM01CEN Mask
Definition at line 11268 of file NUC472_442.h.
| #define EADC_AD1TRGEN0_PWM01CEN_Pos (31) |
EADC_T::AD1TRGEN0: PWM01CEN Position
Definition at line 11267 of file NUC472_442.h.
| #define EADC_AD1TRGEN0_PWM01FEN_Msk (0x1ul << EADC_AD1TRGEN0_PWM01FEN_Pos) |
EADC_T::AD1TRGEN0: PWM01FEN Mask
Definition at line 11262 of file NUC472_442.h.
| #define EADC_AD1TRGEN0_PWM01FEN_Pos (29) |
EADC_T::AD1TRGEN0: PWM01FEN Position
Definition at line 11261 of file NUC472_442.h.
| #define EADC_AD1TRGEN0_PWM01PEN_Msk (0x1ul << EADC_AD1TRGEN0_PWM01PEN_Pos) |
EADC_T::AD1TRGEN0: PWM01PEN Mask
Definition at line 11265 of file NUC472_442.h.
| #define EADC_AD1TRGEN0_PWM01PEN_Pos (30) |
EADC_T::AD1TRGEN0: PWM01PEN Position
Definition at line 11264 of file NUC472_442.h.
| #define EADC_AD1TRGEN0_PWM01REN_Msk (0x1ul << EADC_AD1TRGEN0_PWM01REN_Pos) |
EADC_T::AD1TRGEN0: PWM01REN Mask
Definition at line 11259 of file NUC472_442.h.
| #define EADC_AD1TRGEN0_PWM01REN_Pos (28) |
EADC_T::AD1TRGEN0: PWM01REN Position
Definition at line 11258 of file NUC472_442.h.
| #define EADC_AD1TRGEN1_EPWM00CEN_Msk (0x1ul << EADC_AD1TRGEN1_EPWM00CEN_Pos) |
EADC_T::AD1TRGEN1: EPWM00CEN Mask
Definition at line 11280 of file NUC472_442.h.
| #define EADC_AD1TRGEN1_EPWM00CEN_Pos (3) |
EADC_T::AD1TRGEN1: EPWM00CEN Position
Definition at line 11279 of file NUC472_442.h.
| #define EADC_AD1TRGEN1_EPWM00FEN_Msk (0x1ul << EADC_AD1TRGEN1_EPWM00FEN_Pos) |
EADC_T::AD1TRGEN1: EPWM00FEN Mask
Definition at line 11274 of file NUC472_442.h.
| #define EADC_AD1TRGEN1_EPWM00FEN_Pos (1) |
EADC_T::AD1TRGEN1: EPWM00FEN Position
Definition at line 11273 of file NUC472_442.h.
| #define EADC_AD1TRGEN1_EPWM00PEN_Msk (0x1ul << EADC_AD1TRGEN1_EPWM00PEN_Pos) |
EADC_T::AD1TRGEN1: EPWM00PEN Mask
Definition at line 11277 of file NUC472_442.h.
| #define EADC_AD1TRGEN1_EPWM00PEN_Pos (2) |
EADC_T::AD1TRGEN1: EPWM00PEN Position
Definition at line 11276 of file NUC472_442.h.
| #define EADC_AD1TRGEN1_EPWM00REN_Msk (0x1ul << EADC_AD1TRGEN1_EPWM00REN_Pos) |
EADC_T::AD1TRGEN1: EPWM00REN Mask
Definition at line 11271 of file NUC472_442.h.
| #define EADC_AD1TRGEN1_EPWM00REN_Pos (0) |
EADC_T::AD1TRGEN1: EPWM00REN Position
Definition at line 11270 of file NUC472_442.h.
| #define EADC_AD1TRGEN1_EPWM02CEN_Msk (0x1ul << EADC_AD1TRGEN1_EPWM02CEN_Pos) |
EADC_T::AD1TRGEN1: EPWM02CEN Mask
Definition at line 11292 of file NUC472_442.h.
| #define EADC_AD1TRGEN1_EPWM02CEN_Pos (7) |
EADC_T::AD1TRGEN1: EPWM02CEN Position
Definition at line 11291 of file NUC472_442.h.
| #define EADC_AD1TRGEN1_EPWM02FEN_Msk (0x1ul << EADC_AD1TRGEN1_EPWM02FEN_Pos) |
EADC_T::AD1TRGEN1: EPWM02FEN Mask
Definition at line 11286 of file NUC472_442.h.
| #define EADC_AD1TRGEN1_EPWM02FEN_Pos (5) |
EADC_T::AD1TRGEN1: EPWM02FEN Position
Definition at line 11285 of file NUC472_442.h.
| #define EADC_AD1TRGEN1_EPWM02PEN_Msk (0x1ul << EADC_AD1TRGEN1_EPWM02PEN_Pos) |
EADC_T::AD1TRGEN1: EPWM02PEN Mask
Definition at line 11289 of file NUC472_442.h.
| #define EADC_AD1TRGEN1_EPWM02PEN_Pos (6) |
EADC_T::AD1TRGEN1: EPWM02PEN Position
Definition at line 11288 of file NUC472_442.h.
| #define EADC_AD1TRGEN1_EPWM02REN_Msk (0x1ul << EADC_AD1TRGEN1_EPWM02REN_Pos) |
EADC_T::AD1TRGEN1: EPWM02REN Mask
Definition at line 11283 of file NUC472_442.h.
| #define EADC_AD1TRGEN1_EPWM02REN_Pos (4) |
EADC_T::AD1TRGEN1: EPWM02REN Position
Definition at line 11282 of file NUC472_442.h.
| #define EADC_AD1TRGEN1_EPWM04CEN_Msk (0x1ul << EADC_AD1TRGEN1_EPWM04CEN_Pos) |
EADC_T::AD1TRGEN1: EPWM04CEN Mask
Definition at line 11304 of file NUC472_442.h.
| #define EADC_AD1TRGEN1_EPWM04CEN_Pos (11) |
EADC_T::AD1TRGEN1: EPWM04CEN Position
Definition at line 11303 of file NUC472_442.h.
| #define EADC_AD1TRGEN1_EPWM04FEN_Msk (0x1ul << EADC_AD1TRGEN1_EPWM04FEN_Pos) |
EADC_T::AD1TRGEN1: EPWM04FEN Mask
Definition at line 11298 of file NUC472_442.h.
| #define EADC_AD1TRGEN1_EPWM04FEN_Pos (9) |
EADC_T::AD1TRGEN1: EPWM04FEN Position
Definition at line 11297 of file NUC472_442.h.
| #define EADC_AD1TRGEN1_EPWM04PEN_Msk (0x1ul << EADC_AD1TRGEN1_EPWM04PEN_Pos) |
EADC_T::AD1TRGEN1: EPWM04PEN Mask
Definition at line 11301 of file NUC472_442.h.
| #define EADC_AD1TRGEN1_EPWM04PEN_Pos (10) |
EADC_T::AD1TRGEN1: EPWM04PEN Position
Definition at line 11300 of file NUC472_442.h.
| #define EADC_AD1TRGEN1_EPWM04REN_Msk (0x1ul << EADC_AD1TRGEN1_EPWM04REN_Pos) |
EADC_T::AD1TRGEN1: EPWM04REN Mask
Definition at line 11295 of file NUC472_442.h.
| #define EADC_AD1TRGEN1_EPWM04REN_Pos (8) |
EADC_T::AD1TRGEN1: EPWM04REN Position
Definition at line 11294 of file NUC472_442.h.
| #define EADC_AD1TRGEN1_EPWM10CEN_Msk (0x1ul << EADC_AD1TRGEN1_EPWM10CEN_Pos) |
EADC_T::AD1TRGEN1: EPWM10CEN Mask
Definition at line 11316 of file NUC472_442.h.
| #define EADC_AD1TRGEN1_EPWM10CEN_Pos (15) |
EADC_T::AD1TRGEN1: EPWM10CEN Position
Definition at line 11315 of file NUC472_442.h.
| #define EADC_AD1TRGEN1_EPWM10FEN_Msk (0x1ul << EADC_AD1TRGEN1_EPWM10FEN_Pos) |
EADC_T::AD1TRGEN1: EPWM10FEN Mask
Definition at line 11310 of file NUC472_442.h.
| #define EADC_AD1TRGEN1_EPWM10FEN_Pos (13) |
EADC_T::AD1TRGEN1: EPWM10FEN Position
Definition at line 11309 of file NUC472_442.h.
| #define EADC_AD1TRGEN1_EPWM10PEN_Msk (0x1ul << EADC_AD1TRGEN1_EPWM10PEN_Pos) |
EADC_T::AD1TRGEN1: EPWM10PEN Mask
Definition at line 11313 of file NUC472_442.h.
| #define EADC_AD1TRGEN1_EPWM10PEN_Pos (14) |
EADC_T::AD1TRGEN1: EPWM10PEN Position
Definition at line 11312 of file NUC472_442.h.
| #define EADC_AD1TRGEN1_EPWM10REN_Msk (0x1ul << EADC_AD1TRGEN1_EPWM10REN_Pos) |
EADC_T::AD1TRGEN1: EPWM10REN Mask
Definition at line 11307 of file NUC472_442.h.
| #define EADC_AD1TRGEN1_EPWM10REN_Pos (12) |
EADC_T::AD1TRGEN1: EPWM10REN Position
Definition at line 11306 of file NUC472_442.h.
| #define EADC_AD1TRGEN1_EPWM120FEN_Msk (0x1ul << EADC_AD1TRGEN1_EPWM120FEN_Pos) |
EADC_T::AD1TRGEN1: EPWM120FEN Mask
Definition at line 11322 of file NUC472_442.h.
| #define EADC_AD1TRGEN1_EPWM120FEN_Pos (17) |
EADC_T::AD1TRGEN1: EPWM120FEN Position
Definition at line 11321 of file NUC472_442.h.
| #define EADC_AD1TRGEN1_EPWM12CEN_Msk (0x1ul << EADC_AD1TRGEN1_EPWM12CEN_Pos) |
EADC_T::AD1TRGEN1: EPWM12CEN Mask
Definition at line 11328 of file NUC472_442.h.
| #define EADC_AD1TRGEN1_EPWM12CEN_Pos (19) |
EADC_T::AD1TRGEN1: EPWM12CEN Position
Definition at line 11327 of file NUC472_442.h.
| #define EADC_AD1TRGEN1_EPWM12PEN_Msk (0x1ul << EADC_AD1TRGEN1_EPWM12PEN_Pos) |
EADC_T::AD1TRGEN1: EPWM12PEN Mask
Definition at line 11325 of file NUC472_442.h.
| #define EADC_AD1TRGEN1_EPWM12PEN_Pos (18) |
EADC_T::AD1TRGEN1: EPWM12PEN Position
Definition at line 11324 of file NUC472_442.h.
| #define EADC_AD1TRGEN1_EPWM12REN_Msk (0x1ul << EADC_AD1TRGEN1_EPWM12REN_Pos) |
EADC_T::AD1TRGEN1: EPWM12REN Mask
Definition at line 11319 of file NUC472_442.h.
| #define EADC_AD1TRGEN1_EPWM12REN_Pos (16) |
EADC_T::AD1TRGEN1: EPWM12REN Position
Definition at line 11318 of file NUC472_442.h.
| #define EADC_AD1TRGEN1_EPWM14CEN_Msk (0x1ul << EADC_AD1TRGEN1_EPWM14CEN_Pos) |
EADC_T::AD1TRGEN1: EPWM14CEN Mask
Definition at line 11340 of file NUC472_442.h.
| #define EADC_AD1TRGEN1_EPWM14CEN_Pos (23) |
EADC_T::AD1TRGEN1: EPWM14CEN Position
Definition at line 11339 of file NUC472_442.h.
| #define EADC_AD1TRGEN1_EPWM14FEN_Msk (0x1ul << EADC_AD1TRGEN1_EPWM14FEN_Pos) |
EADC_T::AD1TRGEN1: EPWM14FEN Mask
Definition at line 11334 of file NUC472_442.h.
| #define EADC_AD1TRGEN1_EPWM14FEN_Pos (21) |
EADC_T::AD1TRGEN1: EPWM14FEN Position
Definition at line 11333 of file NUC472_442.h.
| #define EADC_AD1TRGEN1_EPWM14PEN_Msk (0x1ul << EADC_AD1TRGEN1_EPWM14PEN_Pos) |
EADC_T::AD1TRGEN1: EPWM14PEN Mask
Definition at line 11337 of file NUC472_442.h.
| #define EADC_AD1TRGEN1_EPWM14PEN_Pos (22) |
EADC_T::AD1TRGEN1: EPWM14PEN Position
Definition at line 11336 of file NUC472_442.h.
| #define EADC_AD1TRGEN1_EPWM14REN_Msk (0x1ul << EADC_AD1TRGEN1_EPWM14REN_Pos) |
EADC_T::AD1TRGEN1: EPWM14REN Mask
Definition at line 11331 of file NUC472_442.h.
| #define EADC_AD1TRGEN1_EPWM14REN_Pos (20) |
EADC_T::AD1TRGEN1: EPWM14REN Position
Definition at line 11330 of file NUC472_442.h.
| #define EADC_AD1TRGEN1_PWM00CEN_Msk (0x1ul << EADC_AD1TRGEN1_PWM00CEN_Pos) |
EADC_T::AD1TRGEN1: PWM00CEN Mask
Definition at line 11352 of file NUC472_442.h.
| #define EADC_AD1TRGEN1_PWM00CEN_Pos (27) |
EADC_T::AD1TRGEN1: PWM00CEN Position
Definition at line 11351 of file NUC472_442.h.
| #define EADC_AD1TRGEN1_PWM00FEN_Msk (0x1ul << EADC_AD1TRGEN1_PWM00FEN_Pos) |
EADC_T::AD1TRGEN1: PWM00FEN Mask
Definition at line 11346 of file NUC472_442.h.
| #define EADC_AD1TRGEN1_PWM00FEN_Pos (25) |
EADC_T::AD1TRGEN1: PWM00FEN Position
Definition at line 11345 of file NUC472_442.h.
| #define EADC_AD1TRGEN1_PWM00PEN_Msk (0x1ul << EADC_AD1TRGEN1_PWM00PEN_Pos) |
EADC_T::AD1TRGEN1: PWM00PEN Mask
Definition at line 11349 of file NUC472_442.h.
| #define EADC_AD1TRGEN1_PWM00PEN_Pos (26) |
EADC_T::AD1TRGEN1: PWM00PEN Position
Definition at line 11348 of file NUC472_442.h.
| #define EADC_AD1TRGEN1_PWM00REN_Msk (0x1ul << EADC_AD1TRGEN1_PWM00REN_Pos) |
EADC_T::AD1TRGEN1: PWM00REN Mask
Definition at line 11343 of file NUC472_442.h.
| #define EADC_AD1TRGEN1_PWM00REN_Pos (24) |
EADC_T::AD1TRGEN1: PWM00REN Position
Definition at line 11342 of file NUC472_442.h.
| #define EADC_AD1TRGEN1_PWM01CEN_Msk (0x1ul << EADC_AD1TRGEN1_PWM01CEN_Pos) |
EADC_T::AD1TRGEN1: PWM01CEN Mask
Definition at line 11364 of file NUC472_442.h.
| #define EADC_AD1TRGEN1_PWM01CEN_Pos (31) |
EADC_T::AD1TRGEN1: PWM01CEN Position
Definition at line 11363 of file NUC472_442.h.
| #define EADC_AD1TRGEN1_PWM01FEN_Msk (0x1ul << EADC_AD1TRGEN1_PWM01FEN_Pos) |
EADC_T::AD1TRGEN1: PWM01FEN Mask
Definition at line 11358 of file NUC472_442.h.
| #define EADC_AD1TRGEN1_PWM01FEN_Pos (29) |
EADC_T::AD1TRGEN1: PWM01FEN Position
Definition at line 11357 of file NUC472_442.h.
| #define EADC_AD1TRGEN1_PWM01PEN_Msk (0x1ul << EADC_AD1TRGEN1_PWM01PEN_Pos) |
EADC_T::AD1TRGEN1: PWM01PEN Mask
Definition at line 11361 of file NUC472_442.h.
| #define EADC_AD1TRGEN1_PWM01PEN_Pos (30) |
EADC_T::AD1TRGEN1: PWM01PEN Position
Definition at line 11360 of file NUC472_442.h.
| #define EADC_AD1TRGEN1_PWM01REN_Msk (0x1ul << EADC_AD1TRGEN1_PWM01REN_Pos) |
EADC_T::AD1TRGEN1: PWM01REN Mask
Definition at line 11355 of file NUC472_442.h.
| #define EADC_AD1TRGEN1_PWM01REN_Pos (28) |
EADC_T::AD1TRGEN1: PWM01REN Position
Definition at line 11354 of file NUC472_442.h.
| #define EADC_AD1TRGEN2_EPWM00CEN_Msk (0x1ul << EADC_AD1TRGEN2_EPWM00CEN_Pos) |
EADC_T::AD1TRGEN2: EPWM00CEN Mask
Definition at line 11376 of file NUC472_442.h.
| #define EADC_AD1TRGEN2_EPWM00CEN_Pos (3) |
EADC_T::AD1TRGEN2: EPWM00CEN Position
Definition at line 11375 of file NUC472_442.h.
| #define EADC_AD1TRGEN2_EPWM00FEN_Msk (0x1ul << EADC_AD1TRGEN2_EPWM00FEN_Pos) |
EADC_T::AD1TRGEN2: EPWM00FEN Mask
Definition at line 11370 of file NUC472_442.h.
| #define EADC_AD1TRGEN2_EPWM00FEN_Pos (1) |
EADC_T::AD1TRGEN2: EPWM00FEN Position
Definition at line 11369 of file NUC472_442.h.
| #define EADC_AD1TRGEN2_EPWM00PEN_Msk (0x1ul << EADC_AD1TRGEN2_EPWM00PEN_Pos) |
EADC_T::AD1TRGEN2: EPWM00PEN Mask
Definition at line 11373 of file NUC472_442.h.
| #define EADC_AD1TRGEN2_EPWM00PEN_Pos (2) |
EADC_T::AD1TRGEN2: EPWM00PEN Position
Definition at line 11372 of file NUC472_442.h.
| #define EADC_AD1TRGEN2_EPWM00REN_Msk (0x1ul << EADC_AD1TRGEN2_EPWM00REN_Pos) |
EADC_T::AD1TRGEN2: EPWM00REN Mask
Definition at line 11367 of file NUC472_442.h.
| #define EADC_AD1TRGEN2_EPWM00REN_Pos (0) |
EADC_T::AD1TRGEN2: EPWM00REN Position
Definition at line 11366 of file NUC472_442.h.
| #define EADC_AD1TRGEN2_EPWM02CEN_Msk (0x1ul << EADC_AD1TRGEN2_EPWM02CEN_Pos) |
EADC_T::AD1TRGEN2: EPWM02CEN Mask
Definition at line 11388 of file NUC472_442.h.
| #define EADC_AD1TRGEN2_EPWM02CEN_Pos (7) |
EADC_T::AD1TRGEN2: EPWM02CEN Position
Definition at line 11387 of file NUC472_442.h.
| #define EADC_AD1TRGEN2_EPWM02FEN_Msk (0x1ul << EADC_AD1TRGEN2_EPWM02FEN_Pos) |
EADC_T::AD1TRGEN2: EPWM02FEN Mask
Definition at line 11382 of file NUC472_442.h.
| #define EADC_AD1TRGEN2_EPWM02FEN_Pos (5) |
EADC_T::AD1TRGEN2: EPWM02FEN Position
Definition at line 11381 of file NUC472_442.h.
| #define EADC_AD1TRGEN2_EPWM02PEN_Msk (0x1ul << EADC_AD1TRGEN2_EPWM02PEN_Pos) |
EADC_T::AD1TRGEN2: EPWM02PEN Mask
Definition at line 11385 of file NUC472_442.h.
| #define EADC_AD1TRGEN2_EPWM02PEN_Pos (6) |
EADC_T::AD1TRGEN2: EPWM02PEN Position
Definition at line 11384 of file NUC472_442.h.
| #define EADC_AD1TRGEN2_EPWM02REN_Msk (0x1ul << EADC_AD1TRGEN2_EPWM02REN_Pos) |
EADC_T::AD1TRGEN2: EPWM02REN Mask
Definition at line 11379 of file NUC472_442.h.
| #define EADC_AD1TRGEN2_EPWM02REN_Pos (4) |
EADC_T::AD1TRGEN2: EPWM02REN Position
Definition at line 11378 of file NUC472_442.h.
| #define EADC_AD1TRGEN2_EPWM04CEN_Msk (0x1ul << EADC_AD1TRGEN2_EPWM04CEN_Pos) |
EADC_T::AD1TRGEN2: EPWM04CEN Mask
Definition at line 11400 of file NUC472_442.h.
| #define EADC_AD1TRGEN2_EPWM04CEN_Pos (11) |
EADC_T::AD1TRGEN2: EPWM04CEN Position
Definition at line 11399 of file NUC472_442.h.
| #define EADC_AD1TRGEN2_EPWM04FEN_Msk (0x1ul << EADC_AD1TRGEN2_EPWM04FEN_Pos) |
EADC_T::AD1TRGEN2: EPWM04FEN Mask
Definition at line 11394 of file NUC472_442.h.
| #define EADC_AD1TRGEN2_EPWM04FEN_Pos (9) |
EADC_T::AD1TRGEN2: EPWM04FEN Position
Definition at line 11393 of file NUC472_442.h.
| #define EADC_AD1TRGEN2_EPWM04PEN_Msk (0x1ul << EADC_AD1TRGEN2_EPWM04PEN_Pos) |
EADC_T::AD1TRGEN2: EPWM04PEN Mask
Definition at line 11397 of file NUC472_442.h.
| #define EADC_AD1TRGEN2_EPWM04PEN_Pos (10) |
EADC_T::AD1TRGEN2: EPWM04PEN Position
Definition at line 11396 of file NUC472_442.h.
| #define EADC_AD1TRGEN2_EPWM04REN_Msk (0x1ul << EADC_AD1TRGEN2_EPWM04REN_Pos) |
EADC_T::AD1TRGEN2: EPWM04REN Mask
Definition at line 11391 of file NUC472_442.h.
| #define EADC_AD1TRGEN2_EPWM04REN_Pos (8) |
EADC_T::AD1TRGEN2: EPWM04REN Position
Definition at line 11390 of file NUC472_442.h.
| #define EADC_AD1TRGEN2_EPWM10CEN_Msk (0x1ul << EADC_AD1TRGEN2_EPWM10CEN_Pos) |
EADC_T::AD1TRGEN2: EPWM10CEN Mask
Definition at line 11412 of file NUC472_442.h.
| #define EADC_AD1TRGEN2_EPWM10CEN_Pos (15) |
EADC_T::AD1TRGEN2: EPWM10CEN Position
Definition at line 11411 of file NUC472_442.h.
| #define EADC_AD1TRGEN2_EPWM10FEN_Msk (0x1ul << EADC_AD1TRGEN2_EPWM10FEN_Pos) |
EADC_T::AD1TRGEN2: EPWM10FEN Mask
Definition at line 11406 of file NUC472_442.h.
| #define EADC_AD1TRGEN2_EPWM10FEN_Pos (13) |
EADC_T::AD1TRGEN2: EPWM10FEN Position
Definition at line 11405 of file NUC472_442.h.
| #define EADC_AD1TRGEN2_EPWM10PEN_Msk (0x1ul << EADC_AD1TRGEN2_EPWM10PEN_Pos) |
EADC_T::AD1TRGEN2: EPWM10PEN Mask
Definition at line 11409 of file NUC472_442.h.
| #define EADC_AD1TRGEN2_EPWM10PEN_Pos (14) |
EADC_T::AD1TRGEN2: EPWM10PEN Position
Definition at line 11408 of file NUC472_442.h.
| #define EADC_AD1TRGEN2_EPWM10REN_Msk (0x1ul << EADC_AD1TRGEN2_EPWM10REN_Pos) |
EADC_T::AD1TRGEN2: EPWM10REN Mask
Definition at line 11403 of file NUC472_442.h.
| #define EADC_AD1TRGEN2_EPWM10REN_Pos (12) |
EADC_T::AD1TRGEN2: EPWM10REN Position
Definition at line 11402 of file NUC472_442.h.
| #define EADC_AD1TRGEN2_EPWM120FEN_Msk (0x1ul << EADC_AD1TRGEN2_EPWM120FEN_Pos) |
EADC_T::AD1TRGEN2: EPWM120FEN Mask
Definition at line 11418 of file NUC472_442.h.
| #define EADC_AD1TRGEN2_EPWM120FEN_Pos (17) |
EADC_T::AD1TRGEN2: EPWM120FEN Position
Definition at line 11417 of file NUC472_442.h.
| #define EADC_AD1TRGEN2_EPWM12CEN_Msk (0x1ul << EADC_AD1TRGEN2_EPWM12CEN_Pos) |
EADC_T::AD1TRGEN2: EPWM12CEN Mask
Definition at line 11424 of file NUC472_442.h.
| #define EADC_AD1TRGEN2_EPWM12CEN_Pos (19) |
EADC_T::AD1TRGEN2: EPWM12CEN Position
Definition at line 11423 of file NUC472_442.h.
| #define EADC_AD1TRGEN2_EPWM12PEN_Msk (0x1ul << EADC_AD1TRGEN2_EPWM12PEN_Pos) |
EADC_T::AD1TRGEN2: EPWM12PEN Mask
Definition at line 11421 of file NUC472_442.h.
| #define EADC_AD1TRGEN2_EPWM12PEN_Pos (18) |
EADC_T::AD1TRGEN2: EPWM12PEN Position
Definition at line 11420 of file NUC472_442.h.
| #define EADC_AD1TRGEN2_EPWM12REN_Msk (0x1ul << EADC_AD1TRGEN2_EPWM12REN_Pos) |
EADC_T::AD1TRGEN2: EPWM12REN Mask
Definition at line 11415 of file NUC472_442.h.
| #define EADC_AD1TRGEN2_EPWM12REN_Pos (16) |
EADC_T::AD1TRGEN2: EPWM12REN Position
Definition at line 11414 of file NUC472_442.h.
| #define EADC_AD1TRGEN2_EPWM14CEN_Msk (0x1ul << EADC_AD1TRGEN2_EPWM14CEN_Pos) |
EADC_T::AD1TRGEN2: EPWM14CEN Mask
Definition at line 11436 of file NUC472_442.h.
| #define EADC_AD1TRGEN2_EPWM14CEN_Pos (23) |
EADC_T::AD1TRGEN2: EPWM14CEN Position
Definition at line 11435 of file NUC472_442.h.
| #define EADC_AD1TRGEN2_EPWM14FEN_Msk (0x1ul << EADC_AD1TRGEN2_EPWM14FEN_Pos) |
EADC_T::AD1TRGEN2: EPWM14FEN Mask
Definition at line 11430 of file NUC472_442.h.
| #define EADC_AD1TRGEN2_EPWM14FEN_Pos (21) |
EADC_T::AD1TRGEN2: EPWM14FEN Position
Definition at line 11429 of file NUC472_442.h.
| #define EADC_AD1TRGEN2_EPWM14PEN_Msk (0x1ul << EADC_AD1TRGEN2_EPWM14PEN_Pos) |
EADC_T::AD1TRGEN2: EPWM14PEN Mask
Definition at line 11433 of file NUC472_442.h.
| #define EADC_AD1TRGEN2_EPWM14PEN_Pos (22) |
EADC_T::AD1TRGEN2: EPWM14PEN Position
Definition at line 11432 of file NUC472_442.h.
| #define EADC_AD1TRGEN2_EPWM14REN_Msk (0x1ul << EADC_AD1TRGEN2_EPWM14REN_Pos) |
EADC_T::AD1TRGEN2: EPWM14REN Mask
Definition at line 11427 of file NUC472_442.h.
| #define EADC_AD1TRGEN2_EPWM14REN_Pos (20) |
EADC_T::AD1TRGEN2: EPWM14REN Position
Definition at line 11426 of file NUC472_442.h.
| #define EADC_AD1TRGEN2_PWM00CEN_Msk (0x1ul << EADC_AD1TRGEN2_PWM00CEN_Pos) |
EADC_T::AD1TRGEN2: PWM00CEN Mask
Definition at line 11448 of file NUC472_442.h.
| #define EADC_AD1TRGEN2_PWM00CEN_Pos (27) |
EADC_T::AD1TRGEN2: PWM00CEN Position
Definition at line 11447 of file NUC472_442.h.
| #define EADC_AD1TRGEN2_PWM00FEN_Msk (0x1ul << EADC_AD1TRGEN2_PWM00FEN_Pos) |
EADC_T::AD1TRGEN2: PWM00FEN Mask
Definition at line 11442 of file NUC472_442.h.
| #define EADC_AD1TRGEN2_PWM00FEN_Pos (25) |
EADC_T::AD1TRGEN2: PWM00FEN Position
Definition at line 11441 of file NUC472_442.h.
| #define EADC_AD1TRGEN2_PWM00PEN_Msk (0x1ul << EADC_AD1TRGEN2_PWM00PEN_Pos) |
EADC_T::AD1TRGEN2: PWM00PEN Mask
Definition at line 11445 of file NUC472_442.h.
| #define EADC_AD1TRGEN2_PWM00PEN_Pos (26) |
EADC_T::AD1TRGEN2: PWM00PEN Position
Definition at line 11444 of file NUC472_442.h.
| #define EADC_AD1TRGEN2_PWM00REN_Msk (0x1ul << EADC_AD1TRGEN2_PWM00REN_Pos) |
EADC_T::AD1TRGEN2: PWM00REN Mask
Definition at line 11439 of file NUC472_442.h.
| #define EADC_AD1TRGEN2_PWM00REN_Pos (24) |
EADC_T::AD1TRGEN2: PWM00REN Position
Definition at line 11438 of file NUC472_442.h.
| #define EADC_AD1TRGEN2_PWM01CEN_Msk (0x1ul << EADC_AD1TRGEN2_PWM01CEN_Pos) |
EADC_T::AD1TRGEN2: PWM01CEN Mask
Definition at line 11460 of file NUC472_442.h.
| #define EADC_AD1TRGEN2_PWM01CEN_Pos (31) |
EADC_T::AD1TRGEN2: PWM01CEN Position
Definition at line 11459 of file NUC472_442.h.
| #define EADC_AD1TRGEN2_PWM01FEN_Msk (0x1ul << EADC_AD1TRGEN2_PWM01FEN_Pos) |
EADC_T::AD1TRGEN2: PWM01FEN Mask
Definition at line 11454 of file NUC472_442.h.
| #define EADC_AD1TRGEN2_PWM01FEN_Pos (29) |
EADC_T::AD1TRGEN2: PWM01FEN Position
Definition at line 11453 of file NUC472_442.h.
| #define EADC_AD1TRGEN2_PWM01PEN_Msk (0x1ul << EADC_AD1TRGEN2_PWM01PEN_Pos) |
EADC_T::AD1TRGEN2: PWM01PEN Mask
Definition at line 11457 of file NUC472_442.h.
| #define EADC_AD1TRGEN2_PWM01PEN_Pos (30) |
EADC_T::AD1TRGEN2: PWM01PEN Position
Definition at line 11456 of file NUC472_442.h.
| #define EADC_AD1TRGEN2_PWM01REN_Msk (0x1ul << EADC_AD1TRGEN2_PWM01REN_Pos) |
EADC_T::AD1TRGEN2: PWM01REN Mask
Definition at line 11451 of file NUC472_442.h.
| #define EADC_AD1TRGEN2_PWM01REN_Pos (28) |
EADC_T::AD1TRGEN2: PWM01REN Position
Definition at line 11450 of file NUC472_442.h.
| #define EADC_AD1TRGEN3_EPWM00CEN_Msk (0x1ul << EADC_AD1TRGEN3_EPWM00CEN_Pos) |
EADC_T::AD1TRGEN3: EPWM00CEN Mask
Definition at line 11472 of file NUC472_442.h.
| #define EADC_AD1TRGEN3_EPWM00CEN_Pos (3) |
EADC_T::AD1TRGEN3: EPWM00CEN Position
Definition at line 11471 of file NUC472_442.h.
| #define EADC_AD1TRGEN3_EPWM00FEN_Msk (0x1ul << EADC_AD1TRGEN3_EPWM00FEN_Pos) |
EADC_T::AD1TRGEN3: EPWM00FEN Mask
Definition at line 11466 of file NUC472_442.h.
| #define EADC_AD1TRGEN3_EPWM00FEN_Pos (1) |
EADC_T::AD1TRGEN3: EPWM00FEN Position
Definition at line 11465 of file NUC472_442.h.
| #define EADC_AD1TRGEN3_EPWM00PEN_Msk (0x1ul << EADC_AD1TRGEN3_EPWM00PEN_Pos) |
EADC_T::AD1TRGEN3: EPWM00PEN Mask
Definition at line 11469 of file NUC472_442.h.
| #define EADC_AD1TRGEN3_EPWM00PEN_Pos (2) |
EADC_T::AD1TRGEN3: EPWM00PEN Position
Definition at line 11468 of file NUC472_442.h.
| #define EADC_AD1TRGEN3_EPWM00REN_Msk (0x1ul << EADC_AD1TRGEN3_EPWM00REN_Pos) |
EADC_T::AD1TRGEN3: EPWM00REN Mask
Definition at line 11463 of file NUC472_442.h.
| #define EADC_AD1TRGEN3_EPWM00REN_Pos (0) |
EADC_T::AD1TRGEN3: EPWM00REN Position
Definition at line 11462 of file NUC472_442.h.
| #define EADC_AD1TRGEN3_EPWM02CEN_Msk (0x1ul << EADC_AD1TRGEN3_EPWM02CEN_Pos) |
EADC_T::AD1TRGEN3: EPWM02CEN Mask
Definition at line 11484 of file NUC472_442.h.
| #define EADC_AD1TRGEN3_EPWM02CEN_Pos (7) |
EADC_T::AD1TRGEN3: EPWM02CEN Position
Definition at line 11483 of file NUC472_442.h.
| #define EADC_AD1TRGEN3_EPWM02FEN_Msk (0x1ul << EADC_AD1TRGEN3_EPWM02FEN_Pos) |
EADC_T::AD1TRGEN3: EPWM02FEN Mask
Definition at line 11478 of file NUC472_442.h.
| #define EADC_AD1TRGEN3_EPWM02FEN_Pos (5) |
EADC_T::AD1TRGEN3: EPWM02FEN Position
Definition at line 11477 of file NUC472_442.h.
| #define EADC_AD1TRGEN3_EPWM02PEN_Msk (0x1ul << EADC_AD1TRGEN3_EPWM02PEN_Pos) |
EADC_T::AD1TRGEN3: EPWM02PEN Mask
Definition at line 11481 of file NUC472_442.h.
| #define EADC_AD1TRGEN3_EPWM02PEN_Pos (6) |
EADC_T::AD1TRGEN3: EPWM02PEN Position
Definition at line 11480 of file NUC472_442.h.
| #define EADC_AD1TRGEN3_EPWM02REN_Msk (0x1ul << EADC_AD1TRGEN3_EPWM02REN_Pos) |
EADC_T::AD1TRGEN3: EPWM02REN Mask
Definition at line 11475 of file NUC472_442.h.
| #define EADC_AD1TRGEN3_EPWM02REN_Pos (4) |
EADC_T::AD1TRGEN3: EPWM02REN Position
Definition at line 11474 of file NUC472_442.h.
| #define EADC_AD1TRGEN3_EPWM04CEN_Msk (0x1ul << EADC_AD1TRGEN3_EPWM04CEN_Pos) |
EADC_T::AD1TRGEN3: EPWM04CEN Mask
Definition at line 11496 of file NUC472_442.h.
| #define EADC_AD1TRGEN3_EPWM04CEN_Pos (11) |
EADC_T::AD1TRGEN3: EPWM04CEN Position
Definition at line 11495 of file NUC472_442.h.
| #define EADC_AD1TRGEN3_EPWM04FEN_Msk (0x1ul << EADC_AD1TRGEN3_EPWM04FEN_Pos) |
EADC_T::AD1TRGEN3: EPWM04FEN Mask
Definition at line 11490 of file NUC472_442.h.
| #define EADC_AD1TRGEN3_EPWM04FEN_Pos (9) |
EADC_T::AD1TRGEN3: EPWM04FEN Position
Definition at line 11489 of file NUC472_442.h.
| #define EADC_AD1TRGEN3_EPWM04PEN_Msk (0x1ul << EADC_AD1TRGEN3_EPWM04PEN_Pos) |
EADC_T::AD1TRGEN3: EPWM04PEN Mask
Definition at line 11493 of file NUC472_442.h.
| #define EADC_AD1TRGEN3_EPWM04PEN_Pos (10) |
EADC_T::AD1TRGEN3: EPWM04PEN Position
Definition at line 11492 of file NUC472_442.h.
| #define EADC_AD1TRGEN3_EPWM04REN_Msk (0x1ul << EADC_AD1TRGEN3_EPWM04REN_Pos) |
EADC_T::AD1TRGEN3: EPWM04REN Mask
Definition at line 11487 of file NUC472_442.h.
| #define EADC_AD1TRGEN3_EPWM04REN_Pos (8) |
EADC_T::AD1TRGEN3: EPWM04REN Position
Definition at line 11486 of file NUC472_442.h.
| #define EADC_AD1TRGEN3_EPWM10CEN_Msk (0x1ul << EADC_AD1TRGEN3_EPWM10CEN_Pos) |
EADC_T::AD1TRGEN3: EPWM10CEN Mask
Definition at line 11508 of file NUC472_442.h.
| #define EADC_AD1TRGEN3_EPWM10CEN_Pos (15) |
EADC_T::AD1TRGEN3: EPWM10CEN Position
Definition at line 11507 of file NUC472_442.h.
| #define EADC_AD1TRGEN3_EPWM10FEN_Msk (0x1ul << EADC_AD1TRGEN3_EPWM10FEN_Pos) |
EADC_T::AD1TRGEN3: EPWM10FEN Mask
Definition at line 11502 of file NUC472_442.h.
| #define EADC_AD1TRGEN3_EPWM10FEN_Pos (13) |
EADC_T::AD1TRGEN3: EPWM10FEN Position
Definition at line 11501 of file NUC472_442.h.
| #define EADC_AD1TRGEN3_EPWM10PEN_Msk (0x1ul << EADC_AD1TRGEN3_EPWM10PEN_Pos) |
EADC_T::AD1TRGEN3: EPWM10PEN Mask
Definition at line 11505 of file NUC472_442.h.
| #define EADC_AD1TRGEN3_EPWM10PEN_Pos (14) |
EADC_T::AD1TRGEN3: EPWM10PEN Position
Definition at line 11504 of file NUC472_442.h.
| #define EADC_AD1TRGEN3_EPWM10REN_Msk (0x1ul << EADC_AD1TRGEN3_EPWM10REN_Pos) |
EADC_T::AD1TRGEN3: EPWM10REN Mask
Definition at line 11499 of file NUC472_442.h.
| #define EADC_AD1TRGEN3_EPWM10REN_Pos (12) |
EADC_T::AD1TRGEN3: EPWM10REN Position
Definition at line 11498 of file NUC472_442.h.
| #define EADC_AD1TRGEN3_EPWM120FEN_Msk (0x1ul << EADC_AD1TRGEN3_EPWM120FEN_Pos) |
EADC_T::AD1TRGEN3: EPWM120FEN Mask
Definition at line 11514 of file NUC472_442.h.
| #define EADC_AD1TRGEN3_EPWM120FEN_Pos (17) |
EADC_T::AD1TRGEN3: EPWM120FEN Position
Definition at line 11513 of file NUC472_442.h.
| #define EADC_AD1TRGEN3_EPWM12CEN_Msk (0x1ul << EADC_AD1TRGEN3_EPWM12CEN_Pos) |
EADC_T::AD1TRGEN3: EPWM12CEN Mask
Definition at line 11520 of file NUC472_442.h.
| #define EADC_AD1TRGEN3_EPWM12CEN_Pos (19) |
EADC_T::AD1TRGEN3: EPWM12CEN Position
Definition at line 11519 of file NUC472_442.h.
| #define EADC_AD1TRGEN3_EPWM12PEN_Msk (0x1ul << EADC_AD1TRGEN3_EPWM12PEN_Pos) |
EADC_T::AD1TRGEN3: EPWM12PEN Mask
Definition at line 11517 of file NUC472_442.h.
| #define EADC_AD1TRGEN3_EPWM12PEN_Pos (18) |
EADC_T::AD1TRGEN3: EPWM12PEN Position
Definition at line 11516 of file NUC472_442.h.
| #define EADC_AD1TRGEN3_EPWM12REN_Msk (0x1ul << EADC_AD1TRGEN3_EPWM12REN_Pos) |
EADC_T::AD1TRGEN3: EPWM12REN Mask
Definition at line 11511 of file NUC472_442.h.
| #define EADC_AD1TRGEN3_EPWM12REN_Pos (16) |
EADC_T::AD1TRGEN3: EPWM12REN Position
Definition at line 11510 of file NUC472_442.h.
| #define EADC_AD1TRGEN3_EPWM14CEN_Msk (0x1ul << EADC_AD1TRGEN3_EPWM14CEN_Pos) |
EADC_T::AD1TRGEN3: EPWM14CEN Mask
Definition at line 11532 of file NUC472_442.h.
| #define EADC_AD1TRGEN3_EPWM14CEN_Pos (23) |
EADC_T::AD1TRGEN3: EPWM14CEN Position
Definition at line 11531 of file NUC472_442.h.
| #define EADC_AD1TRGEN3_EPWM14FEN_Msk (0x1ul << EADC_AD1TRGEN3_EPWM14FEN_Pos) |
EADC_T::AD1TRGEN3: EPWM14FEN Mask
Definition at line 11526 of file NUC472_442.h.
| #define EADC_AD1TRGEN3_EPWM14FEN_Pos (21) |
EADC_T::AD1TRGEN3: EPWM14FEN Position
Definition at line 11525 of file NUC472_442.h.
| #define EADC_AD1TRGEN3_EPWM14PEN_Msk (0x1ul << EADC_AD1TRGEN3_EPWM14PEN_Pos) |
EADC_T::AD1TRGEN3: EPWM14PEN Mask
Definition at line 11529 of file NUC472_442.h.
| #define EADC_AD1TRGEN3_EPWM14PEN_Pos (22) |
EADC_T::AD1TRGEN3: EPWM14PEN Position
Definition at line 11528 of file NUC472_442.h.
| #define EADC_AD1TRGEN3_EPWM14REN_Msk (0x1ul << EADC_AD1TRGEN3_EPWM14REN_Pos) |
EADC_T::AD1TRGEN3: EPWM14REN Mask
Definition at line 11523 of file NUC472_442.h.
| #define EADC_AD1TRGEN3_EPWM14REN_Pos (20) |
EADC_T::AD1TRGEN3: EPWM14REN Position
Definition at line 11522 of file NUC472_442.h.
| #define EADC_AD1TRGEN3_PWM00CEN_Msk (0x1ul << EADC_AD1TRGEN3_PWM00CEN_Pos) |
EADC_T::AD1TRGEN3: PWM00CEN Mask
Definition at line 11544 of file NUC472_442.h.
| #define EADC_AD1TRGEN3_PWM00CEN_Pos (27) |
EADC_T::AD1TRGEN3: PWM00CEN Position
Definition at line 11543 of file NUC472_442.h.
| #define EADC_AD1TRGEN3_PWM00FEN_Msk (0x1ul << EADC_AD1TRGEN3_PWM00FEN_Pos) |
EADC_T::AD1TRGEN3: PWM00FEN Mask
Definition at line 11538 of file NUC472_442.h.
| #define EADC_AD1TRGEN3_PWM00FEN_Pos (25) |
EADC_T::AD1TRGEN3: PWM00FEN Position
Definition at line 11537 of file NUC472_442.h.
| #define EADC_AD1TRGEN3_PWM00PEN_Msk (0x1ul << EADC_AD1TRGEN3_PWM00PEN_Pos) |
EADC_T::AD1TRGEN3: PWM00PEN Mask
Definition at line 11541 of file NUC472_442.h.
| #define EADC_AD1TRGEN3_PWM00PEN_Pos (26) |
EADC_T::AD1TRGEN3: PWM00PEN Position
Definition at line 11540 of file NUC472_442.h.
| #define EADC_AD1TRGEN3_PWM00REN_Msk (0x1ul << EADC_AD1TRGEN3_PWM00REN_Pos) |
EADC_T::AD1TRGEN3: PWM00REN Mask
Definition at line 11535 of file NUC472_442.h.
| #define EADC_AD1TRGEN3_PWM00REN_Pos (24) |
EADC_T::AD1TRGEN3: PWM00REN Position
Definition at line 11534 of file NUC472_442.h.
| #define EADC_AD1TRGEN3_PWM01CEN_Msk (0x1ul << EADC_AD1TRGEN3_PWM01CEN_Pos) |
EADC_T::AD1TRGEN3: PWM01CEN Mask
Definition at line 11556 of file NUC472_442.h.
| #define EADC_AD1TRGEN3_PWM01CEN_Pos (31) |
EADC_T::AD1TRGEN3: PWM01CEN Position
Definition at line 11555 of file NUC472_442.h.
| #define EADC_AD1TRGEN3_PWM01FEN_Msk (0x1ul << EADC_AD1TRGEN3_PWM01FEN_Pos) |
EADC_T::AD1TRGEN3: PWM01FEN Mask
Definition at line 11550 of file NUC472_442.h.
| #define EADC_AD1TRGEN3_PWM01FEN_Pos (29) |
EADC_T::AD1TRGEN3: PWM01FEN Position
Definition at line 11549 of file NUC472_442.h.
| #define EADC_AD1TRGEN3_PWM01PEN_Msk (0x1ul << EADC_AD1TRGEN3_PWM01PEN_Pos) |
EADC_T::AD1TRGEN3: PWM01PEN Mask
Definition at line 11553 of file NUC472_442.h.
| #define EADC_AD1TRGEN3_PWM01PEN_Pos (30) |
EADC_T::AD1TRGEN3: PWM01PEN Position
Definition at line 11552 of file NUC472_442.h.
| #define EADC_AD1TRGEN3_PWM01REN_Msk (0x1ul << EADC_AD1TRGEN3_PWM01REN_Pos) |
EADC_T::AD1TRGEN3: PWM01REN Mask
Definition at line 11547 of file NUC472_442.h.
| #define EADC_AD1TRGEN3_PWM01REN_Pos (28) |
EADC_T::AD1TRGEN3: PWM01REN Position
Definition at line 11546 of file NUC472_442.h.
| #define EADC_ADIFOV_ADFOV0_Msk (0x1ul << EADC_ADIFOV_ADFOV0_Pos) |
EADC_T::ADIFOV: ADFOV0 Mask
Definition at line 10149 of file NUC472_442.h.
| #define EADC_ADIFOV_ADFOV0_Pos (0) |
EADC_T::ADIFOV: ADFOV0 Position
Definition at line 10148 of file NUC472_442.h.
| #define EADC_ADIFOV_ADFOV1_Msk (0x1ul << EADC_ADIFOV_ADFOV1_Pos) |
EADC_T::ADIFOV: ADFOV1 Mask
Definition at line 10152 of file NUC472_442.h.
| #define EADC_ADIFOV_ADFOV1_Pos (1) |
EADC_T::ADIFOV: ADFOV1 Position
Definition at line 10151 of file NUC472_442.h.
| #define EADC_ADIFOV_ADFOV2_Msk (0x1ul << EADC_ADIFOV_ADFOV2_Pos) |
EADC_T::ADIFOV: ADFOV2 Mask
Definition at line 10155 of file NUC472_442.h.
| #define EADC_ADIFOV_ADFOV2_Pos (2) |
EADC_T::ADIFOV: ADFOV2 Position
Definition at line 10154 of file NUC472_442.h.
| #define EADC_ADIFOV_ADFOV3_Msk (0x1ul << EADC_ADIFOV_ADFOV3_Pos) |
EADC_T::ADIFOV: ADFOV3 Mask
Definition at line 10158 of file NUC472_442.h.
| #define EADC_ADIFOV_ADFOV3_Pos (3) |
EADC_T::ADIFOV: ADFOV3 Position
Definition at line 10157 of file NUC472_442.h.
| #define EADC_CMP0_ADCMPEN_Msk (0x1ul << EADC_CMP0_ADCMPEN_Pos) |
EADC_T::CMP: ADCMPEN Mask
Definition at line 10431 of file NUC472_442.h.
| #define EADC_CMP0_ADCMPEN_Pos (0) |
EADC_T::CMP: ADCMPEN Position
Definition at line 10430 of file NUC472_442.h.
| #define EADC_CMP0_ADCMPIE_Msk (0x1ul << EADC_CMP0_ADCMPIE_Pos) |
EADC_T::CMP: ADCMPIE Mask
Definition at line 10434 of file NUC472_442.h.
| #define EADC_CMP0_ADCMPIE_Pos (1) |
EADC_T::CMP: ADCMPIE Position
Definition at line 10433 of file NUC472_442.h.
| #define EADC_CMP0_CMPCOND_Msk (0x1ul << EADC_CMP0_CMPCOND_Pos) |
EADC_T::CMP: CMPCOND Mask
Definition at line 10437 of file NUC472_442.h.
| #define EADC_CMP0_CMPCOND_Pos (2) |
EADC_T::CMP: CMPCOND Position
Definition at line 10436 of file NUC472_442.h.
| #define EADC_CMP0_CMPDAT_Msk (0xffful << EADC_CMP0_CMPDAT_Pos) |
EADC_T::CMP: CMPDAT Mask
Definition at line 10446 of file NUC472_442.h.
| #define EADC_CMP0_CMPDAT_Pos (16) |
EADC_T::CMP: CMPDAT Position
Definition at line 10445 of file NUC472_442.h.
| #define EADC_CMP0_CMPMCNT_Msk (0xful << EADC_CMP0_CMPMCNT_Pos) |
EADC_T::CMP: CMPMCNT Mask
Definition at line 10443 of file NUC472_442.h.
| #define EADC_CMP0_CMPMCNT_Pos (8) |
EADC_T::CMP: CMPMCNT Position
Definition at line 10442 of file NUC472_442.h.
| #define EADC_CMP0_CMPSPL_Msk (0x7ul << EADC_CMP0_CMPSPL_Pos) |
EADC_T::CMP: CMPSPL Mask
Definition at line 10440 of file NUC472_442.h.
| #define EADC_CMP0_CMPSPL_Pos (3) |
EADC_T::CMP: CMPSPL Position
Definition at line 10439 of file NUC472_442.h.
| #define EADC_CMP1_ADCMPEN_Msk (0x1ul << EADC_CMP1_ADCMPEN_Pos) |
EADC_T::CMP: ADCMPEN Mask
Definition at line 10449 of file NUC472_442.h.
| #define EADC_CMP1_ADCMPEN_Pos (0) |
EADC_T::CMP: ADCMPEN Position
Definition at line 10448 of file NUC472_442.h.
| #define EADC_CMP1_ADCMPIE_Msk (0x1ul << EADC_CMP1_ADCMPIE_Pos) |
EADC_T::CMP: ADCMPIE Mask
Definition at line 10452 of file NUC472_442.h.
| #define EADC_CMP1_ADCMPIE_Pos (1) |
EADC_T::CMP: ADCMPIE Position
Definition at line 10451 of file NUC472_442.h.
| #define EADC_CMP1_CMPCOND_Msk (0x1ul << EADC_CMP1_CMPCOND_Pos) |
EADC_T::CMP: CMPCOND Mask
Definition at line 10455 of file NUC472_442.h.
| #define EADC_CMP1_CMPCOND_Pos (2) |
EADC_T::CMP: CMPCOND Position
Definition at line 10454 of file NUC472_442.h.
| #define EADC_CMP1_CMPDAT_Msk (0xffful << EADC_CMP1_CMPDAT_Pos) |
EADC_T::CMP: CMPDAT Mask
Definition at line 10464 of file NUC472_442.h.
| #define EADC_CMP1_CMPDAT_Pos (16) |
EADC_T::CMP: CMPDAT Position
Definition at line 10463 of file NUC472_442.h.
| #define EADC_CMP1_CMPMCNT_Msk (0xful << EADC_CMP1_CMPMCNT_Pos) |
EADC_T::CMP: CMPMCNT Mask
Definition at line 10461 of file NUC472_442.h.
| #define EADC_CMP1_CMPMCNT_Pos (8) |
EADC_T::CMP: CMPMCNT Position
Definition at line 10460 of file NUC472_442.h.
| #define EADC_CMP1_CMPSPL_Msk (0x7ul << EADC_CMP1_CMPSPL_Pos) |
EADC_T::CMP: CMPSPL Mask
Definition at line 10458 of file NUC472_442.h.
| #define EADC_CMP1_CMPSPL_Pos (3) |
EADC_T::CMP: CMPSPL Position
Definition at line 10457 of file NUC472_442.h.
| #define EADC_CTL_ADCEN_Msk (0x1ul << EADC_CTL_ADCEN_Pos) |
EADC_T::CTL: ADCEN Mask
Definition at line 10119 of file NUC472_442.h.
| #define EADC_CTL_ADCEN_Pos (0) |
EADC_T::CTL: ADCEN Position
Definition at line 10118 of file NUC472_442.h.
| #define EADC_CTL_ADCIEN0_Msk (0x1ul << EADC_CTL_ADCIEN0_Pos) |
EADC_T::CTL: ADCIEN0 Mask
Definition at line 10125 of file NUC472_442.h.
| #define EADC_CTL_ADCIEN0_Pos (2) |
EADC_T::CTL: ADCIEN0 Position
Definition at line 10124 of file NUC472_442.h.
| #define EADC_CTL_ADCIEN1_Msk (0x1ul << EADC_CTL_ADCIEN1_Pos) |
EADC_T::CTL: ADCIEN1 Mask
Definition at line 10128 of file NUC472_442.h.
| #define EADC_CTL_ADCIEN1_Pos (3) |
EADC_T::CTL: ADCIEN1 Position
Definition at line 10127 of file NUC472_442.h.
| #define EADC_CTL_ADCIEN2_Msk (0x1ul << EADC_CTL_ADCIEN2_Pos) |
EADC_T::CTL: ADCIEN2 Mask
Definition at line 10131 of file NUC472_442.h.
| #define EADC_CTL_ADCIEN2_Pos (4) |
EADC_T::CTL: ADCIEN2 Position
Definition at line 10130 of file NUC472_442.h.
| #define EADC_CTL_ADCIEN3_Msk (0x1ul << EADC_CTL_ADCIEN3_Pos) |
EADC_T::CTL: ADCIEN3 Mask
Definition at line 10134 of file NUC472_442.h.
| #define EADC_CTL_ADCIEN3_Pos (5) |
EADC_T::CTL: ADCIEN3 Position
Definition at line 10133 of file NUC472_442.h.
| #define EADC_CTL_ADCRST_Msk (0x1ul << EADC_CTL_ADCRST_Pos) |
EADC_T::CTL: ADCRST Mask
Definition at line 10122 of file NUC472_442.h.
| #define EADC_CTL_ADCRST_Pos (1) |
EADC_T::CTL: ADCRST Position
Definition at line 10121 of file NUC472_442.h.
| #define EADC_DBMEN_AD0DBM0_Msk (0x1ul << EADC_DBMEN_AD0DBM0_Pos) |
EADC_T::DBMEN: AD0DBM0 Mask
Definition at line 10575 of file NUC472_442.h.
| #define EADC_DBMEN_AD0DBM0_Pos (0) |
EADC_T::DBMEN: AD0DBM0 Position
Definition at line 10574 of file NUC472_442.h.
| #define EADC_DBMEN_AD0DBM1_Msk (0x1ul << EADC_DBMEN_AD0DBM1_Pos) |
EADC_T::DBMEN: AD0DBM1 Mask
Definition at line 10578 of file NUC472_442.h.
| #define EADC_DBMEN_AD0DBM1_Pos (1) |
EADC_T::DBMEN: AD0DBM1 Position
Definition at line 10577 of file NUC472_442.h.
| #define EADC_DBMEN_AD0DBM2_Msk (0x1ul << EADC_DBMEN_AD0DBM2_Pos) |
EADC_T::DBMEN: AD0DBM2 Mask
Definition at line 10581 of file NUC472_442.h.
| #define EADC_DBMEN_AD0DBM2_Pos (2) |
EADC_T::DBMEN: AD0DBM2 Position
Definition at line 10580 of file NUC472_442.h.
| #define EADC_DBMEN_AD0DBM3_Msk (0x1ul << EADC_DBMEN_AD0DBM3_Pos) |
EADC_T::DBMEN: AD0DBM3 Mask
Definition at line 10584 of file NUC472_442.h.
| #define EADC_DBMEN_AD0DBM3_Pos (3) |
EADC_T::DBMEN: AD0DBM3 Position
Definition at line 10583 of file NUC472_442.h.
| #define EADC_DBMEN_AD1DBM0_Msk (0x1ul << EADC_DBMEN_AD1DBM0_Pos) |
EADC_T::DBMEN: AD1DBM0 Mask
Definition at line 10587 of file NUC472_442.h.
| #define EADC_DBMEN_AD1DBM0_Pos (8) |
EADC_T::DBMEN: AD1DBM0 Position
Definition at line 10586 of file NUC472_442.h.
| #define EADC_DBMEN_AD1DBM1_Msk (0x1ul << EADC_DBMEN_AD1DBM1_Pos) |
EADC_T::DBMEN: AD1DBM1 Mask
Definition at line 10590 of file NUC472_442.h.
| #define EADC_DBMEN_AD1DBM1_Pos (9) |
EADC_T::DBMEN: AD1DBM1 Position
Definition at line 10589 of file NUC472_442.h.
| #define EADC_DBMEN_AD1DBM2_Msk (0x1ul << EADC_DBMEN_AD1DBM2_Pos) |
EADC_T::DBMEN: AD1DBM2 Mask
Definition at line 10593 of file NUC472_442.h.
| #define EADC_DBMEN_AD1DBM2_Pos (10) |
EADC_T::DBMEN: AD1DBM2 Position
Definition at line 10592 of file NUC472_442.h.
| #define EADC_DBMEN_AD1DBM3_Msk (0x1ul << EADC_DBMEN_AD1DBM3_Pos) |
EADC_T::DBMEN: AD1DBM3 Mask
Definition at line 10596 of file NUC472_442.h.
| #define EADC_DBMEN_AD1DBM3_Pos (11) |
EADC_T::DBMEN: AD1DBM3 Position
Definition at line 10595 of file NUC472_442.h.
| #define EADC_EXTSMPT_EXTSMPT0_Msk (0xfful << EADC_EXTSMPT_EXTSMPT0_Pos) |
EADC_T::EXTSMPT: EXTSMPT0 Mask
Definition at line 10521 of file NUC472_442.h.
| #define EADC_EXTSMPT_EXTSMPT0_Pos (0) |
EADC_T::EXTSMPT: EXTSMPT0 Position
Definition at line 10520 of file NUC472_442.h.
| #define EADC_EXTSMPT_EXTSMPT1_Msk (0xfful << EADC_EXTSMPT_EXTSMPT1_Pos) |
EADC_T::EXTSMPT: EXTSMPT1 Mask
Definition at line 10524 of file NUC472_442.h.
| #define EADC_EXTSMPT_EXTSMPT1_Pos (16) |
EADC_T::EXTSMPT: EXTSMPT1 Position
Definition at line 10523 of file NUC472_442.h.
| #define EADC_INTSRC0_AD0SPIE0_Msk (0x1ul << EADC_INTSRC0_AD0SPIE0_Pos) |
EADC_T::INTSRC: AD0SPIE0 Mask
Definition at line 10599 of file NUC472_442.h.
| #define EADC_INTSRC0_AD0SPIE0_Pos (0) |
EADC_T::INTSRC: AD0SPIE0 Position
Definition at line 10598 of file NUC472_442.h.
| #define EADC_INTSRC0_AD0SPIE1_Msk (0x1ul << EADC_INTSRC0_AD0SPIE1_Pos) |
EADC_T::INTSRC: AD0SPIE1 Mask
Definition at line 10602 of file NUC472_442.h.
| #define EADC_INTSRC0_AD0SPIE1_Pos (1) |
EADC_T::INTSRC: AD0SPIE1 Position
Definition at line 10601 of file NUC472_442.h.
| #define EADC_INTSRC0_AD0SPIE2_Msk (0x1ul << EADC_INTSRC0_AD0SPIE2_Pos) |
EADC_T::INTSRC: AD0SPIE2 Mask
Definition at line 10605 of file NUC472_442.h.
| #define EADC_INTSRC0_AD0SPIE2_Pos (2) |
EADC_T::INTSRC: AD0SPIE2 Position
Definition at line 10604 of file NUC472_442.h.
| #define EADC_INTSRC0_AD0SPIE3_Msk (0x1ul << EADC_INTSRC0_AD0SPIE3_Pos) |
EADC_T::INTSRC: AD0SPIE3 Mask
Definition at line 10608 of file NUC472_442.h.
| #define EADC_INTSRC0_AD0SPIE3_Pos (3) |
EADC_T::INTSRC: AD0SPIE3 Position
Definition at line 10607 of file NUC472_442.h.
| #define EADC_INTSRC0_AD0SPIE4_Msk (0x1ul << EADC_INTSRC0_AD0SPIE4_Pos) |
EADC_T::INTSRC: AD0SPIE4 Mask
Definition at line 10611 of file NUC472_442.h.
| #define EADC_INTSRC0_AD0SPIE4_Pos (4) |
EADC_T::INTSRC: AD0SPIE4 Position
Definition at line 10610 of file NUC472_442.h.
| #define EADC_INTSRC0_AD0SPIE5_Msk (0x1ul << EADC_INTSRC0_AD0SPIE5_Pos) |
EADC_T::INTSRC: AD0SPIE5 Mask
Definition at line 10614 of file NUC472_442.h.
| #define EADC_INTSRC0_AD0SPIE5_Pos (5) |
EADC_T::INTSRC: AD0SPIE5 Position
Definition at line 10613 of file NUC472_442.h.
| #define EADC_INTSRC0_AD0SPIE6_Msk (0x1ul << EADC_INTSRC0_AD0SPIE6_Pos) |
EADC_T::INTSRC: AD0SPIE6 Mask
Definition at line 10617 of file NUC472_442.h.
| #define EADC_INTSRC0_AD0SPIE6_Pos (6) |
EADC_T::INTSRC: AD0SPIE6 Position
Definition at line 10616 of file NUC472_442.h.
| #define EADC_INTSRC0_AD0SPIE7_Msk (0x1ul << EADC_INTSRC0_AD0SPIE7_Pos) |
EADC_T::INTSRC: AD0SPIE7 Mask
Definition at line 10620 of file NUC472_442.h.
| #define EADC_INTSRC0_AD0SPIE7_Pos (7) |
EADC_T::INTSRC: AD0SPIE7 Position
Definition at line 10619 of file NUC472_442.h.
| #define EADC_INTSRC0_AD1SPIE0_Msk (0x1ul << EADC_INTSRC0_AD1SPIE0_Pos) |
EADC_T::INTSRC: AD1SPIE0 Mask
Definition at line 10623 of file NUC472_442.h.
| #define EADC_INTSRC0_AD1SPIE0_Pos (8) |
EADC_T::INTSRC: AD1SPIE0 Position
Definition at line 10622 of file NUC472_442.h.
| #define EADC_INTSRC0_AD1SPIE1_Msk (0x1ul << EADC_INTSRC0_AD1SPIE1_Pos) |
EADC_T::INTSRC: AD1SPIE1 Mask
Definition at line 10626 of file NUC472_442.h.
| #define EADC_INTSRC0_AD1SPIE1_Pos (9) |
EADC_T::INTSRC: AD1SPIE1 Position
Definition at line 10625 of file NUC472_442.h.
| #define EADC_INTSRC0_AD1SPIE2_Msk (0x1ul << EADC_INTSRC0_AD1SPIE2_Pos) |
EADC_T::INTSRC: AD1SPIE2 Mask
Definition at line 10629 of file NUC472_442.h.
| #define EADC_INTSRC0_AD1SPIE2_Pos (10) |
EADC_T::INTSRC: AD1SPIE2 Position
Definition at line 10628 of file NUC472_442.h.
| #define EADC_INTSRC0_AD1SPIE3_Msk (0x1ul << EADC_INTSRC0_AD1SPIE3_Pos) |
EADC_T::INTSRC: AD1SPIE3 Mask
Definition at line 10632 of file NUC472_442.h.
| #define EADC_INTSRC0_AD1SPIE3_Pos (11) |
EADC_T::INTSRC: AD1SPIE3 Position
Definition at line 10631 of file NUC472_442.h.
| #define EADC_INTSRC0_AD1SPIE4_Msk (0x1ul << EADC_INTSRC0_AD1SPIE4_Pos) |
EADC_T::INTSRC: AD1SPIE4 Mask
Definition at line 10635 of file NUC472_442.h.
| #define EADC_INTSRC0_AD1SPIE4_Pos (12) |
EADC_T::INTSRC: AD1SPIE4 Position
Definition at line 10634 of file NUC472_442.h.
| #define EADC_INTSRC0_AD1SPIE5_Msk (0x1ul << EADC_INTSRC0_AD1SPIE5_Pos) |
EADC_T::INTSRC: AD1SPIE5 Mask
Definition at line 10638 of file NUC472_442.h.
| #define EADC_INTSRC0_AD1SPIE5_Pos (13) |
EADC_T::INTSRC: AD1SPIE5 Position
Definition at line 10637 of file NUC472_442.h.
| #define EADC_INTSRC0_AD1SPIE6_Msk (0x1ul << EADC_INTSRC0_AD1SPIE6_Pos) |
EADC_T::INTSRC: AD1SPIE6 Mask
Definition at line 10641 of file NUC472_442.h.
| #define EADC_INTSRC0_AD1SPIE6_Pos (14) |
EADC_T::INTSRC: AD1SPIE6 Position
Definition at line 10640 of file NUC472_442.h.
| #define EADC_INTSRC0_AD1SPIE7_Msk (0x1ul << EADC_INTSRC0_AD1SPIE7_Pos) |
EADC_T::INTSRC: AD1SPIE7 Mask
Definition at line 10644 of file NUC472_442.h.
| #define EADC_INTSRC0_AD1SPIE7_Pos (15) |
EADC_T::INTSRC: AD1SPIE7 Position
Definition at line 10643 of file NUC472_442.h.
| #define EADC_INTSRC1_AD0SPIE0_Msk (0x1ul << EADC_INTSRC1_AD0SPIE0_Pos) |
EADC_T::INTSRC: AD0SPIE0 Mask
Definition at line 10647 of file NUC472_442.h.
| #define EADC_INTSRC1_AD0SPIE0_Pos (0) |
EADC_T::INTSRC: AD0SPIE0 Position
Definition at line 10646 of file NUC472_442.h.
| #define EADC_INTSRC1_AD0SPIE1_Msk (0x1ul << EADC_INTSRC1_AD0SPIE1_Pos) |
EADC_T::INTSRC: AD0SPIE1 Mask
Definition at line 10650 of file NUC472_442.h.
| #define EADC_INTSRC1_AD0SPIE1_Pos (1) |
EADC_T::INTSRC: AD0SPIE1 Position
Definition at line 10649 of file NUC472_442.h.
| #define EADC_INTSRC1_AD0SPIE2_Msk (0x1ul << EADC_INTSRC1_AD0SPIE2_Pos) |
EADC_T::INTSRC: AD0SPIE2 Mask
Definition at line 10653 of file NUC472_442.h.
| #define EADC_INTSRC1_AD0SPIE2_Pos (2) |
EADC_T::INTSRC: AD0SPIE2 Position
Definition at line 10652 of file NUC472_442.h.
| #define EADC_INTSRC1_AD0SPIE3_Msk (0x1ul << EADC_INTSRC1_AD0SPIE3_Pos) |
EADC_T::INTSRC: AD0SPIE3 Mask
Definition at line 10656 of file NUC472_442.h.
| #define EADC_INTSRC1_AD0SPIE3_Pos (3) |
EADC_T::INTSRC: AD0SPIE3 Position
Definition at line 10655 of file NUC472_442.h.
| #define EADC_INTSRC1_AD0SPIE4_Msk (0x1ul << EADC_INTSRC1_AD0SPIE4_Pos) |
EADC_T::INTSRC: AD0SPIE4 Mask
Definition at line 10659 of file NUC472_442.h.
| #define EADC_INTSRC1_AD0SPIE4_Pos (4) |
EADC_T::INTSRC: AD0SPIE4 Position
Definition at line 10658 of file NUC472_442.h.
| #define EADC_INTSRC1_AD0SPIE5_Msk (0x1ul << EADC_INTSRC1_AD0SPIE5_Pos) |
EADC_T::INTSRC: AD0SPIE5 Mask
Definition at line 10662 of file NUC472_442.h.
| #define EADC_INTSRC1_AD0SPIE5_Pos (5) |
EADC_T::INTSRC: AD0SPIE5 Position
Definition at line 10661 of file NUC472_442.h.
| #define EADC_INTSRC1_AD0SPIE6_Msk (0x1ul << EADC_INTSRC1_AD0SPIE6_Pos) |
EADC_T::INTSRC: AD0SPIE6 Mask
Definition at line 10665 of file NUC472_442.h.
| #define EADC_INTSRC1_AD0SPIE6_Pos (6) |
EADC_T::INTSRC: AD0SPIE6 Position
Definition at line 10664 of file NUC472_442.h.
| #define EADC_INTSRC1_AD0SPIE7_Msk (0x1ul << EADC_INTSRC1_AD0SPIE7_Pos) |
EADC_T::INTSRC: AD0SPIE7 Mask
Definition at line 10668 of file NUC472_442.h.
| #define EADC_INTSRC1_AD0SPIE7_Pos (7) |
EADC_T::INTSRC: AD0SPIE7 Position
Definition at line 10667 of file NUC472_442.h.
| #define EADC_INTSRC1_AD1SPIE0_Msk (0x1ul << EADC_INTSRC1_AD1SPIE0_Pos) |
EADC_T::INTSRC: AD1SPIE0 Mask
Definition at line 10671 of file NUC472_442.h.
| #define EADC_INTSRC1_AD1SPIE0_Pos (8) |
EADC_T::INTSRC: AD1SPIE0 Position
Definition at line 10670 of file NUC472_442.h.
| #define EADC_INTSRC1_AD1SPIE1_Msk (0x1ul << EADC_INTSRC1_AD1SPIE1_Pos) |
EADC_T::INTSRC: AD1SPIE1 Mask
Definition at line 10674 of file NUC472_442.h.
| #define EADC_INTSRC1_AD1SPIE1_Pos (9) |
EADC_T::INTSRC: AD1SPIE1 Position
Definition at line 10673 of file NUC472_442.h.
| #define EADC_INTSRC1_AD1SPIE2_Msk (0x1ul << EADC_INTSRC1_AD1SPIE2_Pos) |
EADC_T::INTSRC: AD1SPIE2 Mask
Definition at line 10677 of file NUC472_442.h.
| #define EADC_INTSRC1_AD1SPIE2_Pos (10) |
EADC_T::INTSRC: AD1SPIE2 Position
Definition at line 10676 of file NUC472_442.h.
| #define EADC_INTSRC1_AD1SPIE3_Msk (0x1ul << EADC_INTSRC1_AD1SPIE3_Pos) |
EADC_T::INTSRC: AD1SPIE3 Mask
Definition at line 10680 of file NUC472_442.h.
| #define EADC_INTSRC1_AD1SPIE3_Pos (11) |
EADC_T::INTSRC: AD1SPIE3 Position
Definition at line 10679 of file NUC472_442.h.
| #define EADC_INTSRC1_AD1SPIE4_Msk (0x1ul << EADC_INTSRC1_AD1SPIE4_Pos) |
EADC_T::INTSRC: AD1SPIE4 Mask
Definition at line 10683 of file NUC472_442.h.
| #define EADC_INTSRC1_AD1SPIE4_Pos (12) |
EADC_T::INTSRC: AD1SPIE4 Position
Definition at line 10682 of file NUC472_442.h.
| #define EADC_INTSRC1_AD1SPIE5_Msk (0x1ul << EADC_INTSRC1_AD1SPIE5_Pos) |
EADC_T::INTSRC: AD1SPIE5 Mask
Definition at line 10686 of file NUC472_442.h.
| #define EADC_INTSRC1_AD1SPIE5_Pos (13) |
EADC_T::INTSRC: AD1SPIE5 Position
Definition at line 10685 of file NUC472_442.h.
| #define EADC_INTSRC1_AD1SPIE6_Msk (0x1ul << EADC_INTSRC1_AD1SPIE6_Pos) |
EADC_T::INTSRC: AD1SPIE6 Mask
Definition at line 10689 of file NUC472_442.h.
| #define EADC_INTSRC1_AD1SPIE6_Pos (14) |
EADC_T::INTSRC: AD1SPIE6 Position
Definition at line 10688 of file NUC472_442.h.
| #define EADC_INTSRC1_AD1SPIE7_Msk (0x1ul << EADC_INTSRC1_AD1SPIE7_Pos) |
EADC_T::INTSRC: AD1SPIE7 Mask
Definition at line 10692 of file NUC472_442.h.
| #define EADC_INTSRC1_AD1SPIE7_Pos (15) |
EADC_T::INTSRC: AD1SPIE7 Position
Definition at line 10691 of file NUC472_442.h.
| #define EADC_INTSRC2_AD0SPIE0_Msk (0x1ul << EADC_INTSRC2_AD0SPIE0_Pos) |
EADC_T::INTSRC: AD0SPIE0 Mask
Definition at line 10695 of file NUC472_442.h.
| #define EADC_INTSRC2_AD0SPIE0_Pos (0) |
EADC_T::INTSRC: AD0SPIE0 Position
Definition at line 10694 of file NUC472_442.h.
| #define EADC_INTSRC2_AD0SPIE1_Msk (0x1ul << EADC_INTSRC2_AD0SPIE1_Pos) |
EADC_T::INTSRC: AD0SPIE1 Mask
Definition at line 10698 of file NUC472_442.h.
| #define EADC_INTSRC2_AD0SPIE1_Pos (1) |
EADC_T::INTSRC: AD0SPIE1 Position
Definition at line 10697 of file NUC472_442.h.
| #define EADC_INTSRC2_AD0SPIE2_Msk (0x1ul << EADC_INTSRC2_AD0SPIE2_Pos) |
EADC_T::INTSRC: AD0SPIE2 Mask
Definition at line 10701 of file NUC472_442.h.
| #define EADC_INTSRC2_AD0SPIE2_Pos (2) |
EADC_T::INTSRC: AD0SPIE2 Position
Definition at line 10700 of file NUC472_442.h.
| #define EADC_INTSRC2_AD0SPIE3_Msk (0x1ul << EADC_INTSRC2_AD0SPIE3_Pos) |
EADC_T::INTSRC: AD0SPIE3 Mask
Definition at line 10704 of file NUC472_442.h.
| #define EADC_INTSRC2_AD0SPIE3_Pos (3) |
EADC_T::INTSRC: AD0SPIE3 Position
Definition at line 10703 of file NUC472_442.h.
| #define EADC_INTSRC2_AD0SPIE4_Msk (0x1ul << EADC_INTSRC2_AD0SPIE4_Pos) |
EADC_T::INTSRC: AD0SPIE4 Mask
Definition at line 10707 of file NUC472_442.h.
| #define EADC_INTSRC2_AD0SPIE4_Pos (4) |
EADC_T::INTSRC: AD0SPIE4 Position
Definition at line 10706 of file NUC472_442.h.
| #define EADC_INTSRC2_AD0SPIE5_Msk (0x1ul << EADC_INTSRC2_AD0SPIE5_Pos) |
EADC_T::INTSRC: AD0SPIE5 Mask
Definition at line 10710 of file NUC472_442.h.
| #define EADC_INTSRC2_AD0SPIE5_Pos (5) |
EADC_T::INTSRC: AD0SPIE5 Position
Definition at line 10709 of file NUC472_442.h.
| #define EADC_INTSRC2_AD0SPIE6_Msk (0x1ul << EADC_INTSRC2_AD0SPIE6_Pos) |
EADC_T::INTSRC: AD0SPIE6 Mask
Definition at line 10713 of file NUC472_442.h.
| #define EADC_INTSRC2_AD0SPIE6_Pos (6) |
EADC_T::INTSRC: AD0SPIE6 Position
Definition at line 10712 of file NUC472_442.h.
| #define EADC_INTSRC2_AD0SPIE7_Msk (0x1ul << EADC_INTSRC2_AD0SPIE7_Pos) |
EADC_T::INTSRC: AD0SPIE7 Mask
Definition at line 10716 of file NUC472_442.h.
| #define EADC_INTSRC2_AD0SPIE7_Pos (7) |
EADC_T::INTSRC: AD0SPIE7 Position
Definition at line 10715 of file NUC472_442.h.
| #define EADC_INTSRC2_AD1SPIE0_Msk (0x1ul << EADC_INTSRC2_AD1SPIE0_Pos) |
EADC_T::INTSRC: AD1SPIE0 Mask
Definition at line 10719 of file NUC472_442.h.
| #define EADC_INTSRC2_AD1SPIE0_Pos (8) |
EADC_T::INTSRC: AD1SPIE0 Position
Definition at line 10718 of file NUC472_442.h.
| #define EADC_INTSRC2_AD1SPIE1_Msk (0x1ul << EADC_INTSRC2_AD1SPIE1_Pos) |
EADC_T::INTSRC: AD1SPIE1 Mask
Definition at line 10722 of file NUC472_442.h.
| #define EADC_INTSRC2_AD1SPIE1_Pos (9) |
EADC_T::INTSRC: AD1SPIE1 Position
Definition at line 10721 of file NUC472_442.h.
| #define EADC_INTSRC2_AD1SPIE2_Msk (0x1ul << EADC_INTSRC2_AD1SPIE2_Pos) |
EADC_T::INTSRC: AD1SPIE2 Mask
Definition at line 10725 of file NUC472_442.h.
| #define EADC_INTSRC2_AD1SPIE2_Pos (10) |
EADC_T::INTSRC: AD1SPIE2 Position
Definition at line 10724 of file NUC472_442.h.
| #define EADC_INTSRC2_AD1SPIE3_Msk (0x1ul << EADC_INTSRC2_AD1SPIE3_Pos) |
EADC_T::INTSRC: AD1SPIE3 Mask
Definition at line 10728 of file NUC472_442.h.
| #define EADC_INTSRC2_AD1SPIE3_Pos (11) |
EADC_T::INTSRC: AD1SPIE3 Position
Definition at line 10727 of file NUC472_442.h.
| #define EADC_INTSRC2_AD1SPIE4_Msk (0x1ul << EADC_INTSRC2_AD1SPIE4_Pos) |
EADC_T::INTSRC: AD1SPIE4 Mask
Definition at line 10731 of file NUC472_442.h.
| #define EADC_INTSRC2_AD1SPIE4_Pos (12) |
EADC_T::INTSRC: AD1SPIE4 Position
Definition at line 10730 of file NUC472_442.h.
| #define EADC_INTSRC2_AD1SPIE5_Msk (0x1ul << EADC_INTSRC2_AD1SPIE5_Pos) |
EADC_T::INTSRC: AD1SPIE5 Mask
Definition at line 10734 of file NUC472_442.h.
| #define EADC_INTSRC2_AD1SPIE5_Pos (13) |
EADC_T::INTSRC: AD1SPIE5 Position
Definition at line 10733 of file NUC472_442.h.
| #define EADC_INTSRC2_AD1SPIE6_Msk (0x1ul << EADC_INTSRC2_AD1SPIE6_Pos) |
EADC_T::INTSRC: AD1SPIE6 Mask
Definition at line 10737 of file NUC472_442.h.
| #define EADC_INTSRC2_AD1SPIE6_Pos (14) |
EADC_T::INTSRC: AD1SPIE6 Position
Definition at line 10736 of file NUC472_442.h.
| #define EADC_INTSRC2_AD1SPIE7_Msk (0x1ul << EADC_INTSRC2_AD1SPIE7_Pos) |
EADC_T::INTSRC: AD1SPIE7 Mask
Definition at line 10740 of file NUC472_442.h.
| #define EADC_INTSRC2_AD1SPIE7_Pos (15) |
EADC_T::INTSRC: AD1SPIE7 Position
Definition at line 10739 of file NUC472_442.h.
| #define EADC_INTSRC3_AD0SPIE0_Msk (0x1ul << EADC_INTSRC3_AD0SPIE0_Pos) |
EADC_T::INTSRC: AD0SPIE0 Mask
Definition at line 10743 of file NUC472_442.h.
| #define EADC_INTSRC3_AD0SPIE0_Pos (0) |
EADC_T::INTSRC: AD0SPIE0 Position
Definition at line 10742 of file NUC472_442.h.
| #define EADC_INTSRC3_AD0SPIE1_Msk (0x1ul << EADC_INTSRC3_AD0SPIE1_Pos) |
EADC_T::INTSRC: AD0SPIE1 Mask
Definition at line 10746 of file NUC472_442.h.
| #define EADC_INTSRC3_AD0SPIE1_Pos (1) |
EADC_T::INTSRC: AD0SPIE1 Position
Definition at line 10745 of file NUC472_442.h.
| #define EADC_INTSRC3_AD0SPIE2_Msk (0x1ul << EADC_INTSRC3_AD0SPIE2_Pos) |
EADC_T::INTSRC: AD0SPIE2 Mask
Definition at line 10749 of file NUC472_442.h.
| #define EADC_INTSRC3_AD0SPIE2_Pos (2) |
EADC_T::INTSRC: AD0SPIE2 Position
Definition at line 10748 of file NUC472_442.h.
| #define EADC_INTSRC3_AD0SPIE3_Msk (0x1ul << EADC_INTSRC3_AD0SPIE3_Pos) |
EADC_T::INTSRC: AD0SPIE3 Mask
Definition at line 10752 of file NUC472_442.h.
| #define EADC_INTSRC3_AD0SPIE3_Pos (3) |
EADC_T::INTSRC: AD0SPIE3 Position
Definition at line 10751 of file NUC472_442.h.
| #define EADC_INTSRC3_AD0SPIE4_Msk (0x1ul << EADC_INTSRC3_AD0SPIE4_Pos) |
EADC_T::INTSRC: AD0SPIE4 Mask
Definition at line 10755 of file NUC472_442.h.
| #define EADC_INTSRC3_AD0SPIE4_Pos (4) |
EADC_T::INTSRC: AD0SPIE4 Position
Definition at line 10754 of file NUC472_442.h.
| #define EADC_INTSRC3_AD0SPIE5_Msk (0x1ul << EADC_INTSRC3_AD0SPIE5_Pos) |
EADC_T::INTSRC: AD0SPIE5 Mask
Definition at line 10758 of file NUC472_442.h.
| #define EADC_INTSRC3_AD0SPIE5_Pos (5) |
EADC_T::INTSRC: AD0SPIE5 Position
Definition at line 10757 of file NUC472_442.h.
| #define EADC_INTSRC3_AD0SPIE6_Msk (0x1ul << EADC_INTSRC3_AD0SPIE6_Pos) |
EADC_T::INTSRC: AD0SPIE6 Mask
Definition at line 10761 of file NUC472_442.h.
| #define EADC_INTSRC3_AD0SPIE6_Pos (6) |
EADC_T::INTSRC: AD0SPIE6 Position
Definition at line 10760 of file NUC472_442.h.
| #define EADC_INTSRC3_AD0SPIE7_Msk (0x1ul << EADC_INTSRC3_AD0SPIE7_Pos) |
EADC_T::INTSRC: AD0SPIE7 Mask
Definition at line 10764 of file NUC472_442.h.
| #define EADC_INTSRC3_AD0SPIE7_Pos (7) |
EADC_T::INTSRC: AD0SPIE7 Position
Definition at line 10763 of file NUC472_442.h.
| #define EADC_INTSRC3_AD1SPIE0_Msk (0x1ul << EADC_INTSRC3_AD1SPIE0_Pos) |
EADC_T::INTSRC: AD1SPIE0 Mask
Definition at line 10767 of file NUC472_442.h.
| #define EADC_INTSRC3_AD1SPIE0_Pos (8) |
EADC_T::INTSRC: AD1SPIE0 Position
Definition at line 10766 of file NUC472_442.h.
| #define EADC_INTSRC3_AD1SPIE1_Msk (0x1ul << EADC_INTSRC3_AD1SPIE1_Pos) |
EADC_T::INTSRC: AD1SPIE1 Mask
Definition at line 10770 of file NUC472_442.h.
| #define EADC_INTSRC3_AD1SPIE1_Pos (9) |
EADC_T::INTSRC: AD1SPIE1 Position
Definition at line 10769 of file NUC472_442.h.
| #define EADC_INTSRC3_AD1SPIE2_Msk (0x1ul << EADC_INTSRC3_AD1SPIE2_Pos) |
EADC_T::INTSRC: AD1SPIE2 Mask
Definition at line 10773 of file NUC472_442.h.
| #define EADC_INTSRC3_AD1SPIE2_Pos (10) |
EADC_T::INTSRC: AD1SPIE2 Position
Definition at line 10772 of file NUC472_442.h.
| #define EADC_INTSRC3_AD1SPIE3_Msk (0x1ul << EADC_INTSRC3_AD1SPIE3_Pos) |
EADC_T::INTSRC: AD1SPIE3 Mask
Definition at line 10776 of file NUC472_442.h.
| #define EADC_INTSRC3_AD1SPIE3_Pos (11) |
EADC_T::INTSRC: AD1SPIE3 Position
Definition at line 10775 of file NUC472_442.h.
| #define EADC_INTSRC3_AD1SPIE4_Msk (0x1ul << EADC_INTSRC3_AD1SPIE4_Pos) |
EADC_T::INTSRC: AD1SPIE4 Mask
Definition at line 10779 of file NUC472_442.h.
| #define EADC_INTSRC3_AD1SPIE4_Pos (12) |
EADC_T::INTSRC: AD1SPIE4 Position
Definition at line 10778 of file NUC472_442.h.
| #define EADC_INTSRC3_AD1SPIE5_Msk (0x1ul << EADC_INTSRC3_AD1SPIE5_Pos) |
EADC_T::INTSRC: AD1SPIE5 Mask
Definition at line 10782 of file NUC472_442.h.
| #define EADC_INTSRC3_AD1SPIE5_Pos (13) |
EADC_T::INTSRC: AD1SPIE5 Position
Definition at line 10781 of file NUC472_442.h.
| #define EADC_INTSRC3_AD1SPIE6_Msk (0x1ul << EADC_INTSRC3_AD1SPIE6_Pos) |
EADC_T::INTSRC: AD1SPIE6 Mask
Definition at line 10785 of file NUC472_442.h.
| #define EADC_INTSRC3_AD1SPIE6_Pos (14) |
EADC_T::INTSRC: AD1SPIE6 Position
Definition at line 10784 of file NUC472_442.h.
| #define EADC_INTSRC3_AD1SPIE7_Msk (0x1ul << EADC_INTSRC3_AD1SPIE7_Pos) |
EADC_T::INTSRC: AD1SPIE7 Mask
Definition at line 10788 of file NUC472_442.h.
| #define EADC_INTSRC3_AD1SPIE7_Pos (15) |
EADC_T::INTSRC: AD1SPIE7 Position
Definition at line 10787 of file NUC472_442.h.
| #define EADC_OVSTS_SPOVF15_8_Msk (0xfful << EADC_OVSTS_SPOVF15_8_Pos) |
EADC_T::OVSTS: SPOVF15_8 Mask
Definition at line 10164 of file NUC472_442.h.
| #define EADC_OVSTS_SPOVF15_8_Pos (8) |
EADC_T::OVSTS: SPOVF15_8 Position
Definition at line 10163 of file NUC472_442.h.
| #define EADC_OVSTS_SPOVF7_0_Msk (0xfful << EADC_OVSTS_SPOVF7_0_Pos) |
EADC_T::OVSTS: SPOVF7_0 Mask
Definition at line 10161 of file NUC472_442.h.
| #define EADC_OVSTS_SPOVF7_0_Pos (0) |
EADC_T::OVSTS: SPOVF7_0 Position
Definition at line 10160 of file NUC472_442.h.
| #define EADC_PENDSTS_STPF15_8_Msk (0xfful << EADC_PENDSTS_STPF15_8_Pos) |
EADC_T::PENDSTS: STPF15_8 Mask
Definition at line 10146 of file NUC472_442.h.
| #define EADC_PENDSTS_STPF15_8_Pos (8) |
EADC_T::PENDSTS: STPF15_8 Position
Definition at line 10145 of file NUC472_442.h.
| #define EADC_PENDSTS_STPF7_0_Msk (0xfful << EADC_PENDSTS_STPF7_0_Pos) |
EADC_T::PENDSTS: STPF7_0 Mask
Definition at line 10143 of file NUC472_442.h.
| #define EADC_PENDSTS_STPF7_0_Pos (0) |
EADC_T::PENDSTS: STPF7_0 Position
Definition at line 10142 of file NUC472_442.h.
| #define EADC_SIMUSEL_SIMUSEL0_Msk (0x1ul << EADC_SIMUSEL_SIMUSEL0_Pos) |
EADC_T::SIMUSEL: SIMUSEL0 Mask
Definition at line 10407 of file NUC472_442.h.
| #define EADC_SIMUSEL_SIMUSEL0_Pos (0) |
EADC_T::SIMUSEL: SIMUSEL0 Position
Definition at line 10406 of file NUC472_442.h.
| #define EADC_SIMUSEL_SIMUSEL1_Msk (0x1ul << EADC_SIMUSEL_SIMUSEL1_Pos) |
EADC_T::SIMUSEL: SIMUSEL1 Mask
Definition at line 10410 of file NUC472_442.h.
| #define EADC_SIMUSEL_SIMUSEL1_Pos (1) |
EADC_T::SIMUSEL: SIMUSEL1 Position
Definition at line 10409 of file NUC472_442.h.
| #define EADC_SIMUSEL_SIMUSEL2_Msk (0x1ul << EADC_SIMUSEL_SIMUSEL2_Pos) |
EADC_T::SIMUSEL: SIMUSEL2 Mask
Definition at line 10413 of file NUC472_442.h.
| #define EADC_SIMUSEL_SIMUSEL2_Pos (2) |
EADC_T::SIMUSEL: SIMUSEL2 Position
Definition at line 10412 of file NUC472_442.h.
| #define EADC_SIMUSEL_SIMUSEL3_Msk (0x1ul << EADC_SIMUSEL_SIMUSEL3_Pos) |
EADC_T::SIMUSEL: SIMUSEL3 Mask
Definition at line 10416 of file NUC472_442.h.
| #define EADC_SIMUSEL_SIMUSEL3_Pos (3) |
EADC_T::SIMUSEL: SIMUSEL3 Position
Definition at line 10415 of file NUC472_442.h.
| #define EADC_SIMUSEL_SIMUSEL4_Msk (0x1ul << EADC_SIMUSEL_SIMUSEL4_Pos) |
EADC_T::SIMUSEL: SIMUSEL4 Mask
Definition at line 10419 of file NUC472_442.h.
| #define EADC_SIMUSEL_SIMUSEL4_Pos (4) |
EADC_T::SIMUSEL: SIMUSEL4 Position
Definition at line 10418 of file NUC472_442.h.
| #define EADC_SIMUSEL_SIMUSEL5_Msk (0x1ul << EADC_SIMUSEL_SIMUSEL5_Pos) |
EADC_T::SIMUSEL: SIMUSEL5 Mask
Definition at line 10422 of file NUC472_442.h.
| #define EADC_SIMUSEL_SIMUSEL5_Pos (5) |
EADC_T::SIMUSEL: SIMUSEL5 Position
Definition at line 10421 of file NUC472_442.h.
| #define EADC_SIMUSEL_SIMUSEL6_Msk (0x1ul << EADC_SIMUSEL_SIMUSEL6_Pos) |
EADC_T::SIMUSEL: SIMUSEL6 Mask
Definition at line 10425 of file NUC472_442.h.
| #define EADC_SIMUSEL_SIMUSEL6_Pos (6) |
EADC_T::SIMUSEL: SIMUSEL6 Position
Definition at line 10424 of file NUC472_442.h.
| #define EADC_SIMUSEL_SIMUSEL7_Msk (0x1ul << EADC_SIMUSEL_SIMUSEL7_Pos) |
EADC_T::SIMUSEL: SIMUSEL7 Mask
Definition at line 10428 of file NUC472_442.h.
| #define EADC_SIMUSEL_SIMUSEL7_Pos (7) |
EADC_T::SIMUSEL: SIMUSEL7 Position
Definition at line 10427 of file NUC472_442.h.
| #define EADC_STATUS0_OV_Msk (0xfffful << EADC_STATUS0_OV_Pos) |
EADC_T::STATUS0: OV Mask
Definition at line 10470 of file NUC472_442.h.
| #define EADC_STATUS0_OV_Pos (16) |
EADC_T::STATUS0: OV Position
Definition at line 10469 of file NUC472_442.h.
| #define EADC_STATUS0_VALID_Msk (0xfffful << EADC_STATUS0_VALID_Pos) |
EADC_T::STATUS0: VALID Mask
Definition at line 10467 of file NUC472_442.h.
| #define EADC_STATUS0_VALID_Pos (0) |
EADC_T::STATUS0: VALID Position
Definition at line 10466 of file NUC472_442.h.
| #define EADC_STATUS1_ADCMPF0_Msk (0x1ul << EADC_STATUS1_ADCMPF0_Pos) |
EADC_T::STATUS1: ADCMPF0 Mask
Definition at line 10491 of file NUC472_442.h.
| #define EADC_STATUS1_ADCMPF0_Pos (6) |
EADC_T::STATUS1: ADCMPF0 Position
Definition at line 10490 of file NUC472_442.h.
| #define EADC_STATUS1_ADCMPF1_Msk (0x1ul << EADC_STATUS1_ADCMPF1_Pos) |
EADC_T::STATUS1: ADCMPF1 Mask
Definition at line 10494 of file NUC472_442.h.
| #define EADC_STATUS1_ADCMPF1_Pos (7) |
EADC_T::STATUS1: ADCMPF1 Position
Definition at line 10493 of file NUC472_442.h.
| #define EADC_STATUS1_ADCMPO0_Msk (0x1ul << EADC_STATUS1_ADCMPO0_Pos) |
EADC_T::STATUS1: ADCMPO0 Mask
Definition at line 10485 of file NUC472_442.h.
| #define EADC_STATUS1_ADCMPO0_Pos (4) |
EADC_T::STATUS1: ADCMPO0 Position
Definition at line 10484 of file NUC472_442.h.
| #define EADC_STATUS1_ADCMPO1_Msk (0x1ul << EADC_STATUS1_ADCMPO1_Pos) |
EADC_T::STATUS1: ADCMPO1 Mask
Definition at line 10488 of file NUC472_442.h.
| #define EADC_STATUS1_ADCMPO1_Pos (5) |
EADC_T::STATUS1: ADCMPO1 Position
Definition at line 10487 of file NUC472_442.h.
| #define EADC_STATUS1_ADIF0_Msk (0x1ul << EADC_STATUS1_ADIF0_Pos) |
EADC_T::STATUS1: ADIF0 Mask
Definition at line 10473 of file NUC472_442.h.
| #define EADC_STATUS1_ADIF0_Pos (0) |
EADC_T::STATUS1: ADIF0 Position
Definition at line 10472 of file NUC472_442.h.
| #define EADC_STATUS1_ADIF1_Msk (0x1ul << EADC_STATUS1_ADIF1_Pos) |
EADC_T::STATUS1: ADIF1 Mask
Definition at line 10476 of file NUC472_442.h.
| #define EADC_STATUS1_ADIF1_Pos (1) |
EADC_T::STATUS1: ADIF1 Position
Definition at line 10475 of file NUC472_442.h.
| #define EADC_STATUS1_ADIF2_Msk (0x1ul << EADC_STATUS1_ADIF2_Pos) |
EADC_T::STATUS1: ADIF2 Mask
Definition at line 10479 of file NUC472_442.h.
| #define EADC_STATUS1_ADIF2_Pos (2) |
EADC_T::STATUS1: ADIF2 Position
Definition at line 10478 of file NUC472_442.h.
| #define EADC_STATUS1_ADIF3_Msk (0x1ul << EADC_STATUS1_ADIF3_Pos) |
EADC_T::STATUS1: ADIF3 Mask
Definition at line 10482 of file NUC472_442.h.
| #define EADC_STATUS1_ADIF3_Pos (3) |
EADC_T::STATUS1: ADIF3 Position
Definition at line 10481 of file NUC472_442.h.
| #define EADC_STATUS1_ADOVIF_Msk (0x1ul << EADC_STATUS1_ADOVIF_Pos) |
EADC_T::STATUS1: ADOVIF Mask
Definition at line 10509 of file NUC472_442.h.
| #define EADC_STATUS1_ADOVIF_Pos (24) |
EADC_T::STATUS1: ADOVIF Position
Definition at line 10508 of file NUC472_442.h.
| #define EADC_STATUS1_AOV_Msk (0x1ul << EADC_STATUS1_AOV_Pos) |
EADC_T::STATUS1: AOV Mask
Definition at line 10518 of file NUC472_442.h.
| #define EADC_STATUS1_AOV_Pos (27) |
EADC_T::STATUS1: AOV Position
Definition at line 10517 of file NUC472_442.h.
| #define EADC_STATUS1_AVALID_Msk (0x1ul << EADC_STATUS1_AVALID_Pos) |
EADC_T::STATUS1: AVALID Mask
Definition at line 10515 of file NUC472_442.h.
| #define EADC_STATUS1_AVALID_Pos (26) |
EADC_T::STATUS1: AVALID Position
Definition at line 10514 of file NUC472_442.h.
| #define EADC_STATUS1_BUSY0_Msk (0x1ul << EADC_STATUS1_BUSY0_Pos) |
EADC_T::STATUS1: BUSY0 Mask
Definition at line 10497 of file NUC472_442.h.
| #define EADC_STATUS1_BUSY0_Pos (8) |
EADC_T::STATUS1: BUSY0 Position
Definition at line 10496 of file NUC472_442.h.
| #define EADC_STATUS1_BUSY1_Msk (0x1ul << EADC_STATUS1_BUSY1_Pos) |
EADC_T::STATUS1: BUSY1 Mask
Definition at line 10503 of file NUC472_442.h.
| #define EADC_STATUS1_BUSY1_Pos (16) |
EADC_T::STATUS1: BUSY1 Position
Definition at line 10502 of file NUC472_442.h.
| #define EADC_STATUS1_CHANNEL0_Msk (0xful << EADC_STATUS1_CHANNEL0_Pos) |
EADC_T::STATUS1: CHANNEL0 Mask
Definition at line 10500 of file NUC472_442.h.
| #define EADC_STATUS1_CHANNEL0_Pos (12) |
EADC_T::STATUS1: CHANNEL0 Position
Definition at line 10499 of file NUC472_442.h.
| #define EADC_STATUS1_CHANNEL1_Msk (0xful << EADC_STATUS1_CHANNEL1_Pos) |
EADC_T::STATUS1: CHANNEL1 Mask
Definition at line 10506 of file NUC472_442.h.
| #define EADC_STATUS1_CHANNEL1_Pos (20) |
EADC_T::STATUS1: CHANNEL1 Position
Definition at line 10505 of file NUC472_442.h.
| #define EADC_STATUS1_STOVF_Msk (0x1ul << EADC_STATUS1_STOVF_Pos) |
EADC_T::STATUS1: STOVF Mask
Definition at line 10512 of file NUC472_442.h.
| #define EADC_STATUS1_STOVF_Pos (25) |
EADC_T::STATUS1: STOVF Position
Definition at line 10511 of file NUC472_442.h.
| #define EADC_SWTRG_SWTRG15_8_Msk (0xfful << EADC_SWTRG_SWTRG15_8_Pos) |
EADC_T::SWTRG: SWTRG15_8 Mask
Definition at line 10140 of file NUC472_442.h.
| #define EADC_SWTRG_SWTRG15_8_Pos (8) |
EADC_T::SWTRG: SWTRG15_8 Position
Definition at line 10139 of file NUC472_442.h.
| #define EADC_SWTRG_SWTRG7_0_Msk (0xfful << EADC_SWTRG_SWTRG7_0_Pos) |
EADC_T::SWTRG: SWTRG7_0 Mask
Definition at line 10137 of file NUC472_442.h.
| #define EADC_SWTRG_SWTRG7_0_Pos (0) |
EADC_T::SWTRG: SWTRG7_0 Position
Definition at line 10136 of file NUC472_442.h.
| #define EBI_CTL_CRYPTOEN_Msk (0xful << EBI_CTL_CRYPTOEN_Pos) |
EBI_T::CTL: CRYPTOEN Mask
Definition at line 11696 of file NUC472_442.h.
| #define EBI_CTL_CRYPTOEN_Pos (24) |
EBI_T::CTL: CRYPTOEN Position
Definition at line 11695 of file NUC472_442.h.
| #define EBI_CTL_CSPOLINV_Msk (0xful << EBI_CTL_CSPOLINV_Pos) |
EBI_T::CTL: CSPOLINV Mask
Definition at line 11699 of file NUC472_442.h.
| #define EBI_CTL_CSPOLINV_Pos (28) |
EBI_T::CTL: CSPOLINV Position
Definition at line 11698 of file NUC472_442.h.
| #define EBI_CTL_MCLKDIV_Msk (0x7ul << EBI_CTL_MCLKDIV_Pos) |
EBI_T::CTL: MCLKDIV Mask
Definition at line 11693 of file NUC472_442.h.
| #define EBI_CTL_MCLKDIV_Pos (8) |
@addtogroup EBI_CONST EBI Bit Field Definition Constant Definitions for EBI Controller
EBI_T::CTL: MCLKDIV Position
Definition at line 11692 of file NUC472_442.h.
| #define EBI_KEY0_KEY_Msk (0xfffffffful << EBI_KEY0_KEY_Pos) |
EBI_T::KEY0: KEY Mask
Definition at line 11729 of file NUC472_442.h.
| #define EBI_KEY0_KEY_Pos (0) |
EBI_T::KEY0: KEY Position
Definition at line 11728 of file NUC472_442.h.
| #define EBI_KEY1_KEY_Msk (0xfffffffful << EBI_KEY1_KEY_Pos) |
EBI_T::KEY1: KEY Mask
Definition at line 11732 of file NUC472_442.h.
| #define EBI_KEY1_KEY_Pos (0) |
EBI_T::KEY1: KEY Position
Definition at line 11731 of file NUC472_442.h.
| #define EBI_KEY2_KEY_Msk (0xfffffffful << EBI_KEY2_KEY_Pos) |
EBI_T::KEY2: KEY Mask
Definition at line 11735 of file NUC472_442.h.
| #define EBI_KEY2_KEY_Pos (0) |
EBI_T::KEY2: KEY Position
Definition at line 11734 of file NUC472_442.h.
| #define EBI_KEY3_KEY_Msk (0xfffffffful << EBI_KEY3_KEY_Pos) |
EBI_T::KEY3: KEY Mask
Definition at line 11738 of file NUC472_442.h.
| #define EBI_KEY3_KEY_Pos (0) |
EBI_T::KEY3: KEY Position
Definition at line 11737 of file NUC472_442.h.
| #define EBI_TCTL_CSEN_Msk (0x1ul << EBI_TCTL_CSEN_Pos) |
EBI_T::TCTL: CSEN Mask
Definition at line 11720 of file NUC472_442.h.
| #define EBI_TCTL_CSEN_Pos (28) |
EBI_T::TCTL: CSEN Position
Definition at line 11719 of file NUC472_442.h.
| #define EBI_TCTL_DW16_Msk (0x1ul << EBI_TCTL_DW16_Pos) |
EBI_T::TCTL: DW16 Mask
Definition at line 11723 of file NUC472_442.h.
| #define EBI_TCTL_DW16_Pos (29) |
EBI_T::TCTL: DW16 Position
Definition at line 11722 of file NUC472_442.h.
| #define EBI_TCTL_R2R_Msk (0xful << EBI_TCTL_R2R_Pos) |
EBI_T::TCTL: R2R Mask
Definition at line 11717 of file NUC472_442.h.
| #define EBI_TCTL_R2R_Pos (24) |
EBI_T::TCTL: R2R Position
Definition at line 11716 of file NUC472_442.h.
| #define EBI_TCTL_R2W_Msk (0xful << EBI_TCTL_R2W_Pos) |
EBI_T::TCTL: R2W Mask
Definition at line 11714 of file NUC472_442.h.
| #define EBI_TCTL_R2W_Pos (16) |
EBI_T::TCTL: R2W Position
Definition at line 11713 of file NUC472_442.h.
| #define EBI_TCTL_SEPEN_Msk (0x1ul << EBI_TCTL_SEPEN_Pos) |
EBI_T::TCTL: SEPEN Mask
Definition at line 11726 of file NUC472_442.h.
| #define EBI_TCTL_SEPEN_Pos (30) |
EBI_T::TCTL: SEPEN Position
Definition at line 11725 of file NUC472_442.h.
| #define EBI_TCTL_TACC_Msk (0x1ful << EBI_TCTL_TACC_Pos) |
EBI_T::TCTL: TACC Mask
Definition at line 11705 of file NUC472_442.h.
| #define EBI_TCTL_TACC_Pos (3) |
EBI_T::TCTL: TACC Position
Definition at line 11704 of file NUC472_442.h.
| #define EBI_TCTL_TAHD_Msk (0x7ul << EBI_TCTL_TAHD_Pos) |
EBI_T::TCTL: TAHD Mask
Definition at line 11708 of file NUC472_442.h.
| #define EBI_TCTL_TAHD_Pos (8) |
EBI_T::TCTL: TAHD Position
Definition at line 11707 of file NUC472_442.h.
| #define EBI_TCTL_TALE_Msk (0x7ul << EBI_TCTL_TALE_Pos) |
EBI_T::TCTL: TALE Mask
Definition at line 11702 of file NUC472_442.h.
| #define EBI_TCTL_TALE_Pos (0) |
EBI_T::TCTL: TALE Position
Definition at line 11701 of file NUC472_442.h.
| #define EBI_TCTL_W2X_Msk (0xful << EBI_TCTL_W2X_Pos) |
EBI_T::TCTL: W2X Mask
Definition at line 11711 of file NUC472_442.h.
| #define EBI_TCTL_W2X_Pos (12) |
EBI_T::TCTL: W2X Position
Definition at line 11710 of file NUC472_442.h.
| #define ECAP_CNT_VAL_Msk (0xfffffful << ECAP_CNT_VAL_Pos) |
ECAP_T::CNT: VAL Mask
Definition at line 2666 of file NUC472_442.h.
| #define ECAP_CNT_VAL_Pos (0) |
@addtogroup ECAP_CONST ECAP Bit Field Definition Constant Definitions for ECAP Controller
ECAP_T::CNT: VAL Position
Definition at line 2665 of file NUC472_442.h.
| #define ECAP_CNTCMP_VAL_Msk (0xfffffful << ECAP_CNTCMP_VAL_Pos) |
ECAP_T::CNTCMP: VAL Mask
Definition at line 2678 of file NUC472_442.h.
| #define ECAP_CNTCMP_VAL_Pos (0) |
ECAP_T::CNTCMP: VAL Position
Definition at line 2677 of file NUC472_442.h.
| #define ECAP_CTL0_CAPEN0_Msk (0x1ul << ECAP_CTL0_CAPEN0_Pos) |
ECAP_T::CTL0: CAPEN0 Mask
Definition at line 2687 of file NUC472_442.h.
| #define ECAP_CTL0_CAPEN0_Pos (4) |
ECAP_T::CTL0: CAPEN0 Position
Definition at line 2686 of file NUC472_442.h.
| #define ECAP_CTL0_CAPEN1_Msk (0x1ul << ECAP_CTL0_CAPEN1_Pos) |
ECAP_T::CTL0: CAPEN1 Mask
Definition at line 2690 of file NUC472_442.h.
| #define ECAP_CTL0_CAPEN1_Pos (5) |
ECAP_T::CTL0: CAPEN1 Position
Definition at line 2689 of file NUC472_442.h.
| #define ECAP_CTL0_CAPEN2_Msk (0x1ul << ECAP_CTL0_CAPEN2_Pos) |
ECAP_T::CTL0: CAPEN2 Mask
Definition at line 2693 of file NUC472_442.h.
| #define ECAP_CTL0_CAPEN2_Pos (6) |
ECAP_T::CTL0: CAPEN2 Position
Definition at line 2692 of file NUC472_442.h.
| #define ECAP_CTL0_CAPEN_Msk (0x1ul << ECAP_CTL0_CAPEN_Pos) |
ECAP_T::CTL0: CAPEN Mask
Definition at line 2735 of file NUC472_442.h.
| #define ECAP_CTL0_CAPEN_Pos (29) |
ECAP_T::CTL0: CAPEN Position
Definition at line 2734 of file NUC472_442.h.
| #define ECAP_CTL0_CAPIEN0_Msk (0x1ul << ECAP_CTL0_CAPIEN0_Pos) |
ECAP_T::CTL0: CAPIEN0 Mask
Definition at line 2705 of file NUC472_442.h.
| #define ECAP_CTL0_CAPIEN0_Pos (16) |
ECAP_T::CTL0: CAPIEN0 Position
Definition at line 2704 of file NUC472_442.h.
| #define ECAP_CTL0_CAPIEN1_Msk (0x1ul << ECAP_CTL0_CAPIEN1_Pos) |
ECAP_T::CTL0: CAPIEN1 Mask
Definition at line 2708 of file NUC472_442.h.
| #define ECAP_CTL0_CAPIEN1_Pos (17) |
ECAP_T::CTL0: CAPIEN1 Position
Definition at line 2707 of file NUC472_442.h.
| #define ECAP_CTL0_CAPIEN2_Msk (0x1ul << ECAP_CTL0_CAPIEN2_Pos) |
ECAP_T::CTL0: CAPIEN2 Mask
Definition at line 2711 of file NUC472_442.h.
| #define ECAP_CTL0_CAPIEN2_Pos (18) |
ECAP_T::CTL0: CAPIEN2 Position
Definition at line 2710 of file NUC472_442.h.
| #define ECAP_CTL0_CAPNF_DIS_Msk (0x1ul << ECAP_CTL0_CAPNF_DIS_Pos) |
ECAP_T::CTL0: CAPNF_DIS Mask
Definition at line 2684 of file NUC472_442.h.
| #define ECAP_CTL0_CAPNF_DIS_Pos (3) |
ECAP_T::CTL0: CAPNF_DIS Position
Definition at line 2683 of file NUC472_442.h.
| #define ECAP_CTL0_CAPSEL0_Msk (0x3ul << ECAP_CTL0_CAPSEL0_Pos) |
ECAP_T::CTL0: CAPSEL0 Mask
Definition at line 2696 of file NUC472_442.h.
| #define ECAP_CTL0_CAPSEL0_Pos (8) |
ECAP_T::CTL0: CAPSEL0 Position
Definition at line 2695 of file NUC472_442.h.
| #define ECAP_CTL0_CAPSEL1_Msk (0x3ul << ECAP_CTL0_CAPSEL1_Pos) |
ECAP_T::CTL0: CAPSEL1 Mask
Definition at line 2699 of file NUC472_442.h.
| #define ECAP_CTL0_CAPSEL1_Pos (10) |
ECAP_T::CTL0: CAPSEL1 Position
Definition at line 2698 of file NUC472_442.h.
| #define ECAP_CTL0_CAPSEL2_Msk (0x3ul << ECAP_CTL0_CAPSEL2_Pos) |
ECAP_T::CTL0: CAPSEL2 Mask
Definition at line 2702 of file NUC472_442.h.
| #define ECAP_CTL0_CAPSEL2_Pos (12) |
ECAP_T::CTL0: CAPSEL2 Position
Definition at line 2701 of file NUC472_442.h.
| #define ECAP_CTL0_CMPCLR_Msk (0x1ul << ECAP_CTL0_CMPCLR_Pos) |
ECAP_T::CTL0: CMPCLR Mask
Definition at line 2723 of file NUC472_442.h.
| #define ECAP_CTL0_CMPCLR_Pos (25) |
ECAP_T::CTL0: CMPCLR Position
Definition at line 2722 of file NUC472_442.h.
| #define ECAP_CTL0_CMPEN_Msk (0x1ul << ECAP_CTL0_CMPEN_Pos) |
ECAP_T::CTL0: CMPEN Mask
Definition at line 2732 of file NUC472_442.h.
| #define ECAP_CTL0_CMPEN_Pos (28) |
ECAP_T::CTL0: CMPEN Position
Definition at line 2731 of file NUC472_442.h.
| #define ECAP_CTL0_CMPIEN_Msk (0x1ul << ECAP_CTL0_CMPIEN_Pos) |
ECAP_T::CTL0: CMPIEN Mask
Definition at line 2717 of file NUC472_442.h.
| #define ECAP_CTL0_CMPIEN_Pos (21) |
ECAP_T::CTL0: CMPIEN Position
Definition at line 2716 of file NUC472_442.h.
| #define ECAP_CTL0_CNTEN_Msk (0x1ul << ECAP_CTL0_CNTEN_Pos) |
ECAP_T::CTL0: CNTEN Mask
Definition at line 2720 of file NUC472_442.h.
| #define ECAP_CTL0_CNTEN_Pos (24) |
ECAP_T::CTL0: CNTEN Position
Definition at line 2719 of file NUC472_442.h.
| #define ECAP_CTL0_CPTCLR_Msk (0x1ul << ECAP_CTL0_CPTCLR_Pos) |
ECAP_T::CTL0: CPTCLR Mask
Definition at line 2726 of file NUC472_442.h.
| #define ECAP_CTL0_CPTCLR_Pos (26) |
ECAP_T::CTL0: CPTCLR Position
Definition at line 2725 of file NUC472_442.h.
| #define ECAP_CTL0_NFDIS_Msk (0x3ul << ECAP_CTL0_NFDIS_Pos) |
ECAP_T::CTL0: NFDIS Mask
Definition at line 2681 of file NUC472_442.h.
| #define ECAP_CTL0_NFDIS_Pos (0) |
ECAP_T::CTL0: NFDIS Position
Definition at line 2680 of file NUC472_442.h.
| #define ECAP_CTL0_OVIEN_Msk (0x1ul << ECAP_CTL0_OVIEN_Pos) |
ECAP_T::CTL0: OVIEN Mask
Definition at line 2714 of file NUC472_442.h.
| #define ECAP_CTL0_OVIEN_Pos (20) |
ECAP_T::CTL0: OVIEN Position
Definition at line 2713 of file NUC472_442.h.
| #define ECAP_CTL0_RLDEN_Msk (0x1ul << ECAP_CTL0_RLDEN_Pos) |
ECAP_T::CTL0: RLDEN Mask
Definition at line 2729 of file NUC472_442.h.
| #define ECAP_CTL0_RLDEN_Pos (27) |
ECAP_T::CTL0: RLDEN Position
Definition at line 2728 of file NUC472_442.h.
| #define ECAP_CTL1_CLKSEL_Msk (0x7ul << ECAP_CTL1_CLKSEL_Pos) |
ECAP_T::CTL1: CLKSEL Mask
Definition at line 2750 of file NUC472_442.h.
| #define ECAP_CTL1_CLKSEL_Pos (12) |
ECAP_T::CTL1: CLKSEL Position
Definition at line 2749 of file NUC472_442.h.
| #define ECAP_CTL1_EDGESEL0_Msk (0x3ul << ECAP_CTL1_EDGESEL0_Pos) |
ECAP_T::CTL1: EDGESEL0 Mask
Definition at line 2738 of file NUC472_442.h.
| #define ECAP_CTL1_EDGESEL0_Pos (0) |
ECAP_T::CTL1: EDGESEL0 Position
Definition at line 2737 of file NUC472_442.h.
| #define ECAP_CTL1_EDGESEL1_Msk (0x3ul << ECAP_CTL1_EDGESEL1_Pos) |
ECAP_T::CTL1: EDGESEL1 Mask
Definition at line 2741 of file NUC472_442.h.
| #define ECAP_CTL1_EDGESEL1_Pos (2) |
ECAP_T::CTL1: EDGESEL1 Position
Definition at line 2740 of file NUC472_442.h.
| #define ECAP_CTL1_EDGESEL2_Msk (0x3ul << ECAP_CTL1_EDGESEL2_Pos) |
ECAP_T::CTL1: EDGESEL2 Mask
Definition at line 2744 of file NUC472_442.h.
| #define ECAP_CTL1_EDGESEL2_Pos (4) |
ECAP_T::CTL1: EDGESEL2 Position
Definition at line 2743 of file NUC472_442.h.
| #define ECAP_CTL1_RLDSEL_Msk (0x7ul << ECAP_CTL1_RLDSEL_Pos) |
ECAP_T::CTL1: RLDSEL Mask
Definition at line 2747 of file NUC472_442.h.
| #define ECAP_CTL1_RLDSEL_Pos (8) |
ECAP_T::CTL1: RLDSEL Position
Definition at line 2746 of file NUC472_442.h.
| #define ECAP_CTL1_SRCSEL_Msk (0x3ul << ECAP_CTL1_SRCSEL_Pos) |
ECAP_T::CTL1: SRCSEL Mask
Definition at line 2753 of file NUC472_442.h.
| #define ECAP_CTL1_SRCSEL_Pos (16) |
ECAP_T::CTL1: SRCSEL Position
Definition at line 2752 of file NUC472_442.h.
| #define ECAP_HOLD0_VAL_Msk (0xfffffful << ECAP_HOLD0_VAL_Pos) |
ECAP_T::HOLD0: VAL Mask
Definition at line 2669 of file NUC472_442.h.
| #define ECAP_HOLD0_VAL_Pos (0) |
ECAP_T::HOLD0: VAL Position
Definition at line 2668 of file NUC472_442.h.
| #define ECAP_HOLD1_VAL_Msk (0xfffffful << ECAP_HOLD1_VAL_Pos) |
ECAP_T::HOLD1: VAL Mask
Definition at line 2672 of file NUC472_442.h.
| #define ECAP_HOLD1_VAL_Pos (0) |
ECAP_T::HOLD1: VAL Position
Definition at line 2671 of file NUC472_442.h.
| #define ECAP_HOLD2_VAL_Msk (0xfffffful << ECAP_HOLD2_VAL_Pos) |
ECAP_T::HOLD2: VAL Mask
Definition at line 2675 of file NUC472_442.h.
| #define ECAP_HOLD2_VAL_Pos (0) |
ECAP_T::HOLD2: VAL Position
Definition at line 2674 of file NUC472_442.h.
| #define ECAP_STATUS_CAPF0_Msk (0x1ul << ECAP_STATUS_CAPF0_Pos) |
ECAP_T::STATUS: CAPF0 Mask
Definition at line 2756 of file NUC472_442.h.
| #define ECAP_STATUS_CAPF0_Pos (0) |
ECAP_T::STATUS: CAPF0 Position
Definition at line 2755 of file NUC472_442.h.
| #define ECAP_STATUS_CAPF1_Msk (0x1ul << ECAP_STATUS_CAPF1_Pos) |
ECAP_T::STATUS: CAPF1 Mask
Definition at line 2759 of file NUC472_442.h.
| #define ECAP_STATUS_CAPF1_Pos (1) |
ECAP_T::STATUS: CAPF1 Position
Definition at line 2758 of file NUC472_442.h.
| #define ECAP_STATUS_CAPF2_Msk (0x1ul << ECAP_STATUS_CAPF2_Pos) |
ECAP_T::STATUS: CAPF2 Mask
Definition at line 2762 of file NUC472_442.h.
| #define ECAP_STATUS_CAPF2_Pos (2) |
ECAP_T::STATUS: CAPF2 Position
Definition at line 2761 of file NUC472_442.h.
| #define ECAP_STATUS_CMPF_Msk (0x1ul << ECAP_STATUS_CMPF_Pos) |
ECAP_T::STATUS: CMPF Mask
Definition at line 2765 of file NUC472_442.h.
| #define ECAP_STATUS_CMPF_Pos (4) |
ECAP_T::STATUS: CMPF Position
Definition at line 2764 of file NUC472_442.h.
| #define ECAP_STATUS_OVF_Msk (0x1ul << ECAP_STATUS_OVF_Pos) |
ECAP_T::STATUS: OVF Mask
Definition at line 2768 of file NUC472_442.h.
| #define ECAP_STATUS_OVF_Pos (5) |
ECAP_T::STATUS: OVF Position
Definition at line 2767 of file NUC472_442.h.
| #define EMAC_ALMSEC_SEC_Msk (0xfffffffful << EMAC_ALMSEC_SEC_Pos) |
EMAC_T::ALMSEC: SEC Mask
Definition at line 13916 of file NUC472_442.h.
| #define EMAC_ALMSEC_SEC_Pos (0) |
EMAC_T::ALMSEC: SEC Position
Definition at line 13915 of file NUC472_442.h.
| #define EMAC_ALMSUBSEC_SUBSEC_Msk (0xfffffffful << EMAC_ALMSUBSEC_SUBSEC_Pos) |
EMAC_T::ALMSUBSEC: SUBSEC Mask
Definition at line 13919 of file NUC472_442.h.
| #define EMAC_ALMSUBSEC_SUBSEC_Pos (0) |
EMAC_T::ALMSUBSEC: SUBSEC Position
Definition at line 13918 of file NUC472_442.h.
| #define EMAC_CAM0L_MACADDR0_Msk (0xfful << EMAC_CAM0L_MACADDR0_Pos) |
EMAC_T::CAM0L: MACADDR0 Mask
Definition at line 13289 of file NUC472_442.h.
| #define EMAC_CAM0L_MACADDR0_Pos (16) |
EMAC_T::CAM0L: MACADDR0 Position
Definition at line 13288 of file NUC472_442.h.
| #define EMAC_CAM0L_MACADDR1_Msk (0xfful << EMAC_CAM0L_MACADDR1_Pos) |
EMAC_T::CAM0L: MACADDR1 Mask
Definition at line 13292 of file NUC472_442.h.
| #define EMAC_CAM0L_MACADDR1_Pos (24) |
EMAC_T::CAM0L: MACADDR1 Position
Definition at line 13291 of file NUC472_442.h.
| #define EMAC_CAM0L_Rserved_Msk (0xfffful << EMAC_CAM0L_Rserved_Pos) |
EMAC_T::CAM0L: Rserved Mask
Definition at line 13286 of file NUC472_442.h.
| #define EMAC_CAM0L_Rserved_Pos (0) |
EMAC_T::CAM0L: Rserved Position
Definition at line 13285 of file NUC472_442.h.
| #define EMAC_CAM0M_MACADDR2_Msk (0xfful << EMAC_CAM0M_MACADDR2_Pos) |
EMAC_T::CAM0M: MACADDR2 Mask
Definition at line 13274 of file NUC472_442.h.
| #define EMAC_CAM0M_MACADDR2_Pos (0) |
EMAC_T::CAM0M: MACADDR2 Position
Definition at line 13273 of file NUC472_442.h.
| #define EMAC_CAM0M_MACADDR3_Msk (0xfful << EMAC_CAM0M_MACADDR3_Pos) |
EMAC_T::CAM0M: MACADDR3 Mask
Definition at line 13277 of file NUC472_442.h.
| #define EMAC_CAM0M_MACADDR3_Pos (8) |
EMAC_T::CAM0M: MACADDR3 Position
Definition at line 13276 of file NUC472_442.h.
| #define EMAC_CAM0M_MACADDR4_Msk (0xfful << EMAC_CAM0M_MACADDR4_Pos) |
EMAC_T::CAM0M: MACADDR4 Mask
Definition at line 13280 of file NUC472_442.h.
| #define EMAC_CAM0M_MACADDR4_Pos (16) |
EMAC_T::CAM0M: MACADDR4 Position
Definition at line 13279 of file NUC472_442.h.
| #define EMAC_CAM0M_MACADDR5_Msk (0xfful << EMAC_CAM0M_MACADDR5_Pos) |
EMAC_T::CAM0M: MACADDR5 Mask
Definition at line 13283 of file NUC472_442.h.
| #define EMAC_CAM0M_MACADDR5_Pos (24) |
EMAC_T::CAM0M: MACADDR5 Position
Definition at line 13282 of file NUC472_442.h.
| #define EMAC_CAM10L_MACADDR0_Msk (0xfful << EMAC_CAM10L_MACADDR0_Pos) |
EMAC_T::CAM10L: MACADDR0 Mask
Definition at line 13499 of file NUC472_442.h.
| #define EMAC_CAM10L_MACADDR0_Pos (16) |
EMAC_T::CAM10L: MACADDR0 Position
Definition at line 13498 of file NUC472_442.h.
| #define EMAC_CAM10L_MACADDR1_Msk (0xfful << EMAC_CAM10L_MACADDR1_Pos) |
EMAC_T::CAM10L: MACADDR1 Mask
Definition at line 13502 of file NUC472_442.h.
| #define EMAC_CAM10L_MACADDR1_Pos (24) |
EMAC_T::CAM10L: MACADDR1 Position
Definition at line 13501 of file NUC472_442.h.
| #define EMAC_CAM10L_Rserved_Msk (0xfffful << EMAC_CAM10L_Rserved_Pos) |
EMAC_T::CAM10L: Rserved Mask
Definition at line 13496 of file NUC472_442.h.
| #define EMAC_CAM10L_Rserved_Pos (0) |
EMAC_T::CAM10L: Rserved Position
Definition at line 13495 of file NUC472_442.h.
| #define EMAC_CAM10M_MACADDR2_Msk (0xfful << EMAC_CAM10M_MACADDR2_Pos) |
EMAC_T::CAM10M: MACADDR2 Mask
Definition at line 13484 of file NUC472_442.h.
| #define EMAC_CAM10M_MACADDR2_Pos (0) |
EMAC_T::CAM10M: MACADDR2 Position
Definition at line 13483 of file NUC472_442.h.
| #define EMAC_CAM10M_MACADDR3_Msk (0xfful << EMAC_CAM10M_MACADDR3_Pos) |
EMAC_T::CAM10M: MACADDR3 Mask
Definition at line 13487 of file NUC472_442.h.
| #define EMAC_CAM10M_MACADDR3_Pos (8) |
EMAC_T::CAM10M: MACADDR3 Position
Definition at line 13486 of file NUC472_442.h.
| #define EMAC_CAM10M_MACADDR4_Msk (0xfful << EMAC_CAM10M_MACADDR4_Pos) |
EMAC_T::CAM10M: MACADDR4 Mask
Definition at line 13490 of file NUC472_442.h.
| #define EMAC_CAM10M_MACADDR4_Pos (16) |
EMAC_T::CAM10M: MACADDR4 Position
Definition at line 13489 of file NUC472_442.h.
| #define EMAC_CAM10M_MACADDR5_Msk (0xfful << EMAC_CAM10M_MACADDR5_Pos) |
EMAC_T::CAM10M: MACADDR5 Mask
Definition at line 13493 of file NUC472_442.h.
| #define EMAC_CAM10M_MACADDR5_Pos (24) |
EMAC_T::CAM10M: MACADDR5 Position
Definition at line 13492 of file NUC472_442.h.
| #define EMAC_CAM11L_MACADDR0_Msk (0xfful << EMAC_CAM11L_MACADDR0_Pos) |
EMAC_T::CAM11L: MACADDR0 Mask
Definition at line 13520 of file NUC472_442.h.
| #define EMAC_CAM11L_MACADDR0_Pos (16) |
EMAC_T::CAM11L: MACADDR0 Position
Definition at line 13519 of file NUC472_442.h.
| #define EMAC_CAM11L_MACADDR1_Msk (0xfful << EMAC_CAM11L_MACADDR1_Pos) |
EMAC_T::CAM11L: MACADDR1 Mask
Definition at line 13523 of file NUC472_442.h.
| #define EMAC_CAM11L_MACADDR1_Pos (24) |
EMAC_T::CAM11L: MACADDR1 Position
Definition at line 13522 of file NUC472_442.h.
| #define EMAC_CAM11L_Rserved_Msk (0xfffful << EMAC_CAM11L_Rserved_Pos) |
EMAC_T::CAM11L: Rserved Mask
Definition at line 13517 of file NUC472_442.h.
| #define EMAC_CAM11L_Rserved_Pos (0) |
EMAC_T::CAM11L: Rserved Position
Definition at line 13516 of file NUC472_442.h.
| #define EMAC_CAM11M_MACADDR2_Msk (0xfful << EMAC_CAM11M_MACADDR2_Pos) |
EMAC_T::CAM11M: MACADDR2 Mask
Definition at line 13505 of file NUC472_442.h.
| #define EMAC_CAM11M_MACADDR2_Pos (0) |
EMAC_T::CAM11M: MACADDR2 Position
Definition at line 13504 of file NUC472_442.h.
| #define EMAC_CAM11M_MACADDR3_Msk (0xfful << EMAC_CAM11M_MACADDR3_Pos) |
EMAC_T::CAM11M: MACADDR3 Mask
Definition at line 13508 of file NUC472_442.h.
| #define EMAC_CAM11M_MACADDR3_Pos (8) |
EMAC_T::CAM11M: MACADDR3 Position
Definition at line 13507 of file NUC472_442.h.
| #define EMAC_CAM11M_MACADDR4_Msk (0xfful << EMAC_CAM11M_MACADDR4_Pos) |
EMAC_T::CAM11M: MACADDR4 Mask
Definition at line 13511 of file NUC472_442.h.
| #define EMAC_CAM11M_MACADDR4_Pos (16) |
EMAC_T::CAM11M: MACADDR4 Position
Definition at line 13510 of file NUC472_442.h.
| #define EMAC_CAM11M_MACADDR5_Msk (0xfful << EMAC_CAM11M_MACADDR5_Pos) |
EMAC_T::CAM11M: MACADDR5 Mask
Definition at line 13514 of file NUC472_442.h.
| #define EMAC_CAM11M_MACADDR5_Pos (24) |
EMAC_T::CAM11M: MACADDR5 Position
Definition at line 13513 of file NUC472_442.h.
| #define EMAC_CAM12L_MACADDR0_Msk (0xfful << EMAC_CAM12L_MACADDR0_Pos) |
EMAC_T::CAM12L: MACADDR0 Mask
Definition at line 13541 of file NUC472_442.h.
| #define EMAC_CAM12L_MACADDR0_Pos (16) |
EMAC_T::CAM12L: MACADDR0 Position
Definition at line 13540 of file NUC472_442.h.
| #define EMAC_CAM12L_MACADDR1_Msk (0xfful << EMAC_CAM12L_MACADDR1_Pos) |
EMAC_T::CAM12L: MACADDR1 Mask
Definition at line 13544 of file NUC472_442.h.
| #define EMAC_CAM12L_MACADDR1_Pos (24) |
EMAC_T::CAM12L: MACADDR1 Position
Definition at line 13543 of file NUC472_442.h.
| #define EMAC_CAM12L_Rserved_Msk (0xfffful << EMAC_CAM12L_Rserved_Pos) |
EMAC_T::CAM12L: Rserved Mask
Definition at line 13538 of file NUC472_442.h.
| #define EMAC_CAM12L_Rserved_Pos (0) |
EMAC_T::CAM12L: Rserved Position
Definition at line 13537 of file NUC472_442.h.
| #define EMAC_CAM12M_MACADDR2_Msk (0xfful << EMAC_CAM12M_MACADDR2_Pos) |
EMAC_T::CAM12M: MACADDR2 Mask
Definition at line 13526 of file NUC472_442.h.
| #define EMAC_CAM12M_MACADDR2_Pos (0) |
EMAC_T::CAM12M: MACADDR2 Position
Definition at line 13525 of file NUC472_442.h.
| #define EMAC_CAM12M_MACADDR3_Msk (0xfful << EMAC_CAM12M_MACADDR3_Pos) |
EMAC_T::CAM12M: MACADDR3 Mask
Definition at line 13529 of file NUC472_442.h.
| #define EMAC_CAM12M_MACADDR3_Pos (8) |
EMAC_T::CAM12M: MACADDR3 Position
Definition at line 13528 of file NUC472_442.h.
| #define EMAC_CAM12M_MACADDR4_Msk (0xfful << EMAC_CAM12M_MACADDR4_Pos) |
EMAC_T::CAM12M: MACADDR4 Mask
Definition at line 13532 of file NUC472_442.h.
| #define EMAC_CAM12M_MACADDR4_Pos (16) |
EMAC_T::CAM12M: MACADDR4 Position
Definition at line 13531 of file NUC472_442.h.
| #define EMAC_CAM12M_MACADDR5_Msk (0xfful << EMAC_CAM12M_MACADDR5_Pos) |
EMAC_T::CAM12M: MACADDR5 Mask
Definition at line 13535 of file NUC472_442.h.
| #define EMAC_CAM12M_MACADDR5_Pos (24) |
EMAC_T::CAM12M: MACADDR5 Position
Definition at line 13534 of file NUC472_442.h.
| #define EMAC_CAM13L_MACADDR0_Msk (0xfful << EMAC_CAM13L_MACADDR0_Pos) |
EMAC_T::CAM13L: MACADDR0 Mask
Definition at line 13562 of file NUC472_442.h.
| #define EMAC_CAM13L_MACADDR0_Pos (16) |
EMAC_T::CAM13L: MACADDR0 Position
Definition at line 13561 of file NUC472_442.h.
| #define EMAC_CAM13L_MACADDR1_Msk (0xfful << EMAC_CAM13L_MACADDR1_Pos) |
EMAC_T::CAM13L: MACADDR1 Mask
Definition at line 13565 of file NUC472_442.h.
| #define EMAC_CAM13L_MACADDR1_Pos (24) |
EMAC_T::CAM13L: MACADDR1 Position
Definition at line 13564 of file NUC472_442.h.
| #define EMAC_CAM13L_Rserved_Msk (0xfffful << EMAC_CAM13L_Rserved_Pos) |
EMAC_T::CAM13L: Rserved Mask
Definition at line 13559 of file NUC472_442.h.
| #define EMAC_CAM13L_Rserved_Pos (0) |
EMAC_T::CAM13L: Rserved Position
Definition at line 13558 of file NUC472_442.h.
| #define EMAC_CAM13M_MACADDR2_Msk (0xfful << EMAC_CAM13M_MACADDR2_Pos) |
EMAC_T::CAM13M: MACADDR2 Mask
Definition at line 13547 of file NUC472_442.h.
| #define EMAC_CAM13M_MACADDR2_Pos (0) |
EMAC_T::CAM13M: MACADDR2 Position
Definition at line 13546 of file NUC472_442.h.
| #define EMAC_CAM13M_MACADDR3_Msk (0xfful << EMAC_CAM13M_MACADDR3_Pos) |
EMAC_T::CAM13M: MACADDR3 Mask
Definition at line 13550 of file NUC472_442.h.
| #define EMAC_CAM13M_MACADDR3_Pos (8) |
EMAC_T::CAM13M: MACADDR3 Position
Definition at line 13549 of file NUC472_442.h.
| #define EMAC_CAM13M_MACADDR4_Msk (0xfful << EMAC_CAM13M_MACADDR4_Pos) |
EMAC_T::CAM13M: MACADDR4 Mask
Definition at line 13553 of file NUC472_442.h.
| #define EMAC_CAM13M_MACADDR4_Pos (16) |
EMAC_T::CAM13M: MACADDR4 Position
Definition at line 13552 of file NUC472_442.h.
| #define EMAC_CAM13M_MACADDR5_Msk (0xfful << EMAC_CAM13M_MACADDR5_Pos) |
EMAC_T::CAM13M: MACADDR5 Mask
Definition at line 13556 of file NUC472_442.h.
| #define EMAC_CAM13M_MACADDR5_Pos (24) |
EMAC_T::CAM13M: MACADDR5 Position
Definition at line 13555 of file NUC472_442.h.
| #define EMAC_CAM14L_MACADDR0_Msk (0xfful << EMAC_CAM14L_MACADDR0_Pos) |
EMAC_T::CAM14L: MACADDR0 Mask
Definition at line 13583 of file NUC472_442.h.
| #define EMAC_CAM14L_MACADDR0_Pos (16) |
EMAC_T::CAM14L: MACADDR0 Position
Definition at line 13582 of file NUC472_442.h.
| #define EMAC_CAM14L_MACADDR1_Msk (0xfful << EMAC_CAM14L_MACADDR1_Pos) |
EMAC_T::CAM14L: MACADDR1 Mask
Definition at line 13586 of file NUC472_442.h.
| #define EMAC_CAM14L_MACADDR1_Pos (24) |
EMAC_T::CAM14L: MACADDR1 Position
Definition at line 13585 of file NUC472_442.h.
| #define EMAC_CAM14L_Rserved_Msk (0xfffful << EMAC_CAM14L_Rserved_Pos) |
EMAC_T::CAM14L: Rserved Mask
Definition at line 13580 of file NUC472_442.h.
| #define EMAC_CAM14L_Rserved_Pos (0) |
EMAC_T::CAM14L: Rserved Position
Definition at line 13579 of file NUC472_442.h.
| #define EMAC_CAM14M_MACADDR2_Msk (0xfful << EMAC_CAM14M_MACADDR2_Pos) |
EMAC_T::CAM14M: MACADDR2 Mask
Definition at line 13568 of file NUC472_442.h.
| #define EMAC_CAM14M_MACADDR2_Pos (0) |
EMAC_T::CAM14M: MACADDR2 Position
Definition at line 13567 of file NUC472_442.h.
| #define EMAC_CAM14M_MACADDR3_Msk (0xfful << EMAC_CAM14M_MACADDR3_Pos) |
EMAC_T::CAM14M: MACADDR3 Mask
Definition at line 13571 of file NUC472_442.h.
| #define EMAC_CAM14M_MACADDR3_Pos (8) |
EMAC_T::CAM14M: MACADDR3 Position
Definition at line 13570 of file NUC472_442.h.
| #define EMAC_CAM14M_MACADDR4_Msk (0xfful << EMAC_CAM14M_MACADDR4_Pos) |
EMAC_T::CAM14M: MACADDR4 Mask
Definition at line 13574 of file NUC472_442.h.
| #define EMAC_CAM14M_MACADDR4_Pos (16) |
EMAC_T::CAM14M: MACADDR4 Position
Definition at line 13573 of file NUC472_442.h.
| #define EMAC_CAM14M_MACADDR5_Msk (0xfful << EMAC_CAM14M_MACADDR5_Pos) |
EMAC_T::CAM14M: MACADDR5 Mask
Definition at line 13577 of file NUC472_442.h.
| #define EMAC_CAM14M_MACADDR5_Pos (24) |
EMAC_T::CAM14M: MACADDR5 Position
Definition at line 13576 of file NUC472_442.h.
| #define EMAC_CAM15LSB_OPERAND_Msk (0xfful << EMAC_CAM15LSB_OPERAND_Pos) |
EMAC_T::CAM15LSB: OPERAND Mask
Definition at line 13595 of file NUC472_442.h.
| #define EMAC_CAM15LSB_OPERAND_Pos (24) |
EMAC_T::CAM15LSB: OPERAND Position
Definition at line 13594 of file NUC472_442.h.
| #define EMAC_CAM15MSB_LENGTH_Msk (0xfffful << EMAC_CAM15MSB_LENGTH_Pos) |
EMAC_T::CAM15MSB: LENGTH Mask
Definition at line 13592 of file NUC472_442.h.
| #define EMAC_CAM15MSB_LENGTH_Pos (16) |
EMAC_T::CAM15MSB: LENGTH Position
Definition at line 13591 of file NUC472_442.h.
| #define EMAC_CAM15MSB_OPCODE_Msk (0xfffful << EMAC_CAM15MSB_OPCODE_Pos) |
EMAC_T::CAM15MSB: OPCODE Mask
Definition at line 13589 of file NUC472_442.h.
| #define EMAC_CAM15MSB_OPCODE_Pos (0) |
EMAC_T::CAM15MSB: OPCODE Position
Definition at line 13588 of file NUC472_442.h.
| #define EMAC_CAM1L_MACADDR0_Msk (0xfful << EMAC_CAM1L_MACADDR0_Pos) |
EMAC_T::CAM1L: MACADDR0 Mask
Definition at line 13310 of file NUC472_442.h.
| #define EMAC_CAM1L_MACADDR0_Pos (16) |
EMAC_T::CAM1L: MACADDR0 Position
Definition at line 13309 of file NUC472_442.h.
| #define EMAC_CAM1L_MACADDR1_Msk (0xfful << EMAC_CAM1L_MACADDR1_Pos) |
EMAC_T::CAM1L: MACADDR1 Mask
Definition at line 13313 of file NUC472_442.h.
| #define EMAC_CAM1L_MACADDR1_Pos (24) |
EMAC_T::CAM1L: MACADDR1 Position
Definition at line 13312 of file NUC472_442.h.
| #define EMAC_CAM1L_Rserved_Msk (0xfffful << EMAC_CAM1L_Rserved_Pos) |
EMAC_T::CAM1L: Rserved Mask
Definition at line 13307 of file NUC472_442.h.
| #define EMAC_CAM1L_Rserved_Pos (0) |
EMAC_T::CAM1L: Rserved Position
Definition at line 13306 of file NUC472_442.h.
| #define EMAC_CAM1M_MACADDR2_Msk (0xfful << EMAC_CAM1M_MACADDR2_Pos) |
EMAC_T::CAM1M: MACADDR2 Mask
Definition at line 13295 of file NUC472_442.h.
| #define EMAC_CAM1M_MACADDR2_Pos (0) |
EMAC_T::CAM1M: MACADDR2 Position
Definition at line 13294 of file NUC472_442.h.
| #define EMAC_CAM1M_MACADDR3_Msk (0xfful << EMAC_CAM1M_MACADDR3_Pos) |
EMAC_T::CAM1M: MACADDR3 Mask
Definition at line 13298 of file NUC472_442.h.
| #define EMAC_CAM1M_MACADDR3_Pos (8) |
EMAC_T::CAM1M: MACADDR3 Position
Definition at line 13297 of file NUC472_442.h.
| #define EMAC_CAM1M_MACADDR4_Msk (0xfful << EMAC_CAM1M_MACADDR4_Pos) |
EMAC_T::CAM1M: MACADDR4 Mask
Definition at line 13301 of file NUC472_442.h.
| #define EMAC_CAM1M_MACADDR4_Pos (16) |
EMAC_T::CAM1M: MACADDR4 Position
Definition at line 13300 of file NUC472_442.h.
| #define EMAC_CAM1M_MACADDR5_Msk (0xfful << EMAC_CAM1M_MACADDR5_Pos) |
EMAC_T::CAM1M: MACADDR5 Mask
Definition at line 13304 of file NUC472_442.h.
| #define EMAC_CAM1M_MACADDR5_Pos (24) |
EMAC_T::CAM1M: MACADDR5 Position
Definition at line 13303 of file NUC472_442.h.
| #define EMAC_CAM2L_MACADDR0_Msk (0xfful << EMAC_CAM2L_MACADDR0_Pos) |
EMAC_T::CAM2L: MACADDR0 Mask
Definition at line 13331 of file NUC472_442.h.
| #define EMAC_CAM2L_MACADDR0_Pos (16) |
EMAC_T::CAM2L: MACADDR0 Position
Definition at line 13330 of file NUC472_442.h.
| #define EMAC_CAM2L_MACADDR1_Msk (0xfful << EMAC_CAM2L_MACADDR1_Pos) |
EMAC_T::CAM2L: MACADDR1 Mask
Definition at line 13334 of file NUC472_442.h.
| #define EMAC_CAM2L_MACADDR1_Pos (24) |
EMAC_T::CAM2L: MACADDR1 Position
Definition at line 13333 of file NUC472_442.h.
| #define EMAC_CAM2L_Rserved_Msk (0xfffful << EMAC_CAM2L_Rserved_Pos) |
EMAC_T::CAM2L: Rserved Mask
Definition at line 13328 of file NUC472_442.h.
| #define EMAC_CAM2L_Rserved_Pos (0) |
EMAC_T::CAM2L: Rserved Position
Definition at line 13327 of file NUC472_442.h.
| #define EMAC_CAM2M_MACADDR2_Msk (0xfful << EMAC_CAM2M_MACADDR2_Pos) |
EMAC_T::CAM2M: MACADDR2 Mask
Definition at line 13316 of file NUC472_442.h.
| #define EMAC_CAM2M_MACADDR2_Pos (0) |
EMAC_T::CAM2M: MACADDR2 Position
Definition at line 13315 of file NUC472_442.h.
| #define EMAC_CAM2M_MACADDR3_Msk (0xfful << EMAC_CAM2M_MACADDR3_Pos) |
EMAC_T::CAM2M: MACADDR3 Mask
Definition at line 13319 of file NUC472_442.h.
| #define EMAC_CAM2M_MACADDR3_Pos (8) |
EMAC_T::CAM2M: MACADDR3 Position
Definition at line 13318 of file NUC472_442.h.
| #define EMAC_CAM2M_MACADDR4_Msk (0xfful << EMAC_CAM2M_MACADDR4_Pos) |
EMAC_T::CAM2M: MACADDR4 Mask
Definition at line 13322 of file NUC472_442.h.
| #define EMAC_CAM2M_MACADDR4_Pos (16) |
EMAC_T::CAM2M: MACADDR4 Position
Definition at line 13321 of file NUC472_442.h.
| #define EMAC_CAM2M_MACADDR5_Msk (0xfful << EMAC_CAM2M_MACADDR5_Pos) |
EMAC_T::CAM2M: MACADDR5 Mask
Definition at line 13325 of file NUC472_442.h.
| #define EMAC_CAM2M_MACADDR5_Pos (24) |
EMAC_T::CAM2M: MACADDR5 Position
Definition at line 13324 of file NUC472_442.h.
| #define EMAC_CAM3L_MACADDR0_Msk (0xfful << EMAC_CAM3L_MACADDR0_Pos) |
EMAC_T::CAM3L: MACADDR0 Mask
Definition at line 13352 of file NUC472_442.h.
| #define EMAC_CAM3L_MACADDR0_Pos (16) |
EMAC_T::CAM3L: MACADDR0 Position
Definition at line 13351 of file NUC472_442.h.
| #define EMAC_CAM3L_MACADDR1_Msk (0xfful << EMAC_CAM3L_MACADDR1_Pos) |
EMAC_T::CAM3L: MACADDR1 Mask
Definition at line 13355 of file NUC472_442.h.
| #define EMAC_CAM3L_MACADDR1_Pos (24) |
EMAC_T::CAM3L: MACADDR1 Position
Definition at line 13354 of file NUC472_442.h.
| #define EMAC_CAM3L_Rserved_Msk (0xfffful << EMAC_CAM3L_Rserved_Pos) |
EMAC_T::CAM3L: Rserved Mask
Definition at line 13349 of file NUC472_442.h.
| #define EMAC_CAM3L_Rserved_Pos (0) |
EMAC_T::CAM3L: Rserved Position
Definition at line 13348 of file NUC472_442.h.
| #define EMAC_CAM3M_MACADDR2_Msk (0xfful << EMAC_CAM3M_MACADDR2_Pos) |
EMAC_T::CAM3M: MACADDR2 Mask
Definition at line 13337 of file NUC472_442.h.
| #define EMAC_CAM3M_MACADDR2_Pos (0) |
EMAC_T::CAM3M: MACADDR2 Position
Definition at line 13336 of file NUC472_442.h.
| #define EMAC_CAM3M_MACADDR3_Msk (0xfful << EMAC_CAM3M_MACADDR3_Pos) |
EMAC_T::CAM3M: MACADDR3 Mask
Definition at line 13340 of file NUC472_442.h.
| #define EMAC_CAM3M_MACADDR3_Pos (8) |
EMAC_T::CAM3M: MACADDR3 Position
Definition at line 13339 of file NUC472_442.h.
| #define EMAC_CAM3M_MACADDR4_Msk (0xfful << EMAC_CAM3M_MACADDR4_Pos) |
EMAC_T::CAM3M: MACADDR4 Mask
Definition at line 13343 of file NUC472_442.h.
| #define EMAC_CAM3M_MACADDR4_Pos (16) |
EMAC_T::CAM3M: MACADDR4 Position
Definition at line 13342 of file NUC472_442.h.
| #define EMAC_CAM3M_MACADDR5_Msk (0xfful << EMAC_CAM3M_MACADDR5_Pos) |
EMAC_T::CAM3M: MACADDR5 Mask
Definition at line 13346 of file NUC472_442.h.
| #define EMAC_CAM3M_MACADDR5_Pos (24) |
EMAC_T::CAM3M: MACADDR5 Position
Definition at line 13345 of file NUC472_442.h.
| #define EMAC_CAM4L_MACADDR0_Msk (0xfful << EMAC_CAM4L_MACADDR0_Pos) |
EMAC_T::CAM4L: MACADDR0 Mask
Definition at line 13373 of file NUC472_442.h.
| #define EMAC_CAM4L_MACADDR0_Pos (16) |
EMAC_T::CAM4L: MACADDR0 Position
Definition at line 13372 of file NUC472_442.h.
| #define EMAC_CAM4L_MACADDR1_Msk (0xfful << EMAC_CAM4L_MACADDR1_Pos) |
EMAC_T::CAM4L: MACADDR1 Mask
Definition at line 13376 of file NUC472_442.h.
| #define EMAC_CAM4L_MACADDR1_Pos (24) |
EMAC_T::CAM4L: MACADDR1 Position
Definition at line 13375 of file NUC472_442.h.
| #define EMAC_CAM4L_Rserved_Msk (0xfffful << EMAC_CAM4L_Rserved_Pos) |
EMAC_T::CAM4L: Rserved Mask
Definition at line 13370 of file NUC472_442.h.
| #define EMAC_CAM4L_Rserved_Pos (0) |
EMAC_T::CAM4L: Rserved Position
Definition at line 13369 of file NUC472_442.h.
| #define EMAC_CAM4M_MACADDR2_Msk (0xfful << EMAC_CAM4M_MACADDR2_Pos) |
EMAC_T::CAM4M: MACADDR2 Mask
Definition at line 13358 of file NUC472_442.h.
| #define EMAC_CAM4M_MACADDR2_Pos (0) |
EMAC_T::CAM4M: MACADDR2 Position
Definition at line 13357 of file NUC472_442.h.
| #define EMAC_CAM4M_MACADDR3_Msk (0xfful << EMAC_CAM4M_MACADDR3_Pos) |
EMAC_T::CAM4M: MACADDR3 Mask
Definition at line 13361 of file NUC472_442.h.
| #define EMAC_CAM4M_MACADDR3_Pos (8) |
EMAC_T::CAM4M: MACADDR3 Position
Definition at line 13360 of file NUC472_442.h.
| #define EMAC_CAM4M_MACADDR4_Msk (0xfful << EMAC_CAM4M_MACADDR4_Pos) |
EMAC_T::CAM4M: MACADDR4 Mask
Definition at line 13364 of file NUC472_442.h.
| #define EMAC_CAM4M_MACADDR4_Pos (16) |
EMAC_T::CAM4M: MACADDR4 Position
Definition at line 13363 of file NUC472_442.h.
| #define EMAC_CAM4M_MACADDR5_Msk (0xfful << EMAC_CAM4M_MACADDR5_Pos) |
EMAC_T::CAM4M: MACADDR5 Mask
Definition at line 13367 of file NUC472_442.h.
| #define EMAC_CAM4M_MACADDR5_Pos (24) |
EMAC_T::CAM4M: MACADDR5 Position
Definition at line 13366 of file NUC472_442.h.
| #define EMAC_CAM5L_MACADDR0_Msk (0xfful << EMAC_CAM5L_MACADDR0_Pos) |
EMAC_T::CAM5L: MACADDR0 Mask
Definition at line 13394 of file NUC472_442.h.
| #define EMAC_CAM5L_MACADDR0_Pos (16) |
EMAC_T::CAM5L: MACADDR0 Position
Definition at line 13393 of file NUC472_442.h.
| #define EMAC_CAM5L_MACADDR1_Msk (0xfful << EMAC_CAM5L_MACADDR1_Pos) |
EMAC_T::CAM5L: MACADDR1 Mask
Definition at line 13397 of file NUC472_442.h.
| #define EMAC_CAM5L_MACADDR1_Pos (24) |
EMAC_T::CAM5L: MACADDR1 Position
Definition at line 13396 of file NUC472_442.h.
| #define EMAC_CAM5L_Rserved_Msk (0xfffful << EMAC_CAM5L_Rserved_Pos) |
EMAC_T::CAM5L: Rserved Mask
Definition at line 13391 of file NUC472_442.h.
| #define EMAC_CAM5L_Rserved_Pos (0) |
EMAC_T::CAM5L: Rserved Position
Definition at line 13390 of file NUC472_442.h.
| #define EMAC_CAM5M_MACADDR2_Msk (0xfful << EMAC_CAM5M_MACADDR2_Pos) |
EMAC_T::CAM5M: MACADDR2 Mask
Definition at line 13379 of file NUC472_442.h.
| #define EMAC_CAM5M_MACADDR2_Pos (0) |
EMAC_T::CAM5M: MACADDR2 Position
Definition at line 13378 of file NUC472_442.h.
| #define EMAC_CAM5M_MACADDR3_Msk (0xfful << EMAC_CAM5M_MACADDR3_Pos) |
EMAC_T::CAM5M: MACADDR3 Mask
Definition at line 13382 of file NUC472_442.h.
| #define EMAC_CAM5M_MACADDR3_Pos (8) |
EMAC_T::CAM5M: MACADDR3 Position
Definition at line 13381 of file NUC472_442.h.
| #define EMAC_CAM5M_MACADDR4_Msk (0xfful << EMAC_CAM5M_MACADDR4_Pos) |
EMAC_T::CAM5M: MACADDR4 Mask
Definition at line 13385 of file NUC472_442.h.
| #define EMAC_CAM5M_MACADDR4_Pos (16) |
EMAC_T::CAM5M: MACADDR4 Position
Definition at line 13384 of file NUC472_442.h.
| #define EMAC_CAM5M_MACADDR5_Msk (0xfful << EMAC_CAM5M_MACADDR5_Pos) |
EMAC_T::CAM5M: MACADDR5 Mask
Definition at line 13388 of file NUC472_442.h.
| #define EMAC_CAM5M_MACADDR5_Pos (24) |
EMAC_T::CAM5M: MACADDR5 Position
Definition at line 13387 of file NUC472_442.h.
| #define EMAC_CAM6L_MACADDR0_Msk (0xfful << EMAC_CAM6L_MACADDR0_Pos) |
EMAC_T::CAM6L: MACADDR0 Mask
Definition at line 13415 of file NUC472_442.h.
| #define EMAC_CAM6L_MACADDR0_Pos (16) |
EMAC_T::CAM6L: MACADDR0 Position
Definition at line 13414 of file NUC472_442.h.
| #define EMAC_CAM6L_MACADDR1_Msk (0xfful << EMAC_CAM6L_MACADDR1_Pos) |
EMAC_T::CAM6L: MACADDR1 Mask
Definition at line 13418 of file NUC472_442.h.
| #define EMAC_CAM6L_MACADDR1_Pos (24) |
EMAC_T::CAM6L: MACADDR1 Position
Definition at line 13417 of file NUC472_442.h.
| #define EMAC_CAM6L_Rserved_Msk (0xfffful << EMAC_CAM6L_Rserved_Pos) |
EMAC_T::CAM6L: Rserved Mask
Definition at line 13412 of file NUC472_442.h.
| #define EMAC_CAM6L_Rserved_Pos (0) |
EMAC_T::CAM6L: Rserved Position
Definition at line 13411 of file NUC472_442.h.
| #define EMAC_CAM6M_MACADDR2_Msk (0xfful << EMAC_CAM6M_MACADDR2_Pos) |
EMAC_T::CAM6M: MACADDR2 Mask
Definition at line 13400 of file NUC472_442.h.
| #define EMAC_CAM6M_MACADDR2_Pos (0) |
EMAC_T::CAM6M: MACADDR2 Position
Definition at line 13399 of file NUC472_442.h.
| #define EMAC_CAM6M_MACADDR3_Msk (0xfful << EMAC_CAM6M_MACADDR3_Pos) |
EMAC_T::CAM6M: MACADDR3 Mask
Definition at line 13403 of file NUC472_442.h.
| #define EMAC_CAM6M_MACADDR3_Pos (8) |
EMAC_T::CAM6M: MACADDR3 Position
Definition at line 13402 of file NUC472_442.h.
| #define EMAC_CAM6M_MACADDR4_Msk (0xfful << EMAC_CAM6M_MACADDR4_Pos) |
EMAC_T::CAM6M: MACADDR4 Mask
Definition at line 13406 of file NUC472_442.h.
| #define EMAC_CAM6M_MACADDR4_Pos (16) |
EMAC_T::CAM6M: MACADDR4 Position
Definition at line 13405 of file NUC472_442.h.
| #define EMAC_CAM6M_MACADDR5_Msk (0xfful << EMAC_CAM6M_MACADDR5_Pos) |
EMAC_T::CAM6M: MACADDR5 Mask
Definition at line 13409 of file NUC472_442.h.
| #define EMAC_CAM6M_MACADDR5_Pos (24) |
EMAC_T::CAM6M: MACADDR5 Position
Definition at line 13408 of file NUC472_442.h.
| #define EMAC_CAM7L_MACADDR0_Msk (0xfful << EMAC_CAM7L_MACADDR0_Pos) |
EMAC_T::CAM7L: MACADDR0 Mask
Definition at line 13436 of file NUC472_442.h.
| #define EMAC_CAM7L_MACADDR0_Pos (16) |
EMAC_T::CAM7L: MACADDR0 Position
Definition at line 13435 of file NUC472_442.h.
| #define EMAC_CAM7L_MACADDR1_Msk (0xfful << EMAC_CAM7L_MACADDR1_Pos) |
EMAC_T::CAM7L: MACADDR1 Mask
Definition at line 13439 of file NUC472_442.h.
| #define EMAC_CAM7L_MACADDR1_Pos (24) |
EMAC_T::CAM7L: MACADDR1 Position
Definition at line 13438 of file NUC472_442.h.
| #define EMAC_CAM7L_Rserved_Msk (0xfffful << EMAC_CAM7L_Rserved_Pos) |
EMAC_T::CAM7L: Rserved Mask
Definition at line 13433 of file NUC472_442.h.
| #define EMAC_CAM7L_Rserved_Pos (0) |
EMAC_T::CAM7L: Rserved Position
Definition at line 13432 of file NUC472_442.h.
| #define EMAC_CAM7M_MACADDR2_Msk (0xfful << EMAC_CAM7M_MACADDR2_Pos) |
EMAC_T::CAM7M: MACADDR2 Mask
Definition at line 13421 of file NUC472_442.h.
| #define EMAC_CAM7M_MACADDR2_Pos (0) |
EMAC_T::CAM7M: MACADDR2 Position
Definition at line 13420 of file NUC472_442.h.
| #define EMAC_CAM7M_MACADDR3_Msk (0xfful << EMAC_CAM7M_MACADDR3_Pos) |
EMAC_T::CAM7M: MACADDR3 Mask
Definition at line 13424 of file NUC472_442.h.
| #define EMAC_CAM7M_MACADDR3_Pos (8) |
EMAC_T::CAM7M: MACADDR3 Position
Definition at line 13423 of file NUC472_442.h.
| #define EMAC_CAM7M_MACADDR4_Msk (0xfful << EMAC_CAM7M_MACADDR4_Pos) |
EMAC_T::CAM7M: MACADDR4 Mask
Definition at line 13427 of file NUC472_442.h.
| #define EMAC_CAM7M_MACADDR4_Pos (16) |
EMAC_T::CAM7M: MACADDR4 Position
Definition at line 13426 of file NUC472_442.h.
| #define EMAC_CAM7M_MACADDR5_Msk (0xfful << EMAC_CAM7M_MACADDR5_Pos) |
EMAC_T::CAM7M: MACADDR5 Mask
Definition at line 13430 of file NUC472_442.h.
| #define EMAC_CAM7M_MACADDR5_Pos (24) |
EMAC_T::CAM7M: MACADDR5 Position
Definition at line 13429 of file NUC472_442.h.
| #define EMAC_CAM8L_MACADDR0_Msk (0xfful << EMAC_CAM8L_MACADDR0_Pos) |
EMAC_T::CAM8L: MACADDR0 Mask
Definition at line 13457 of file NUC472_442.h.
| #define EMAC_CAM8L_MACADDR0_Pos (16) |
EMAC_T::CAM8L: MACADDR0 Position
Definition at line 13456 of file NUC472_442.h.
| #define EMAC_CAM8L_MACADDR1_Msk (0xfful << EMAC_CAM8L_MACADDR1_Pos) |
EMAC_T::CAM8L: MACADDR1 Mask
Definition at line 13460 of file NUC472_442.h.
| #define EMAC_CAM8L_MACADDR1_Pos (24) |
EMAC_T::CAM8L: MACADDR1 Position
Definition at line 13459 of file NUC472_442.h.
| #define EMAC_CAM8L_Rserved_Msk (0xfffful << EMAC_CAM8L_Rserved_Pos) |
EMAC_T::CAM8L: Rserved Mask
Definition at line 13454 of file NUC472_442.h.
| #define EMAC_CAM8L_Rserved_Pos (0) |
EMAC_T::CAM8L: Rserved Position
Definition at line 13453 of file NUC472_442.h.
| #define EMAC_CAM8M_MACADDR2_Msk (0xfful << EMAC_CAM8M_MACADDR2_Pos) |
EMAC_T::CAM8M: MACADDR2 Mask
Definition at line 13442 of file NUC472_442.h.
| #define EMAC_CAM8M_MACADDR2_Pos (0) |
EMAC_T::CAM8M: MACADDR2 Position
Definition at line 13441 of file NUC472_442.h.
| #define EMAC_CAM8M_MACADDR3_Msk (0xfful << EMAC_CAM8M_MACADDR3_Pos) |
EMAC_T::CAM8M: MACADDR3 Mask
Definition at line 13445 of file NUC472_442.h.
| #define EMAC_CAM8M_MACADDR3_Pos (8) |
EMAC_T::CAM8M: MACADDR3 Position
Definition at line 13444 of file NUC472_442.h.
| #define EMAC_CAM8M_MACADDR4_Msk (0xfful << EMAC_CAM8M_MACADDR4_Pos) |
EMAC_T::CAM8M: MACADDR4 Mask
Definition at line 13448 of file NUC472_442.h.
| #define EMAC_CAM8M_MACADDR4_Pos (16) |
EMAC_T::CAM8M: MACADDR4 Position
Definition at line 13447 of file NUC472_442.h.
| #define EMAC_CAM8M_MACADDR5_Msk (0xfful << EMAC_CAM8M_MACADDR5_Pos) |
EMAC_T::CAM8M: MACADDR5 Mask
Definition at line 13451 of file NUC472_442.h.
| #define EMAC_CAM8M_MACADDR5_Pos (24) |
EMAC_T::CAM8M: MACADDR5 Position
Definition at line 13450 of file NUC472_442.h.
| #define EMAC_CAM9L_MACADDR0_Msk (0xfful << EMAC_CAM9L_MACADDR0_Pos) |
EMAC_T::CAM9L: MACADDR0 Mask
Definition at line 13478 of file NUC472_442.h.
| #define EMAC_CAM9L_MACADDR0_Pos (16) |
EMAC_T::CAM9L: MACADDR0 Position
Definition at line 13477 of file NUC472_442.h.
| #define EMAC_CAM9L_MACADDR1_Msk (0xfful << EMAC_CAM9L_MACADDR1_Pos) |
EMAC_T::CAM9L: MACADDR1 Mask
Definition at line 13481 of file NUC472_442.h.
| #define EMAC_CAM9L_MACADDR1_Pos (24) |
EMAC_T::CAM9L: MACADDR1 Position
Definition at line 13480 of file NUC472_442.h.
| #define EMAC_CAM9L_Rserved_Msk (0xfffful << EMAC_CAM9L_Rserved_Pos) |
EMAC_T::CAM9L: Rserved Mask
Definition at line 13475 of file NUC472_442.h.
| #define EMAC_CAM9L_Rserved_Pos (0) |
EMAC_T::CAM9L: Rserved Position
Definition at line 13474 of file NUC472_442.h.
| #define EMAC_CAM9M_MACADDR2_Msk (0xfful << EMAC_CAM9M_MACADDR2_Pos) |
EMAC_T::CAM9M: MACADDR2 Mask
Definition at line 13463 of file NUC472_442.h.
| #define EMAC_CAM9M_MACADDR2_Pos (0) |
EMAC_T::CAM9M: MACADDR2 Position
Definition at line 13462 of file NUC472_442.h.
| #define EMAC_CAM9M_MACADDR3_Msk (0xfful << EMAC_CAM9M_MACADDR3_Pos) |
EMAC_T::CAM9M: MACADDR3 Mask
Definition at line 13466 of file NUC472_442.h.
| #define EMAC_CAM9M_MACADDR3_Pos (8) |
EMAC_T::CAM9M: MACADDR3 Position
Definition at line 13465 of file NUC472_442.h.
| #define EMAC_CAM9M_MACADDR4_Msk (0xfful << EMAC_CAM9M_MACADDR4_Pos) |
EMAC_T::CAM9M: MACADDR4 Mask
Definition at line 13469 of file NUC472_442.h.
| #define EMAC_CAM9M_MACADDR4_Pos (16) |
EMAC_T::CAM9M: MACADDR4 Position
Definition at line 13468 of file NUC472_442.h.
| #define EMAC_CAM9M_MACADDR5_Msk (0xfful << EMAC_CAM9M_MACADDR5_Pos) |
EMAC_T::CAM9M: MACADDR5 Mask
Definition at line 13472 of file NUC472_442.h.
| #define EMAC_CAM9M_MACADDR5_Pos (24) |
EMAC_T::CAM9M: MACADDR5 Position
Definition at line 13471 of file NUC472_442.h.
| #define EMAC_CAMCTL_ABP_Msk (0x1ul << EMAC_CAMCTL_ABP_Pos) |
EMAC_T::CAMCTL: ABP Mask
Definition at line 13262 of file NUC472_442.h.
| #define EMAC_CAMCTL_ABP_Pos (2) |
EMAC_T::CAMCTL: ABP Position
Definition at line 13261 of file NUC472_442.h.
| #define EMAC_CAMCTL_AMP_Msk (0x1ul << EMAC_CAMCTL_AMP_Pos) |
EMAC_T::CAMCTL: AMP Mask
Definition at line 13259 of file NUC472_442.h.
| #define EMAC_CAMCTL_AMP_Pos (1) |
EMAC_T::CAMCTL: AMP Position
Definition at line 13258 of file NUC472_442.h.
| #define EMAC_CAMCTL_AUP_Msk (0x1ul << EMAC_CAMCTL_AUP_Pos) |
EMAC_T::CAMCTL: AUP Mask
Definition at line 13256 of file NUC472_442.h.
| #define EMAC_CAMCTL_AUP_Pos (0) |
@addtogroup EMAC_CONST EMAC Bit Field Definition Constant Definitions for EMAC Controller
EMAC_T::CAMCTL: AUP Position
Definition at line 13255 of file NUC472_442.h.
| #define EMAC_CAMCTL_CMPEN_Msk (0x1ul << EMAC_CAMCTL_CMPEN_Pos) |
EMAC_T::CAMCTL: CMPEN Mask
Definition at line 13268 of file NUC472_442.h.
| #define EMAC_CAMCTL_CMPEN_Pos (4) |
EMAC_T::CAMCTL: CMPEN Position
Definition at line 13267 of file NUC472_442.h.
| #define EMAC_CAMCTL_COMPEN_Msk (0x1ul << EMAC_CAMCTL_COMPEN_Pos) |
EMAC_T::CAMCTL: COMPEN Mask
Definition at line 13265 of file NUC472_442.h.
| #define EMAC_CAMCTL_COMPEN_Pos (3) |
EMAC_T::CAMCTL: COMPEN Position
Definition at line 13264 of file NUC472_442.h.
| #define EMAC_CAMEN_CAMxEN_Msk (0x1ul << EMAC_CAMEN_CAMxEN_Pos) |
EMAC_T::CAMEN: CAMxEN Mask
Definition at line 13271 of file NUC472_442.h.
| #define EMAC_CAMEN_CAMxEN_Pos (0) |
EMAC_T::CAMEN: CAMxEN Position
Definition at line 13270 of file NUC472_442.h.
| #define EMAC_CRXBSA_CRXBSA_Msk (0xfffffffful << EMAC_CRXBSA_CRXBSA_Pos) |
EMAC_T::CRXBSA: CRXBSA Mask
Definition at line 13880 of file NUC472_442.h.
| #define EMAC_CRXBSA_CRXBSA_Pos (0) |
EMAC_T::CRXBSA: CRXBSA Position
Definition at line 13879 of file NUC472_442.h.
| #define EMAC_CRXDSA_CRXDSA_Msk (0xfffffffful << EMAC_CRXDSA_CRXDSA_Pos) |
EMAC_T::CRXDSA: CRXDSA Mask
Definition at line 13877 of file NUC472_442.h.
| #define EMAC_CRXDSA_CRXDSA_Pos (0) |
EMAC_T::CRXDSA: CRXDSA Position
Definition at line 13876 of file NUC472_442.h.
| #define EMAC_CTL_ACP_Msk (0x1ul << EMAC_CTL_ACP_Pos) |
EMAC_T::CTL: ACP Mask
Definition at line 13613 of file NUC472_442.h.
| #define EMAC_CTL_ACP_Pos (3) |
EMAC_T::CTL: ACP Position
Definition at line 13612 of file NUC472_442.h.
| #define EMAC_CTL_AEP_Msk (0x1ul << EMAC_CTL_AEP_Pos) |
EMAC_T::CTL: AEP Mask
Definition at line 13616 of file NUC472_442.h.
| #define EMAC_CTL_AEP_Pos (4) |
EMAC_T::CTL: AEP Position
Definition at line 13615 of file NUC472_442.h.
| #define EMAC_CTL_ALP_Msk (0x1ul << EMAC_CTL_ALP_Pos) |
EMAC_T::CTL: ALP Mask
Definition at line 13607 of file NUC472_442.h.
| #define EMAC_CTL_ALP_Pos (1) |
EMAC_T::CTL: ALP Position
Definition at line 13606 of file NUC472_442.h.
| #define EMAC_CTL_ARP_Msk (0x1ul << EMAC_CTL_ARP_Pos) |
EMAC_T::CTL: ARP Mask
Definition at line 13610 of file NUC472_442.h.
| #define EMAC_CTL_ARP_Pos (2) |
EMAC_T::CTL: ARP Position
Definition at line 13609 of file NUC472_442.h.
| #define EMAC_CTL_FUDUP_Msk (0x1ul << EMAC_CTL_FUDUP_Pos) |
EMAC_T::CTL: FUDUP Mask
Definition at line 13637 of file NUC472_442.h.
| #define EMAC_CTL_FUDUP_Pos (18) |
EMAC_T::CTL: FUDUP Position
Definition at line 13636 of file NUC472_442.h.
| #define EMAC_CTL_NODEF_Msk (0x1ul << EMAC_CTL_NODEF_Pos) |
EMAC_T::CTL: NODEF Mask
Definition at line 13628 of file NUC472_442.h.
| #define EMAC_CTL_NODEF_Pos (9) |
EMAC_T::CTL: NODEF Position
Definition at line 13627 of file NUC472_442.h.
| #define EMAC_CTL_OPMODE_Msk (0x1ul << EMAC_CTL_OPMODE_Pos) |
EMAC_T::CTL: OPMODE Mask
Definition at line 13643 of file NUC472_442.h.
| #define EMAC_CTL_OPMODE_Pos (20) |
EMAC_T::CTL: OPMODE Position
Definition at line 13642 of file NUC472_442.h.
| #define EMAC_CTL_RMIIEN_Msk (0x1ul << EMAC_CTL_RMIIEN_Pos) |
EMAC_T::CTL: RMIIEN Mask
Definition at line 13646 of file NUC472_442.h.
| #define EMAC_CTL_RMIIEN_Pos (22) |
EMAC_T::CTL: RMIIEN Position
Definition at line 13645 of file NUC472_442.h.
| #define EMAC_CTL_RMIIRXCTL_Msk (0x1ul << EMAC_CTL_RMIIRXCTL_Pos) |
EMAC_T::CTL: RMIIRXCTL Mask
Definition at line 13640 of file NUC472_442.h.
| #define EMAC_CTL_RMIIRXCTL_Pos (19) |
EMAC_T::CTL: RMIIRXCTL Position
Definition at line 13639 of file NUC472_442.h.
| #define EMAC_CTL_RST_Msk (0x1ul << EMAC_CTL_RST_Pos) |
EMAC_T::CTL: RST Mask
Definition at line 13649 of file NUC472_442.h.
| #define EMAC_CTL_RST_Pos (24) |
EMAC_T::CTL: RST Position
Definition at line 13648 of file NUC472_442.h.
| #define EMAC_CTL_RXON_Msk (0x1ul << EMAC_CTL_RXON_Pos) |
EMAC_T::CTL: RXON Mask
Definition at line 13604 of file NUC472_442.h.
| #define EMAC_CTL_RXON_Pos (0) |
EMAC_T::CTL: RXON Position
Definition at line 13603 of file NUC472_442.h.
| #define EMAC_CTL_SDPZ_Msk (0x1ul << EMAC_CTL_SDPZ_Pos) |
EMAC_T::CTL: SDPZ Mask
Definition at line 13631 of file NUC472_442.h.
| #define EMAC_CTL_SDPZ_Pos (16) |
EMAC_T::CTL: SDPZ Position
Definition at line 13630 of file NUC472_442.h.
| #define EMAC_CTL_SQECHKEN_Msk (0x1ul << EMAC_CTL_SQECHKEN_Pos) |
EMAC_T::CTL: SQECHKEN Mask
Definition at line 13634 of file NUC472_442.h.
| #define EMAC_CTL_SQECHKEN_Pos (17) |
EMAC_T::CTL: SQECHKEN Position
Definition at line 13633 of file NUC472_442.h.
| #define EMAC_CTL_STRIPCRC_Msk (0x1ul << EMAC_CTL_STRIPCRC_Pos) |
EMAC_T::CTL: STRIPCRC Mask
Definition at line 13619 of file NUC472_442.h.
| #define EMAC_CTL_STRIPCRC_Pos (5) |
EMAC_T::CTL: STRIPCRC Position
Definition at line 13618 of file NUC472_442.h.
| #define EMAC_CTL_TXON_Msk (0x1ul << EMAC_CTL_TXON_Pos) |
EMAC_T::CTL: TXON Mask
Definition at line 13625 of file NUC472_442.h.
| #define EMAC_CTL_TXON_Pos (8) |
EMAC_T::CTL: TXON Position
Definition at line 13624 of file NUC472_442.h.
| #define EMAC_CTL_WOLEN_Msk (0x1ul << EMAC_CTL_WOLEN_Pos) |
EMAC_T::CTL: WOLEN Mask
Definition at line 13622 of file NUC472_442.h.
| #define EMAC_CTL_WOLEN_Pos (6) |
EMAC_T::CTL: WOLEN Position
Definition at line 13621 of file NUC472_442.h.
| #define EMAC_CTXBSA_CTXBSA_Msk (0xfffffffful << EMAC_CTXBSA_CTXBSA_Pos) |
EMAC_T::CTXBSA: CTXBSA Mask
Definition at line 13874 of file NUC472_442.h.
| #define EMAC_CTXBSA_CTXBSA_Pos (0) |
EMAC_T::CTXBSA: CTXBSA Position
Definition at line 13873 of file NUC472_442.h.
| #define EMAC_CTXDSA_CTXDSA_Msk (0xfffffffful << EMAC_CTXDSA_CTXDSA_Pos) |
EMAC_T::CTXDSA: CTXDSA Mask
Definition at line 13871 of file NUC472_442.h.
| #define EMAC_CTXDSA_CTXDSA_Pos (0) |
EMAC_T::CTXDSA: CTXDSA Position
Definition at line 13870 of file NUC472_442.h.
| #define EMAC_FIFOCTL_BURSTLEN_Msk (0x3ul << EMAC_FIFOCTL_BURSTLEN_Pos) |
EMAC_T::FIFOCTL: BURSTLEN Mask
Definition at line 13679 of file NUC472_442.h.
| #define EMAC_FIFOCTL_BURSTLEN_Pos (20) |
EMAC_T::FIFOCTL: BURSTLEN Position
Definition at line 13678 of file NUC472_442.h.
| #define EMAC_FIFOCTL_RXFIFOTH_Msk (0x3ul << EMAC_FIFOCTL_RXFIFOTH_Pos) |
EMAC_T::FIFOCTL: RXFIFOTH Mask
Definition at line 13673 of file NUC472_442.h.
| #define EMAC_FIFOCTL_RXFIFOTH_Pos (0) |
EMAC_T::FIFOCTL: RXFIFOTH Position
Definition at line 13672 of file NUC472_442.h.
| #define EMAC_FIFOCTL_TXFIFOTH_Msk (0x3ul << EMAC_FIFOCTL_TXFIFOTH_Pos) |
EMAC_T::FIFOCTL: TXFIFOTH Mask
Definition at line 13676 of file NUC472_442.h.
| #define EMAC_FIFOCTL_TXFIFOTH_Pos (8) |
EMAC_T::FIFOCTL: TXFIFOTH Position
Definition at line 13675 of file NUC472_442.h.
| #define EMAC_FRSTS_RXFLT_Msk (0xfffful << EMAC_FRSTS_RXFLT_Pos) |
EMAC_T::FRSTS: RXFLT Mask
Definition at line 13868 of file NUC472_442.h.
| #define EMAC_FRSTS_RXFLT_Pos (0) |
EMAC_T::FRSTS: RXFLT Position
Definition at line 13867 of file NUC472_442.h.
| #define EMAC_GENSTS_CFRIF_Msk (0x1ul << EMAC_GENSTS_CFRIF_Pos) |
EMAC_T::GENSTS: CFRIF Mask
Definition at line 13835 of file NUC472_442.h.
| #define EMAC_GENSTS_CFRIF_Pos (0) |
EMAC_T::GENSTS: CFRIF Position
Definition at line 13834 of file NUC472_442.h.
| #define EMAC_GENSTS_COLCNT_Msk (0xful << EMAC_GENSTS_COLCNT_Pos) |
EMAC_T::GENSTS: COLCNT Mask
Definition at line 13844 of file NUC472_442.h.
| #define EMAC_GENSTS_COLCNT_Pos (4) |
EMAC_T::GENSTS: COLCNT Position
Definition at line 13843 of file NUC472_442.h.
| #define EMAC_GENSTS_DEF_Msk (0x1ul << EMAC_GENSTS_DEF_Pos) |
EMAC_T::GENSTS: DEF Mask
Definition at line 13847 of file NUC472_442.h.
| #define EMAC_GENSTS_DEF_Pos (8) |
EMAC_T::GENSTS: DEF Position
Definition at line 13846 of file NUC472_442.h.
| #define EMAC_GENSTS_RPSTS_Msk (0x1ul << EMAC_GENSTS_RPSTS_Pos) |
EMAC_T::GENSTS: RPSTS Mask
Definition at line 13859 of file NUC472_442.h.
| #define EMAC_GENSTS_RPSTS_Pos (12) |
EMAC_T::GENSTS: RPSTS Position
Definition at line 13858 of file NUC472_442.h.
| #define EMAC_GENSTS_RXFFULL_Msk (0x1ul << EMAC_GENSTS_RXFFULL_Pos) |
EMAC_T::GENSTS: RXFFULL Mask
Definition at line 13841 of file NUC472_442.h.
| #define EMAC_GENSTS_RXFFULL_Pos (2) |
EMAC_T::GENSTS: RXFFULL Position
Definition at line 13840 of file NUC472_442.h.
| #define EMAC_GENSTS_RXHALT_Msk (0x1ul << EMAC_GENSTS_RXHALT_Pos) |
EMAC_T::GENSTS: RXHALT Mask
Definition at line 13838 of file NUC472_442.h.
| #define EMAC_GENSTS_RXHALT_Pos (1) |
EMAC_T::GENSTS: RXHALT Position
Definition at line 13837 of file NUC472_442.h.
| #define EMAC_GENSTS_SQE_Msk (0x1ul << EMAC_GENSTS_SQE_Pos) |
EMAC_T::GENSTS: SQE Mask
Definition at line 13853 of file NUC472_442.h.
| #define EMAC_GENSTS_SQE_Pos (10) |
EMAC_T::GENSTS: SQE Position
Definition at line 13852 of file NUC472_442.h.
| #define EMAC_GENSTS_TXHALT_Msk (0x1ul << EMAC_GENSTS_TXHALT_Pos) |
EMAC_T::GENSTS: TXHALT Mask
Definition at line 13856 of file NUC472_442.h.
| #define EMAC_GENSTS_TXHALT_Pos (11) |
EMAC_T::GENSTS: TXHALT Position
Definition at line 13855 of file NUC472_442.h.
| #define EMAC_GENSTS_TXPAUSED_Msk (0x1ul << EMAC_GENSTS_TXPAUSED_Pos) |
EMAC_T::GENSTS: TXPAUSED Mask
Definition at line 13850 of file NUC472_442.h.
| #define EMAC_GENSTS_TXPAUSED_Pos (9) |
EMAC_T::GENSTS: TXPAUSED Position
Definition at line 13849 of file NUC472_442.h.
| #define EMAC_INTEN_ALIEIEN_Msk (0x1ul << EMAC_INTEN_ALIEIEN_Pos) |
EMAC_T::INTEN: ALIEIEN Mask
Definition at line 13706 of file NUC472_442.h.
| #define EMAC_INTEN_ALIEIEN_Pos (5) |
EMAC_T::INTEN: ALIEIEN Position
Definition at line 13705 of file NUC472_442.h.
| #define EMAC_INTEN_CFRIEN_Msk (0x1ul << EMAC_INTEN_CFRIEN_Pos) |
EMAC_T::INTEN: CFRIEN Mask
Definition at line 13727 of file NUC472_442.h.
| #define EMAC_INTEN_CFRIEN_Pos (14) |
EMAC_T::INTEN: CFRIEN Position
Definition at line 13726 of file NUC472_442.h.
| #define EMAC_INTEN_CRCEIEN_Msk (0x1ul << EMAC_INTEN_CRCEIEN_Pos) |
EMAC_T::INTEN: CRCEIEN Mask
Definition at line 13694 of file NUC472_442.h.
| #define EMAC_INTEN_CRCEIEN_Pos (1) |
EMAC_T::INTEN: CRCEIEN Position
Definition at line 13693 of file NUC472_442.h.
| #define EMAC_INTEN_DENIEN_Msk (0x1ul << EMAC_INTEN_DENIEN_Pos) |
EMAC_T::INTEN: DENIEN Mask
Definition at line 13718 of file NUC472_442.h.
| #define EMAC_INTEN_DENIEN_Pos (9) |
EMAC_T::INTEN: DENIEN Position
Definition at line 13717 of file NUC472_442.h.
| #define EMAC_INTEN_EXDEFIEN_Msk (0x1ul << EMAC_INTEN_EXDEFIEN_Pos) |
EMAC_T::INTEN: EXDEFIEN Mask
Definition at line 13742 of file NUC472_442.h.
| #define EMAC_INTEN_EXDEFIEN_Pos (19) |
EMAC_T::INTEN: EXDEFIEN Position
Definition at line 13741 of file NUC472_442.h.
| #define EMAC_INTEN_LCIEN_Msk (0x1ul << EMAC_INTEN_LCIEN_Pos) |
EMAC_T::INTEN: LCIEN Mask
Definition at line 13751 of file NUC472_442.h.
| #define EMAC_INTEN_LCIEN_Pos (22) |
EMAC_T::INTEN: LCIEN Position
Definition at line 13750 of file NUC472_442.h.
| #define EMAC_INTEN_LPIEN_Msk (0x1ul << EMAC_INTEN_LPIEN_Pos) |
EMAC_T::INTEN: LPIEN Mask
Definition at line 13700 of file NUC472_442.h.
| #define EMAC_INTEN_LPIEN_Pos (3) |
EMAC_T::INTEN: LPIEN Position
Definition at line 13699 of file NUC472_442.h.
| #define EMAC_INTEN_MFLEIEN_Msk (0x1ul << EMAC_INTEN_MFLEIEN_Pos) |
EMAC_T::INTEN: MFLEIEN Mask
Definition at line 13715 of file NUC472_442.h.
| #define EMAC_INTEN_MFLEIEN_Pos (8) |
EMAC_T::INTEN: MFLEIEN Position
Definition at line 13714 of file NUC472_442.h.
| #define EMAC_INTEN_MPCOVIEN_Msk (0x1ul << EMAC_INTEN_MPCOVIEN_Pos) |
EMAC_T::INTEN: MPCOVIEN Mask
Definition at line 13712 of file NUC472_442.h.
| #define EMAC_INTEN_MPCOVIEN_Pos (7) |
EMAC_T::INTEN: MPCOVIEN Position
Definition at line 13711 of file NUC472_442.h.
| #define EMAC_INTEN_NCSIEN_Msk (0x1ul << EMAC_INTEN_NCSIEN_Pos) |
EMAC_T::INTEN: NCSIEN Mask
Definition at line 13745 of file NUC472_442.h.
| #define EMAC_INTEN_NCSIEN_Pos (20) |
EMAC_T::INTEN: NCSIEN Position
Definition at line 13744 of file NUC472_442.h.
| #define EMAC_INTEN_RDUIEN_Msk (0x1ul << EMAC_INTEN_RDUIEN_Pos) |
EMAC_T::INTEN: RDUIEN Mask
Definition at line 13721 of file NUC472_442.h.
| #define EMAC_INTEN_RDUIEN_Pos (10) |
EMAC_T::INTEN: RDUIEN Position
Definition at line 13720 of file NUC472_442.h.
| #define EMAC_INTEN_RPIEN_Msk (0x1ul << EMAC_INTEN_RPIEN_Pos) |
EMAC_T::INTEN: RPIEN Mask
Definition at line 13709 of file NUC472_442.h.
| #define EMAC_INTEN_RPIEN_Pos (6) |
EMAC_T::INTEN: RPIEN Position
Definition at line 13708 of file NUC472_442.h.
| #define EMAC_INTEN_RXBEIEN_Msk (0x1ul << EMAC_INTEN_RXBEIEN_Pos) |
EMAC_T::INTEN: RXBEIEN Mask
Definition at line 13724 of file NUC472_442.h.
| #define EMAC_INTEN_RXBEIEN_Pos (11) |
EMAC_T::INTEN: RXBEIEN Position
Definition at line 13723 of file NUC472_442.h.
| #define EMAC_INTEN_RXGDIEN_Msk (0x1ul << EMAC_INTEN_RXGDIEN_Pos) |
EMAC_T::INTEN: RXGDIEN Mask
Definition at line 13703 of file NUC472_442.h.
| #define EMAC_INTEN_RXGDIEN_Pos (4) |
EMAC_T::INTEN: RXGDIEN Position
Definition at line 13702 of file NUC472_442.h.
| #define EMAC_INTEN_RXIEN_Msk (0x1ul << EMAC_INTEN_RXIEN_Pos) |
EMAC_T::INTEN: RXIEN Mask
Definition at line 13691 of file NUC472_442.h.
| #define EMAC_INTEN_RXIEN_Pos (0) |
EMAC_T::INTEN: RXIEN Position
Definition at line 13690 of file NUC472_442.h.
| #define EMAC_INTEN_RXOVIEN_Msk (0x1ul << EMAC_INTEN_RXOVIEN_Pos) |
EMAC_T::INTEN: RXOVIEN Mask
Definition at line 13697 of file NUC472_442.h.
| #define EMAC_INTEN_RXOVIEN_Pos (2) |
EMAC_T::INTEN: RXOVIEN Position
Definition at line 13696 of file NUC472_442.h.
| #define EMAC_INTEN_TDUIEN_Msk (0x1ul << EMAC_INTEN_TDUIEN_Pos) |
EMAC_T::INTEN: TDUIEN Mask
Definition at line 13754 of file NUC472_442.h.
| #define EMAC_INTEN_TDUIEN_Pos (23) |
EMAC_T::INTEN: TDUIEN Position
Definition at line 13753 of file NUC472_442.h.
| #define EMAC_INTEN_TSALMIEN_Msk (0x1ul << EMAC_INTEN_TSALMIEN_Pos) |
EMAC_T::INTEN: TSALMIEN Mask
Definition at line 13760 of file NUC472_442.h.
| #define EMAC_INTEN_TSALMIEN_Pos (28) |
EMAC_T::INTEN: TSALMIEN Position
Definition at line 13759 of file NUC472_442.h.
| #define EMAC_INTEN_TXABTIEN_Msk (0x1ul << EMAC_INTEN_TXABTIEN_Pos) |
EMAC_T::INTEN: TXABTIEN Mask
Definition at line 13748 of file NUC472_442.h.
| #define EMAC_INTEN_TXABTIEN_Pos (21) |
EMAC_T::INTEN: TXABTIEN Position
Definition at line 13747 of file NUC472_442.h.
| #define EMAC_INTEN_TXBEIEN_Msk (0x1ul << EMAC_INTEN_TXBEIEN_Pos) |
EMAC_T::INTEN: TXBEIEN Mask
Definition at line 13757 of file NUC472_442.h.
| #define EMAC_INTEN_TXBEIEN_Pos (24) |
EMAC_T::INTEN: TXBEIEN Position
Definition at line 13756 of file NUC472_442.h.
| #define EMAC_INTEN_TXCPIEN_Msk (0x1ul << EMAC_INTEN_TXCPIEN_Pos) |
EMAC_T::INTEN: TXCPIEN Mask
Definition at line 13739 of file NUC472_442.h.
| #define EMAC_INTEN_TXCPIEN_Pos (18) |
EMAC_T::INTEN: TXCPIEN Position
Definition at line 13738 of file NUC472_442.h.
| #define EMAC_INTEN_TXIEN_Msk (0x1ul << EMAC_INTEN_TXIEN_Pos) |
EMAC_T::INTEN: TXIEN Mask
Definition at line 13733 of file NUC472_442.h.
| #define EMAC_INTEN_TXIEN_Pos (16) |
EMAC_T::INTEN: TXIEN Position
Definition at line 13732 of file NUC472_442.h.
| #define EMAC_INTEN_TXUDIEN_Msk (0x1ul << EMAC_INTEN_TXUDIEN_Pos) |
EMAC_T::INTEN: TXUDIEN Mask
Definition at line 13736 of file NUC472_442.h.
| #define EMAC_INTEN_TXUDIEN_Pos (17) |
EMAC_T::INTEN: TXUDIEN Position
Definition at line 13735 of file NUC472_442.h.
| #define EMAC_INTEN_WOLIEN_Msk (0x1ul << EMAC_INTEN_WOLIEN_Pos) |
EMAC_T::INTEN: WOLIEN Mask
Definition at line 13730 of file NUC472_442.h.
| #define EMAC_INTEN_WOLIEN_Pos (15) |
EMAC_T::INTEN: WOLIEN Position
Definition at line 13729 of file NUC472_442.h.
| #define EMAC_INTSTS_ALIEIF_Msk (0x1ul << EMAC_INTSTS_ALIEIF_Pos) |
EMAC_T::INTSTS: ALIEIF Mask
Definition at line 13778 of file NUC472_442.h.
| #define EMAC_INTSTS_ALIEIF_Pos (5) |
EMAC_T::INTSTS: ALIEIF Position
Definition at line 13777 of file NUC472_442.h.
| #define EMAC_INTSTS_CFRIF_Msk (0x1ul << EMAC_INTSTS_CFRIF_Pos) |
EMAC_T::INTSTS: CFRIF Mask
Definition at line 13799 of file NUC472_442.h.
| #define EMAC_INTSTS_CFRIF_Pos (14) |
EMAC_T::INTSTS: CFRIF Position
Definition at line 13798 of file NUC472_442.h.
| #define EMAC_INTSTS_CRCEIF_Msk (0x1ul << EMAC_INTSTS_CRCEIF_Pos) |
EMAC_T::INTSTS: CRCEIF Mask
Definition at line 13766 of file NUC472_442.h.
| #define EMAC_INTSTS_CRCEIF_Pos (1) |
EMAC_T::INTSTS: CRCEIF Position
Definition at line 13765 of file NUC472_442.h.
| #define EMAC_INTSTS_DENIF_Msk (0x1ul << EMAC_INTSTS_DENIF_Pos) |
EMAC_T::INTSTS: DENIF Mask
Definition at line 13790 of file NUC472_442.h.
| #define EMAC_INTSTS_DENIF_Pos (9) |
EMAC_T::INTSTS: DENIF Position
Definition at line 13789 of file NUC472_442.h.
| #define EMAC_INTSTS_EXDEFIF_Msk (0x1ul << EMAC_INTSTS_EXDEFIF_Pos) |
EMAC_T::INTSTS: EXDEFIF Mask
Definition at line 13814 of file NUC472_442.h.
| #define EMAC_INTSTS_EXDEFIF_Pos (19) |
EMAC_T::INTSTS: EXDEFIF Position
Definition at line 13813 of file NUC472_442.h.
| #define EMAC_INTSTS_LCIF_Msk (0x1ul << EMAC_INTSTS_LCIF_Pos) |
EMAC_T::INTSTS: LCIF Mask
Definition at line 13823 of file NUC472_442.h.
| #define EMAC_INTSTS_LCIF_Pos (22) |
EMAC_T::INTSTS: LCIF Position
Definition at line 13822 of file NUC472_442.h.
| #define EMAC_INTSTS_LPIF_Msk (0x1ul << EMAC_INTSTS_LPIF_Pos) |
EMAC_T::INTSTS: LPIF Mask
Definition at line 13772 of file NUC472_442.h.
| #define EMAC_INTSTS_LPIF_Pos (3) |
EMAC_T::INTSTS: LPIF Position
Definition at line 13771 of file NUC472_442.h.
| #define EMAC_INTSTS_MFLEIF_Msk (0x1ul << EMAC_INTSTS_MFLEIF_Pos) |
EMAC_T::INTSTS: MFLEIF Mask
Definition at line 13787 of file NUC472_442.h.
| #define EMAC_INTSTS_MFLEIF_Pos (8) |
EMAC_T::INTSTS: MFLEIF Position
Definition at line 13786 of file NUC472_442.h.
| #define EMAC_INTSTS_MPCOVIF_Msk (0x1ul << EMAC_INTSTS_MPCOVIF_Pos) |
EMAC_T::INTSTS: MPCOVIF Mask
Definition at line 13784 of file NUC472_442.h.
| #define EMAC_INTSTS_MPCOVIF_Pos (7) |
EMAC_T::INTSTS: MPCOVIF Position
Definition at line 13783 of file NUC472_442.h.
| #define EMAC_INTSTS_NCSIF_Msk (0x1ul << EMAC_INTSTS_NCSIF_Pos) |
EMAC_T::INTSTS: NCSIF Mask
Definition at line 13817 of file NUC472_442.h.
| #define EMAC_INTSTS_NCSIF_Pos (20) |
EMAC_T::INTSTS: NCSIF Position
Definition at line 13816 of file NUC472_442.h.
| #define EMAC_INTSTS_RDUIF_Msk (0x1ul << EMAC_INTSTS_RDUIF_Pos) |
EMAC_T::INTSTS: RDUIF Mask
Definition at line 13793 of file NUC472_442.h.
| #define EMAC_INTSTS_RDUIF_Pos (10) |
EMAC_T::INTSTS: RDUIF Position
Definition at line 13792 of file NUC472_442.h.
| #define EMAC_INTSTS_RPIF_Msk (0x1ul << EMAC_INTSTS_RPIF_Pos) |
EMAC_T::INTSTS: RPIF Mask
Definition at line 13781 of file NUC472_442.h.
| #define EMAC_INTSTS_RPIF_Pos (6) |
EMAC_T::INTSTS: RPIF Position
Definition at line 13780 of file NUC472_442.h.
| #define EMAC_INTSTS_RXBEIF_Msk (0x1ul << EMAC_INTSTS_RXBEIF_Pos) |
EMAC_T::INTSTS: RXBEIF Mask
Definition at line 13796 of file NUC472_442.h.
| #define EMAC_INTSTS_RXBEIF_Pos (11) |
EMAC_T::INTSTS: RXBEIF Position
Definition at line 13795 of file NUC472_442.h.
| #define EMAC_INTSTS_RXGDIF_Msk (0x1ul << EMAC_INTSTS_RXGDIF_Pos) |
EMAC_T::INTSTS: RXGDIF Mask
Definition at line 13775 of file NUC472_442.h.
| #define EMAC_INTSTS_RXGDIF_Pos (4) |
EMAC_T::INTSTS: RXGDIF Position
Definition at line 13774 of file NUC472_442.h.
| #define EMAC_INTSTS_RXIF_Msk (0x1ul << EMAC_INTSTS_RXIF_Pos) |
EMAC_T::INTSTS: RXIF Mask
Definition at line 13763 of file NUC472_442.h.
| #define EMAC_INTSTS_RXIF_Pos (0) |
EMAC_T::INTSTS: RXIF Position
Definition at line 13762 of file NUC472_442.h.
| #define EMAC_INTSTS_RXOVIF_Msk (0x1ul << EMAC_INTSTS_RXOVIF_Pos) |
EMAC_T::INTSTS: RXOVIF Mask
Definition at line 13769 of file NUC472_442.h.
| #define EMAC_INTSTS_RXOVIF_Pos (2) |
EMAC_T::INTSTS: RXOVIF Position
Definition at line 13768 of file NUC472_442.h.
| #define EMAC_INTSTS_TDUIF_Msk (0x1ul << EMAC_INTSTS_TDUIF_Pos) |
EMAC_T::INTSTS: TDUIF Mask
Definition at line 13826 of file NUC472_442.h.
| #define EMAC_INTSTS_TDUIF_Pos (23) |
EMAC_T::INTSTS: TDUIF Position
Definition at line 13825 of file NUC472_442.h.
| #define EMAC_INTSTS_TSALMIF_Msk (0x1ul << EMAC_INTSTS_TSALMIF_Pos) |
EMAC_T::INTSTS: TSALMIF Mask
Definition at line 13832 of file NUC472_442.h.
| #define EMAC_INTSTS_TSALMIF_Pos (28) |
EMAC_T::INTSTS: TSALMIF Position
Definition at line 13831 of file NUC472_442.h.
| #define EMAC_INTSTS_TXABTIF_Msk (0x1ul << EMAC_INTSTS_TXABTIF_Pos) |
EMAC_T::INTSTS: TXABTIF Mask
Definition at line 13820 of file NUC472_442.h.
| #define EMAC_INTSTS_TXABTIF_Pos (21) |
EMAC_T::INTSTS: TXABTIF Position
Definition at line 13819 of file NUC472_442.h.
| #define EMAC_INTSTS_TXBEIF_Msk (0x1ul << EMAC_INTSTS_TXBEIF_Pos) |
EMAC_T::INTSTS: TXBEIF Mask
Definition at line 13829 of file NUC472_442.h.
| #define EMAC_INTSTS_TXBEIF_Pos (24) |
EMAC_T::INTSTS: TXBEIF Position
Definition at line 13828 of file NUC472_442.h.
| #define EMAC_INTSTS_TXCPIF_Msk (0x1ul << EMAC_INTSTS_TXCPIF_Pos) |
EMAC_T::INTSTS: TXCPIF Mask
Definition at line 13811 of file NUC472_442.h.
| #define EMAC_INTSTS_TXCPIF_Pos (18) |
EMAC_T::INTSTS: TXCPIF Position
Definition at line 13810 of file NUC472_442.h.
| #define EMAC_INTSTS_TXIF_Msk (0x1ul << EMAC_INTSTS_TXIF_Pos) |
EMAC_T::INTSTS: TXIF Mask
Definition at line 13805 of file NUC472_442.h.
| #define EMAC_INTSTS_TXIF_Pos (16) |
EMAC_T::INTSTS: TXIF Position
Definition at line 13804 of file NUC472_442.h.
| #define EMAC_INTSTS_TXUDIF_Msk (0x1ul << EMAC_INTSTS_TXUDIF_Pos) |
EMAC_T::INTSTS: TXUDIF Mask
Definition at line 13808 of file NUC472_442.h.
| #define EMAC_INTSTS_TXUDIF_Pos (17) |
EMAC_T::INTSTS: TXUDIF Position
Definition at line 13807 of file NUC472_442.h.
| #define EMAC_INTSTS_WOLIF_Msk (0x1ul << EMAC_INTSTS_WOLIF_Pos) |
EMAC_T::INTSTS: WOLIF Mask
Definition at line 13802 of file NUC472_442.h.
| #define EMAC_INTSTS_WOLIF_Pos (15) |
EMAC_T::INTSTS: WOLIF Position
Definition at line 13801 of file NUC472_442.h.
| #define EMAC_MIIMCTL_BUSY_Msk (0x1ul << EMAC_MIIMCTL_BUSY_Pos) |
EMAC_T::MIIMCTL: BUSY Mask
Definition at line 13664 of file NUC472_442.h.
| #define EMAC_MIIMCTL_BUSY_Pos (17) |
EMAC_T::MIIMCTL: BUSY Position
Definition at line 13663 of file NUC472_442.h.
| #define EMAC_MIIMCTL_MDCON_Msk (0x1ul << EMAC_MIIMCTL_MDCON_Pos) |
EMAC_T::MIIMCTL: MDCON Mask
Definition at line 13670 of file NUC472_442.h.
| #define EMAC_MIIMCTL_MDCON_Pos (19) |
EMAC_T::MIIMCTL: MDCON Position
Definition at line 13669 of file NUC472_442.h.
| #define EMAC_MIIMCTL_PHYADDR_Msk (0x1ful << EMAC_MIIMCTL_PHYADDR_Pos) |
EMAC_T::MIIMCTL: PHYADDR Mask
Definition at line 13658 of file NUC472_442.h.
| #define EMAC_MIIMCTL_PHYADDR_Pos (8) |
EMAC_T::MIIMCTL: PHYADDR Position
Definition at line 13657 of file NUC472_442.h.
| #define EMAC_MIIMCTL_PHYREG_Msk (0x1ful << EMAC_MIIMCTL_PHYREG_Pos) |
EMAC_T::MIIMCTL: PHYREG Mask
Definition at line 13655 of file NUC472_442.h.
| #define EMAC_MIIMCTL_PHYREG_Pos (0) |
EMAC_T::MIIMCTL: PHYREG Position
Definition at line 13654 of file NUC472_442.h.
| #define EMAC_MIIMCTL_PREAMSP_Msk (0x1ul << EMAC_MIIMCTL_PREAMSP_Pos) |
EMAC_T::MIIMCTL: PREAMSP Mask
Definition at line 13667 of file NUC472_442.h.
| #define EMAC_MIIMCTL_PREAMSP_Pos (18) |
EMAC_T::MIIMCTL: PREAMSP Position
Definition at line 13666 of file NUC472_442.h.
| #define EMAC_MIIMCTL_WRITE_Msk (0x1ul << EMAC_MIIMCTL_WRITE_Pos) |
EMAC_T::MIIMCTL: WRITE Mask
Definition at line 13661 of file NUC472_442.h.
| #define EMAC_MIIMCTL_WRITE_Pos (16) |
EMAC_T::MIIMCTL: WRITE Position
Definition at line 13660 of file NUC472_442.h.
| #define EMAC_MIIMDAT_DATA_Msk (0xfffful << EMAC_MIIMDAT_DATA_Pos) |
EMAC_T::MIIMDAT: DATA Mask
Definition at line 13652 of file NUC472_442.h.
| #define EMAC_MIIMDAT_DATA_Pos (0) |
EMAC_T::MIIMDAT: DATA Position
Definition at line 13651 of file NUC472_442.h.
| #define EMAC_MPCNT_MPCNT_Msk (0xfffful << EMAC_MPCNT_MPCNT_Pos) |
EMAC_T::MPCNT: MPCNT Mask
Definition at line 13862 of file NUC472_442.h.
| #define EMAC_MPCNT_MPCNT_Pos (0) |
EMAC_T::MPCNT: MPCNT Position
Definition at line 13861 of file NUC472_442.h.
| #define EMAC_MRFL_MRFL_Msk (0xfffful << EMAC_MRFL_MRFL_Pos) |
EMAC_T::MRFL: MRFL Mask
Definition at line 13688 of file NUC472_442.h.
| #define EMAC_MRFL_MRFL_Pos (0) |
EMAC_T::MRFL: MRFL Position
Definition at line 13687 of file NUC472_442.h.
| #define EMAC_RPCNT_RPCNT_Msk (0xfffful << EMAC_RPCNT_RPCNT_Pos) |
EMAC_T::RPCNT: RPCNT Mask
Definition at line 13865 of file NUC472_442.h.
| #define EMAC_RPCNT_RPCNT_Pos (0) |
EMAC_T::RPCNT: RPCNT Position
Definition at line 13864 of file NUC472_442.h.
| #define EMAC_RXDSA_RXDSA_Msk (0xfffffffful << EMAC_RXDSA_RXDSA_Pos) |
EMAC_T::RXDSA: RXDSA Mask
Definition at line 13601 of file NUC472_442.h.
| #define EMAC_RXDSA_RXDSA_Pos (0) |
EMAC_T::RXDSA: RXDSA Position
Definition at line 13600 of file NUC472_442.h.
| #define EMAC_RXST_RXST_Msk (0xfffffffful << EMAC_RXST_RXST_Pos) |
EMAC_T::RXST: RXST Mask
Definition at line 13685 of file NUC472_442.h.
| #define EMAC_RXST_RXST_Pos (0) |
EMAC_T::RXST: RXST Position
Definition at line 13684 of file NUC472_442.h.
| #define EMAC_TSADDEND_ADDEND_Msk (0xfffffffful << EMAC_TSADDEND_ADDEND_Pos) |
EMAC_T::TSADDEND: ADDEND Mask
Definition at line 13907 of file NUC472_442.h.
| #define EMAC_TSADDEND_ADDEND_Pos (0) |
EMAC_T::TSADDEND: ADDEND Position
Definition at line 13906 of file NUC472_442.h.
| #define EMAC_TSCTL_TSALMEN_Msk (0x1ul << EMAC_TSCTL_TSALMEN_Pos) |
EMAC_T::TSCTL: TSALMEN Mask
Definition at line 13895 of file NUC472_442.h.
| #define EMAC_TSCTL_TSALMEN_Pos (5) |
EMAC_T::TSCTL: TSALMEN Position
Definition at line 13894 of file NUC472_442.h.
| #define EMAC_TSCTL_TSEN_Msk (0x1ul << EMAC_TSCTL_TSEN_Pos) |
EMAC_T::TSCTL: TSEN Mask
Definition at line 13883 of file NUC472_442.h.
| #define EMAC_TSCTL_TSEN_Pos (0) |
EMAC_T::TSCTL: TSEN Position
Definition at line 13882 of file NUC472_442.h.
| #define EMAC_TSCTL_TSIEN_Msk (0x1ul << EMAC_TSCTL_TSIEN_Pos) |
EMAC_T::TSCTL: TSIEN Mask
Definition at line 13886 of file NUC472_442.h.
| #define EMAC_TSCTL_TSIEN_Pos (1) |
EMAC_T::TSCTL: TSIEN Position
Definition at line 13885 of file NUC472_442.h.
| #define EMAC_TSCTL_TSMODE_Msk (0x1ul << EMAC_TSCTL_TSMODE_Pos) |
EMAC_T::TSCTL: TSMODE Mask
Definition at line 13889 of file NUC472_442.h.
| #define EMAC_TSCTL_TSMODE_Pos (2) |
EMAC_T::TSCTL: TSMODE Position
Definition at line 13888 of file NUC472_442.h.
| #define EMAC_TSCTL_TSUPDATE_Msk (0x1ul << EMAC_TSCTL_TSUPDATE_Pos) |
EMAC_T::TSCTL: TSUPDATE Mask
Definition at line 13892 of file NUC472_442.h.
| #define EMAC_TSCTL_TSUPDATE_Pos (3) |
EMAC_T::TSCTL: TSUPDATE Position
Definition at line 13891 of file NUC472_442.h.
| #define EMAC_TSINC_CNTINC_Msk (0xfful << EMAC_TSINC_CNTINC_Pos) |
EMAC_T::TSINC: CNTINC Mask
Definition at line 13904 of file NUC472_442.h.
| #define EMAC_TSINC_CNTINC_Pos (0) |
EMAC_T::TSINC: CNTINC Position
Definition at line 13903 of file NUC472_442.h.
| #define EMAC_TSSEC_SEC_Msk (0xfffffffful << EMAC_TSSEC_SEC_Pos) |
EMAC_T::TSSEC: SEC Mask
Definition at line 13898 of file NUC472_442.h.
| #define EMAC_TSSEC_SEC_Pos (0) |
EMAC_T::TSSEC: SEC Position
Definition at line 13897 of file NUC472_442.h.
| #define EMAC_TSSUBSEC_SUBSEC_Msk (0xfffffffful << EMAC_TSSUBSEC_SUBSEC_Pos) |
EMAC_T::TSSUBSEC: SUBSEC Mask
Definition at line 13901 of file NUC472_442.h.
| #define EMAC_TSSUBSEC_SUBSEC_Pos (0) |
EMAC_T::TSSUBSEC: SUBSEC Position
Definition at line 13900 of file NUC472_442.h.
| #define EMAC_TXDSA_TXDSA_Msk (0xfffffffful << EMAC_TXDSA_TXDSA_Pos) |
EMAC_T::TXDSA: TXDSA Mask
Definition at line 13598 of file NUC472_442.h.
| #define EMAC_TXDSA_TXDSA_Pos (0) |
EMAC_T::TXDSA: TXDSA Position
Definition at line 13597 of file NUC472_442.h.
| #define EMAC_TXST_TXST_Msk (0xfffffffful << EMAC_TXST_TXST_Pos) |
EMAC_T::TXST: TXST Mask
Definition at line 13682 of file NUC472_442.h.
| #define EMAC_TXST_TXST_Pos (0) |
EMAC_T::TXST: TXST Position
Definition at line 13681 of file NUC472_442.h.
| #define EMAC_UPDSEC_SEC_Msk (0xfffffffful << EMAC_UPDSEC_SEC_Pos) |
EMAC_T::UPDSEC: SEC Mask
Definition at line 13910 of file NUC472_442.h.
| #define EMAC_UPDSEC_SEC_Pos (0) |
EMAC_T::UPDSEC: SEC Position
Definition at line 13909 of file NUC472_442.h.
| #define EMAC_UPDSUBSEC_SUBSEC_Msk (0xfffffffful << EMAC_UPDSUBSEC_SUBSEC_Pos) |
EMAC_T::UPDSUBSEC: SUBSEC Mask
Definition at line 13913 of file NUC472_442.h.
| #define EMAC_UPDSUBSEC_SUBSEC_Pos (0) |
EMAC_T::UPDSUBSEC: SUBSEC Position
Definition at line 13912 of file NUC472_442.h.
| #define EPWM_ASYMCMP0_CMP_Msk (0xfffful << EPWM_ASYMCMP0_CMP_Pos) |
EPWM_T::ASYMCMP0: CMP Mask
Definition at line 14514 of file NUC472_442.h.
| #define EPWM_ASYMCMP0_CMP_Pos (0) |
EPWM_T::ASYMCMP0: CMP Position
Definition at line 14513 of file NUC472_442.h.
| #define EPWM_ASYMCMP2_CMP_Msk (0xfffful << EPWM_ASYMCMP2_CMP_Pos) |
EPWM_T::ASYMCMP2: CMP Mask
Definition at line 14517 of file NUC472_442.h.
| #define EPWM_ASYMCMP2_CMP_Pos (0) |
EPWM_T::ASYMCMP2: CMP Position
Definition at line 14516 of file NUC472_442.h.
| #define EPWM_ASYMCMP4_CMP_Msk (0xfffful << EPWM_ASYMCMP4_CMP_Pos) |
EPWM_T::ASYMCMP4: CMP Mask
Definition at line 14520 of file NUC472_442.h.
| #define EPWM_ASYMCMP4_CMP_Pos (0) |
EPWM_T::ASYMCMP4: CMP Position
Definition at line 14519 of file NUC472_442.h.
| #define EPWM_ASYMCTL_ASYMEN_Msk (0x1ul << EPWM_ASYMCTL_ASYMEN_Pos) |
EPWM_T::ASYMCTL: ASYMEN Mask
Definition at line 14541 of file NUC472_442.h.
| #define EPWM_ASYMCTL_ASYMEN_Pos (0) |
EPWM_T::ASYMCTL: ASYMEN Position
Definition at line 14540 of file NUC472_442.h.
| #define EPWM_ASYMCTL_ASYMMODE0_Msk (0x3ul << EPWM_ASYMCTL_ASYMMODE0_Pos) |
EPWM_T::ASYMCTL: ASYMMODE0 Mask
Definition at line 14544 of file NUC472_442.h.
| #define EPWM_ASYMCTL_ASYMMODE0_Pos (8) |
EPWM_T::ASYMCTL: ASYMMODE0 Position
Definition at line 14543 of file NUC472_442.h.
| #define EPWM_ASYMCTL_ASYMMODE2_Msk (0x3ul << EPWM_ASYMCTL_ASYMMODE2_Pos) |
EPWM_T::ASYMCTL: ASYMMODE2 Mask
Definition at line 14547 of file NUC472_442.h.
| #define EPWM_ASYMCTL_ASYMMODE2_Pos (16) |
EPWM_T::ASYMCTL: ASYMMODE2 Position
Definition at line 14546 of file NUC472_442.h.
| #define EPWM_ASYMCTL_ASYMMODE4_Msk (0x3ul << EPWM_ASYMCTL_ASYMMODE4_Pos) |
EPWM_T::ASYMCTL: ASYMMODE4 Mask
Definition at line 14550 of file NUC472_442.h.
| #define EPWM_ASYMCTL_ASYMMODE4_Pos (24) |
EPWM_T::ASYMCTL: ASYMMODE4 Position
Definition at line 14549 of file NUC472_442.h.
| #define EPWM_BRKOUT_BRKOUT_Msk (0x3ful << EPWM_BRKOUT_BRKOUT_Pos) |
EPWM_T::BRKOUT: BRKOUT Mask
Definition at line 14535 of file NUC472_442.h.
| #define EPWM_BRKOUT_BRKOUT_Pos (0) |
EPWM_T::BRKOUT: BRKOUT Position
Definition at line 14534 of file NUC472_442.h.
| #define EPWM_CMPDAT0_CMP_Msk (0xfffful << EPWM_CMPDAT0_CMP_Pos) |
EPWM_T::CMPDAT0: CMP Mask
Definition at line 14499 of file NUC472_442.h.
| #define EPWM_CMPDAT0_CMP_Pos (0) |
EPWM_T::CMPDAT0: CMP Position
Definition at line 14498 of file NUC472_442.h.
| #define EPWM_CMPDAT2_CMP_Msk (0xfffful << EPWM_CMPDAT2_CMP_Pos) |
EPWM_T::CMPDAT2: CMP Mask
Definition at line 14502 of file NUC472_442.h.
| #define EPWM_CMPDAT2_CMP_Pos (0) |
EPWM_T::CMPDAT2: CMP Position
Definition at line 14501 of file NUC472_442.h.
| #define EPWM_CMPDAT4_CMP_Msk (0xfffful << EPWM_CMPDAT4_CMP_Pos) |
EPWM_T::CMPDAT4: CMP Mask
Definition at line 14505 of file NUC472_442.h.
| #define EPWM_CMPDAT4_CMP_Pos (0) |
EPWM_T::CMPDAT4: CMP Position
Definition at line 14504 of file NUC472_442.h.
| #define EPWM_CTL_BRK0NFDIS_Msk (0x1ul << EPWM_CTL_BRK0NFDIS_Pos) |
EPWM_T::CTL: BRK0NFDIS Mask
Definition at line 14460 of file NUC472_442.h.
| #define EPWM_CTL_BRK0NFDIS_Pos (28) |
EPWM_T::CTL: BRK0NFDIS Position
Definition at line 14459 of file NUC472_442.h.
| #define EPWM_CTL_BRK0NFSEL_Msk (0x3ul << EPWM_CTL_BRK0NFSEL_Pos) |
EPWM_T::CTL: BRK0NFSEL Mask
Definition at line 14442 of file NUC472_442.h.
| #define EPWM_CTL_BRK0NFSEL_Pos (20) |
EPWM_T::CTL: BRK0NFSEL Position
Definition at line 14441 of file NUC472_442.h.
| #define EPWM_CTL_BRK1NFDIS_Msk (0x1ul << EPWM_CTL_BRK1NFDIS_Pos) |
EPWM_T::CTL: BRK1NFDIS Mask
Definition at line 14463 of file NUC472_442.h.
| #define EPWM_CTL_BRK1NFDIS_Pos (29) |
EPWM_T::CTL: BRK1NFDIS Position
Definition at line 14462 of file NUC472_442.h.
| #define EPWM_CTL_BRK1NFSEL_Msk (0x3ul << EPWM_CTL_BRK1NFSEL_Pos) |
EPWM_T::CTL: BRK1NFSEL Mask
Definition at line 14445 of file NUC472_442.h.
| #define EPWM_CTL_BRK1NFSEL_Pos (22) |
EPWM_T::CTL: BRK1NFSEL Position
Definition at line 14444 of file NUC472_442.h.
| #define EPWM_CTL_BRK1SEL_Msk (0x3ul << EPWM_CTL_BRK1SEL_Pos) |
EPWM_T::CTL: BRK1SEL Mask
Definition at line 14439 of file NUC472_442.h.
| #define EPWM_CTL_BRK1SEL_Pos (18) |
EPWM_T::CTL: BRK1SEL Position
Definition at line 14438 of file NUC472_442.h.
| #define EPWM_CTL_BRKIEN_Msk (0x1ul << EPWM_CTL_BRKIEN_Pos) |
EPWM_T::CTL: BRKIEN Mask
Definition at line 14403 of file NUC472_442.h.
| #define EPWM_CTL_BRKIEN_Pos (5) |
EPWM_T::CTL: BRKIEN Position
Definition at line 14402 of file NUC472_442.h.
| #define EPWM_CTL_BRKP0EN_Msk (0x1ul << EPWM_CTL_BRKP0EN_Pos) |
EPWM_T::CTL: BRKP0EN Mask
Definition at line 14433 of file NUC472_442.h.
| #define EPWM_CTL_BRKP0EN_Pos (16) |
EPWM_T::CTL: BRKP0EN Position
Definition at line 14432 of file NUC472_442.h.
| #define EPWM_CTL_BRKP0INV_Msk (0x1ul << EPWM_CTL_BRKP0INV_Pos) |
EPWM_T::CTL: BRKP0INV Mask
Definition at line 14427 of file NUC472_442.h.
| #define EPWM_CTL_BRKP0INV_Pos (14) |
EPWM_T::CTL: BRKP0INV Position
Definition at line 14426 of file NUC472_442.h.
| #define EPWM_CTL_BRKP1EN_Msk (0x1ul << EPWM_CTL_BRKP1EN_Pos) |
EPWM_T::CTL: BRKP1EN Mask
Definition at line 14436 of file NUC472_442.h.
| #define EPWM_CTL_BRKP1EN_Pos (17) |
EPWM_T::CTL: BRKP1EN Position
Definition at line 14435 of file NUC472_442.h.
| #define EPWM_CTL_BRKP1INV_Msk (0x1ul << EPWM_CTL_BRKP1INV_Pos) |
EPWM_T::CTL: BRKP1INV Mask
Definition at line 14430 of file NUC472_442.h.
| #define EPWM_CTL_BRKP1INV_Pos (15) |
EPWM_T::CTL: BRKP1INV Position
Definition at line 14429 of file NUC472_442.h.
| #define EPWM_CTL_CLKDIV_Msk (0x3ul << EPWM_CTL_CLKDIV_Pos) |
EPWM_T::CTL: CLKDIV Mask
Definition at line 14397 of file NUC472_442.h.
| #define EPWM_CTL_CLKDIV_Pos (2) |
EPWM_T::CTL: CLKDIV Position
Definition at line 14396 of file NUC472_442.h.
| #define EPWM_CTL_CNTCLR_Msk (0x1ul << EPWM_CTL_CNTCLR_Pos) |
EPWM_T::CTL: CNTCLR Mask
Definition at line 14418 of file NUC472_442.h.
| #define EPWM_CTL_CNTCLR_Pos (11) |
EPWM_T::CTL: CNTCLR Position
Definition at line 14417 of file NUC472_442.h.
| #define EPWM_CTL_CNTEN_Msk (0x1ul << EPWM_CTL_CNTEN_Pos) |
EPWM_T::CTL: CNTEN Mask
Definition at line 14409 of file NUC472_442.h.
| #define EPWM_CTL_CNTEN_Pos (7) |
EPWM_T::CTL: CNTEN Position
Definition at line 14408 of file NUC472_442.h.
| #define EPWM_CTL_CNTTYPE_Msk (0x1ul << EPWM_CTL_CNTTYPE_Pos) |
EPWM_T::CTL: CNTTYPE Mask
Definition at line 14421 of file NUC472_442.h.
| #define EPWM_CTL_CNTTYPE_Pos (12) |
EPWM_T::CTL: CNTTYPE Position
Definition at line 14420 of file NUC472_442.h.
| #define EPWM_CTL_CPO0BKEN_Msk (0x1ul << EPWM_CTL_CPO0BKEN_Pos) |
EPWM_T::CTL: CPO0BKEN Mask
Definition at line 14448 of file NUC472_442.h.
| #define EPWM_CTL_CPO0BKEN_Pos (24) |
EPWM_T::CTL: CPO0BKEN Position
Definition at line 14447 of file NUC472_442.h.
| #define EPWM_CTL_CPO1BKEN_Msk (0x1ul << EPWM_CTL_CPO1BKEN_Pos) |
EPWM_T::CTL: CPO1BKEN Mask
Definition at line 14451 of file NUC472_442.h.
| #define EPWM_CTL_CPO1BKEN_Pos (25) |
EPWM_T::CTL: CPO1BKEN Position
Definition at line 14450 of file NUC472_442.h.
| #define EPWM_CTL_CPO2BKEN_Msk (0x1ul << EPWM_CTL_CPO2BKEN_Pos) |
EPWM_T::CTL: CPO2BKEN Mask
Definition at line 14454 of file NUC472_442.h.
| #define EPWM_CTL_CPO2BKEN_Pos (26) |
EPWM_T::CTL: CPO2BKEN Position
Definition at line 14453 of file NUC472_442.h.
| #define EPWM_CTL_CTRLD_Msk (0x1ul << EPWM_CTL_CTRLD_Pos) |
EPWM_T::CTL: CTRLD Mask
Definition at line 14466 of file NUC472_442.h.
| #define EPWM_CTL_CTRLD_Pos (31) |
EPWM_T::CTL: CTRLD Position
Definition at line 14465 of file NUC472_442.h.
| #define EPWM_CTL_GROUPEN_Msk (0x1ul << EPWM_CTL_GROUPEN_Pos) |
EPWM_T::CTL: GROUPEN Mask
Definition at line 14424 of file NUC472_442.h.
| #define EPWM_CTL_GROUPEN_Pos (13) |
EPWM_T::CTL: GROUPEN Position
Definition at line 14423 of file NUC472_442.h.
| #define EPWM_CTL_INTTYPE_Msk (0x1ul << EPWM_CTL_INTTYPE_Pos) |
EPWM_T::CTL: INTTYPE Mask
Definition at line 14412 of file NUC472_442.h.
| #define EPWM_CTL_INTTYPE_Pos (8) |
EPWM_T::CTL: INTTYPE Position
Definition at line 14411 of file NUC472_442.h.
| #define EPWM_CTL_LOAD_Msk (0x1ul << EPWM_CTL_LOAD_Pos) |
EPWM_T::CTL: LOAD Mask
Definition at line 14406 of file NUC472_442.h.
| #define EPWM_CTL_LOAD_Pos (6) |
EPWM_T::CTL: LOAD Position
Definition at line 14405 of file NUC472_442.h.
| #define EPWM_CTL_LVDBKEN_Msk (0x1ul << EPWM_CTL_LVDBKEN_Pos) |
EPWM_T::CTL: LVDBKEN Mask
Definition at line 14457 of file NUC472_442.h.
| #define EPWM_CTL_LVDBKEN_Pos (27) |
EPWM_T::CTL: LVDBKEN Position
Definition at line 14456 of file NUC472_442.h.
| #define EPWM_CTL_MODE_Msk (0x3ul << EPWM_CTL_MODE_Pos) |
EPWM_T::CTL: MODE Mask
Definition at line 14394 of file NUC472_442.h.
| #define EPWM_CTL_MODE_Pos (0) |
@addtogroup EPWM_CONST EPWM Bit Field Definition Constant Definitions for EPWM Controller
EPWM_T::CTL: MODE Position
Definition at line 14393 of file NUC472_442.h.
| #define EPWM_CTL_PINV_Msk (0x1ul << EPWM_CTL_PINV_Pos) |
EPWM_T::CTL: PINV Mask
Definition at line 14415 of file NUC472_442.h.
| #define EPWM_CTL_PINV_Pos (9) |
EPWM_T::CTL: PINV Position
Definition at line 14414 of file NUC472_442.h.
| #define EPWM_CTL_PWMIEN_Msk (0x1ul << EPWM_CTL_PWMIEN_Pos) |
EPWM_T::CTL: PWMIEN Mask
Definition at line 14400 of file NUC472_442.h.
| #define EPWM_CTL_PWMIEN_Pos (4) |
EPWM_T::CTL: PWMIEN Position
Definition at line 14399 of file NUC472_442.h.
| #define EPWM_DTCTL_DTCNT_Msk (0x7fful << EPWM_DTCTL_DTCNT_Pos) |
EPWM_T::DTCTL: DTCNT Mask
Definition at line 14523 of file NUC472_442.h.
| #define EPWM_DTCTL_DTCNT_Pos (0) |
EPWM_T::DTCTL: DTCNT Position
Definition at line 14522 of file NUC472_442.h.
| #define EPWM_DTCTL_DTEN0_Msk (0x1ul << EPWM_DTCTL_DTEN0_Pos) |
EPWM_T::DTCTL: DTEN0 Mask
Definition at line 14526 of file NUC472_442.h.
| #define EPWM_DTCTL_DTEN0_Pos (16) |
EPWM_T::DTCTL: DTEN0 Position
Definition at line 14525 of file NUC472_442.h.
| #define EPWM_DTCTL_DTEN2_Msk (0x1ul << EPWM_DTCTL_DTEN2_Pos) |
EPWM_T::DTCTL: DTEN2 Mask
Definition at line 14529 of file NUC472_442.h.
| #define EPWM_DTCTL_DTEN2_Pos (17) |
EPWM_T::DTCTL: DTEN2 Position
Definition at line 14528 of file NUC472_442.h.
| #define EPWM_DTCTL_DTEN4_Msk (0x1ul << EPWM_DTCTL_DTEN4_Pos) |
EPWM_T::DTCTL: DTEN4 Mask
Definition at line 14532 of file NUC472_442.h.
| #define EPWM_DTCTL_DTEN4_Pos (18) |
EPWM_T::DTCTL: DTEN4 Position
Definition at line 14531 of file NUC472_442.h.
| #define EPWM_EINTCTL_EDGEIEN0_Msk (0x1ul << EPWM_EINTCTL_EDGEIEN0_Pos) |
EPWM_T::EINTCTL: EDGEIEN0 Mask
Definition at line 14556 of file NUC472_442.h.
| #define EPWM_EINTCTL_EDGEIEN0_Pos (0) |
EPWM_T::EINTCTL: EDGEIEN0 Position
Definition at line 14555 of file NUC472_442.h.
| #define EPWM_EINTCTL_EDGEIEN2_Msk (0x1ul << EPWM_EINTCTL_EDGEIEN2_Pos) |
EPWM_T::EINTCTL: EDGEIEN2 Mask
Definition at line 14559 of file NUC472_442.h.
| #define EPWM_EINTCTL_EDGEIEN2_Pos (1) |
EPWM_T::EINTCTL: EDGEIEN2 Position
Definition at line 14558 of file NUC472_442.h.
| #define EPWM_EINTCTL_EDGEIEN4_Msk (0x1ul << EPWM_EINTCTL_EDGEIEN4_Pos) |
EPWM_T::EINTCTL: EDGEIEN4 Mask
Definition at line 14562 of file NUC472_442.h.
| #define EPWM_EINTCTL_EDGEIEN4_Pos (2) |
EPWM_T::EINTCTL: EDGEIEN4 Position
Definition at line 14561 of file NUC472_442.h.
| #define EPWM_EINTCTL_EINTTYPE0_Msk (0x1ul << EPWM_EINTCTL_EINTTYPE0_Pos) |
EPWM_T::EINTCTL: EINTTYPE0 Mask
Definition at line 14565 of file NUC472_442.h.
| #define EPWM_EINTCTL_EINTTYPE0_Pos (8) |
EPWM_T::EINTCTL: EINTTYPE0 Position
Definition at line 14564 of file NUC472_442.h.
| #define EPWM_EINTCTL_EINTTYPE2_Msk (0x1ul << EPWM_EINTCTL_EINTTYPE2_Pos) |
EPWM_T::EINTCTL: EINTTYPE2 Mask
Definition at line 14568 of file NUC472_442.h.
| #define EPWM_EINTCTL_EINTTYPE2_Pos (9) |
EPWM_T::EINTCTL: EINTTYPE2 Position
Definition at line 14567 of file NUC472_442.h.
| #define EPWM_EINTCTL_EINTTYPE4_Msk (0x1ul << EPWM_EINTCTL_EINTTYPE4_Pos) |
EPWM_T::EINTCTL: EINTTYPE4 Mask
Definition at line 14571 of file NUC472_442.h.
| #define EPWM_EINTCTL_EINTTYPE4_Pos (10) |
EPWM_T::EINTCTL: EINTTYPE4 Position
Definition at line 14570 of file NUC472_442.h.
| #define EPWM_MSK_MSKDAT_Msk (0x3ful << EPWM_MSK_MSKDAT_Pos) |
EPWM_T::MSK: MSKDAT Mask
Definition at line 14511 of file NUC472_442.h.
| #define EPWM_MSK_MSKDAT_Pos (0) |
EPWM_T::MSK: MSKDAT Position
Definition at line 14510 of file NUC472_442.h.
| #define EPWM_MSKEN_MSKEN_Msk (0x3ful << EPWM_MSKEN_MSKEN_Pos) |
EPWM_T::MSKEN: MSKEN Mask
Definition at line 14508 of file NUC472_442.h.
| #define EPWM_MSKEN_MSKEN_Pos (0) |
EPWM_T::MSKEN: MSKEN Position
Definition at line 14507 of file NUC472_442.h.
| #define EPWM_NPCTL_NEGPOLAR_Msk (0x3ful << EPWM_NPCTL_NEGPOLAR_Pos) |
EPWM_T::NPCTL: NEGPOLAR Mask
Definition at line 14538 of file NUC472_442.h.
| #define EPWM_NPCTL_NEGPOLAR_Pos (0) |
EPWM_T::NPCTL: NEGPOLAR Position
Definition at line 14537 of file NUC472_442.h.
| #define EPWM_OUTEN0_EVENOUTEN_Msk (0x1ul << EPWM_OUTEN0_EVENOUTEN_Pos) |
EPWM_T::OUTEN0: EVENOUTEN Mask
Definition at line 14574 of file NUC472_442.h.
| #define EPWM_OUTEN0_EVENOUTEN_Pos (0) |
EPWM_T::OUTEN0: EVENOUTEN Position
Definition at line 14573 of file NUC472_442.h.
| #define EPWM_OUTEN0_ODDOUTEN_Msk (0x1ul << EPWM_OUTEN0_ODDOUTEN_Pos) |
EPWM_T::OUTEN0: ODDOUTEN Mask
Definition at line 14577 of file NUC472_442.h.
| #define EPWM_OUTEN0_ODDOUTEN_Pos (1) |
EPWM_T::OUTEN0: ODDOUTEN Position
Definition at line 14576 of file NUC472_442.h.
| #define EPWM_PERIOD_PERIOD_Msk (0xfffful << EPWM_PERIOD_PERIOD_Pos) |
EPWM_T::PERIOD: PERIOD Mask
Definition at line 14496 of file NUC472_442.h.
| #define EPWM_PERIOD_PERIOD_Pos (0) |
EPWM_T::PERIOD: PERIOD Position
Definition at line 14495 of file NUC472_442.h.
| #define EPWM_PERIODCNT_PERIODCNT_Msk (0xful << EPWM_PERIODCNT_PERIODCNT_Pos) |
EPWM_T::PERIODCNT: PERIODCNT Mask
Definition at line 14553 of file NUC472_442.h.
| #define EPWM_PERIODCNT_PERIODCNT_Pos (0) |
EPWM_T::PERIODCNT: PERIODCNT Position
Definition at line 14552 of file NUC472_442.h.
| #define EPWM_STATUS_BRK0LOCK_Msk (0x1ul << EPWM_STATUS_BRK0LOCK_Pos) |
EPWM_T::STATUS: BRK0LOCK Mask
Definition at line 14487 of file NUC472_442.h.
| #define EPWM_STATUS_BRK0LOCK_Pos (8) |
EPWM_T::STATUS: BRK0LOCK Position
Definition at line 14486 of file NUC472_442.h.
| #define EPWM_STATUS_BRK0STS_Msk (0x1ul << EPWM_STATUS_BRK0STS_Pos) |
EPWM_T::STATUS: BRK0STS Mask
Definition at line 14490 of file NUC472_442.h.
| #define EPWM_STATUS_BRK0STS_Pos (24) |
EPWM_T::STATUS: BRK0STS Position
Definition at line 14489 of file NUC472_442.h.
| #define EPWM_STATUS_BRK1STS_Msk (0x1ul << EPWM_STATUS_BRK1STS_Pos) |
EPWM_T::STATUS: BRK1STS Mask
Definition at line 14493 of file NUC472_442.h.
| #define EPWM_STATUS_BRK1STS_Pos (25) |
EPWM_T::STATUS: BRK1STS Position
Definition at line 14492 of file NUC472_442.h.
| #define EPWM_STATUS_BRKIF0_Msk (0x1ul << EPWM_STATUS_BRKIF0_Pos) |
EPWM_T::STATUS: BRKIF0 Mask
Definition at line 14469 of file NUC472_442.h.
| #define EPWM_STATUS_BRKIF0_Pos (0) |
EPWM_T::STATUS: BRKIF0 Position
Definition at line 14468 of file NUC472_442.h.
| #define EPWM_STATUS_BRKIF1_Msk (0x1ul << EPWM_STATUS_BRKIF1_Pos) |
EPWM_T::STATUS: BRKIF1 Mask
Definition at line 14472 of file NUC472_442.h.
| #define EPWM_STATUS_BRKIF1_Pos (1) |
EPWM_T::STATUS: BRKIF1 Position
Definition at line 14471 of file NUC472_442.h.
| #define EPWM_STATUS_EIF0_Msk (0x1ul << EPWM_STATUS_EIF0_Pos) |
EPWM_T::STATUS: EIF0 Mask
Definition at line 14478 of file NUC472_442.h.
| #define EPWM_STATUS_EIF0_Pos (4) |
EPWM_T::STATUS: EIF0 Position
Definition at line 14477 of file NUC472_442.h.
| #define EPWM_STATUS_EIF2_Msk (0x1ul << EPWM_STATUS_EIF2_Pos) |
EPWM_T::STATUS: EIF2 Mask
Definition at line 14481 of file NUC472_442.h.
| #define EPWM_STATUS_EIF2_Pos (5) |
EPWM_T::STATUS: EIF2 Position
Definition at line 14480 of file NUC472_442.h.
| #define EPWM_STATUS_EIF4_Msk (0x1ul << EPWM_STATUS_EIF4_Pos) |
EPWM_T::STATUS: EIF4 Mask
Definition at line 14484 of file NUC472_442.h.
| #define EPWM_STATUS_EIF4_Pos (6) |
EPWM_T::STATUS: EIF4 Position
Definition at line 14483 of file NUC472_442.h.
| #define EPWM_STATUS_PIF_Msk (0x1ul << EPWM_STATUS_PIF_Pos) |
EPWM_T::STATUS: PIF Mask
Definition at line 14475 of file NUC472_442.h.
| #define EPWM_STATUS_PIF_Pos (2) |
EPWM_T::STATUS: PIF Position
Definition at line 14474 of file NUC472_442.h.
| #define FMC_DFBA_DFBA_Msk (0xfffffffful << FMC_DFBA_DFBA_Pos) |
FMC_T::DFBA: DFBA Mask
Definition at line 14943 of file NUC472_442.h.
| #define FMC_DFBA_DFBA_Pos (0) |
FMC_T::DFBA: DFBA Position
Definition at line 14942 of file NUC472_442.h.
| #define FMC_FBWP_BWP_Msk (0xfffffffful << FMC_FBWP_BWP_Pos) |
FMC_T::FBWP: BWP Mask
Definition at line 14964 of file NUC472_442.h.
| #define FMC_FBWP_BWP_Pos (0) |
FMC_T::FBWP: BWP Position
Definition at line 14963 of file NUC472_442.h.
| #define FMC_FTCTL_FOM_Msk (0x7ul << FMC_FTCTL_FOM_Pos) |
FMC_T::FTCTL: FOM Mask
Definition at line 14946 of file NUC472_442.h.
| #define FMC_FTCTL_FOM_Pos (4) |
FMC_T::FTCTL: FOM Position
Definition at line 14945 of file NUC472_442.h.
| #define FMC_ISPADDR_ISPADDR_Msk (0xfffffffful << FMC_ISPADDR_ISPADDR_Pos) |
FMC_T::ISPADDR: ISPADDR Mask
Definition at line 14931 of file NUC472_442.h.
| #define FMC_ISPADDR_ISPADDR_Pos (0) |
FMC_T::ISPADDR: ISPADDR Position
Definition at line 14930 of file NUC472_442.h.
| #define FMC_ISPCMD_CMD_Msk (0x3ful << FMC_ISPCMD_CMD_Pos) |
FMC_T::ISPCMD: CMD Mask
Definition at line 14937 of file NUC472_442.h.
| #define FMC_ISPCMD_CMD_Pos (0) |
FMC_T::ISPCMD: CMD Position
Definition at line 14936 of file NUC472_442.h.
| #define FMC_ISPCTL_APUEN_Msk (0x1ul << FMC_ISPCTL_APUEN_Pos) |
FMC_T::ISPCTL: APUEN Mask
Definition at line 14919 of file NUC472_442.h.
| #define FMC_ISPCTL_APUEN_Pos (3) |
FMC_T::ISPCTL: APUEN Position
Definition at line 14918 of file NUC472_442.h.
| #define FMC_ISPCTL_BS_Msk (0x1ul << FMC_ISPCTL_BS_Pos) |
FMC_T::ISPCTL: BS Mask
Definition at line 14916 of file NUC472_442.h.
| #define FMC_ISPCTL_BS_Pos (1) |
FMC_T::ISPCTL: BS Position
Definition at line 14915 of file NUC472_442.h.
| #define FMC_ISPCTL_CFGUEN_Msk (0x1ul << FMC_ISPCTL_CFGUEN_Pos) |
FMC_T::ISPCTL: CFGUEN Mask
Definition at line 14922 of file NUC472_442.h.
| #define FMC_ISPCTL_CFGUEN_Pos (4) |
FMC_T::ISPCTL: CFGUEN Position
Definition at line 14921 of file NUC472_442.h.
| #define FMC_ISPCTL_ISPEN_Msk (0x1ul << FMC_ISPCTL_ISPEN_Pos) |
FMC_T::ISPCTL: ISPEN Mask
Definition at line 14913 of file NUC472_442.h.
| #define FMC_ISPCTL_ISPEN_Pos (0) |
@addtogroup FMC_CONST FMC Bit Field Definition Constant Definitions for FMC Controller
FMC_T::ISPCTL: ISPEN Position
Definition at line 14912 of file NUC472_442.h.
| #define FMC_ISPCTL_ISPFF_Msk (0x1ul << FMC_ISPCTL_ISPFF_Pos) |
FMC_T::ISPCTL: ISPFF Mask
Definition at line 14928 of file NUC472_442.h.
| #define FMC_ISPCTL_ISPFF_Pos (6) |
FMC_T::ISPCTL: ISPFF Position
Definition at line 14927 of file NUC472_442.h.
| #define FMC_ISPCTL_LDUEN_Msk (0x1ul << FMC_ISPCTL_LDUEN_Pos) |
FMC_T::ISPCTL: LDUEN Mask
Definition at line 14925 of file NUC472_442.h.
| #define FMC_ISPCTL_LDUEN_Pos (5) |
FMC_T::ISPCTL: LDUEN Position
Definition at line 14924 of file NUC472_442.h.
| #define FMC_ISPDAT_ISPDAT_Msk (0xfffffffful << FMC_ISPDAT_ISPDAT_Pos) |
FMC_T::ISPDAT: ISPDAT Mask
Definition at line 14934 of file NUC472_442.h.
| #define FMC_ISPDAT_ISPDAT_Pos (0) |
FMC_T::ISPDAT: ISPDAT Position
Definition at line 14933 of file NUC472_442.h.
| #define FMC_ISPSTS_CBS_Msk (0x3ul << FMC_ISPSTS_CBS_Pos) |
FMC_T::ISPSTS: CBS Mask
Definition at line 14952 of file NUC472_442.h.
| #define FMC_ISPSTS_CBS_Pos (1) |
FMC_T::ISPSTS: CBS Position
Definition at line 14951 of file NUC472_442.h.
| #define FMC_ISPSTS_CFGCRCF_Msk (0x1ul << FMC_ISPSTS_CFGCRCF_Pos) |
FMC_T::ISPSTS: CFGCRCF Mask
Definition at line 14961 of file NUC472_442.h.
| #define FMC_ISPSTS_CFGCRCF_Pos (26) |
FMC_T::ISPSTS: CFGCRCF Position
Definition at line 14960 of file NUC472_442.h.
| #define FMC_ISPSTS_ISPBUSY_Msk (0x1ul << FMC_ISPSTS_ISPBUSY_Pos) |
FMC_T::ISPSTS: ISPBUSY Mask
Definition at line 14949 of file NUC472_442.h.
| #define FMC_ISPSTS_ISPBUSY_Pos (0) |
FMC_T::ISPSTS: ISPBUSY Position
Definition at line 14948 of file NUC472_442.h.
| #define FMC_ISPSTS_ISPFF_Msk (0x1ul << FMC_ISPSTS_ISPFF_Pos) |
FMC_T::ISPSTS: ISPFF Mask
Definition at line 14955 of file NUC472_442.h.
| #define FMC_ISPSTS_ISPFF_Pos (6) |
FMC_T::ISPSTS: ISPFF Position
Definition at line 14954 of file NUC472_442.h.
| #define FMC_ISPSTS_VECMAP_Msk (0xffful << FMC_ISPSTS_VECMAP_Pos) |
FMC_T::ISPSTS: VECMAP Mask
Definition at line 14958 of file NUC472_442.h.
| #define FMC_ISPSTS_VECMAP_Pos (9) |
FMC_T::ISPSTS: VECMAP Position
Definition at line 14957 of file NUC472_442.h.
| #define FMC_ISPTRG_ISPGO_Msk (0x1ul << FMC_ISPTRG_ISPGO_Pos) |
FMC_T::ISPTRG: ISPGO Mask
Definition at line 14940 of file NUC472_442.h.
| #define FMC_ISPTRG_ISPGO_Pos (0) |
FMC_T::ISPTRG: ISPGO Position
Definition at line 14939 of file NUC472_442.h.
| #define FMC_MPADDR_MPADDR_Msk (0xfffffffful << FMC_MPADDR_MPADDR_Pos) |
FMC_T::MPADDR: MPADDR Mask
Definition at line 14997 of file NUC472_442.h.
| #define FMC_MPADDR_MPADDR_Pos (0) |
FMC_T::MPADDR: MPADDR Position
Definition at line 14996 of file NUC472_442.h.
| #define FMC_MPDAT0_ISPDAT0_Msk (0xfffffffful << FMC_MPDAT0_ISPDAT0_Pos) |
FMC_T::MPDAT0: ISPDAT0 Mask
Definition at line 14967 of file NUC472_442.h.
| #define FMC_MPDAT0_ISPDAT0_Pos (0) |
FMC_T::MPDAT0: ISPDAT0 Position
Definition at line 14966 of file NUC472_442.h.
| #define FMC_MPDAT1_ISPDAT1_Msk (0xfffffffful << FMC_MPDAT1_ISPDAT1_Pos) |
FMC_T::MPDAT1: ISPDAT1 Mask
Definition at line 14970 of file NUC472_442.h.
| #define FMC_MPDAT1_ISPDAT1_Pos (0) |
FMC_T::MPDAT1: ISPDAT1 Position
Definition at line 14969 of file NUC472_442.h.
| #define FMC_MPDAT2_ISPDAT2_Msk (0xfffffffful << FMC_MPDAT2_ISPDAT2_Pos) |
FMC_T::MPDAT2: ISPDAT2 Mask
Definition at line 14973 of file NUC472_442.h.
| #define FMC_MPDAT2_ISPDAT2_Pos (0) |
FMC_T::MPDAT2: ISPDAT2 Position
Definition at line 14972 of file NUC472_442.h.
| #define FMC_MPDAT3_ISPDAT3_Msk (0xfffffffful << FMC_MPDAT3_ISPDAT3_Pos) |
FMC_T::MPDAT3: ISPDAT3 Mask
Definition at line 14976 of file NUC472_442.h.
| #define FMC_MPDAT3_ISPDAT3_Pos (0) |
FMC_T::MPDAT3: ISPDAT3 Position
Definition at line 14975 of file NUC472_442.h.
| #define FMC_MPSTS_D0_Msk (0x1ul << FMC_MPSTS_D0_Pos) |
FMC_T::MPSTS: D0 Mask
Definition at line 14985 of file NUC472_442.h.
| #define FMC_MPSTS_D0_Pos (4) |
FMC_T::MPSTS: D0 Position
Definition at line 14984 of file NUC472_442.h.
| #define FMC_MPSTS_D1_Msk (0x1ul << FMC_MPSTS_D1_Pos) |
FMC_T::MPSTS: D1 Mask
Definition at line 14988 of file NUC472_442.h.
| #define FMC_MPSTS_D1_Pos (5) |
FMC_T::MPSTS: D1 Position
Definition at line 14987 of file NUC472_442.h.
| #define FMC_MPSTS_D2_Msk (0x1ul << FMC_MPSTS_D2_Pos) |
FMC_T::MPSTS: D2 Mask
Definition at line 14991 of file NUC472_442.h.
| #define FMC_MPSTS_D2_Pos (6) |
FMC_T::MPSTS: D2 Position
Definition at line 14990 of file NUC472_442.h.
| #define FMC_MPSTS_D3_Msk (0x1ul << FMC_MPSTS_D3_Pos) |
FMC_T::MPSTS: D3 Mask
Definition at line 14994 of file NUC472_442.h.
| #define FMC_MPSTS_D3_Pos (7) |
FMC_T::MPSTS: D3 Position
Definition at line 14993 of file NUC472_442.h.
| #define FMC_MPSTS_ISPFF_Msk (0x1ul << FMC_MPSTS_ISPFF_Pos) |
FMC_T::MPSTS: ISPFF Mask
Definition at line 14982 of file NUC472_442.h.
| #define FMC_MPSTS_ISPFF_Pos (2) |
FMC_T::MPSTS: ISPFF Position
Definition at line 14981 of file NUC472_442.h.
| #define FMC_MPSTS_MPBUSY_Msk (0x1ul << FMC_MPSTS_MPBUSY_Pos) |
FMC_T::MPSTS: MPBUSY Mask
Definition at line 14979 of file NUC472_442.h.
| #define FMC_MPSTS_MPBUSY_Pos (0) |
FMC_T::MPSTS: WMPBUSY Position
Definition at line 14978 of file NUC472_442.h.
| #define GPIO_DATMSK_DATMSK0_Msk (0x1ul << GPIO_DATMSK_DATMSK0_Pos) |
GPIO_T::DATMSK: DATMSK0 Mask
Definition at line 16369 of file NUC472_442.h.
| #define GPIO_DATMSK_DATMSK0_Pos (0) |
GPIO_T::DATMSK: DATMSK0 Position
Definition at line 16368 of file NUC472_442.h.
| #define GPIO_DATMSK_DATMSK10_Msk (0x1ul << GPIO_DATMSK_DATMSK10_Pos) |
GPIO_T::DATMSK: DATMSK10 Mask
Definition at line 16399 of file NUC472_442.h.
| #define GPIO_DATMSK_DATMSK10_Pos (10) |
GPIO_T::DATMSK: DATMSK10 Position
Definition at line 16398 of file NUC472_442.h.
| #define GPIO_DATMSK_DATMSK11_Msk (0x1ul << GPIO_DATMSK_DATMSK11_Pos) |
GPIO_T::DATMSK: DATMSK11 Mask
Definition at line 16402 of file NUC472_442.h.
| #define GPIO_DATMSK_DATMSK11_Pos (11) |
GPIO_T::DATMSK: DATMSK11 Position
Definition at line 16401 of file NUC472_442.h.
| #define GPIO_DATMSK_DATMSK12_Msk (0x1ul << GPIO_DATMSK_DATMSK12_Pos) |
GPIO_T::DATMSK: DATMSK12 Mask
Definition at line 16405 of file NUC472_442.h.
| #define GPIO_DATMSK_DATMSK12_Pos (12) |
GPIO_T::DATMSK: DATMSK12 Position
Definition at line 16404 of file NUC472_442.h.
| #define GPIO_DATMSK_DATMSK13_Msk (0x1ul << GPIO_DATMSK_DATMSK13_Pos) |
GPIO_T::DATMSK: DATMSK13 Mask
Definition at line 16408 of file NUC472_442.h.
| #define GPIO_DATMSK_DATMSK13_Pos (13) |
GPIO_T::DATMSK: DATMSK13 Position
Definition at line 16407 of file NUC472_442.h.
| #define GPIO_DATMSK_DATMSK14_Msk (0x1ul << GPIO_DATMSK_DATMSK14_Pos) |
GPIO_T::DATMSK: DATMSK14 Mask
Definition at line 16411 of file NUC472_442.h.
| #define GPIO_DATMSK_DATMSK14_Pos (14) |
GPIO_T::DATMSK: DATMSK14 Position
Definition at line 16410 of file NUC472_442.h.
| #define GPIO_DATMSK_DATMSK15_Msk (0x1ul << GPIO_DATMSK_DATMSK15_Pos) |
GPIO_T::DATMSK: DATMSK15 Mask
Definition at line 16414 of file NUC472_442.h.
| #define GPIO_DATMSK_DATMSK15_Pos (15) |
GPIO_T::DATMSK: DATMSK15 Position
Definition at line 16413 of file NUC472_442.h.
| #define GPIO_DATMSK_DATMSK1_Msk (0x1ul << GPIO_DATMSK_DATMSK1_Pos) |
GPIO_T::DATMSK: DATMSK1 Mask
Definition at line 16372 of file NUC472_442.h.
| #define GPIO_DATMSK_DATMSK1_Pos (1) |
GPIO_T::DATMSK: DATMSK1 Position
Definition at line 16371 of file NUC472_442.h.
| #define GPIO_DATMSK_DATMSK2_Msk (0x1ul << GPIO_DATMSK_DATMSK2_Pos) |
GPIO_T::DATMSK: DATMSK2 Mask
Definition at line 16375 of file NUC472_442.h.
| #define GPIO_DATMSK_DATMSK2_Pos (2) |
GPIO_T::DATMSK: DATMSK2 Position
Definition at line 16374 of file NUC472_442.h.
| #define GPIO_DATMSK_DATMSK3_Msk (0x1ul << GPIO_DATMSK_DATMSK3_Pos) |
GPIO_T::DATMSK: DATMSK3 Mask
Definition at line 16378 of file NUC472_442.h.
| #define GPIO_DATMSK_DATMSK3_Pos (3) |
GPIO_T::DATMSK: DATMSK3 Position
Definition at line 16377 of file NUC472_442.h.
| #define GPIO_DATMSK_DATMSK4_Msk (0x1ul << GPIO_DATMSK_DATMSK4_Pos) |
GPIO_T::DATMSK: DATMSK4 Mask
Definition at line 16381 of file NUC472_442.h.
| #define GPIO_DATMSK_DATMSK4_Pos (4) |
GPIO_T::DATMSK: DATMSK4 Position
Definition at line 16380 of file NUC472_442.h.
| #define GPIO_DATMSK_DATMSK5_Msk (0x1ul << GPIO_DATMSK_DATMSK5_Pos) |
GPIO_T::DATMSK: DATMSK5 Mask
Definition at line 16384 of file NUC472_442.h.
| #define GPIO_DATMSK_DATMSK5_Pos (5) |
GPIO_T::DATMSK: DATMSK5 Position
Definition at line 16383 of file NUC472_442.h.
| #define GPIO_DATMSK_DATMSK6_Msk (0x1ul << GPIO_DATMSK_DATMSK6_Pos) |
GPIO_T::DATMSK: DATMSK6 Mask
Definition at line 16387 of file NUC472_442.h.
| #define GPIO_DATMSK_DATMSK6_Pos (6) |
GPIO_T::DATMSK: DATMSK6 Position
Definition at line 16386 of file NUC472_442.h.
| #define GPIO_DATMSK_DATMSK7_Msk (0x1ul << GPIO_DATMSK_DATMSK7_Pos) |
GPIO_T::DATMSK: DATMSK7 Mask
Definition at line 16390 of file NUC472_442.h.
| #define GPIO_DATMSK_DATMSK7_Pos (7) |
GPIO_T::DATMSK: DATMSK7 Position
Definition at line 16389 of file NUC472_442.h.
| #define GPIO_DATMSK_DATMSK8_Msk (0x1ul << GPIO_DATMSK_DATMSK8_Pos) |
GPIO_T::DATMSK: DATMSK8 Mask
Definition at line 16393 of file NUC472_442.h.
| #define GPIO_DATMSK_DATMSK8_Pos (8) |
GPIO_T::DATMSK: DATMSK8 Position
Definition at line 16392 of file NUC472_442.h.
| #define GPIO_DATMSK_DATMSK9_Msk (0x1ul << GPIO_DATMSK_DATMSK9_Pos) |
GPIO_T::DATMSK: DATMSK9 Mask
Definition at line 16396 of file NUC472_442.h.
| #define GPIO_DATMSK_DATMSK9_Pos (9) |
GPIO_T::DATMSK: DATMSK9 Position
Definition at line 16395 of file NUC472_442.h.
| #define GPIO_DBCTL_DBCLKSEL_Msk (0xful << GPIO_DBCTL_DBCLKSEL_Pos) |
GPIO_DB_T::DBCTL: DBCLKSEL Mask
Definition at line 16801 of file NUC472_442.h.
| #define GPIO_DBCTL_DBCLKSEL_Pos (0) |
GPIO_DB_T::DBCTL: DBCLKSEL Position
Definition at line 16800 of file NUC472_442.h.
| #define GPIO_DBCTL_DBCLKSRC_Msk (0x1ul << GPIO_DBCTL_DBCLKSRC_Pos) |
GPIO_DB_T::DBCTL: DBCLKSRC Mask
Definition at line 16804 of file NUC472_442.h.
| #define GPIO_DBCTL_DBCLKSRC_Pos (4) |
GPIO_DB_T::DBCTL: DBCLKSRC Position
Definition at line 16803 of file NUC472_442.h.
| #define GPIO_DBCTL_ICLKON_Msk (0x1ul << GPIO_DBCTL_ICLKON_Pos) |
GPIO_DB_T::DBCTL: ICLKON Mask
Definition at line 16807 of file NUC472_442.h.
| #define GPIO_DBCTL_ICLKON_Pos (5) |
GPIO_DB_T::DBCTL: ICLKON Position
Definition at line 16806 of file NUC472_442.h.
| #define GPIO_DBEN_DBEN0_Msk (0x1ul << GPIO_DBEN_DBEN0_Pos) |
GPIO_T::DBEN: DBEN0 Mask
Definition at line 16465 of file NUC472_442.h.
| #define GPIO_DBEN_DBEN0_Pos (0) |
GPIO_T::DBEN: DBEN0 Position
Definition at line 16464 of file NUC472_442.h.
| #define GPIO_DBEN_DBEN10_Msk (0x1ul << GPIO_DBEN_DBEN10_Pos) |
GPIO_T::DBEN: DBEN10 Mask
Definition at line 16495 of file NUC472_442.h.
| #define GPIO_DBEN_DBEN10_Pos (10) |
GPIO_T::DBEN: DBEN10 Position
Definition at line 16494 of file NUC472_442.h.
| #define GPIO_DBEN_DBEN11_Msk (0x1ul << GPIO_DBEN_DBEN11_Pos) |
GPIO_T::DBEN: DBEN11 Mask
Definition at line 16498 of file NUC472_442.h.
| #define GPIO_DBEN_DBEN11_Pos (11) |
GPIO_T::DBEN: DBEN11 Position
Definition at line 16497 of file NUC472_442.h.
| #define GPIO_DBEN_DBEN12_Msk (0x1ul << GPIO_DBEN_DBEN12_Pos) |
GPIO_T::DBEN: DBEN12 Mask
Definition at line 16501 of file NUC472_442.h.
| #define GPIO_DBEN_DBEN12_Pos (12) |
GPIO_T::DBEN: DBEN12 Position
Definition at line 16500 of file NUC472_442.h.
| #define GPIO_DBEN_DBEN13_Msk (0x1ul << GPIO_DBEN_DBEN13_Pos) |
GPIO_T::DBEN: DBEN13 Mask
Definition at line 16504 of file NUC472_442.h.
| #define GPIO_DBEN_DBEN13_Pos (13) |
GPIO_T::DBEN: DBEN13 Position
Definition at line 16503 of file NUC472_442.h.
| #define GPIO_DBEN_DBEN14_Msk (0x1ul << GPIO_DBEN_DBEN14_Pos) |
GPIO_T::DBEN: DBEN14 Mask
Definition at line 16507 of file NUC472_442.h.
| #define GPIO_DBEN_DBEN14_Pos (14) |
GPIO_T::DBEN: DBEN14 Position
Definition at line 16506 of file NUC472_442.h.
| #define GPIO_DBEN_DBEN15_Msk (0x1ul << GPIO_DBEN_DBEN15_Pos) |
GPIO_T::DBEN: DBEN15 Mask
Definition at line 16510 of file NUC472_442.h.
| #define GPIO_DBEN_DBEN15_Pos (15) |
GPIO_T::DBEN: DBEN15 Position
Definition at line 16509 of file NUC472_442.h.
| #define GPIO_DBEN_DBEN1_Msk (0x1ul << GPIO_DBEN_DBEN1_Pos) |
GPIO_T::DBEN: DBEN1 Mask
Definition at line 16468 of file NUC472_442.h.
| #define GPIO_DBEN_DBEN1_Pos (1) |
GPIO_T::DBEN: DBEN1 Position
Definition at line 16467 of file NUC472_442.h.
| #define GPIO_DBEN_DBEN2_Msk (0x1ul << GPIO_DBEN_DBEN2_Pos) |
GPIO_T::DBEN: DBEN2 Mask
Definition at line 16471 of file NUC472_442.h.
| #define GPIO_DBEN_DBEN2_Pos (2) |
GPIO_T::DBEN: DBEN2 Position
Definition at line 16470 of file NUC472_442.h.
| #define GPIO_DBEN_DBEN3_Msk (0x1ul << GPIO_DBEN_DBEN3_Pos) |
GPIO_T::DBEN: DBEN3 Mask
Definition at line 16474 of file NUC472_442.h.
| #define GPIO_DBEN_DBEN3_Pos (3) |
GPIO_T::DBEN: DBEN3 Position
Definition at line 16473 of file NUC472_442.h.
| #define GPIO_DBEN_DBEN4_Msk (0x1ul << GPIO_DBEN_DBEN4_Pos) |
GPIO_T::DBEN: DBEN4 Mask
Definition at line 16477 of file NUC472_442.h.
| #define GPIO_DBEN_DBEN4_Pos (4) |
GPIO_T::DBEN: DBEN4 Position
Definition at line 16476 of file NUC472_442.h.
| #define GPIO_DBEN_DBEN5_Msk (0x1ul << GPIO_DBEN_DBEN5_Pos) |
GPIO_T::DBEN: DBEN5 Mask
Definition at line 16480 of file NUC472_442.h.
| #define GPIO_DBEN_DBEN5_Pos (5) |
GPIO_T::DBEN: DBEN5 Position
Definition at line 16479 of file NUC472_442.h.
| #define GPIO_DBEN_DBEN6_Msk (0x1ul << GPIO_DBEN_DBEN6_Pos) |
GPIO_T::DBEN: DBEN6 Mask
Definition at line 16483 of file NUC472_442.h.
| #define GPIO_DBEN_DBEN6_Pos (6) |
GPIO_T::DBEN: DBEN6 Position
Definition at line 16482 of file NUC472_442.h.
| #define GPIO_DBEN_DBEN7_Msk (0x1ul << GPIO_DBEN_DBEN7_Pos) |
GPIO_T::DBEN: DBEN7 Mask
Definition at line 16486 of file NUC472_442.h.
| #define GPIO_DBEN_DBEN7_Pos (7) |
GPIO_T::DBEN: DBEN7 Position
Definition at line 16485 of file NUC472_442.h.
| #define GPIO_DBEN_DBEN8_Msk (0x1ul << GPIO_DBEN_DBEN8_Pos) |
GPIO_T::DBEN: DBEN8 Mask
Definition at line 16489 of file NUC472_442.h.
| #define GPIO_DBEN_DBEN8_Pos (8) |
GPIO_T::DBEN: DBEN8 Position
Definition at line 16488 of file NUC472_442.h.
| #define GPIO_DBEN_DBEN9_Msk (0x1ul << GPIO_DBEN_DBEN9_Pos) |
GPIO_T::DBEN: DBEN9 Mask
Definition at line 16492 of file NUC472_442.h.
| #define GPIO_DBEN_DBEN9_Pos (9) |
GPIO_T::DBEN: DBEN9 Position
Definition at line 16491 of file NUC472_442.h.
| #define GPIO_DINOFF_DINOFF0_Msk (0x1ul << GPIO_DINOFF_DINOFF0_Pos) |
GPIO_T::DINOFF: DINOFF0 Mask
Definition at line 16273 of file NUC472_442.h.
| #define GPIO_DINOFF_DINOFF0_Pos (16) |
GPIO_T::DINOFF: DINOFF0 Position
Definition at line 16272 of file NUC472_442.h.
| #define GPIO_DINOFF_DINOFF10_Msk (0x1ul << GPIO_DINOFF_DINOFF10_Pos) |
GPIO_T::DINOFF: DINOFF10 Mask
Definition at line 16303 of file NUC472_442.h.
| #define GPIO_DINOFF_DINOFF10_Pos (26) |
GPIO_T::DINOFF: DINOFF10 Position
Definition at line 16302 of file NUC472_442.h.
| #define GPIO_DINOFF_DINOFF11_Msk (0x1ul << GPIO_DINOFF_DINOFF11_Pos) |
GPIO_T::DINOFF: DINOFF11 Mask
Definition at line 16306 of file NUC472_442.h.
| #define GPIO_DINOFF_DINOFF11_Pos (27) |
GPIO_T::DINOFF: DINOFF11 Position
Definition at line 16305 of file NUC472_442.h.
| #define GPIO_DINOFF_DINOFF12_Msk (0x1ul << GPIO_DINOFF_DINOFF12_Pos) |
GPIO_T::DINOFF: DINOFF12 Mask
Definition at line 16309 of file NUC472_442.h.
| #define GPIO_DINOFF_DINOFF12_Pos (28) |
GPIO_T::DINOFF: DINOFF12 Position
Definition at line 16308 of file NUC472_442.h.
| #define GPIO_DINOFF_DINOFF13_Msk (0x1ul << GPIO_DINOFF_DINOFF13_Pos) |
GPIO_T::DINOFF: DINOFF13 Mask
Definition at line 16312 of file NUC472_442.h.
| #define GPIO_DINOFF_DINOFF13_Pos (29) |
GPIO_T::DINOFF: DINOFF13 Position
Definition at line 16311 of file NUC472_442.h.
| #define GPIO_DINOFF_DINOFF14_Msk (0x1ul << GPIO_DINOFF_DINOFF14_Pos) |
GPIO_T::DINOFF: DINOFF14 Mask
Definition at line 16315 of file NUC472_442.h.
| #define GPIO_DINOFF_DINOFF14_Pos (30) |
GPIO_T::DINOFF: DINOFF14 Position
Definition at line 16314 of file NUC472_442.h.
| #define GPIO_DINOFF_DINOFF15_Msk (0x1ul << GPIO_DINOFF_DINOFF15_Pos) |
GPIO_T::DINOFF: DINOFF15 Mask
Definition at line 16318 of file NUC472_442.h.
| #define GPIO_DINOFF_DINOFF15_Pos (31) |
GPIO_T::DINOFF: DINOFF15 Position
Definition at line 16317 of file NUC472_442.h.
| #define GPIO_DINOFF_DINOFF1_Msk (0x1ul << GPIO_DINOFF_DINOFF1_Pos) |
GPIO_T::DINOFF: DINOFF1 Mask
Definition at line 16276 of file NUC472_442.h.
| #define GPIO_DINOFF_DINOFF1_Pos (17) |
GPIO_T::DINOFF: DINOFF1 Position
Definition at line 16275 of file NUC472_442.h.
| #define GPIO_DINOFF_DINOFF2_Msk (0x1ul << GPIO_DINOFF_DINOFF2_Pos) |
GPIO_T::DINOFF: DINOFF2 Mask
Definition at line 16279 of file NUC472_442.h.
| #define GPIO_DINOFF_DINOFF2_Pos (18) |
GPIO_T::DINOFF: DINOFF2 Position
Definition at line 16278 of file NUC472_442.h.
| #define GPIO_DINOFF_DINOFF3_Msk (0x1ul << GPIO_DINOFF_DINOFF3_Pos) |
GPIO_T::DINOFF: DINOFF3 Mask
Definition at line 16282 of file NUC472_442.h.
| #define GPIO_DINOFF_DINOFF3_Pos (19) |
GPIO_T::DINOFF: DINOFF3 Position
Definition at line 16281 of file NUC472_442.h.
| #define GPIO_DINOFF_DINOFF4_Msk (0x1ul << GPIO_DINOFF_DINOFF4_Pos) |
GPIO_T::DINOFF: DINOFF4 Mask
Definition at line 16285 of file NUC472_442.h.
| #define GPIO_DINOFF_DINOFF4_Pos (20) |
GPIO_T::DINOFF: DINOFF4 Position
Definition at line 16284 of file NUC472_442.h.
| #define GPIO_DINOFF_DINOFF5_Msk (0x1ul << GPIO_DINOFF_DINOFF5_Pos) |
GPIO_T::DINOFF: DINOFF5 Mask
Definition at line 16288 of file NUC472_442.h.
| #define GPIO_DINOFF_DINOFF5_Pos (21) |
GPIO_T::DINOFF: DINOFF5 Position
Definition at line 16287 of file NUC472_442.h.
| #define GPIO_DINOFF_DINOFF6_Msk (0x1ul << GPIO_DINOFF_DINOFF6_Pos) |
GPIO_T::DINOFF: DINOFF6 Mask
Definition at line 16291 of file NUC472_442.h.
| #define GPIO_DINOFF_DINOFF6_Pos (22) |
GPIO_T::DINOFF: DINOFF6 Position
Definition at line 16290 of file NUC472_442.h.
| #define GPIO_DINOFF_DINOFF7_Msk (0x1ul << GPIO_DINOFF_DINOFF7_Pos) |
GPIO_T::DINOFF: DINOFF7 Mask
Definition at line 16294 of file NUC472_442.h.
| #define GPIO_DINOFF_DINOFF7_Pos (23) |
GPIO_T::DINOFF: DINOFF7 Position
Definition at line 16293 of file NUC472_442.h.
| #define GPIO_DINOFF_DINOFF8_Msk (0x1ul << GPIO_DINOFF_DINOFF8_Pos) |
GPIO_T::DINOFF: DINOFF8 Mask
Definition at line 16297 of file NUC472_442.h.
| #define GPIO_DINOFF_DINOFF8_Pos (24) |
GPIO_T::DINOFF: DINOFF8 Position
Definition at line 16296 of file NUC472_442.h.
| #define GPIO_DINOFF_DINOFF9_Msk (0x1ul << GPIO_DINOFF_DINOFF9_Pos) |
GPIO_T::DINOFF: DINOFF9 Mask
Definition at line 16300 of file NUC472_442.h.
| #define GPIO_DINOFF_DINOFF9_Pos (25) |
GPIO_T::DINOFF: DINOFF9 Position
Definition at line 16299 of file NUC472_442.h.
| #define GPIO_DOUT_DOUT0_Msk (0x1ul << GPIO_DOUT_DOUT0_Pos) |
GPIO_T::DOUT: DOUT0 Mask
Definition at line 16321 of file NUC472_442.h.
| #define GPIO_DOUT_DOUT0_Pos (0) |
GPIO_T::DOUT: DOUT0 Position
Definition at line 16320 of file NUC472_442.h.
| #define GPIO_DOUT_DOUT10_Msk (0x1ul << GPIO_DOUT_DOUT10_Pos) |
GPIO_T::DOUT: DOUT10 Mask
Definition at line 16351 of file NUC472_442.h.
| #define GPIO_DOUT_DOUT10_Pos (10) |
GPIO_T::DOUT: DOUT10 Position
Definition at line 16350 of file NUC472_442.h.
| #define GPIO_DOUT_DOUT11_Msk (0x1ul << GPIO_DOUT_DOUT11_Pos) |
GPIO_T::DOUT: DOUT11 Mask
Definition at line 16354 of file NUC472_442.h.
| #define GPIO_DOUT_DOUT11_Pos (11) |
GPIO_T::DOUT: DOUT11 Position
Definition at line 16353 of file NUC472_442.h.
| #define GPIO_DOUT_DOUT12_Msk (0x1ul << GPIO_DOUT_DOUT12_Pos) |
GPIO_T::DOUT: DOUT12 Mask
Definition at line 16357 of file NUC472_442.h.
| #define GPIO_DOUT_DOUT12_Pos (12) |
GPIO_T::DOUT: DOUT12 Position
Definition at line 16356 of file NUC472_442.h.
| #define GPIO_DOUT_DOUT13_Msk (0x1ul << GPIO_DOUT_DOUT13_Pos) |
GPIO_T::DOUT: DOUT13 Mask
Definition at line 16360 of file NUC472_442.h.
| #define GPIO_DOUT_DOUT13_Pos (13) |
GPIO_T::DOUT: DOUT13 Position
Definition at line 16359 of file NUC472_442.h.
| #define GPIO_DOUT_DOUT14_Msk (0x1ul << GPIO_DOUT_DOUT14_Pos) |
GPIO_T::DOUT: DOUT14 Mask
Definition at line 16363 of file NUC472_442.h.
| #define GPIO_DOUT_DOUT14_Pos (14) |
GPIO_T::DOUT: DOUT14 Position
Definition at line 16362 of file NUC472_442.h.
| #define GPIO_DOUT_DOUT15_Msk (0x1ul << GPIO_DOUT_DOUT15_Pos) |
GPIO_T::DOUT: DOUT15 Mask
Definition at line 16366 of file NUC472_442.h.
| #define GPIO_DOUT_DOUT15_Pos (15) |
GPIO_T::DOUT: DOUT15 Position
Definition at line 16365 of file NUC472_442.h.
| #define GPIO_DOUT_DOUT1_Msk (0x1ul << GPIO_DOUT_DOUT1_Pos) |
GPIO_T::DOUT: DOUT1 Mask
Definition at line 16324 of file NUC472_442.h.
| #define GPIO_DOUT_DOUT1_Pos (1) |
GPIO_T::DOUT: DOUT1 Position
Definition at line 16323 of file NUC472_442.h.
| #define GPIO_DOUT_DOUT2_Msk (0x1ul << GPIO_DOUT_DOUT2_Pos) |
GPIO_T::DOUT: DOUT2 Mask
Definition at line 16327 of file NUC472_442.h.
| #define GPIO_DOUT_DOUT2_Pos (2) |
GPIO_T::DOUT: DOUT2 Position
Definition at line 16326 of file NUC472_442.h.
| #define GPIO_DOUT_DOUT3_Msk (0x1ul << GPIO_DOUT_DOUT3_Pos) |
GPIO_T::DOUT: DOUT3 Mask
Definition at line 16330 of file NUC472_442.h.
| #define GPIO_DOUT_DOUT3_Pos (3) |
GPIO_T::DOUT: DOUT3 Position
Definition at line 16329 of file NUC472_442.h.
| #define GPIO_DOUT_DOUT4_Msk (0x1ul << GPIO_DOUT_DOUT4_Pos) |
GPIO_T::DOUT: DOUT4 Mask
Definition at line 16333 of file NUC472_442.h.
| #define GPIO_DOUT_DOUT4_Pos (4) |
GPIO_T::DOUT: DOUT4 Position
Definition at line 16332 of file NUC472_442.h.
| #define GPIO_DOUT_DOUT5_Msk (0x1ul << GPIO_DOUT_DOUT5_Pos) |
GPIO_T::DOUT: DOUT5 Mask
Definition at line 16336 of file NUC472_442.h.
| #define GPIO_DOUT_DOUT5_Pos (5) |
GPIO_T::DOUT: DOUT5 Position
Definition at line 16335 of file NUC472_442.h.
| #define GPIO_DOUT_DOUT6_Msk (0x1ul << GPIO_DOUT_DOUT6_Pos) |
GPIO_T::DOUT: DOUT6 Mask
Definition at line 16339 of file NUC472_442.h.
| #define GPIO_DOUT_DOUT6_Pos (6) |
GPIO_T::DOUT: DOUT6 Position
Definition at line 16338 of file NUC472_442.h.
| #define GPIO_DOUT_DOUT7_Msk (0x1ul << GPIO_DOUT_DOUT7_Pos) |
GPIO_T::DOUT: DOUT7 Mask
Definition at line 16342 of file NUC472_442.h.
| #define GPIO_DOUT_DOUT7_Pos (7) |
GPIO_T::DOUT: DOUT7 Position
Definition at line 16341 of file NUC472_442.h.
| #define GPIO_DOUT_DOUT8_Msk (0x1ul << GPIO_DOUT_DOUT8_Pos) |
GPIO_T::DOUT: DOUT8 Mask
Definition at line 16345 of file NUC472_442.h.
| #define GPIO_DOUT_DOUT8_Pos (8) |
GPIO_T::DOUT: DOUT8 Position
Definition at line 16344 of file NUC472_442.h.
| #define GPIO_DOUT_DOUT9_Msk (0x1ul << GPIO_DOUT_DOUT9_Pos) |
GPIO_T::DOUT: DOUT9 Mask
Definition at line 16348 of file NUC472_442.h.
| #define GPIO_DOUT_DOUT9_Pos (9) |
GPIO_T::DOUT: DOUT9 Position
Definition at line 16347 of file NUC472_442.h.
| #define GPIO_INTEN_FLIEN0_Msk (0x1ul << GPIO_INTEN_FLIEN0_Pos) |
GPIO_T::INTEN: FLIEN0 Mask
Definition at line 16561 of file NUC472_442.h.
| #define GPIO_INTEN_FLIEN0_Pos (0) |
GPIO_T::INTEN: FLIEN0 Position
Definition at line 16560 of file NUC472_442.h.
| #define GPIO_INTEN_FLIEN10_Msk (0x1ul << GPIO_INTEN_FLIEN10_Pos) |
GPIO_T::INTEN: FLIEN10 Mask
Definition at line 16591 of file NUC472_442.h.
| #define GPIO_INTEN_FLIEN10_Pos (10) |
GPIO_T::INTEN: FLIEN10 Position
Definition at line 16590 of file NUC472_442.h.
| #define GPIO_INTEN_FLIEN11_Msk (0x1ul << GPIO_INTEN_FLIEN11_Pos) |
GPIO_T::INTEN: FLIEN11 Mask
Definition at line 16594 of file NUC472_442.h.
| #define GPIO_INTEN_FLIEN11_Pos (11) |
GPIO_T::INTEN: FLIEN11 Position
Definition at line 16593 of file NUC472_442.h.
| #define GPIO_INTEN_FLIEN12_Msk (0x1ul << GPIO_INTEN_FLIEN12_Pos) |
GPIO_T::INTEN: FLIEN12 Mask
Definition at line 16597 of file NUC472_442.h.
| #define GPIO_INTEN_FLIEN12_Pos (12) |
GPIO_T::INTEN: FLIEN12 Position
Definition at line 16596 of file NUC472_442.h.
| #define GPIO_INTEN_FLIEN13_Msk (0x1ul << GPIO_INTEN_FLIEN13_Pos) |
GPIO_T::INTEN: FLIEN13 Mask
Definition at line 16600 of file NUC472_442.h.
| #define GPIO_INTEN_FLIEN13_Pos (13) |
GPIO_T::INTEN: FLIEN13 Position
Definition at line 16599 of file NUC472_442.h.
| #define GPIO_INTEN_FLIEN14_Msk (0x1ul << GPIO_INTEN_FLIEN14_Pos) |
GPIO_T::INTEN: FLIEN14 Mask
Definition at line 16603 of file NUC472_442.h.
| #define GPIO_INTEN_FLIEN14_Pos (14) |
GPIO_T::INTEN: FLIEN14 Position
Definition at line 16602 of file NUC472_442.h.
| #define GPIO_INTEN_FLIEN15_Msk (0x1ul << GPIO_INTEN_FLIEN15_Pos) |
GPIO_T::INTEN: FLIEN15 Mask
Definition at line 16606 of file NUC472_442.h.
| #define GPIO_INTEN_FLIEN15_Pos (15) |
GPIO_T::INTEN: FLIEN15 Position
Definition at line 16605 of file NUC472_442.h.
| #define GPIO_INTEN_FLIEN1_Msk (0x1ul << GPIO_INTEN_FLIEN1_Pos) |
GPIO_T::INTEN: FLIEN1 Mask
Definition at line 16564 of file NUC472_442.h.
| #define GPIO_INTEN_FLIEN1_Pos (1) |
GPIO_T::INTEN: FLIEN1 Position
Definition at line 16563 of file NUC472_442.h.
| #define GPIO_INTEN_FLIEN2_Msk (0x1ul << GPIO_INTEN_FLIEN2_Pos) |
GPIO_T::INTEN: FLIEN2 Mask
Definition at line 16567 of file NUC472_442.h.
| #define GPIO_INTEN_FLIEN2_Pos (2) |
GPIO_T::INTEN: FLIEN2 Position
Definition at line 16566 of file NUC472_442.h.
| #define GPIO_INTEN_FLIEN3_Msk (0x1ul << GPIO_INTEN_FLIEN3_Pos) |
GPIO_T::INTEN: FLIEN3 Mask
Definition at line 16570 of file NUC472_442.h.
| #define GPIO_INTEN_FLIEN3_Pos (3) |
GPIO_T::INTEN: FLIEN3 Position
Definition at line 16569 of file NUC472_442.h.
| #define GPIO_INTEN_FLIEN4_Msk (0x1ul << GPIO_INTEN_FLIEN4_Pos) |
GPIO_T::INTEN: FLIEN4 Mask
Definition at line 16573 of file NUC472_442.h.
| #define GPIO_INTEN_FLIEN4_Pos (4) |
GPIO_T::INTEN: FLIEN4 Position
Definition at line 16572 of file NUC472_442.h.
| #define GPIO_INTEN_FLIEN5_Msk (0x1ul << GPIO_INTEN_FLIEN5_Pos) |
GPIO_T::INTEN: FLIEN5 Mask
Definition at line 16576 of file NUC472_442.h.
| #define GPIO_INTEN_FLIEN5_Pos (5) |
GPIO_T::INTEN: FLIEN5 Position
Definition at line 16575 of file NUC472_442.h.
| #define GPIO_INTEN_FLIEN6_Msk (0x1ul << GPIO_INTEN_FLIEN6_Pos) |
GPIO_T::INTEN: FLIEN6 Mask
Definition at line 16579 of file NUC472_442.h.
| #define GPIO_INTEN_FLIEN6_Pos (6) |
GPIO_T::INTEN: FLIEN6 Position
Definition at line 16578 of file NUC472_442.h.
| #define GPIO_INTEN_FLIEN7_Msk (0x1ul << GPIO_INTEN_FLIEN7_Pos) |
GPIO_T::INTEN: FLIEN7 Mask
Definition at line 16582 of file NUC472_442.h.
| #define GPIO_INTEN_FLIEN7_Pos (7) |
GPIO_T::INTEN: FLIEN7 Position
Definition at line 16581 of file NUC472_442.h.
| #define GPIO_INTEN_FLIEN8_Msk (0x1ul << GPIO_INTEN_FLIEN8_Pos) |
GPIO_T::INTEN: FLIEN8 Mask
Definition at line 16585 of file NUC472_442.h.
| #define GPIO_INTEN_FLIEN8_Pos (8) |
GPIO_T::INTEN: FLIEN8 Position
Definition at line 16584 of file NUC472_442.h.
| #define GPIO_INTEN_FLIEN9_Msk (0x1ul << GPIO_INTEN_FLIEN9_Pos) |
GPIO_T::INTEN: FLIEN9 Mask
Definition at line 16588 of file NUC472_442.h.
| #define GPIO_INTEN_FLIEN9_Pos (9) |
GPIO_T::INTEN: FLIEN9 Position
Definition at line 16587 of file NUC472_442.h.
| #define GPIO_INTEN_RHIEN0_Msk (0x1ul << GPIO_INTEN_RHIEN0_Pos) |
GPIO_T::INTEN: RHIEN0 Mask
Definition at line 16609 of file NUC472_442.h.
| #define GPIO_INTEN_RHIEN0_Pos (16) |
GPIO_T::INTEN: RHIEN0 Position
Definition at line 16608 of file NUC472_442.h.
| #define GPIO_INTEN_RHIEN10_Msk (0x1ul << GPIO_INTEN_RHIEN10_Pos) |
GPIO_T::INTEN: RHIEN10 Mask
Definition at line 16639 of file NUC472_442.h.
| #define GPIO_INTEN_RHIEN10_Pos (26) |
GPIO_T::INTEN: RHIEN10 Position
Definition at line 16638 of file NUC472_442.h.
| #define GPIO_INTEN_RHIEN11_Msk (0x1ul << GPIO_INTEN_RHIEN11_Pos) |
GPIO_T::INTEN: RHIEN11 Mask
Definition at line 16642 of file NUC472_442.h.
| #define GPIO_INTEN_RHIEN11_Pos (27) |
GPIO_T::INTEN: RHIEN11 Position
Definition at line 16641 of file NUC472_442.h.
| #define GPIO_INTEN_RHIEN12_Msk (0x1ul << GPIO_INTEN_RHIEN12_Pos) |
GPIO_T::INTEN: RHIEN12 Mask
Definition at line 16645 of file NUC472_442.h.
| #define GPIO_INTEN_RHIEN12_Pos (28) |
GPIO_T::INTEN: RHIEN12 Position
Definition at line 16644 of file NUC472_442.h.
| #define GPIO_INTEN_RHIEN13_Msk (0x1ul << GPIO_INTEN_RHIEN13_Pos) |
GPIO_T::INTEN: RHIEN13 Mask
Definition at line 16648 of file NUC472_442.h.
| #define GPIO_INTEN_RHIEN13_Pos (29) |
GPIO_T::INTEN: RHIEN13 Position
Definition at line 16647 of file NUC472_442.h.
| #define GPIO_INTEN_RHIEN14_Msk (0x1ul << GPIO_INTEN_RHIEN14_Pos) |
GPIO_T::INTEN: RHIEN14 Mask
Definition at line 16651 of file NUC472_442.h.
| #define GPIO_INTEN_RHIEN14_Pos (30) |
GPIO_T::INTEN: RHIEN14 Position
Definition at line 16650 of file NUC472_442.h.
| #define GPIO_INTEN_RHIEN15_Msk (0x1ul << GPIO_INTEN_RHIEN15_Pos) |
GPIO_T::INTEN: RHIEN15 Mask
Definition at line 16654 of file NUC472_442.h.
| #define GPIO_INTEN_RHIEN15_Pos (31) |
GPIO_T::INTEN: RHIEN15 Position
Definition at line 16653 of file NUC472_442.h.
| #define GPIO_INTEN_RHIEN1_Msk (0x1ul << GPIO_INTEN_RHIEN1_Pos) |
GPIO_T::INTEN: RHIEN1 Mask
Definition at line 16612 of file NUC472_442.h.
| #define GPIO_INTEN_RHIEN1_Pos (17) |
GPIO_T::INTEN: RHIEN1 Position
Definition at line 16611 of file NUC472_442.h.
| #define GPIO_INTEN_RHIEN2_Msk (0x1ul << GPIO_INTEN_RHIEN2_Pos) |
GPIO_T::INTEN: RHIEN2 Mask
Definition at line 16615 of file NUC472_442.h.
| #define GPIO_INTEN_RHIEN2_Pos (18) |
GPIO_T::INTEN: RHIEN2 Position
Definition at line 16614 of file NUC472_442.h.
| #define GPIO_INTEN_RHIEN3_Msk (0x1ul << GPIO_INTEN_RHIEN3_Pos) |
GPIO_T::INTEN: RHIEN3 Mask
Definition at line 16618 of file NUC472_442.h.
| #define GPIO_INTEN_RHIEN3_Pos (19) |
GPIO_T::INTEN: RHIEN3 Position
Definition at line 16617 of file NUC472_442.h.
| #define GPIO_INTEN_RHIEN4_Msk (0x1ul << GPIO_INTEN_RHIEN4_Pos) |
GPIO_T::INTEN: RHIEN4 Mask
Definition at line 16621 of file NUC472_442.h.
| #define GPIO_INTEN_RHIEN4_Pos (20) |
GPIO_T::INTEN: RHIEN4 Position
Definition at line 16620 of file NUC472_442.h.
| #define GPIO_INTEN_RHIEN5_Msk (0x1ul << GPIO_INTEN_RHIEN5_Pos) |
GPIO_T::INTEN: RHIEN5 Mask
Definition at line 16624 of file NUC472_442.h.
| #define GPIO_INTEN_RHIEN5_Pos (21) |
GPIO_T::INTEN: RHIEN5 Position
Definition at line 16623 of file NUC472_442.h.
| #define GPIO_INTEN_RHIEN6_Msk (0x1ul << GPIO_INTEN_RHIEN6_Pos) |
GPIO_T::INTEN: RHIEN6 Mask
Definition at line 16627 of file NUC472_442.h.
| #define GPIO_INTEN_RHIEN6_Pos (22) |
GPIO_T::INTEN: RHIEN6 Position
Definition at line 16626 of file NUC472_442.h.
| #define GPIO_INTEN_RHIEN7_Msk (0x1ul << GPIO_INTEN_RHIEN7_Pos) |
GPIO_T::INTEN: RHIEN7 Mask
Definition at line 16630 of file NUC472_442.h.
| #define GPIO_INTEN_RHIEN7_Pos (23) |
GPIO_T::INTEN: RHIEN7 Position
Definition at line 16629 of file NUC472_442.h.
| #define GPIO_INTEN_RHIEN8_Msk (0x1ul << GPIO_INTEN_RHIEN8_Pos) |
GPIO_T::INTEN: RHIEN8 Mask
Definition at line 16633 of file NUC472_442.h.
| #define GPIO_INTEN_RHIEN8_Pos (24) |
GPIO_T::INTEN: RHIEN8 Position
Definition at line 16632 of file NUC472_442.h.
| #define GPIO_INTEN_RHIEN9_Msk (0x1ul << GPIO_INTEN_RHIEN9_Pos) |
GPIO_T::INTEN: RHIEN9 Mask
Definition at line 16636 of file NUC472_442.h.
| #define GPIO_INTEN_RHIEN9_Pos (25) |
GPIO_T::INTEN: RHIEN9 Position
Definition at line 16635 of file NUC472_442.h.
| #define GPIO_INTSRC_INTSRC0_Msk (0x1ul << GPIO_INTSRC_INTSRC0_Pos) |
GPIO_T::INTSRC: INTSRC0 Mask
Definition at line 16657 of file NUC472_442.h.
| #define GPIO_INTSRC_INTSRC0_Pos (0) |
GPIO_T::INTSRC: INTSRC0 Position
Definition at line 16656 of file NUC472_442.h.
| #define GPIO_INTSRC_INTSRC10_Msk (0x1ul << GPIO_INTSRC_INTSRC10_Pos) |
GPIO_T::INTSRC: INTSRC10 Mask
Definition at line 16687 of file NUC472_442.h.
| #define GPIO_INTSRC_INTSRC10_Pos (10) |
GPIO_T::INTSRC: INTSRC10 Position
Definition at line 16686 of file NUC472_442.h.
| #define GPIO_INTSRC_INTSRC11_Msk (0x1ul << GPIO_INTSRC_INTSRC11_Pos) |
GPIO_T::INTSRC: INTSRC11 Mask
Definition at line 16690 of file NUC472_442.h.
| #define GPIO_INTSRC_INTSRC11_Pos (11) |
GPIO_T::INTSRC: INTSRC11 Position
Definition at line 16689 of file NUC472_442.h.
| #define GPIO_INTSRC_INTSRC12_Msk (0x1ul << GPIO_INTSRC_INTSRC12_Pos) |
GPIO_T::INTSRC: INTSRC12 Mask
Definition at line 16693 of file NUC472_442.h.
| #define GPIO_INTSRC_INTSRC12_Pos (12) |
GPIO_T::INTSRC: INTSRC12 Position
Definition at line 16692 of file NUC472_442.h.
| #define GPIO_INTSRC_INTSRC13_Msk (0x1ul << GPIO_INTSRC_INTSRC13_Pos) |
GPIO_T::INTSRC: INTSRC13 Mask
Definition at line 16696 of file NUC472_442.h.
| #define GPIO_INTSRC_INTSRC13_Pos (13) |
GPIO_T::INTSRC: INTSRC13 Position
Definition at line 16695 of file NUC472_442.h.
| #define GPIO_INTSRC_INTSRC14_Msk (0x1ul << GPIO_INTSRC_INTSRC14_Pos) |
GPIO_T::INTSRC: INTSRC14 Mask
Definition at line 16699 of file NUC472_442.h.
| #define GPIO_INTSRC_INTSRC14_Pos (14) |
GPIO_T::INTSRC: INTSRC14 Position
Definition at line 16698 of file NUC472_442.h.
| #define GPIO_INTSRC_INTSRC15_Msk (0x1ul << GPIO_INTSRC_INTSRC15_Pos) |
GPIO_T::INTSRC: INTSRC15 Mask
Definition at line 16702 of file NUC472_442.h.
| #define GPIO_INTSRC_INTSRC15_Pos (15) |
GPIO_T::INTSRC: INTSRC15 Position
Definition at line 16701 of file NUC472_442.h.
| #define GPIO_INTSRC_INTSRC1_Msk (0x1ul << GPIO_INTSRC_INTSRC1_Pos) |
GPIO_T::INTSRC: INTSRC1 Mask
Definition at line 16660 of file NUC472_442.h.
| #define GPIO_INTSRC_INTSRC1_Pos (1) |
GPIO_T::INTSRC: INTSRC1 Position
Definition at line 16659 of file NUC472_442.h.
| #define GPIO_INTSRC_INTSRC2_Msk (0x1ul << GPIO_INTSRC_INTSRC2_Pos) |
GPIO_T::INTSRC: INTSRC2 Mask
Definition at line 16663 of file NUC472_442.h.
| #define GPIO_INTSRC_INTSRC2_Pos (2) |
GPIO_T::INTSRC: INTSRC2 Position
Definition at line 16662 of file NUC472_442.h.
| #define GPIO_INTSRC_INTSRC3_Msk (0x1ul << GPIO_INTSRC_INTSRC3_Pos) |
GPIO_T::INTSRC: INTSRC3 Mask
Definition at line 16666 of file NUC472_442.h.
| #define GPIO_INTSRC_INTSRC3_Pos (3) |
GPIO_T::INTSRC: INTSRC3 Position
Definition at line 16665 of file NUC472_442.h.
| #define GPIO_INTSRC_INTSRC4_Msk (0x1ul << GPIO_INTSRC_INTSRC4_Pos) |
GPIO_T::INTSRC: INTSRC4 Mask
Definition at line 16669 of file NUC472_442.h.
| #define GPIO_INTSRC_INTSRC4_Pos (4) |
GPIO_T::INTSRC: INTSRC4 Position
Definition at line 16668 of file NUC472_442.h.
| #define GPIO_INTSRC_INTSRC5_Msk (0x1ul << GPIO_INTSRC_INTSRC5_Pos) |
GPIO_T::INTSRC: INTSRC5 Mask
Definition at line 16672 of file NUC472_442.h.
| #define GPIO_INTSRC_INTSRC5_Pos (5) |
GPIO_T::INTSRC: INTSRC5 Position
Definition at line 16671 of file NUC472_442.h.
| #define GPIO_INTSRC_INTSRC6_Msk (0x1ul << GPIO_INTSRC_INTSRC6_Pos) |
GPIO_T::INTSRC: INTSRC6 Mask
Definition at line 16675 of file NUC472_442.h.
| #define GPIO_INTSRC_INTSRC6_Pos (6) |
GPIO_T::INTSRC: INTSRC6 Position
Definition at line 16674 of file NUC472_442.h.
| #define GPIO_INTSRC_INTSRC7_Msk (0x1ul << GPIO_INTSRC_INTSRC7_Pos) |
GPIO_T::INTSRC: INTSRC7 Mask
Definition at line 16678 of file NUC472_442.h.
| #define GPIO_INTSRC_INTSRC7_Pos (7) |
GPIO_T::INTSRC: INTSRC7 Position
Definition at line 16677 of file NUC472_442.h.
| #define GPIO_INTSRC_INTSRC8_Msk (0x1ul << GPIO_INTSRC_INTSRC8_Pos) |
GPIO_T::INTSRC: INTSRC8 Mask
Definition at line 16681 of file NUC472_442.h.
| #define GPIO_INTSRC_INTSRC8_Pos (8) |
GPIO_T::INTSRC: INTSRC8 Position
Definition at line 16680 of file NUC472_442.h.
| #define GPIO_INTSRC_INTSRC9_Msk (0x1ul << GPIO_INTSRC_INTSRC9_Pos) |
GPIO_T::INTSRC: INTSRC9 Mask
Definition at line 16684 of file NUC472_442.h.
| #define GPIO_INTSRC_INTSRC9_Pos (9) |
GPIO_T::INTSRC: INTSRC9 Position
Definition at line 16683 of file NUC472_442.h.
| #define GPIO_INTTYPE_TYPE0_Msk (0x1ul << GPIO_INTTYPE_TYPE0_Pos) |
GPIO_T::INTTYPE: TYPE0 Mask
Definition at line 16513 of file NUC472_442.h.
| #define GPIO_INTTYPE_TYPE0_Pos (0) |
GPIO_T::INTTYPE: TYPE0 Position
Definition at line 16512 of file NUC472_442.h.
| #define GPIO_INTTYPE_TYPE10_Msk (0x1ul << GPIO_INTTYPE_TYPE10_Pos) |
GPIO_T::INTTYPE: TYPE10 Mask
Definition at line 16543 of file NUC472_442.h.
| #define GPIO_INTTYPE_TYPE10_Pos (10) |
GPIO_T::INTTYPE: TYPE10 Position
Definition at line 16542 of file NUC472_442.h.
| #define GPIO_INTTYPE_TYPE11_Msk (0x1ul << GPIO_INTTYPE_TYPE11_Pos) |
GPIO_T::INTTYPE: TYPE11 Mask
Definition at line 16546 of file NUC472_442.h.
| #define GPIO_INTTYPE_TYPE11_Pos (11) |
GPIO_T::INTTYPE: TYPE11 Position
Definition at line 16545 of file NUC472_442.h.
| #define GPIO_INTTYPE_TYPE12_Msk (0x1ul << GPIO_INTTYPE_TYPE12_Pos) |
GPIO_T::INTTYPE: TYPE12 Mask
Definition at line 16549 of file NUC472_442.h.
| #define GPIO_INTTYPE_TYPE12_Pos (12) |
GPIO_T::INTTYPE: TYPE12 Position
Definition at line 16548 of file NUC472_442.h.
| #define GPIO_INTTYPE_TYPE13_Msk (0x1ul << GPIO_INTTYPE_TYPE13_Pos) |
GPIO_T::INTTYPE: TYPE13 Mask
Definition at line 16552 of file NUC472_442.h.
| #define GPIO_INTTYPE_TYPE13_Pos (13) |
GPIO_T::INTTYPE: TYPE13 Position
Definition at line 16551 of file NUC472_442.h.
| #define GPIO_INTTYPE_TYPE14_Msk (0x1ul << GPIO_INTTYPE_TYPE14_Pos) |
GPIO_T::INTTYPE: TYPE14 Mask
Definition at line 16555 of file NUC472_442.h.
| #define GPIO_INTTYPE_TYPE14_Pos (14) |
GPIO_T::INTTYPE: TYPE14 Position
Definition at line 16554 of file NUC472_442.h.
| #define GPIO_INTTYPE_TYPE15_Msk (0x1ul << GPIO_INTTYPE_TYPE15_Pos) |
GPIO_T::INTTYPE: TYPE15 Mask
Definition at line 16558 of file NUC472_442.h.
| #define GPIO_INTTYPE_TYPE15_Pos (15) |
GPIO_T::INTTYPE: TYPE15 Position
Definition at line 16557 of file NUC472_442.h.
| #define GPIO_INTTYPE_TYPE1_Msk (0x1ul << GPIO_INTTYPE_TYPE1_Pos) |
GPIO_T::INTTYPE: TYPE1 Mask
Definition at line 16516 of file NUC472_442.h.
| #define GPIO_INTTYPE_TYPE1_Pos (1) |
GPIO_T::INTTYPE: TYPE1 Position
Definition at line 16515 of file NUC472_442.h.
| #define GPIO_INTTYPE_TYPE2_Msk (0x1ul << GPIO_INTTYPE_TYPE2_Pos) |
GPIO_T::INTTYPE: TYPE2 Mask
Definition at line 16519 of file NUC472_442.h.
| #define GPIO_INTTYPE_TYPE2_Pos (2) |
GPIO_T::INTTYPE: TYPE2 Position
Definition at line 16518 of file NUC472_442.h.
| #define GPIO_INTTYPE_TYPE3_Msk (0x1ul << GPIO_INTTYPE_TYPE3_Pos) |
GPIO_T::INTTYPE: TYPE3 Mask
Definition at line 16522 of file NUC472_442.h.
| #define GPIO_INTTYPE_TYPE3_Pos (3) |
GPIO_T::INTTYPE: TYPE3 Position
Definition at line 16521 of file NUC472_442.h.
| #define GPIO_INTTYPE_TYPE4_Msk (0x1ul << GPIO_INTTYPE_TYPE4_Pos) |
GPIO_T::INTTYPE: TYPE4 Mask
Definition at line 16525 of file NUC472_442.h.
| #define GPIO_INTTYPE_TYPE4_Pos (4) |
GPIO_T::INTTYPE: TYPE4 Position
Definition at line 16524 of file NUC472_442.h.
| #define GPIO_INTTYPE_TYPE5_Msk (0x1ul << GPIO_INTTYPE_TYPE5_Pos) |
GPIO_T::INTTYPE: TYPE5 Mask
Definition at line 16528 of file NUC472_442.h.
| #define GPIO_INTTYPE_TYPE5_Pos (5) |
GPIO_T::INTTYPE: TYPE5 Position
Definition at line 16527 of file NUC472_442.h.
| #define GPIO_INTTYPE_TYPE6_Msk (0x1ul << GPIO_INTTYPE_TYPE6_Pos) |
GPIO_T::INTTYPE: TYPE6 Mask
Definition at line 16531 of file NUC472_442.h.
| #define GPIO_INTTYPE_TYPE6_Pos (6) |
GPIO_T::INTTYPE: TYPE6 Position
Definition at line 16530 of file NUC472_442.h.
| #define GPIO_INTTYPE_TYPE7_Msk (0x1ul << GPIO_INTTYPE_TYPE7_Pos) |
GPIO_T::INTTYPE: TYPE7 Mask
Definition at line 16534 of file NUC472_442.h.
| #define GPIO_INTTYPE_TYPE7_Pos (7) |
GPIO_T::INTTYPE: TYPE7 Position
Definition at line 16533 of file NUC472_442.h.
| #define GPIO_INTTYPE_TYPE8_Msk (0x1ul << GPIO_INTTYPE_TYPE8_Pos) |
GPIO_T::INTTYPE: TYPE8 Mask
Definition at line 16537 of file NUC472_442.h.
| #define GPIO_INTTYPE_TYPE8_Pos (8) |
GPIO_T::INTTYPE: TYPE8 Position
Definition at line 16536 of file NUC472_442.h.
| #define GPIO_INTTYPE_TYPE9_Msk (0x1ul << GPIO_INTTYPE_TYPE9_Pos) |
GPIO_T::INTTYPE: TYPE9 Mask
Definition at line 16540 of file NUC472_442.h.
| #define GPIO_INTTYPE_TYPE9_Pos (9) |
GPIO_T::INTTYPE: TYPE9 Position
Definition at line 16539 of file NUC472_442.h.
| #define GPIO_MODE_MODE0_Msk (0x3ul << GPIO_MODE_MODE0_Pos) |
GPIO_T::MODE: MODE0 Mask
Definition at line 16225 of file NUC472_442.h.
| #define GPIO_MODE_MODE0_Pos (0) |
@addtogroup GPIO_CONST GPIO Bit Field Definition Constant Definitions for GPIO Controller
GPIO_T::MODE: MODE0 Position
Definition at line 16224 of file NUC472_442.h.
| #define GPIO_MODE_MODE10_Msk (0x3ul << GPIO_MODE_MODE10_Pos) |
GPIO_T::MODE: MODE10 Mask
Definition at line 16255 of file NUC472_442.h.
| #define GPIO_MODE_MODE10_Pos (20) |
GPIO_T::MODE: MODE10 Position
Definition at line 16254 of file NUC472_442.h.
| #define GPIO_MODE_MODE11_Msk (0x3ul << GPIO_MODE_MODE11_Pos) |
GPIO_T::MODE: MODE11 Mask
Definition at line 16258 of file NUC472_442.h.
| #define GPIO_MODE_MODE11_Pos (22) |
GPIO_T::MODE: MODE11 Position
Definition at line 16257 of file NUC472_442.h.
| #define GPIO_MODE_MODE12_Msk (0x3ul << GPIO_MODE_MODE12_Pos) |
GPIO_T::MODE: MODE12 Mask
Definition at line 16261 of file NUC472_442.h.
| #define GPIO_MODE_MODE12_Pos (24) |
GPIO_T::MODE: MODE12 Position
Definition at line 16260 of file NUC472_442.h.
| #define GPIO_MODE_MODE13_Msk (0x3ul << GPIO_MODE_MODE13_Pos) |
GPIO_T::MODE: MODE13 Mask
Definition at line 16264 of file NUC472_442.h.
| #define GPIO_MODE_MODE13_Pos (26) |
GPIO_T::MODE: MODE13 Position
Definition at line 16263 of file NUC472_442.h.
| #define GPIO_MODE_MODE14_Msk (0x3ul << GPIO_MODE_MODE14_Pos) |
GPIO_T::MODE: MODE14 Mask
Definition at line 16267 of file NUC472_442.h.
| #define GPIO_MODE_MODE14_Pos (28) |
GPIO_T::MODE: MODE14 Position
Definition at line 16266 of file NUC472_442.h.
| #define GPIO_MODE_MODE15_Msk (0x3ul << GPIO_MODE_MODE15_Pos) |
GPIO_T::MODE: MODE15 Mask
Definition at line 16270 of file NUC472_442.h.
| #define GPIO_MODE_MODE15_Pos (30) |
GPIO_T::MODE: MODE15 Position
Definition at line 16269 of file NUC472_442.h.
| #define GPIO_MODE_MODE1_Msk (0x3ul << GPIO_MODE_MODE1_Pos) |
GPIO_T::MODE: MODE1 Mask
Definition at line 16228 of file NUC472_442.h.
| #define GPIO_MODE_MODE1_Pos (2) |
GPIO_T::MODE: MODE1 Position
Definition at line 16227 of file NUC472_442.h.
| #define GPIO_MODE_MODE2_Msk (0x3ul << GPIO_MODE_MODE2_Pos) |
GPIO_T::MODE: MODE2 Mask
Definition at line 16231 of file NUC472_442.h.
| #define GPIO_MODE_MODE2_Pos (4) |
GPIO_T::MODE: MODE2 Position
Definition at line 16230 of file NUC472_442.h.
| #define GPIO_MODE_MODE3_Msk (0x3ul << GPIO_MODE_MODE3_Pos) |
GPIO_T::MODE: MODE3 Mask
Definition at line 16234 of file NUC472_442.h.
| #define GPIO_MODE_MODE3_Pos (6) |
GPIO_T::MODE: MODE3 Position
Definition at line 16233 of file NUC472_442.h.
| #define GPIO_MODE_MODE4_Msk (0x3ul << GPIO_MODE_MODE4_Pos) |
GPIO_T::MODE: MODE4 Mask
Definition at line 16237 of file NUC472_442.h.
| #define GPIO_MODE_MODE4_Pos (8) |
GPIO_T::MODE: MODE4 Position
Definition at line 16236 of file NUC472_442.h.
| #define GPIO_MODE_MODE5_Msk (0x3ul << GPIO_MODE_MODE5_Pos) |
GPIO_T::MODE: MODE5 Mask
Definition at line 16240 of file NUC472_442.h.
| #define GPIO_MODE_MODE5_Pos (10) |
GPIO_T::MODE: MODE5 Position
Definition at line 16239 of file NUC472_442.h.
| #define GPIO_MODE_MODE6_Msk (0x3ul << GPIO_MODE_MODE6_Pos) |
GPIO_T::MODE: MODE6 Mask
Definition at line 16243 of file NUC472_442.h.
| #define GPIO_MODE_MODE6_Pos (12) |
GPIO_T::MODE: MODE6 Position
Definition at line 16242 of file NUC472_442.h.
| #define GPIO_MODE_MODE7_Msk (0x3ul << GPIO_MODE_MODE7_Pos) |
GPIO_T::MODE: MODE7 Mask
Definition at line 16246 of file NUC472_442.h.
| #define GPIO_MODE_MODE7_Pos (14) |
GPIO_T::MODE: MODE7 Position
Definition at line 16245 of file NUC472_442.h.
| #define GPIO_MODE_MODE8_Msk (0x3ul << GPIO_MODE_MODE8_Pos) |
GPIO_T::MODE: MODE8 Mask
Definition at line 16249 of file NUC472_442.h.
| #define GPIO_MODE_MODE8_Pos (16) |
GPIO_T::MODE: MODE8 Position
Definition at line 16248 of file NUC472_442.h.
| #define GPIO_MODE_MODE9_Msk (0x3ul << GPIO_MODE_MODE9_Pos) |
GPIO_T::MODE: MODE9 Mask
Definition at line 16252 of file NUC472_442.h.
| #define GPIO_MODE_MODE9_Pos (18) |
GPIO_T::MODE: MODE9 Position
Definition at line 16251 of file NUC472_442.h.
| #define GPIO_PIN_PIN0_Msk (0x1ul << GPIO_PIN_PIN0_Pos) |
GPIO_T::PIN: PIN0 Mask
Definition at line 16417 of file NUC472_442.h.
| #define GPIO_PIN_PIN0_Pos (0) |
GPIO_T::PIN: PIN0 Position
Definition at line 16416 of file NUC472_442.h.
| #define GPIO_PIN_PIN10_Msk (0x1ul << GPIO_PIN_PIN10_Pos) |
GPIO_T::PIN: PIN10 Mask
Definition at line 16447 of file NUC472_442.h.
| #define GPIO_PIN_PIN10_Pos (10) |
GPIO_T::PIN: PIN10 Position
Definition at line 16446 of file NUC472_442.h.
| #define GPIO_PIN_PIN11_Msk (0x1ul << GPIO_PIN_PIN11_Pos) |
GPIO_T::PIN: PIN11 Mask
Definition at line 16450 of file NUC472_442.h.
| #define GPIO_PIN_PIN11_Pos (11) |
GPIO_T::PIN: PIN11 Position
Definition at line 16449 of file NUC472_442.h.
| #define GPIO_PIN_PIN12_Msk (0x1ul << GPIO_PIN_PIN12_Pos) |
GPIO_T::PIN: PIN12 Mask
Definition at line 16453 of file NUC472_442.h.
| #define GPIO_PIN_PIN12_Pos (12) |
GPIO_T::PIN: PIN12 Position
Definition at line 16452 of file NUC472_442.h.
| #define GPIO_PIN_PIN13_Msk (0x1ul << GPIO_PIN_PIN13_Pos) |
GPIO_T::PIN: PIN13 Mask
Definition at line 16456 of file NUC472_442.h.
| #define GPIO_PIN_PIN13_Pos (13) |
GPIO_T::PIN: PIN13 Position
Definition at line 16455 of file NUC472_442.h.
| #define GPIO_PIN_PIN14_Msk (0x1ul << GPIO_PIN_PIN14_Pos) |
GPIO_T::PIN: PIN14 Mask
Definition at line 16459 of file NUC472_442.h.
| #define GPIO_PIN_PIN14_Pos (14) |
GPIO_T::PIN: PIN14 Position
Definition at line 16458 of file NUC472_442.h.
| #define GPIO_PIN_PIN15_Msk (0x1ul << GPIO_PIN_PIN15_Pos) |
GPIO_T::PIN: PIN15 Mask
Definition at line 16462 of file NUC472_442.h.
| #define GPIO_PIN_PIN15_Pos (15) |
GPIO_T::PIN: PIN15 Position
Definition at line 16461 of file NUC472_442.h.
| #define GPIO_PIN_PIN1_Msk (0x1ul << GPIO_PIN_PIN1_Pos) |
GPIO_T::PIN: PIN1 Mask
Definition at line 16420 of file NUC472_442.h.
| #define GPIO_PIN_PIN1_Pos (1) |
GPIO_T::PIN: PIN1 Position
Definition at line 16419 of file NUC472_442.h.
| #define GPIO_PIN_PIN2_Msk (0x1ul << GPIO_PIN_PIN2_Pos) |
GPIO_T::PIN: PIN2 Mask
Definition at line 16423 of file NUC472_442.h.
| #define GPIO_PIN_PIN2_Pos (2) |
GPIO_T::PIN: PIN2 Position
Definition at line 16422 of file NUC472_442.h.
| #define GPIO_PIN_PIN3_Msk (0x1ul << GPIO_PIN_PIN3_Pos) |
GPIO_T::PIN: PIN3 Mask
Definition at line 16426 of file NUC472_442.h.
| #define GPIO_PIN_PIN3_Pos (3) |
GPIO_T::PIN: PIN3 Position
Definition at line 16425 of file NUC472_442.h.
| #define GPIO_PIN_PIN4_Msk (0x1ul << GPIO_PIN_PIN4_Pos) |
GPIO_T::PIN: PIN4 Mask
Definition at line 16429 of file NUC472_442.h.
| #define GPIO_PIN_PIN4_Pos (4) |
GPIO_T::PIN: PIN4 Position
Definition at line 16428 of file NUC472_442.h.
| #define GPIO_PIN_PIN5_Msk (0x1ul << GPIO_PIN_PIN5_Pos) |
GPIO_T::PIN: PIN5 Mask
Definition at line 16432 of file NUC472_442.h.
| #define GPIO_PIN_PIN5_Pos (5) |
GPIO_T::PIN: PIN5 Position
Definition at line 16431 of file NUC472_442.h.
| #define GPIO_PIN_PIN6_Msk (0x1ul << GPIO_PIN_PIN6_Pos) |
GPIO_T::PIN: PIN6 Mask
Definition at line 16435 of file NUC472_442.h.
| #define GPIO_PIN_PIN6_Pos (6) |
GPIO_T::PIN: PIN6 Position
Definition at line 16434 of file NUC472_442.h.
| #define GPIO_PIN_PIN7_Msk (0x1ul << GPIO_PIN_PIN7_Pos) |
GPIO_T::PIN: PIN7 Mask
Definition at line 16438 of file NUC472_442.h.
| #define GPIO_PIN_PIN7_Pos (7) |
GPIO_T::PIN: PIN7 Position
Definition at line 16437 of file NUC472_442.h.
| #define GPIO_PIN_PIN8_Msk (0x1ul << GPIO_PIN_PIN8_Pos) |
GPIO_T::PIN: PIN8 Mask
Definition at line 16441 of file NUC472_442.h.
| #define GPIO_PIN_PIN8_Pos (8) |
GPIO_T::PIN: PIN8 Position
Definition at line 16440 of file NUC472_442.h.
| #define GPIO_PIN_PIN9_Msk (0x1ul << GPIO_PIN_PIN9_Pos) |
GPIO_T::PIN: PIN9 Mask
Definition at line 16444 of file NUC472_442.h.
| #define GPIO_PIN_PIN9_Pos (9) |
GPIO_T::PIN: PIN9 Position
Definition at line 16443 of file NUC472_442.h.
| #define GPIO_SLEWCTL_HSREN0_Msk (0x1ul << GPIO_SLEWCTL_HSREN0_Pos) |
GPIO_T::SLEWCTL: HSREN0 Mask
Definition at line 16753 of file NUC472_442.h.
| #define GPIO_SLEWCTL_HSREN0_Pos (0) |
GPIO_T::SLEWCTL: HSREN0 Position
Definition at line 16752 of file NUC472_442.h.
| #define GPIO_SLEWCTL_HSREN10_Msk (0x1ul << GPIO_SLEWCTL_HSREN10_Pos) |
GPIO_T::SLEWCTL: HSREN10 Mask
Definition at line 16783 of file NUC472_442.h.
| #define GPIO_SLEWCTL_HSREN10_Pos (10) |
GPIO_T::SLEWCTL: HSREN10 Position
Definition at line 16782 of file NUC472_442.h.
| #define GPIO_SLEWCTL_HSREN11_Msk (0x1ul << GPIO_SLEWCTL_HSREN11_Pos) |
GPIO_T::SLEWCTL: HSREN11 Mask
Definition at line 16786 of file NUC472_442.h.
| #define GPIO_SLEWCTL_HSREN11_Pos (11) |
GPIO_T::SLEWCTL: HSREN11 Position
Definition at line 16785 of file NUC472_442.h.
| #define GPIO_SLEWCTL_HSREN12_Msk (0x1ul << GPIO_SLEWCTL_HSREN12_Pos) |
GPIO_T::SLEWCTL: HSREN12 Mask
Definition at line 16789 of file NUC472_442.h.
| #define GPIO_SLEWCTL_HSREN12_Pos (12) |
GPIO_T::SLEWCTL: HSREN12 Position
Definition at line 16788 of file NUC472_442.h.
| #define GPIO_SLEWCTL_HSREN13_Msk (0x1ul << GPIO_SLEWCTL_HSREN13_Pos) |
GPIO_T::SLEWCTL: HSREN13 Mask
Definition at line 16792 of file NUC472_442.h.
| #define GPIO_SLEWCTL_HSREN13_Pos (13) |
GPIO_T::SLEWCTL: HSREN13 Position
Definition at line 16791 of file NUC472_442.h.
| #define GPIO_SLEWCTL_HSREN14_Msk (0x1ul << GPIO_SLEWCTL_HSREN14_Pos) |
GPIO_T::SLEWCTL: HSREN14 Mask
Definition at line 16795 of file NUC472_442.h.
| #define GPIO_SLEWCTL_HSREN14_Pos (14) |
GPIO_T::SLEWCTL: HSREN14 Position
Definition at line 16794 of file NUC472_442.h.
| #define GPIO_SLEWCTL_HSREN15_Msk (0x1ul << GPIO_SLEWCTL_HSREN15_Pos) |
GPIO_T::SLEWCTL: HSREN15 Mask
Definition at line 16798 of file NUC472_442.h.
| #define GPIO_SLEWCTL_HSREN15_Pos (15) |
GPIO_T::SLEWCTL: HSREN15 Position
Definition at line 16797 of file NUC472_442.h.
| #define GPIO_SLEWCTL_HSREN1_Msk (0x1ul << GPIO_SLEWCTL_HSREN1_Pos) |
GPIO_T::SLEWCTL: HSREN1 Mask
Definition at line 16756 of file NUC472_442.h.
| #define GPIO_SLEWCTL_HSREN1_Pos (1) |
GPIO_T::SLEWCTL: HSREN1 Position
Definition at line 16755 of file NUC472_442.h.
| #define GPIO_SLEWCTL_HSREN2_Msk (0x1ul << GPIO_SLEWCTL_HSREN2_Pos) |
GPIO_T::SLEWCTL: HSREN2 Mask
Definition at line 16759 of file NUC472_442.h.
| #define GPIO_SLEWCTL_HSREN2_Pos (2) |
GPIO_T::SLEWCTL: HSREN2 Position
Definition at line 16758 of file NUC472_442.h.
| #define GPIO_SLEWCTL_HSREN3_Msk (0x1ul << GPIO_SLEWCTL_HSREN3_Pos) |
GPIO_T::SLEWCTL: HSREN3 Mask
Definition at line 16762 of file NUC472_442.h.
| #define GPIO_SLEWCTL_HSREN3_Pos (3) |
GPIO_T::SLEWCTL: HSREN3 Position
Definition at line 16761 of file NUC472_442.h.
| #define GPIO_SLEWCTL_HSREN4_Msk (0x1ul << GPIO_SLEWCTL_HSREN4_Pos) |
GPIO_T::SLEWCTL: HSREN4 Mask
Definition at line 16765 of file NUC472_442.h.
| #define GPIO_SLEWCTL_HSREN4_Pos (4) |
GPIO_T::SLEWCTL: HSREN4 Position
Definition at line 16764 of file NUC472_442.h.
| #define GPIO_SLEWCTL_HSREN5_Msk (0x1ul << GPIO_SLEWCTL_HSREN5_Pos) |
GPIO_T::SLEWCTL: HSREN5 Mask
Definition at line 16768 of file NUC472_442.h.
| #define GPIO_SLEWCTL_HSREN5_Pos (5) |
GPIO_T::SLEWCTL: HSREN5 Position
Definition at line 16767 of file NUC472_442.h.
| #define GPIO_SLEWCTL_HSREN6_Msk (0x1ul << GPIO_SLEWCTL_HSREN6_Pos) |
GPIO_T::SLEWCTL: HSREN6 Mask
Definition at line 16771 of file NUC472_442.h.
| #define GPIO_SLEWCTL_HSREN6_Pos (6) |
GPIO_T::SLEWCTL: HSREN6 Position
Definition at line 16770 of file NUC472_442.h.
| #define GPIO_SLEWCTL_HSREN7_Msk (0x1ul << GPIO_SLEWCTL_HSREN7_Pos) |
GPIO_T::SLEWCTL: HSREN7 Mask
Definition at line 16774 of file NUC472_442.h.
| #define GPIO_SLEWCTL_HSREN7_Pos (7) |
GPIO_T::SLEWCTL: HSREN7 Position
Definition at line 16773 of file NUC472_442.h.
| #define GPIO_SLEWCTL_HSREN8_Msk (0x1ul << GPIO_SLEWCTL_HSREN8_Pos) |
GPIO_T::SLEWCTL: HSREN8 Mask
Definition at line 16777 of file NUC472_442.h.
| #define GPIO_SLEWCTL_HSREN8_Pos (8) |
GPIO_T::SLEWCTL: HSREN8 Position
Definition at line 16776 of file NUC472_442.h.
| #define GPIO_SLEWCTL_HSREN9_Msk (0x1ul << GPIO_SLEWCTL_HSREN9_Pos) |
GPIO_T::SLEWCTL: HSREN9 Mask
Definition at line 16780 of file NUC472_442.h.
| #define GPIO_SLEWCTL_HSREN9_Pos (9) |
GPIO_T::SLEWCTL: HSREN9 Position
Definition at line 16779 of file NUC472_442.h.
| #define GPIO_SMTEN_SMTEN0_Msk (0x1ul << GPIO_SMTEN_SMTEN0_Pos) |
GPIO_T::SMTEN: SMTEN0 Mask
Definition at line 16705 of file NUC472_442.h.
| #define GPIO_SMTEN_SMTEN0_Pos (0) |
GPIO_T::SMTEN: SMTEN0 Position
Definition at line 16704 of file NUC472_442.h.
| #define GPIO_SMTEN_SMTEN10_Msk (0x1ul << GPIO_SMTEN_SMTEN10_Pos) |
GPIO_T::SMTEN: SMTEN10 Mask
Definition at line 16735 of file NUC472_442.h.
| #define GPIO_SMTEN_SMTEN10_Pos (10) |
GPIO_T::SMTEN: SMTEN10 Position
Definition at line 16734 of file NUC472_442.h.
| #define GPIO_SMTEN_SMTEN11_Msk (0x1ul << GPIO_SMTEN_SMTEN11_Pos) |
GPIO_T::SMTEN: SMTEN11 Mask
Definition at line 16738 of file NUC472_442.h.
| #define GPIO_SMTEN_SMTEN11_Pos (11) |
GPIO_T::SMTEN: SMTEN11 Position
Definition at line 16737 of file NUC472_442.h.
| #define GPIO_SMTEN_SMTEN12_Msk (0x1ul << GPIO_SMTEN_SMTEN12_Pos) |
GPIO_T::SMTEN: SMTEN12 Mask
Definition at line 16741 of file NUC472_442.h.
| #define GPIO_SMTEN_SMTEN12_Pos (12) |
GPIO_T::SMTEN: SMTEN12 Position
Definition at line 16740 of file NUC472_442.h.
| #define GPIO_SMTEN_SMTEN13_Msk (0x1ul << GPIO_SMTEN_SMTEN13_Pos) |
GPIO_T::SMTEN: SMTEN13 Mask
Definition at line 16744 of file NUC472_442.h.
| #define GPIO_SMTEN_SMTEN13_Pos (13) |
GPIO_T::SMTEN: SMTEN13 Position
Definition at line 16743 of file NUC472_442.h.
| #define GPIO_SMTEN_SMTEN14_Msk (0x1ul << GPIO_SMTEN_SMTEN14_Pos) |
GPIO_T::SMTEN: SMTEN14 Mask
Definition at line 16747 of file NUC472_442.h.
| #define GPIO_SMTEN_SMTEN14_Pos (14) |
GPIO_T::SMTEN: SMTEN14 Position
Definition at line 16746 of file NUC472_442.h.
| #define GPIO_SMTEN_SMTEN15_Msk (0x1ul << GPIO_SMTEN_SMTEN15_Pos) |
GPIO_T::SMTEN: SMTEN15 Mask
Definition at line 16750 of file NUC472_442.h.
| #define GPIO_SMTEN_SMTEN15_Pos (15) |
GPIO_T::SMTEN: SMTEN15 Position
Definition at line 16749 of file NUC472_442.h.
| #define GPIO_SMTEN_SMTEN1_Msk (0x1ul << GPIO_SMTEN_SMTEN1_Pos) |
GPIO_T::SMTEN: SMTEN1 Mask
Definition at line 16708 of file NUC472_442.h.
| #define GPIO_SMTEN_SMTEN1_Pos (1) |
GPIO_T::SMTEN: SMTEN1 Position
Definition at line 16707 of file NUC472_442.h.
| #define GPIO_SMTEN_SMTEN2_Msk (0x1ul << GPIO_SMTEN_SMTEN2_Pos) |
GPIO_T::SMTEN: SMTEN2 Mask
Definition at line 16711 of file NUC472_442.h.
| #define GPIO_SMTEN_SMTEN2_Pos (2) |
GPIO_T::SMTEN: SMTEN2 Position
Definition at line 16710 of file NUC472_442.h.
| #define GPIO_SMTEN_SMTEN3_Msk (0x1ul << GPIO_SMTEN_SMTEN3_Pos) |
GPIO_T::SMTEN: SMTEN3 Mask
Definition at line 16714 of file NUC472_442.h.
| #define GPIO_SMTEN_SMTEN3_Pos (3) |
GPIO_T::SMTEN: SMTEN3 Position
Definition at line 16713 of file NUC472_442.h.
| #define GPIO_SMTEN_SMTEN4_Msk (0x1ul << GPIO_SMTEN_SMTEN4_Pos) |
GPIO_T::SMTEN: SMTEN4 Mask
Definition at line 16717 of file NUC472_442.h.
| #define GPIO_SMTEN_SMTEN4_Pos (4) |
GPIO_T::SMTEN: SMTEN4 Position
Definition at line 16716 of file NUC472_442.h.
| #define GPIO_SMTEN_SMTEN5_Msk (0x1ul << GPIO_SMTEN_SMTEN5_Pos) |
GPIO_T::SMTEN: SMTEN5 Mask
Definition at line 16720 of file NUC472_442.h.
| #define GPIO_SMTEN_SMTEN5_Pos (5) |
GPIO_T::SMTEN: SMTEN5 Position
Definition at line 16719 of file NUC472_442.h.
| #define GPIO_SMTEN_SMTEN6_Msk (0x1ul << GPIO_SMTEN_SMTEN6_Pos) |
GPIO_T::SMTEN: SMTEN6 Mask
Definition at line 16723 of file NUC472_442.h.
| #define GPIO_SMTEN_SMTEN6_Pos (6) |
GPIO_T::SMTEN: SMTEN6 Position
Definition at line 16722 of file NUC472_442.h.
| #define GPIO_SMTEN_SMTEN7_Msk (0x1ul << GPIO_SMTEN_SMTEN7_Pos) |
GPIO_T::SMTEN: SMTEN7 Mask
Definition at line 16726 of file NUC472_442.h.
| #define GPIO_SMTEN_SMTEN7_Pos (7) |
GPIO_T::SMTEN: SMTEN7 Position
Definition at line 16725 of file NUC472_442.h.
| #define GPIO_SMTEN_SMTEN8_Msk (0x1ul << GPIO_SMTEN_SMTEN8_Pos) |
GPIO_T::SMTEN: SMTEN8 Mask
Definition at line 16729 of file NUC472_442.h.
| #define GPIO_SMTEN_SMTEN8_Pos (8) |
GPIO_T::SMTEN: SMTEN8 Position
Definition at line 16728 of file NUC472_442.h.
| #define GPIO_SMTEN_SMTEN9_Msk (0x1ul << GPIO_SMTEN_SMTEN9_Pos) |
GPIO_T::SMTEN: SMTEN9 Mask
Definition at line 16732 of file NUC472_442.h.
| #define GPIO_SMTEN_SMTEN9_Pos (9) |
GPIO_T::SMTEN: SMTEN9 Position
Definition at line 16731 of file NUC472_442.h.
| #define I2C_ADDR0_ADDR_Msk (0x7ful << I2C_ADDR0_ADDR_Pos) |
I2C_T::ADDR0: ADDR Mask
Definition at line 17108 of file NUC472_442.h.
| #define I2C_ADDR0_ADDR_Pos (1) |
I2C_T::ADDR0: ADDR Position
Definition at line 17107 of file NUC472_442.h.
| #define I2C_ADDR0_GC_Msk (0x1ul << I2C_ADDR0_GC_Pos) |
I2C_T::ADDR0: GC Mask
Definition at line 17105 of file NUC472_442.h.
| #define I2C_ADDR0_GC_Pos (0) |
I2C_T::ADDR0: GC Position
Definition at line 17104 of file NUC472_442.h.
| #define I2C_ADDR1_ADDR_Msk (0x7ful << I2C_ADDR1_ADDR_Pos) |
I2C_T::ADDR1: ADDR Mask
Definition at line 17132 of file NUC472_442.h.
| #define I2C_ADDR1_ADDR_Pos (1) |
I2C_T::ADDR1: ADDR Position
Definition at line 17131 of file NUC472_442.h.
| #define I2C_ADDR1_GC_Msk (0x1ul << I2C_ADDR1_GC_Pos) |
I2C_T::ADDR1: GC Mask
Definition at line 17129 of file NUC472_442.h.
| #define I2C_ADDR1_GC_Pos (0) |
I2C_T::ADDR1: GC Position
Definition at line 17128 of file NUC472_442.h.
| #define I2C_ADDR2_ADDR_Msk (0x7ful << I2C_ADDR2_ADDR_Pos) |
I2C_T::ADDR2: ADDR Mask
Definition at line 17138 of file NUC472_442.h.
| #define I2C_ADDR2_ADDR_Pos (1) |
I2C_T::ADDR2: ADDR Position
Definition at line 17137 of file NUC472_442.h.
| #define I2C_ADDR2_GC_Msk (0x1ul << I2C_ADDR2_GC_Pos) |
I2C_T::ADDR2: GC Mask
Definition at line 17135 of file NUC472_442.h.
| #define I2C_ADDR2_GC_Pos (0) |
I2C_T::ADDR2: GC Position
Definition at line 17134 of file NUC472_442.h.
| #define I2C_ADDR3_ADDR_Msk (0x7ful << I2C_ADDR3_ADDR_Pos) |
I2C_T::ADDR3: ADDR Mask
Definition at line 17144 of file NUC472_442.h.
| #define I2C_ADDR3_ADDR_Pos (1) |
I2C_T::ADDR3: ADDR Position
Definition at line 17143 of file NUC472_442.h.
| #define I2C_ADDR3_GC_Msk (0x1ul << I2C_ADDR3_GC_Pos) |
I2C_T::ADDR3: GC Mask
Definition at line 17141 of file NUC472_442.h.
| #define I2C_ADDR3_GC_Pos (0) |
I2C_T::ADDR3: GC Position
Definition at line 17140 of file NUC472_442.h.
| #define I2C_ADDRMSK0_ADDRMSK_Msk (0x7ful << I2C_ADDRMSK0_ADDRMSK_Pos) |
I2C_T::ADDRMSK0: ADDRMSK Mask
Definition at line 17147 of file NUC472_442.h.
| #define I2C_ADDRMSK0_ADDRMSK_Pos (1) |
I2C_T::ADDRMSK0: ADDRMSK Position
Definition at line 17146 of file NUC472_442.h.
| #define I2C_ADDRMSK1_ADDRMSK_Msk (0x7ful << I2C_ADDRMSK1_ADDRMSK_Pos) |
I2C_T::ADDRMSK1: ADDRMSK Mask
Definition at line 17150 of file NUC472_442.h.
| #define I2C_ADDRMSK1_ADDRMSK_Pos (1) |
I2C_T::ADDRMSK1: ADDRMSK Position
Definition at line 17149 of file NUC472_442.h.
| #define I2C_ADDRMSK2_ADDRMSK_Msk (0x7ful << I2C_ADDRMSK2_ADDRMSK_Pos) |
I2C_T::ADDRMSK2: ADDRMSK Mask
Definition at line 17153 of file NUC472_442.h.
| #define I2C_ADDRMSK2_ADDRMSK_Pos (1) |
I2C_T::ADDRMSK2: ADDRMSK Position
Definition at line 17152 of file NUC472_442.h.
| #define I2C_ADDRMSK3_ADDRMSK_Msk (0x7ful << I2C_ADDRMSK3_ADDRMSK_Pos) |
I2C_T::ADDRMSK3: ADDRMSK Mask
Definition at line 17156 of file NUC472_442.h.
| #define I2C_ADDRMSK3_ADDRMSK_Pos (1) |
I2C_T::ADDRMSK3: ADDRMSK Position
Definition at line 17155 of file NUC472_442.h.
| #define I2C_CLKDIV_DIVIDER_Msk (0xfful << I2C_CLKDIV_DIVIDER_Pos) |
I2C_T::CLKDIV: DIVIDER Mask
Definition at line 17117 of file NUC472_442.h.
| #define I2C_CLKDIV_DIVIDER_Pos (0) |
I2C_T::CLKDIV: DIVIDER Position
Definition at line 17116 of file NUC472_442.h.
| #define I2C_CTL_AA_Msk (0x1ul << I2C_CTL_AA_Pos) |
I2C_T::CTL: AA Mask
Definition at line 17087 of file NUC472_442.h.
| #define I2C_CTL_AA_Pos (2) |
@addtogroup I2C_CONST I2C Bit Field Definition Constant Definitions for I2C Controller
I2C_T::CTL: AA Position
Definition at line 17086 of file NUC472_442.h.
| #define I2C_CTL_I2CEN_Msk (0x1ul << I2C_CTL_I2CEN_Pos) |
I2C_T::CTL: I2CEN Mask
Definition at line 17099 of file NUC472_442.h.
| #define I2C_CTL_I2CEN_Pos (6) |
I2C_T::CTL: I2CEN Position
Definition at line 17098 of file NUC472_442.h.
| #define I2C_CTL_INTEN_Msk (0x1ul << I2C_CTL_INTEN_Pos) |
I2C_T::CTL: INTEN Mask
Definition at line 17102 of file NUC472_442.h.
| #define I2C_CTL_INTEN_Pos (7) |
I2C_T::CTL: INTEN Position
Definition at line 17101 of file NUC472_442.h.
| #define I2C_CTL_SI_Msk (0x1ul << I2C_CTL_SI_Pos) |
I2C_T::CTL: SI Mask
Definition at line 17090 of file NUC472_442.h.
| #define I2C_CTL_SI_Pos (3) |
I2C_T::CTL: SI Position
Definition at line 17089 of file NUC472_442.h.
| #define I2C_CTL_STA_Msk (0x1ul << I2C_CTL_STA_Pos) |
I2C_T::CTL: STA Mask
Definition at line 17096 of file NUC472_442.h.
| #define I2C_CTL_STA_Pos (5) |
I2C_T::CTL: STA Position
Definition at line 17095 of file NUC472_442.h.
| #define I2C_CTL_STO_Msk (0x1ul << I2C_CTL_STO_Pos) |
I2C_T::CTL: STO Mask
Definition at line 17093 of file NUC472_442.h.
| #define I2C_CTL_STO_Pos (4) |
I2C_T::CTL: STO Position
Definition at line 17092 of file NUC472_442.h.
| #define I2C_DAT_DAT_Msk (0xfful << I2C_DAT_DAT_Pos) |
I2C_T::DAT: DAT Mask
Definition at line 17111 of file NUC472_442.h.
| #define I2C_DAT_DAT_Pos (0) |
I2C_T::DAT: DAT Position
Definition at line 17110 of file NUC472_442.h.
| #define I2C_STATUS_STATUS_Msk (0xfful << I2C_STATUS_STATUS_Pos) |
I2C_T::STATUS: STATUS Mask
Definition at line 17114 of file NUC472_442.h.
| #define I2C_STATUS_STATUS_Pos (0) |
I2C_T::STATUS: STATUS Position
Definition at line 17113 of file NUC472_442.h.
| #define I2C_TOCTL_TOCDIV4_Msk (0x1ul << I2C_TOCTL_TOCDIV4_Pos) |
I2C_T::TOCTL: TOCDIV4 Mask
Definition at line 17123 of file NUC472_442.h.
| #define I2C_TOCTL_TOCDIV4_Pos (1) |
I2C_T::TOCTL: TOCDIV4 Position
Definition at line 17122 of file NUC472_442.h.
| #define I2C_TOCTL_TOCEN_Msk (0x1ul << I2C_TOCTL_TOCEN_Pos) |
I2C_T::TOCTL: TOCEN Mask
Definition at line 17126 of file NUC472_442.h.
| #define I2C_TOCTL_TOCEN_Pos (2) |
I2C_T::TOCTL: TOCEN Position
Definition at line 17125 of file NUC472_442.h.
| #define I2C_TOCTL_TOIF_Msk (0x1ul << I2C_TOCTL_TOIF_Pos) |
I2C_T::TOCTL: TOIF Mask
Definition at line 17120 of file NUC472_442.h.
| #define I2C_TOCTL_TOIF_Pos (0) |
I2C_T::TOCTL: TOIF Position
Definition at line 17119 of file NUC472_442.h.
| #define I2C_WKCTL_WKEN_Msk (0x1ul << I2C_WKCTL_WKEN_Pos) |
I2C_T::WKCTL: WKEN Mask
Definition at line 17159 of file NUC472_442.h.
| #define I2C_WKCTL_WKEN_Pos (0) |
I2C_T::WKCTL: WKEN Position
Definition at line 17158 of file NUC472_442.h.
| #define I2C_WKSTS_WKIF_Msk (0x1ul << I2C_WKSTS_WKIF_Pos) |
I2C_T::WKSTS: WKIF Mask
Definition at line 17162 of file NUC472_442.h.
| #define I2C_WKSTS_WKIF_Pos (0) |
I2C_T::WKSTS: WKIF Position
Definition at line 17161 of file NUC472_442.h.
| #define I2S_CLKDIV_BCLKDIV_Msk (0x1fful << I2S_CLKDIV_BCLKDIV_Pos) |
I2S_T::CLKDIV: BCLKDIV Mask
Definition at line 17540 of file NUC472_442.h.
| #define I2S_CLKDIV_BCLKDIV_Pos (8) |
I2S_T::CLKDIV: BCLKDIV Position
Definition at line 17539 of file NUC472_442.h.
| #define I2S_CLKDIV_MCLKDIV_Msk (0x3ful << I2S_CLKDIV_MCLKDIV_Pos) |
I2S_T::CLKDIV: MCLKDIV Mask
Definition at line 17537 of file NUC472_442.h.
| #define I2S_CLKDIV_MCLKDIV_Pos (0) |
I2S_T::CLKDIV: MCLKDIV Position
Definition at line 17536 of file NUC472_442.h.
| #define I2S_CTL_FORMAT_Msk (0x1ul << I2S_CTL_FORMAT_Pos) |
I2S_T::CTL: FORMAT Mask
Definition at line 17498 of file NUC472_442.h.
| #define I2S_CTL_FORMAT_Pos (7) |
I2S_T::CTL: FORMAT Position
Definition at line 17497 of file NUC472_442.h.
| #define I2S_CTL_I2SEN_Msk (0x1ul << I2S_CTL_I2SEN_Pos) |
I2S_T::CTL: I2SEN Mask
Definition at line 17480 of file NUC472_442.h.
| #define I2S_CTL_I2SEN_Pos (0) |
@addtogroup I2S_CONST I2S Bit Field Definition Constant Definitions for I2S Controller
I2S_T::CTL: I2SEN Position
Definition at line 17479 of file NUC472_442.h.
| #define I2S_CTL_LZCEN_Msk (0x1ul << I2S_CTL_LZCEN_Pos) |
I2S_T::CTL: LZCEN Mask
Definition at line 17516 of file NUC472_442.h.
| #define I2S_CTL_LZCEN_Pos (17) |
I2S_T::CTL: LZCEN Position
Definition at line 17515 of file NUC472_442.h.
| #define I2S_CTL_MCLKEN_Msk (0x1ul << I2S_CTL_MCLKEN_Pos) |
I2S_T::CTL: MCLKEN Mask
Definition at line 17510 of file NUC472_442.h.
| #define I2S_CTL_MCLKEN_Pos (15) |
I2S_T::CTL: MCLKEN Position
Definition at line 17509 of file NUC472_442.h.
| #define I2S_CTL_MONO_Msk (0x1ul << I2S_CTL_MONO_Pos) |
I2S_T::CTL: MONO Mask
Definition at line 17495 of file NUC472_442.h.
| #define I2S_CTL_MONO_Pos (6) |
I2S_T::CTL: MONO Position
Definition at line 17494 of file NUC472_442.h.
| #define I2S_CTL_MUTE_Msk (0x1ul << I2S_CTL_MUTE_Pos) |
I2S_T::CTL: MUTE Mask
Definition at line 17489 of file NUC472_442.h.
| #define I2S_CTL_MUTE_Pos (3) |
I2S_T::CTL: MUTE Position
Definition at line 17488 of file NUC472_442.h.
| #define I2S_CTL_PCMEN_Msk (0x1ul << I2S_CTL_PCMEN_Pos) |
I2S_T::CTL: PCMEN Mask
Definition at line 17534 of file NUC472_442.h.
| #define I2S_CTL_PCMEN_Pos (24) |
I2S_T::CTL: PCMEN Position
Definition at line 17533 of file NUC472_442.h.
| #define I2S_CTL_RXCLR_Msk (0x1ul << I2S_CTL_RXCLR_Pos) |
I2S_T::CTL: RXCLR Mask
Definition at line 17522 of file NUC472_442.h.
| #define I2S_CTL_RXCLR_Pos (19) |
I2S_T::CTL: RXCLR Position
Definition at line 17521 of file NUC472_442.h.
| #define I2S_CTL_RXEN_Msk (0x1ul << I2S_CTL_RXEN_Pos) |
I2S_T::CTL: RXEN Mask
Definition at line 17486 of file NUC472_442.h.
| #define I2S_CTL_RXEN_Pos (2) |
I2S_T::CTL: RXEN Position
Definition at line 17485 of file NUC472_442.h.
| #define I2S_CTL_RXLCH_Msk (0x1ul << I2S_CTL_RXLCH_Pos) |
I2S_T::CTL: RXLCH Mask
Definition at line 17531 of file NUC472_442.h.
| #define I2S_CTL_RXLCH_Pos (23) |
I2S_T::CTL: RXLCH Position
Definition at line 17530 of file NUC472_442.h.
| #define I2S_CTL_RXPDMAEN_Msk (0x1ul << I2S_CTL_RXPDMAEN_Pos) |
I2S_T::CTL: RXPDMAEN Mask
Definition at line 17528 of file NUC472_442.h.
| #define I2S_CTL_RXPDMAEN_Pos (21) |
I2S_T::CTL: RXPDMAEN Position
Definition at line 17527 of file NUC472_442.h.
| #define I2S_CTL_RXTH_Msk (0x7ul << I2S_CTL_RXTH_Pos) |
I2S_T::CTL: RXTH Mask
Definition at line 17507 of file NUC472_442.h.
| #define I2S_CTL_RXTH_Pos (12) |
I2S_T::CTL: RXTH Position
Definition at line 17506 of file NUC472_442.h.
| #define I2S_CTL_RZCEN_Msk (0x1ul << I2S_CTL_RZCEN_Pos) |
I2S_T::CTL: RZCEN Mask
Definition at line 17513 of file NUC472_442.h.
| #define I2S_CTL_RZCEN_Pos (16) |
I2S_T::CTL: RZCEN Position
Definition at line 17512 of file NUC472_442.h.
| #define I2S_CTL_SLAVE_Msk (0x1ul << I2S_CTL_SLAVE_Pos) |
I2S_T::CTL: SLAVE Mask
Definition at line 17501 of file NUC472_442.h.
| #define I2S_CTL_SLAVE_Pos (8) |
I2S_T::CTL: SLAVE Position
Definition at line 17500 of file NUC472_442.h.
| #define I2S_CTL_TXCLR_Msk (0x1ul << I2S_CTL_TXCLR_Pos) |
I2S_T::CTL: TXCLR Mask
Definition at line 17519 of file NUC472_442.h.
| #define I2S_CTL_TXCLR_Pos (18) |
I2S_T::CTL: TXCLR Position
Definition at line 17518 of file NUC472_442.h.
| #define I2S_CTL_TXEN_Msk (0x1ul << I2S_CTL_TXEN_Pos) |
I2S_T::CTL: TXEN Mask
Definition at line 17483 of file NUC472_442.h.
| #define I2S_CTL_TXEN_Pos (1) |
I2S_T::CTL: TXEN Position
Definition at line 17482 of file NUC472_442.h.
| #define I2S_CTL_TXPDMAEN_Msk (0x1ul << I2S_CTL_TXPDMAEN_Pos) |
I2S_T::CTL: TXPDMAEN Mask
Definition at line 17525 of file NUC472_442.h.
| #define I2S_CTL_TXPDMAEN_Pos (20) |
I2S_T::CTL: TXPDMAEN Position
Definition at line 17524 of file NUC472_442.h.
| #define I2S_CTL_TXTH_Msk (0x7ul << I2S_CTL_TXTH_Pos) |
I2S_T::CTL: TXTH Mask
Definition at line 17504 of file NUC472_442.h.
| #define I2S_CTL_TXTH_Pos (9) |
I2S_T::CTL: TXTH Position
Definition at line 17503 of file NUC472_442.h.
| #define I2S_CTL_WDWIDTH_Msk (0x3ul << I2S_CTL_WDWIDTH_Pos) |
I2S_T::CTL: WDWIDTH Mask
Definition at line 17492 of file NUC472_442.h.
| #define I2S_CTL_WDWIDTH_Pos (4) |
I2S_T::CTL: WDWIDTH Position
Definition at line 17491 of file NUC472_442.h.
| #define I2S_IEN_LZCIEN_Msk (0x1ul << I2S_IEN_LZCIEN_Pos) |
I2S_T::IEN: LZCIEN Mask
Definition at line 17564 of file NUC472_442.h.
| #define I2S_IEN_LZCIEN_Pos (12) |
I2S_T::IEN: LZCIEN Position
Definition at line 17563 of file NUC472_442.h.
| #define I2S_IEN_RXOVIEN_Msk (0x1ul << I2S_IEN_RXOVIEN_Pos) |
I2S_T::IEN: RXOVIEN Mask
Definition at line 17546 of file NUC472_442.h.
| #define I2S_IEN_RXOVIEN_Pos (1) |
I2S_T::IEN: RXOVIEN Position
Definition at line 17545 of file NUC472_442.h.
| #define I2S_IEN_RXTHIEN_Msk (0x1ul << I2S_IEN_RXTHIEN_Pos) |
I2S_T::IEN: RXTHIEN Mask
Definition at line 17549 of file NUC472_442.h.
| #define I2S_IEN_RXTHIEN_Pos (2) |
I2S_T::IEN: RXTHIEN Position
Definition at line 17548 of file NUC472_442.h.
| #define I2S_IEN_RXUDIEN_Msk (0x1ul << I2S_IEN_RXUDIEN_Pos) |
I2S_T::IEN: RXUDIEN Mask
Definition at line 17543 of file NUC472_442.h.
| #define I2S_IEN_RXUDIEN_Pos (0) |
I2S_T::IEN: RXUDIEN Position
Definition at line 17542 of file NUC472_442.h.
| #define I2S_IEN_RZCIEN_Msk (0x1ul << I2S_IEN_RZCIEN_Pos) |
I2S_T::IEN: RZCIEN Mask
Definition at line 17561 of file NUC472_442.h.
| #define I2S_IEN_RZCIEN_Pos (11) |
I2S_T::IEN: RZCIEN Position
Definition at line 17560 of file NUC472_442.h.
| #define I2S_IEN_TXOVIEN_Msk (0x1ul << I2S_IEN_TXOVIEN_Pos) |
I2S_T::IEN: TXOVIEN Mask
Definition at line 17555 of file NUC472_442.h.
| #define I2S_IEN_TXOVIEN_Pos (9) |
I2S_T::IEN: TXOVIEN Position
Definition at line 17554 of file NUC472_442.h.
| #define I2S_IEN_TXTHIEN_Msk (0x1ul << I2S_IEN_TXTHIEN_Pos) |
I2S_T::IEN: TXTHIEN Mask
Definition at line 17558 of file NUC472_442.h.
| #define I2S_IEN_TXTHIEN_Pos (10) |
I2S_T::IEN: TXTHIEN Position
Definition at line 17557 of file NUC472_442.h.
| #define I2S_IEN_TXUDIEN_Msk (0x1ul << I2S_IEN_TXUDIEN_Pos) |
I2S_T::IEN: TXUDIEN Mask
Definition at line 17552 of file NUC472_442.h.
| #define I2S_IEN_TXUDIEN_Pos (8) |
I2S_T::IEN: TXUDIEN Position
Definition at line 17551 of file NUC472_442.h.
| #define I2S_RX_RX_Msk (0xfffffffful << I2S_RX_RX_Pos) |
I2S_T::RX: RX Mask
Definition at line 17627 of file NUC472_442.h.
| #define I2S_RX_RX_Pos (0) |
I2S_T::RX: RX Position
Definition at line 17626 of file NUC472_442.h.
| #define I2S_STATUS_I2SIF_Msk (0x1ul << I2S_STATUS_I2SIF_Pos) |
I2S_T::STATUS: I2SIF Mask
Definition at line 17567 of file NUC472_442.h.
| #define I2S_STATUS_I2SIF_Pos (0) |
I2S_T::STATUS: I2SIF Position
Definition at line 17566 of file NUC472_442.h.
| #define I2S_STATUS_LZCIF_Msk (0x1ul << I2S_STATUS_LZCIF_Pos) |
I2S_T::STATUS: LZCIF Mask
Definition at line 17615 of file NUC472_442.h.
| #define I2S_STATUS_LZCIF_Pos (23) |
I2S_T::STATUS: LZCIF Position
Definition at line 17614 of file NUC472_442.h.
| #define I2S_STATUS_RIGHT_Msk (0x1ul << I2S_STATUS_RIGHT_Pos) |
I2S_T::STATUS: RIGHT Mask
Definition at line 17576 of file NUC472_442.h.
| #define I2S_STATUS_RIGHT_Pos (3) |
I2S_T::STATUS: RIGHT Position
Definition at line 17575 of file NUC472_442.h.
| #define I2S_STATUS_RXCNT_Msk (0xful << I2S_STATUS_RXCNT_Pos) |
I2S_T::STATUS: RXCNT Mask
Definition at line 17618 of file NUC472_442.h.
| #define I2S_STATUS_RXCNT_Pos (24) |
I2S_T::STATUS: RXCNT Position
Definition at line 17617 of file NUC472_442.h.
| #define I2S_STATUS_RXEMPTY_Msk (0x1ul << I2S_STATUS_RXEMPTY_Pos) |
I2S_T::STATUS: RXEMPTY Mask
Definition at line 17591 of file NUC472_442.h.
| #define I2S_STATUS_RXEMPTY_Pos (12) |
I2S_T::STATUS: RXEMPTY Position
Definition at line 17590 of file NUC472_442.h.
| #define I2S_STATUS_RXFULL_Msk (0x1ul << I2S_STATUS_RXFULL_Pos) |
I2S_T::STATUS: RXFULL Mask
Definition at line 17588 of file NUC472_442.h.
| #define I2S_STATUS_RXFULL_Pos (11) |
I2S_T::STATUS: RXFULL Position
Definition at line 17587 of file NUC472_442.h.
| #define I2S_STATUS_RXIF_Msk (0x1ul << I2S_STATUS_RXIF_Pos) |
I2S_T::STATUS: RXIF Mask
Definition at line 17570 of file NUC472_442.h.
| #define I2S_STATUS_RXIF_Pos (1) |
I2S_T::STATUS: RXIF Position
Definition at line 17569 of file NUC472_442.h.
| #define I2S_STATUS_RXOVIF_Msk (0x1ul << I2S_STATUS_RXOVIF_Pos) |
I2S_T::STATUS: RXOVIF Mask
Definition at line 17582 of file NUC472_442.h.
| #define I2S_STATUS_RXOVIF_Pos (9) |
I2S_T::STATUS: RXOVIF Position
Definition at line 17581 of file NUC472_442.h.
| #define I2S_STATUS_RXTHIF_Msk (0x1ul << I2S_STATUS_RXTHIF_Pos) |
I2S_T::STATUS: RXTHIF Mask
Definition at line 17585 of file NUC472_442.h.
| #define I2S_STATUS_RXTHIF_Pos (10) |
I2S_T::STATUS: RXTHIF Position
Definition at line 17584 of file NUC472_442.h.
| #define I2S_STATUS_RXUDIF_Msk (0x1ul << I2S_STATUS_RXUDIF_Pos) |
I2S_T::STATUS: RXUDIF Mask
Definition at line 17579 of file NUC472_442.h.
| #define I2S_STATUS_RXUDIF_Pos (8) |
I2S_T::STATUS: RXUDIF Position
Definition at line 17578 of file NUC472_442.h.
| #define I2S_STATUS_RZCIF_Msk (0x1ul << I2S_STATUS_RZCIF_Pos) |
I2S_T::STATUS: RZCIF Mask
Definition at line 17612 of file NUC472_442.h.
| #define I2S_STATUS_RZCIF_Pos (22) |
I2S_T::STATUS: RZCIF Position
Definition at line 17611 of file NUC472_442.h.
| #define I2S_STATUS_TXBUSY_Msk (0x1ul << I2S_STATUS_TXBUSY_Pos) |
I2S_T::STATUS: TXBUSY Mask
Definition at line 17609 of file NUC472_442.h.
| #define I2S_STATUS_TXBUSY_Pos (21) |
I2S_T::STATUS: TXBUSY Position
Definition at line 17608 of file NUC472_442.h.
| #define I2S_STATUS_TXCNT_Msk (0xful << I2S_STATUS_TXCNT_Pos) |
I2S_T::STATUS: TXCNT Mask
Definition at line 17621 of file NUC472_442.h.
| #define I2S_STATUS_TXCNT_Pos (28) |
I2S_T::STATUS: TXCNT Position
Definition at line 17620 of file NUC472_442.h.
| #define I2S_STATUS_TXEMPTY_Msk (0x1ul << I2S_STATUS_TXEMPTY_Pos) |
I2S_T::STATUS: TXEMPTY Mask
Definition at line 17606 of file NUC472_442.h.
| #define I2S_STATUS_TXEMPTY_Pos (20) |
I2S_T::STATUS: TXEMPTY Position
Definition at line 17605 of file NUC472_442.h.
| #define I2S_STATUS_TXFULL_Msk (0x1ul << I2S_STATUS_TXFULL_Pos) |
I2S_T::STATUS: TXFULL Mask
Definition at line 17603 of file NUC472_442.h.
| #define I2S_STATUS_TXFULL_Pos (19) |
I2S_T::STATUS: TXFULL Position
Definition at line 17602 of file NUC472_442.h.
| #define I2S_STATUS_TXIF_Msk (0x1ul << I2S_STATUS_TXIF_Pos) |
I2S_T::STATUS: TXIF Mask
Definition at line 17573 of file NUC472_442.h.
| #define I2S_STATUS_TXIF_Pos (2) |
I2S_T::STATUS: TXIF Position
Definition at line 17572 of file NUC472_442.h.
| #define I2S_STATUS_TXOVIF_Msk (0x1ul << I2S_STATUS_TXOVIF_Pos) |
I2S_T::STATUS: TXOVIF Mask
Definition at line 17597 of file NUC472_442.h.
| #define I2S_STATUS_TXOVIF_Pos (17) |
I2S_T::STATUS: TXOVIF Position
Definition at line 17596 of file NUC472_442.h.
| #define I2S_STATUS_TXTHIF_Msk (0x1ul << I2S_STATUS_TXTHIF_Pos) |
I2S_T::STATUS: TXTHIF Mask
Definition at line 17600 of file NUC472_442.h.
| #define I2S_STATUS_TXTHIF_Pos (18) |
I2S_T::STATUS: TXTHIF Position
Definition at line 17599 of file NUC472_442.h.
| #define I2S_STATUS_TXUDIF_Msk (0x1ul << I2S_STATUS_TXUDIF_Pos) |
I2S_T::STATUS: TXUDIF Mask
Definition at line 17594 of file NUC472_442.h.
| #define I2S_STATUS_TXUDIF_Pos (16) |
I2S_T::STATUS: TXUDIF Position
Definition at line 17593 of file NUC472_442.h.
| #define I2S_TX_TX_Msk (0xfffffffful << I2S_TX_TX_Pos) |
I2S_T::TX: TX Mask
Definition at line 17624 of file NUC472_442.h.
| #define I2S_TX_TX_Pos (0) |
I2S_T::TX: TX Position
Definition at line 17623 of file NUC472_442.h.
| #define OPA_CTL_OPAIE0_Msk (0x1ul << OPA_CTL_OPAIE0_Pos) |
OPA_T::CTL: OPAIE0 Mask
Definition at line 17718 of file NUC472_442.h.
| #define OPA_CTL_OPAIE0_Pos (8) |
OPA_T::CTL: OPAIE0 Position
Definition at line 17717 of file NUC472_442.h.
| #define OPA_CTL_OPAIE1_Msk (0x1ul << OPA_CTL_OPAIE1_Pos) |
OPA_T::CTL: OPAIE1 Mask
Definition at line 17721 of file NUC472_442.h.
| #define OPA_CTL_OPAIE1_Pos (9) |
OPA_T::CTL: OPAIE1 Position
Definition at line 17720 of file NUC472_442.h.
| #define OPA_CTL_OPEN0_Msk (0x1ul << OPA_CTL_OPEN0_Pos) |
OPA_T::CTL: OPEN0 Mask
Definition at line 17706 of file NUC472_442.h.
| #define OPA_CTL_OPEN0_Pos (0) |
@addtogroup OPA_CONST OPA Bit Field Definition Constant Definitions for OPA Controller
OPA_T::CTL: OPEN0 Position
Definition at line 17705 of file NUC472_442.h.
| #define OPA_CTL_OPEN1_Msk (0x1ul << OPA_CTL_OPEN1_Pos) |
OPA_T::CTL: OPEN1 Mask
Definition at line 17709 of file NUC472_442.h.
| #define OPA_CTL_OPEN1_Pos (1) |
OPA_T::CTL: OPEN1 Position
Definition at line 17708 of file NUC472_442.h.
| #define OPA_CTL_OPSMTEN0_Msk (0x1ul << OPA_CTL_OPSMTEN0_Pos) |
OPA_T::CTL: OPSMTEN0 Mask
Definition at line 17712 of file NUC472_442.h.
| #define OPA_CTL_OPSMTEN0_Pos (4) |
OPA_T::CTL: OPSMTEN0 Position
Definition at line 17711 of file NUC472_442.h.
| #define OPA_CTL_OPSMTEN1_Msk (0x1ul << OPA_CTL_OPSMTEN1_Pos) |
OPA_T::CTL: OPSMTEN1 Mask
Definition at line 17715 of file NUC472_442.h.
| #define OPA_CTL_OPSMTEN1_Pos (5) |
OPA_T::CTL: OPSMTEN1 Position
Definition at line 17714 of file NUC472_442.h.
| #define OPA_STATUS_OPDF0_Msk (0x1ul << OPA_STATUS_OPDF0_Pos) |
OPA_T::STATUS: OPDF0 Mask
Definition at line 17730 of file NUC472_442.h.
| #define OPA_STATUS_OPDF0_Pos (4) |
OPA_T::STATUS: OPDF0 Position
Definition at line 17729 of file NUC472_442.h.
| #define OPA_STATUS_OPDF1_Msk (0x1ul << OPA_STATUS_OPDF1_Pos) |
OPA_T::STATUS: OPDF1 Mask
Definition at line 17733 of file NUC472_442.h.
| #define OPA_STATUS_OPDF1_Pos (5) |
OPA_T::STATUS: OPDF1 Position
Definition at line 17732 of file NUC472_442.h.
| #define OPA_STATUS_OPDO0_Msk (0x1ul << OPA_STATUS_OPDO0_Pos) |
OPA_T::STATUS: OPDO0 Mask
Definition at line 17724 of file NUC472_442.h.
| #define OPA_STATUS_OPDO0_Pos (0) |
OPA_T::STATUS: OPDO0 Position
Definition at line 17723 of file NUC472_442.h.
| #define OPA_STATUS_OPDO1_Msk (0x1ul << OPA_STATUS_OPDO1_Pos) |
OPA_T::STATUS: OPDO1 Mask
Definition at line 17727 of file NUC472_442.h.
| #define OPA_STATUS_OPDO1_Pos (1) |
OPA_T::STATUS: OPDO1 Position
Definition at line 17726 of file NUC472_442.h.
| #define OTG_CTL_BUSREQ_Msk (0x1ul << OTG_CTL_BUSREQ_Pos) |
OTG_T::CTL: BUSREQ Mask
Definition at line 17976 of file NUC472_442.h.
| #define OTG_CTL_BUSREQ_Pos (1) |
OTG_T::CTL: BUSREQ Position
Definition at line 17975 of file NUC472_442.h.
| #define OTG_CTL_HNPREQEN_Msk (0x1ul << OTG_CTL_HNPREQEN_Pos) |
OTG_T::CTL: HNPREQEN Mask
Definition at line 17979 of file NUC472_442.h.
| #define OTG_CTL_HNPREQEN_Pos (2) |
OTG_T::CTL: HNPREQEN Position
Definition at line 17978 of file NUC472_442.h.
| #define OTG_CTL_OTGEN_Msk (0x1ul << OTG_CTL_OTGEN_Pos) |
OTG_T::CTL: OTGEN Mask
Definition at line 17982 of file NUC472_442.h.
| #define OTG_CTL_OTGEN_Pos (4) |
OTG_T::CTL: OTGEN Position
Definition at line 17981 of file NUC472_442.h.
| #define OTG_CTL_PDEVCKON_Msk (0x1ul << OTG_CTL_PDEVCKON_Pos) |
OTG_T::CTL: PDEVCKON Mask
Definition at line 17985 of file NUC472_442.h.
| #define OTG_CTL_PDEVCKON_Pos (7) |
OTG_T::CTL: PDEVCKON Position
Definition at line 17984 of file NUC472_442.h.
| #define OTG_CTL_VBUSDROP_Msk (0x1ul << OTG_CTL_VBUSDROP_Pos) |
OTG_T::CTL: VBUSDROP Mask
Definition at line 17973 of file NUC472_442.h.
| #define OTG_CTL_VBUSDROP_Pos (0) |
@addtogroup OTG_CONST OTG Bit Field Definition Constant Definitions for OTG Controller
OTG_T::CTL: VBUSDROP Position
Definition at line 17972 of file NUC472_442.h.
| #define OTG_CTL_WKEN_Msk (0x1ul << OTG_CTL_WKEN_Pos) |
OTG_T::CTL: WKEN Mask
Definition at line 17988 of file NUC472_442.h.
| #define OTG_CTL_WKEN_Pos (8) |
OTG_T::CTL: WKEN Position
Definition at line 17987 of file NUC472_442.h.
| #define OTG_INTEN_AVLDCHGIEN_Msk (0x1ul << OTG_INTEN_AVLDCHGIEN_Pos) |
OTG_T::INTEN: AVLDCHGIEN Mask
Definition at line 18042 of file NUC472_442.h.
| #define OTG_INTEN_AVLDCHGIEN_Pos (9) |
OTG_T::INTEN: AVLDCHGIEN Position
Definition at line 18041 of file NUC472_442.h.
| #define OTG_INTEN_BVLDCHGIEN_Msk (0x1ul << OTG_INTEN_BVLDCHGIEN_Pos) |
OTG_T::INTEN: BVLDCHGIEN Mask
Definition at line 18039 of file NUC472_442.h.
| #define OTG_INTEN_BVLDCHGIEN_Pos (8) |
OTG_T::INTEN: BVLDCHGIEN Position
Definition at line 18038 of file NUC472_442.h.
| #define OTG_INTEN_GOIDLEIEN_Msk (0x1ul << OTG_INTEN_GOIDLEIEN_Pos) |
OTG_T::INTEN: GOIDLEIEN Mask
Definition at line 18027 of file NUC472_442.h.
| #define OTG_INTEN_GOIDLEIEN_Pos (4) |
OTG_T::INTEN: GOIDLEIEN Position
Definition at line 18026 of file NUC472_442.h.
| #define OTG_INTEN_HNPFIEN_Msk (0x1ul << OTG_INTEN_HNPFIEN_Pos) |
OTG_T::INTEN: HNPFIEN Mask
Definition at line 18024 of file NUC472_442.h.
| #define OTG_INTEN_HNPFIEN_Pos (3) |
OTG_T::INTEN: HNPFIEN Position
Definition at line 18023 of file NUC472_442.h.
| #define OTG_INTEN_HOSTIEN_Msk (0x1ul << OTG_INTEN_HOSTIEN_Pos) |
OTG_T::INTEN: HOSTIEN Mask
Definition at line 18036 of file NUC472_442.h.
| #define OTG_INTEN_HOSTIEN_Pos (7) |
OTG_T::INTEN: HOSTIEN Position
Definition at line 18035 of file NUC472_442.h.
| #define OTG_INTEN_IDCHGIEN_Msk (0x1ul << OTG_INTEN_IDCHGIEN_Pos) |
OTG_T::INTEN: IDCHGIEN Mask
Definition at line 18030 of file NUC472_442.h.
| #define OTG_INTEN_IDCHGIEN_Pos (5) |
OTG_T::INTEN: IDCHGIEN Position
Definition at line 18029 of file NUC472_442.h.
| #define OTG_INTEN_PDEVIEN_Msk (0x1ul << OTG_INTEN_PDEVIEN_Pos) |
OTG_T::INTEN: PDEVIEN Mask
Definition at line 18033 of file NUC472_442.h.
| #define OTG_INTEN_PDEVIEN_Pos (6) |
OTG_T::INTEN: PDEVIEN Position
Definition at line 18032 of file NUC472_442.h.
| #define OTG_INTEN_ROLECHGIEN_Msk (0x1ul << OTG_INTEN_ROLECHGIEN_Pos) |
OTG_T::INTEN: ROLECHGIEN Mask
Definition at line 18015 of file NUC472_442.h.
| #define OTG_INTEN_ROLECHGIEN_Pos (0) |
OTG_T::INTEN: ROLECHGIEN Position
Definition at line 18014 of file NUC472_442.h.
| #define OTG_INTEN_SECHGIEN_Msk (0x1ul << OTG_INTEN_SECHGIEN_Pos) |
OTG_T::INTEN: SECHGIEN Mask
Definition at line 18048 of file NUC472_442.h.
| #define OTG_INTEN_SECHGIEN_Pos (11) |
OTG_T::INTEN: SECHGIEN Position
Definition at line 18047 of file NUC472_442.h.
| #define OTG_INTEN_SRPDETIEN_Msk (0x1ul << OTG_INTEN_SRPDETIEN_Pos) |
OTG_T::INTEN: SRPDETIEN Mask
Definition at line 18051 of file NUC472_442.h.
| #define OTG_INTEN_SRPDETIEN_Pos (13) |
OTG_T::INTEN: SRPDETIEN Position
Definition at line 18050 of file NUC472_442.h.
| #define OTG_INTEN_SRPFIEN_Msk (0x1ul << OTG_INTEN_SRPFIEN_Pos) |
OTG_T::INTEN: SRPFIEN Mask
Definition at line 18021 of file NUC472_442.h.
| #define OTG_INTEN_SRPFIEN_Pos (2) |
OTG_T::INTEN: SRPFIEN Position
Definition at line 18020 of file NUC472_442.h.
| #define OTG_INTEN_VBCHGIEN_Msk (0x1ul << OTG_INTEN_VBCHGIEN_Pos) |
OTG_T::INTEN: VBCHGIEN Mask
Definition at line 18045 of file NUC472_442.h.
| #define OTG_INTEN_VBCHGIEN_Pos (10) |
OTG_T::INTEN: VBCHGIEN Position
Definition at line 18044 of file NUC472_442.h.
| #define OTG_INTEN_VBEIEN_Msk (0x1ul << OTG_INTEN_VBEIEN_Pos) |
OTG_T::INTEN: VBEIEN Mask
Definition at line 18018 of file NUC472_442.h.
| #define OTG_INTEN_VBEIEN_Pos (1) |
OTG_T::INTEN: VBEIEN Position
Definition at line 18017 of file NUC472_442.h.
| #define OTG_INTSTS_AVLDCHGIF_Msk (0x1ul << OTG_INTSTS_AVLDCHGIF_Pos) |
OTG_T::INTSTS: AVLDCHGIF Mask
Definition at line 18081 of file NUC472_442.h.
| #define OTG_INTSTS_AVLDCHGIF_Pos (9) |
OTG_T::INTSTS: AVLDCHGIF Position
Definition at line 18080 of file NUC472_442.h.
| #define OTG_INTSTS_BVLDCHGIF_Msk (0x1ul << OTG_INTSTS_BVLDCHGIF_Pos) |
OTG_T::INTSTS: BVLDCHGIF Mask
Definition at line 18078 of file NUC472_442.h.
| #define OTG_INTSTS_BVLDCHGIF_Pos (8) |
OTG_T::INTSTS: BVLDCHGIF Position
Definition at line 18077 of file NUC472_442.h.
| #define OTG_INTSTS_GOIDLEIF_Msk (0x1ul << OTG_INTSTS_GOIDLEIF_Pos) |
OTG_T::INTSTS: GOIDLEIF Mask
Definition at line 18066 of file NUC472_442.h.
| #define OTG_INTSTS_GOIDLEIF_Pos (4) |
OTG_T::INTSTS: GOIDLEIF Position
Definition at line 18065 of file NUC472_442.h.
| #define OTG_INTSTS_HNPFIF_Msk (0x1ul << OTG_INTSTS_HNPFIF_Pos) |
OTG_T::INTSTS: HNPFIF Mask
Definition at line 18063 of file NUC472_442.h.
| #define OTG_INTSTS_HNPFIF_Pos (3) |
OTG_T::INTSTS: HNPFIF Position
Definition at line 18062 of file NUC472_442.h.
| #define OTG_INTSTS_HOSTIF_Msk (0x1ul << OTG_INTSTS_HOSTIF_Pos) |
OTG_T::INTSTS: HOSTIF Mask
Definition at line 18075 of file NUC472_442.h.
| #define OTG_INTSTS_HOSTIF_Pos (7) |
OTG_T::INTSTS: HOSTIF Position
Definition at line 18074 of file NUC472_442.h.
| #define OTG_INTSTS_IDCHGIF_Msk (0x1ul << OTG_INTSTS_IDCHGIF_Pos) |
OTG_T::INTSTS: IDCHGIF Mask
Definition at line 18069 of file NUC472_442.h.
| #define OTG_INTSTS_IDCHGIF_Pos (5) |
OTG_T::INTSTS: IDCHGIF Position
Definition at line 18068 of file NUC472_442.h.
| #define OTG_INTSTS_PDEVIF_Msk (0x1ul << OTG_INTSTS_PDEVIF_Pos) |
OTG_T::INTSTS: PDEVIF Mask
Definition at line 18072 of file NUC472_442.h.
| #define OTG_INTSTS_PDEVIF_Pos (6) |
OTG_T::INTSTS: PDEVIF Position
Definition at line 18071 of file NUC472_442.h.
| #define OTG_INTSTS_ROLECHGIF_Msk (0x1ul << OTG_INTSTS_ROLECHGIF_Pos) |
OTG_T::INTSTS: ROLECHGIF Mask
Definition at line 18054 of file NUC472_442.h.
| #define OTG_INTSTS_ROLECHGIF_Pos (0) |
OTG_T::INTSTS: ROLECHGIF Position
Definition at line 18053 of file NUC472_442.h.
| #define OTG_INTSTS_SECHGIF_Msk (0x1ul << OTG_INTSTS_SECHGIF_Pos) |
OTG_T::INTSTS: SECHGIF Mask
Definition at line 18087 of file NUC472_442.h.
| #define OTG_INTSTS_SECHGIF_Pos (11) |
OTG_T::INTSTS: SECHGIF Position
Definition at line 18086 of file NUC472_442.h.
| #define OTG_INTSTS_SRPDETIF_Msk (0x1ul << OTG_INTSTS_SRPDETIF_Pos) |
OTG_T::INTSTS: SRPDETIF Mask
Definition at line 18090 of file NUC472_442.h.
| #define OTG_INTSTS_SRPDETIF_Pos (13) |
OTG_T::INTSTS: SRPDETIF Position
Definition at line 18089 of file NUC472_442.h.
| #define OTG_INTSTS_SRPFIF_Msk (0x1ul << OTG_INTSTS_SRPFIF_Pos) |
OTG_T::INTSTS: SRPFIF Mask
Definition at line 18060 of file NUC472_442.h.
| #define OTG_INTSTS_SRPFIF_Pos (2) |
OTG_T::INTSTS: SRPFIF Position
Definition at line 18059 of file NUC472_442.h.
| #define OTG_INTSTS_VBCHGIF_Msk (0x1ul << OTG_INTSTS_VBCHGIF_Pos) |
OTG_T::INTSTS: VBCHGIF Mask
Definition at line 18084 of file NUC472_442.h.
| #define OTG_INTSTS_VBCHGIF_Pos (10) |
OTG_T::INTSTS: VBCHGIF Position
Definition at line 18083 of file NUC472_442.h.
| #define OTG_INTSTS_VBEIF_Msk (0x1ul << OTG_INTSTS_VBEIF_Pos) |
OTG_T::INTSTS: VBEIF Mask
Definition at line 18057 of file NUC472_442.h.
| #define OTG_INTSTS_VBEIF_Pos (1) |
OTG_T::INTSTS: VBEIF Position
Definition at line 18056 of file NUC472_442.h.
| #define OTG_PHYCTL_DMPDEN_Msk (0x1ul << OTG_PHYCTL_DMPDEN_Pos) |
OTG_T::PHYCTL: DMPDEN Mask
Definition at line 17997 of file NUC472_442.h.
| #define OTG_PHYCTL_DMPDEN_Pos (2) |
OTG_T::PHYCTL: DMPDEN Position
Definition at line 17996 of file NUC472_442.h.
| #define OTG_PHYCTL_DPPDEN_Msk (0x1ul << OTG_PHYCTL_DPPDEN_Pos) |
OTG_T::PHYCTL: DPPDEN Mask
Definition at line 17994 of file NUC472_442.h.
| #define OTG_PHYCTL_DPPDEN_Pos (1) |
OTG_T::PHYCTL: DPPDEN Position
Definition at line 17993 of file NUC472_442.h.
| #define OTG_PHYCTL_IDDETEN_Msk (0x1ul << OTG_PHYCTL_IDDETEN_Pos) |
OTG_T::PHYCTL: IDDETEN Mask
Definition at line 18006 of file NUC472_442.h.
| #define OTG_PHYCTL_IDDETEN_Pos (7) |
OTG_T::PHYCTL: IDDETEN Position
Definition at line 18005 of file NUC472_442.h.
| #define OTG_PHYCTL_OTGPHYEN_Msk (0x1ul << OTG_PHYCTL_OTGPHYEN_Pos) |
OTG_T::PHYCTL: OTGPHYEN Mask
Definition at line 18012 of file NUC472_442.h.
| #define OTG_PHYCTL_OTGPHYEN_Pos (9) |
OTG_T::PHYCTL: OTGPHYEN Position
Definition at line 18011 of file NUC472_442.h.
| #define OTG_PHYCTL_PHYCLK_Msk (0x1ul << OTG_PHYCTL_PHYCLK_Pos) |
OTG_T::PHYCTL: PHYCLK Mask
Definition at line 18009 of file NUC472_442.h.
| #define OTG_PHYCTL_PHYCLK_Pos (8) |
OTG_T::PHYCTL: PHYCLK Position
Definition at line 18008 of file NUC472_442.h.
| #define OTG_PHYCTL_SWPDEN_Msk (0x1ul << OTG_PHYCTL_SWPDEN_Pos) |
OTG_T::PHYCTL: SWPDEN Mask
Definition at line 17991 of file NUC472_442.h.
| #define OTG_PHYCTL_SWPDEN_Pos (0) |
OTG_T::PHYCTL: SWPDEN Position
Definition at line 17990 of file NUC472_442.h.
| #define OTG_PHYCTL_VBENPOL_Msk (0x1ul << OTG_PHYCTL_VBENPOL_Pos) |
OTG_T::PHYCTL: VBUSPOL Mask
Definition at line 18003 of file NUC472_442.h.
| #define OTG_PHYCTL_VBENPOL_Pos (6) |
OTG_T::PHYCTL: VBUSPOL Position
Definition at line 18002 of file NUC472_442.h.
| #define OTG_PHYCTL_VBSTSPOL_Msk (0x1ul << OTG_PHYCTL_VBSTSPOL_Pos) |
OTG_T::PHYCTL: VBSTSPOL Mask
Definition at line 18000 of file NUC472_442.h.
| #define OTG_PHYCTL_VBSTSPOL_Pos (5) |
OTG_T::PHYCTL: VBSTSPOL Position
Definition at line 17999 of file NUC472_442.h.
| #define OTG_STATUS_AVLD_Msk (0x1ul << OTG_STATUS_AVLD_Pos) |
OTG_T::STATUS: AVLD Mask
Definition at line 18105 of file NUC472_442.h.
| #define OTG_STATUS_AVLD_Pos (4) |
OTG_T::STATUS: AVLD Position
Definition at line 18104 of file NUC472_442.h.
| #define OTG_STATUS_BVLD_Msk (0x1ul << OTG_STATUS_BVLD_Pos) |
OTG_T::STATUS: BVLD Mask
Definition at line 18102 of file NUC472_442.h.
| #define OTG_STATUS_BVLD_Pos (3) |
OTG_T::STATUS: BVLD Position
Definition at line 18101 of file NUC472_442.h.
| #define OTG_STATUS_IDSTS_Msk (0x1ul << OTG_STATUS_IDSTS_Pos) |
OTG_T::STATUS: IDSTS Mask
Definition at line 18096 of file NUC472_442.h.
| #define OTG_STATUS_IDSTS_Pos (1) |
OTG_T::STATUS: IDSTS Position
Definition at line 18095 of file NUC472_442.h.
| #define OTG_STATUS_OVERCUR_Msk (0x1ul << OTG_STATUS_OVERCUR_Pos) |
OTG_T::STATUS: OVERCUR Mask
Definition at line 18093 of file NUC472_442.h.
| #define OTG_STATUS_OVERCUR_Pos (0) |
OTG_T::STATUS: OVERCUR Position
Definition at line 18092 of file NUC472_442.h.
| #define OTG_STATUS_SESSEND_Msk (0x1ul << OTG_STATUS_SESSEND_Pos) |
OTG_T::STATUS: SESSEND Mask
Definition at line 18099 of file NUC472_442.h.
| #define OTG_STATUS_SESSEND_Pos (2) |
OTG_T::STATUS: SESSEND Position
Definition at line 18098 of file NUC472_442.h.
| #define OTG_STATUS_VBUSVLD_Msk (0x1ul << OTG_STATUS_VBUSVLD_Pos) |
OTG_T::STATUS: VBUSVLD Mask
Definition at line 18108 of file NUC472_442.h.
| #define OTG_STATUS_VBUSVLD_Pos (5) |
OTG_T::STATUS: VBUSVLD Position
Definition at line 18107 of file NUC472_442.h.
| #define PDMA_ABTSTS_ABTIF_Msk (0xfffful << PDMA_ABTSTS_ABTIF_Pos) |
PDMA_T::ABTSTS: ABTIF Mask
Definition at line 18673 of file NUC472_442.h.
| #define PDMA_ABTSTS_ABTIF_Pos (0) |
PDMA_T::ABTSTS: ABTIF Position
Definition at line 18672 of file NUC472_442.h.
| #define PDMA_CHCTL_CHEN_Msk (0xfffful << PDMA_CHCTL_CHEN_Pos) |
PDMA_T::CHCTL: CHEN Mask
Definition at line 18643 of file NUC472_442.h.
| #define PDMA_CHCTL_CHEN_Pos (0) |
PDMA_T::CHCTL: CHEN Position
Definition at line 18642 of file NUC472_442.h.
| #define PDMA_DSCT_CTL_BURSIZE_Msk (0x7ul << PDMA_DSCT_CTL_BURSIZE_Pos) |
DSCT_T::CTL: BURSIZE Mask
Definition at line 18616 of file NUC472_442.h.
| #define PDMA_DSCT_CTL_BURSIZE_Pos (4) |
DSCT_T::CTL: BURSIZE Position
Definition at line 18615 of file NUC472_442.h.
| #define PDMA_DSCT_CTL_DAINC_Msk (0x3ul << PDMA_DSCT_CTL_DAINC_Pos) |
DSCT_T::CTL: DAINC Mask
Definition at line 18625 of file NUC472_442.h.
| #define PDMA_DSCT_CTL_DAINC_Pos (10) |
DSCT_T::CTL: DAINC Position
Definition at line 18624 of file NUC472_442.h.
| #define PDMA_DSCT_CTL_OPMODE_Msk (0x3ul << PDMA_DSCT_CTL_OPMODE_Pos) |
DSCT_T::CTL: OPMODE Mask
Definition at line 18610 of file NUC472_442.h.
| #define PDMA_DSCT_CTL_OPMODE_Pos (0) |
@addtogroup PDMA_CONST PDMA Bit Field Definition Constant Definitions for PDMA Controller
DSCT_T::CTL: OPMODE Position
Definition at line 18609 of file NUC472_442.h.
| #define PDMA_DSCT_CTL_SAINC_Msk (0x3ul << PDMA_DSCT_CTL_SAINC_Pos) |
DSCT_T::CTL: SAINC Mask
Definition at line 18622 of file NUC472_442.h.
| #define PDMA_DSCT_CTL_SAINC_Pos (8) |
DSCT_T::CTL: SAINC Position
Definition at line 18621 of file NUC472_442.h.
| #define PDMA_DSCT_CTL_TBINTDIS_Msk (0x1ul << PDMA_DSCT_CTL_TBINTDIS_Pos) |
DSCT_T::CTL: TBINTDIS Mask
Definition at line 18619 of file NUC472_442.h.
| #define PDMA_DSCT_CTL_TBINTDIS_Pos (7) |
DSCT_T::CTL: TBINTDIS Position
Definition at line 18618 of file NUC472_442.h.
| #define PDMA_DSCT_CTL_TXCNT_Msk (0x3ffful << PDMA_DSCT_CTL_TXCNT_Pos) |
DSCT_T::CTL: TXCNT Mask
Definition at line 18631 of file NUC472_442.h.
| #define PDMA_DSCT_CTL_TXCNT_Pos (16) |
DSCT_T::CTL: TXCNT Position
Definition at line 18630 of file NUC472_442.h.
| #define PDMA_DSCT_CTL_TXTYPE_Msk (0x1ul << PDMA_DSCT_CTL_TXTYPE_Pos) |
DSCT_T::CTL: TXTYPE Mask
Definition at line 18613 of file NUC472_442.h.
| #define PDMA_DSCT_CTL_TXTYPE_Pos (2) |
DSCT_T::CTL: TXTYPE Position
Definition at line 18612 of file NUC472_442.h.
| #define PDMA_DSCT_CTL_TXWIDTH_Msk (0x3ul << PDMA_DSCT_CTL_TXWIDTH_Pos) |
DSCT_T::CTL: TXWIDTH Mask
Definition at line 18628 of file NUC472_442.h.
| #define PDMA_DSCT_CTL_TXWIDTH_Pos (12) |
DSCT_T::CTL: TXWIDTH Position
Definition at line 18627 of file NUC472_442.h.
| #define PDMA_DSCT_ENDDA_ENDDA_Msk (0xfffffffful << PDMA_DSCT_ENDDA_ENDDA_Pos) |
DSCT_T::ENDDA: ENDDA Mask
Definition at line 18637 of file NUC472_442.h.
| #define PDMA_DSCT_ENDDA_ENDDA_Pos (0) |
DSCT_T::ENDDA: ENDDA Position
Definition at line 18636 of file NUC472_442.h.
| #define PDMA_DSCT_ENDSA_ENDSA_Msk (0xfffffffful << PDMA_DSCT_ENDSA_ENDSA_Pos) |
DSCT_T::ENDSA: ENDSA Mask
Definition at line 18634 of file NUC472_442.h.
| #define PDMA_DSCT_ENDSA_ENDSA_Pos (0) |
DSCT_T::ENDSA: ENDSA Position
Definition at line 18633 of file NUC472_442.h.
| #define PDMA_DSCT_NEXT_NEXT_Msk (0x3ffful << PDMA_DSCT_NEXT_NEXT_Pos) |
DSCT_T::NEXT: NEXT Mask
Definition at line 18640 of file NUC472_442.h.
| #define PDMA_DSCT_NEXT_NEXT_Pos (2) |
DSCT_T::NEXT: NEXT Position
Definition at line 18639 of file NUC472_442.h.
| #define PDMA_INTEN_INTEN_Msk (0xfffful << PDMA_INTEN_INTEN_Pos) |
PDMA_T::INTEN: INTEN Mask
Definition at line 18661 of file NUC472_442.h.
| #define PDMA_INTEN_INTEN_Pos (0) |
PDMA_T::INTEN: INTEN Position
Definition at line 18660 of file NUC472_442.h.
| #define PDMA_INTSTS_ABTIF_Msk (0x1ul << PDMA_INTSTS_ABTIF_Pos) |
PDMA_T::INTSTS: ABTIF Mask
Definition at line 18664 of file NUC472_442.h.
| #define PDMA_INTSTS_ABTIF_Pos (0) |
PDMA_T::INTSTS: ABTIF Position
Definition at line 18663 of file NUC472_442.h.
| #define PDMA_INTSTS_TDIF_Msk (0x1ul << PDMA_INTSTS_TDIF_Pos) |
PDMA_T::INTSTS: TDIF Mask
Definition at line 18667 of file NUC472_442.h.
| #define PDMA_INTSTS_TDIF_Pos (1) |
PDMA_T::INTSTS: TDIF Position
Definition at line 18666 of file NUC472_442.h.
| #define PDMA_INTSTS_TEIF_Msk (0x1ul << PDMA_INTSTS_TEIF_Pos) |
PDMA_T::INTSTS: TEIF Mask
Definition at line 18670 of file NUC472_442.h.
| #define PDMA_INTSTS_TEIF_Pos (2) |
PDMA_T::INTSTS: TEIF Position
Definition at line 18669 of file NUC472_442.h.
| #define PDMA_PRICLR_FPRICLR_Msk (0xfffful << PDMA_PRICLR_FPRICLR_Pos) |
PDMA_T::PRICLR: FPRICLR Mask
Definition at line 18658 of file NUC472_442.h.
| #define PDMA_PRICLR_FPRICLR_Pos (0) |
PDMA_T::PRICLR: FPRICLR Position
Definition at line 18657 of file NUC472_442.h.
| #define PDMA_PRISET_FPRISET_Msk (0xfffful << PDMA_PRISET_FPRISET_Pos) |
PDMA_T::PRISET: FPRISET Mask
Definition at line 18655 of file NUC472_442.h.
| #define PDMA_PRISET_FPRISET_Pos (0) |
PDMA_T::PRISET: FPRISET Position
Definition at line 18654 of file NUC472_442.h.
| #define PDMA_REQSEL0_3_REQSRC0_Msk (0x1ful << PDMA_REQSEL0_3_REQSRC0_Pos) |
PDMA_T::REQSEL0_3: REQSRC0 Mask
Definition at line 18688 of file NUC472_442.h.
| #define PDMA_REQSEL0_3_REQSRC0_Pos (0) |
PDMA_T::REQSEL0_3: REQSRC0 Position
Definition at line 18687 of file NUC472_442.h.
| #define PDMA_REQSEL0_3_REQSRC1_Msk (0x1ful << PDMA_REQSEL0_3_REQSRC1_Pos) |
PDMA_T::REQSEL0_3: REQSRC1 Mask
Definition at line 18691 of file NUC472_442.h.
| #define PDMA_REQSEL0_3_REQSRC1_Pos (8) |
PDMA_T::REQSEL0_3: REQSRC1 Position
Definition at line 18690 of file NUC472_442.h.
| #define PDMA_REQSEL0_3_REQSRC2_Msk (0x1ful << PDMA_REQSEL0_3_REQSRC2_Pos) |
PDMA_T::REQSEL0_3: REQSRC2 Mask
Definition at line 18694 of file NUC472_442.h.
| #define PDMA_REQSEL0_3_REQSRC2_Pos (16) |
PDMA_T::REQSEL0_3: REQSRC2 Position
Definition at line 18693 of file NUC472_442.h.
| #define PDMA_REQSEL0_3_REQSRC3_Msk (0x1ful << PDMA_REQSEL0_3_REQSRC3_Pos) |
PDMA_T::REQSEL0_3: REQSRC3 Mask
Definition at line 18697 of file NUC472_442.h.
| #define PDMA_REQSEL0_3_REQSRC3_Pos (24) |
PDMA_T::REQSEL0_3: REQSRC3 Position
Definition at line 18696 of file NUC472_442.h.
| #define PDMA_REQSEL12_15_REQSRC12_Msk (0x1ful << PDMA_REQSEL12_15_REQSRC12_Pos) |
PDMA_T::REQSEL12_15: REQSRC12 Mask
Definition at line 18724 of file NUC472_442.h.
| #define PDMA_REQSEL12_15_REQSRC12_Pos (0) |
PDMA_T::REQSEL12_15: REQSRC12 Position
Definition at line 18723 of file NUC472_442.h.
| #define PDMA_REQSEL12_15_REQSRC13_Msk (0x1ful << PDMA_REQSEL12_15_REQSRC13_Pos) |
PDMA_T::REQSEL12_15: REQSRC13 Mask
Definition at line 18727 of file NUC472_442.h.
| #define PDMA_REQSEL12_15_REQSRC13_Pos (8) |
PDMA_T::REQSEL12_15: REQSRC13 Position
Definition at line 18726 of file NUC472_442.h.
| #define PDMA_REQSEL12_15_REQSRC14_Msk (0x1ful << PDMA_REQSEL12_15_REQSRC14_Pos) |
PDMA_T::REQSEL12_15: REQSRC14 Mask
Definition at line 18730 of file NUC472_442.h.
| #define PDMA_REQSEL12_15_REQSRC14_Pos (16) |
PDMA_T::REQSEL12_15: REQSRC14 Position
Definition at line 18729 of file NUC472_442.h.
| #define PDMA_REQSEL12_15_REQSRC15_Msk (0x1ful << PDMA_REQSEL12_15_REQSRC15_Pos) |
PDMA_T::REQSEL12_15: REQSRC15 Mask
Definition at line 18733 of file NUC472_442.h.
| #define PDMA_REQSEL12_15_REQSRC15_Pos (24) |
PDMA_T::REQSEL12_15: REQSRC15 Position
Definition at line 18732 of file NUC472_442.h.
| #define PDMA_REQSEL4_7_REQSRC4_Msk (0x1ful << PDMA_REQSEL4_7_REQSRC4_Pos) |
PDMA_T::REQSEL4_7: REQSRC4 Mask
Definition at line 18700 of file NUC472_442.h.
| #define PDMA_REQSEL4_7_REQSRC4_Pos (0) |
PDMA_T::REQSEL4_7: REQSRC4 Position
Definition at line 18699 of file NUC472_442.h.
| #define PDMA_REQSEL4_7_REQSRC5_Msk (0x1ful << PDMA_REQSEL4_7_REQSRC5_Pos) |
PDMA_T::REQSEL4_7: REQSRC5 Mask
Definition at line 18703 of file NUC472_442.h.
| #define PDMA_REQSEL4_7_REQSRC5_Pos (8) |
PDMA_T::REQSEL4_7: REQSRC5 Position
Definition at line 18702 of file NUC472_442.h.
| #define PDMA_REQSEL4_7_REQSRC6_Msk (0x1ful << PDMA_REQSEL4_7_REQSRC6_Pos) |
PDMA_T::REQSEL4_7: REQSRC6 Mask
Definition at line 18706 of file NUC472_442.h.
| #define PDMA_REQSEL4_7_REQSRC6_Pos (16) |
PDMA_T::REQSEL4_7: REQSRC6 Position
Definition at line 18705 of file NUC472_442.h.
| #define PDMA_REQSEL4_7_REQSRC7_Msk (0x1ful << PDMA_REQSEL4_7_REQSRC7_Pos) |
PDMA_T::REQSEL4_7: REQSRC7 Mask
Definition at line 18709 of file NUC472_442.h.
| #define PDMA_REQSEL4_7_REQSRC7_Pos (24) |
PDMA_T::REQSEL4_7: REQSRC7 Position
Definition at line 18708 of file NUC472_442.h.
| #define PDMA_REQSEL8_11_REQSRC10_Msk (0x1ful << PDMA_REQSEL8_11_REQSRC10_Pos) |
PDMA_T::REQSEL8_11: REQSRC10 Mask
Definition at line 18718 of file NUC472_442.h.
| #define PDMA_REQSEL8_11_REQSRC10_Pos (16) |
PDMA_T::REQSEL8_11: REQSRC10 Position
Definition at line 18717 of file NUC472_442.h.
| #define PDMA_REQSEL8_11_REQSRC11_Msk (0x1ful << PDMA_REQSEL8_11_REQSRC11_Pos) |
PDMA_T::REQSEL8_11: REQSRC11 Mask
Definition at line 18721 of file NUC472_442.h.
| #define PDMA_REQSEL8_11_REQSRC11_Pos (24) |
PDMA_T::REQSEL8_11: REQSRC11 Position
Definition at line 18720 of file NUC472_442.h.
| #define PDMA_REQSEL8_11_REQSRC8_Msk (0x1ful << PDMA_REQSEL8_11_REQSRC8_Pos) |
PDMA_T::REQSEL8_11: REQSRC8 Mask
Definition at line 18712 of file NUC472_442.h.
| #define PDMA_REQSEL8_11_REQSRC8_Pos (0) |
PDMA_T::REQSEL8_11: REQSRC8 Position
Definition at line 18711 of file NUC472_442.h.
| #define PDMA_REQSEL8_11_REQSRC9_Msk (0x1ful << PDMA_REQSEL8_11_REQSRC9_Pos) |
PDMA_T::REQSEL8_11: REQSRC9 Mask
Definition at line 18715 of file NUC472_442.h.
| #define PDMA_REQSEL8_11_REQSRC9_Pos (8) |
PDMA_T::REQSEL8_11: REQSRC9 Position
Definition at line 18714 of file NUC472_442.h.
| #define PDMA_SCATBA_SCATBA_Msk (0xfffful << PDMA_SCATBA_SCATBA_Pos) |
PDMA_T::SCATBA: SCATBA Mask
Definition at line 18685 of file NUC472_442.h.
| #define PDMA_SCATBA_SCATBA_Pos (16) |
PDMA_T::SCATBA: SCATBA Position
Definition at line 18684 of file NUC472_442.h.
| #define PDMA_SCATSTS_TEMPTYF_Msk (0xfffful << PDMA_SCATSTS_TEMPTYF_Pos) |
PDMA_T::SCATSTS: TEMPTYF Mask
Definition at line 18679 of file NUC472_442.h.
| #define PDMA_SCATSTS_TEMPTYF_Pos (0) |
PDMA_T::SCATSTS: TEMPTYF Position
Definition at line 18678 of file NUC472_442.h.
| #define PDMA_STOP_STOP_Msk (0xfffful << PDMA_STOP_STOP_Pos) |
PDMA_T::STOP: STOP Mask
Definition at line 18646 of file NUC472_442.h.
| #define PDMA_STOP_STOP_Pos (0) |
PDMA_T::STOP: STOP Position
Definition at line 18645 of file NUC472_442.h.
| #define PDMA_SWREQ_SWREQ_Msk (0xffful << PDMA_SWREQ_SWREQ_Pos) |
PDMA_T::SWREQ: SWREQ Mask
Definition at line 18649 of file NUC472_442.h.
| #define PDMA_SWREQ_SWREQ_Pos (0) |
PDMA_T::SWREQ: SWREQ Position
Definition at line 18648 of file NUC472_442.h.
| #define PDMA_TACTSTS_TXACTF_Msk (0xfffful << PDMA_TACTSTS_TXACTF_Pos) |
PDMA_T::TACTSTS: TXACTF Mask
Definition at line 18682 of file NUC472_442.h.
| #define PDMA_TACTSTS_TXACTF_Pos (0) |
PDMA_T::TACTSTS: TXACTF Position
Definition at line 18681 of file NUC472_442.h.
| #define PDMA_TDSTS_TDIF_Msk (0xfffful << PDMA_TDSTS_TDIF_Pos) |
PDMA_T::TDSTS: TDIF Mask
Definition at line 18676 of file NUC472_442.h.
| #define PDMA_TDSTS_TDIF_Pos (0) |
PDMA_T::TDSTS: TDIF Position
Definition at line 18675 of file NUC472_442.h.
| #define PDMA_TRGSTS_REQSTS_Msk (0xfffful << PDMA_TRGSTS_REQSTS_Pos) |
PDMA_T::TRGSTS: REQSTS Mask
Definition at line 18652 of file NUC472_442.h.
| #define PDMA_TRGSTS_REQSTS_Pos (0) |
PDMA_T::TRGSTS: REQSTS Position
Definition at line 18651 of file NUC472_442.h.
| #define PS2_CTL_ACK_Msk (0x1ul << PS2_CTL_ACK_Pos) |
PS2_T::CTL: ACK Mask
Definition at line 18969 of file NUC472_442.h.
| #define PS2_CTL_ACK_Pos (7) |
PS2_T::CTL: ACK Position
Definition at line 18968 of file NUC472_442.h.
| #define PS2_CTL_CLRFIFO_Msk (0x1ul << PS2_CTL_CLRFIFO_Pos) |
PS2_T::CTL: CLRFIFO Mask
Definition at line 18972 of file NUC472_442.h.
| #define PS2_CTL_CLRFIFO_Pos (8) |
PS2_T::CTL: CLRFIFO Position
Definition at line 18971 of file NUC472_442.h.
| #define PS2_CTL_FPS2CLK_Msk (0x1ul << PS2_CTL_FPS2CLK_Pos) |
PS2_T::CTL: FPS2CLK Mask
Definition at line 18978 of file NUC472_442.h.
| #define PS2_CTL_FPS2CLK_Pos (10) |
PS2_T::CTL: FPS2CLK Position
Definition at line 18977 of file NUC472_442.h.
| #define PS2_CTL_FPS2DAT_Msk (0x1ul << PS2_CTL_FPS2DAT_Pos) |
PS2_T::CTL: FPS2DAT Mask
Definition at line 18981 of file NUC472_442.h.
| #define PS2_CTL_FPS2DAT_Pos (11) |
PS2_T::CTL: FPS2DAT Position
Definition at line 18980 of file NUC472_442.h.
| #define PS2_CTL_OVERRIDE_Msk (0x1ul << PS2_CTL_OVERRIDE_Pos) |
PS2_T::CTL: OVERRIDE Mask
Definition at line 18975 of file NUC472_442.h.
| #define PS2_CTL_OVERRIDE_Pos (9) |
PS2_T::CTL: OVERRIDE Position
Definition at line 18974 of file NUC472_442.h.
| #define PS2_CTL_PS2EN_Msk (0x1ul << PS2_CTL_PS2EN_Pos) |
PS2_T::CTL: PS2EN Mask
Definition at line 18957 of file NUC472_442.h.
| #define PS2_CTL_PS2EN_Pos (0) |
@addtogroup PS2_CONST PS2 Bit Field Definition Constant Definitions for PS2 Controller
PS2_T::CTL: PS2EN Position
Definition at line 18956 of file NUC472_442.h.
| #define PS2_CTL_RXIEN_Msk (0x1ul << PS2_CTL_RXIEN_Pos) |
PS2_T::CTL: RXIEN Mask
Definition at line 18963 of file NUC472_442.h.
| #define PS2_CTL_RXIEN_Pos (2) |
PS2_T::CTL: RXIEN Position
Definition at line 18962 of file NUC472_442.h.
| #define PS2_CTL_TXFDEPTH_Msk (0xful << PS2_CTL_TXFDEPTH_Pos) |
PS2_T::CTL: TXFDEPTH Mask
Definition at line 18966 of file NUC472_442.h.
| #define PS2_CTL_TXFDEPTH_Pos (3) |
PS2_T::CTL: TXFDEPTH Position
Definition at line 18965 of file NUC472_442.h.
| #define PS2_CTL_TXIEN_Msk (0x1ul << PS2_CTL_TXIEN_Pos) |
PS2_T::CTL: TXIEN Mask
Definition at line 18960 of file NUC472_442.h.
| #define PS2_CTL_TXIEN_Pos (1) |
PS2_T::CTL: TXIEN Position
Definition at line 18959 of file NUC472_442.h.
| #define PS2_INTSTS_RXIF_Msk (0x1ul << PS2_INTSTS_RXIF_Pos) |
PS2_T::INTSTS: RXIF Mask
Definition at line 19026 of file NUC472_442.h.
| #define PS2_INTSTS_RXIF_Pos (0) |
PS2_T::INTSTS: RXIF Position
Definition at line 19025 of file NUC472_442.h.
| #define PS2_INTSTS_TXIF_Msk (0x1ul << PS2_INTSTS_TXIF_Pos) |
PS2_T::INTSTS: TXIF Mask
Definition at line 19029 of file NUC472_442.h.
| #define PS2_INTSTS_TXIF_Pos (1) |
PS2_T::INTSTS: TXIF Position
Definition at line 19028 of file NUC472_442.h.
| #define PS2_RXDAT_DAT_Msk (0xfful << PS2_RXDAT_DAT_Pos) |
PS2_T::RXDAT: DAT Mask
Definition at line 18996 of file NUC472_442.h.
| #define PS2_RXDAT_DAT_Pos (0) |
PS2_T::RXDAT: DAT Position
Definition at line 18995 of file NUC472_442.h.
| #define PS2_STATUS_BYTEIDX_Msk (0xful << PS2_STATUS_BYTEIDX_Pos) |
PS2_T::STATUS: BYTEIDX Mask
Definition at line 19023 of file NUC472_442.h.
| #define PS2_STATUS_BYTEIDX_Pos (8) |
PS2_T::STATUS: BYTEIDX Position
Definition at line 19022 of file NUC472_442.h.
| #define PS2_STATUS_CLKSTAT_Msk (0x1ul << PS2_STATUS_CLKSTAT_Pos) |
PS2_T::STATUS: CLKSTAT Mask
Definition at line 18999 of file NUC472_442.h.
| #define PS2_STATUS_CLKSTAT_Pos (0) |
PS2_T::STATUS: CLKSTAT Position
Definition at line 18998 of file NUC472_442.h.
| #define PS2_STATUS_DATSTAT_Msk (0x1ul << PS2_STATUS_DATSTAT_Pos) |
PS2_T::STATUS: DATSTAT Mask
Definition at line 19002 of file NUC472_442.h.
| #define PS2_STATUS_DATSTAT_Pos (1) |
PS2_T::STATUS: DATSTAT Position
Definition at line 19001 of file NUC472_442.h.
| #define PS2_STATUS_FRAMEERR_Msk (0x1ul << PS2_STATUS_FRAMEERR_Pos) |
PS2_T::STATUS: FRAMEERR Mask
Definition at line 19005 of file NUC472_442.h.
| #define PS2_STATUS_FRAMEERR_Pos (2) |
PS2_T::STATUS: FRAMEERR Position
Definition at line 19004 of file NUC472_442.h.
| #define PS2_STATUS_RXBUSY_Msk (0x1ul << PS2_STATUS_RXBUSY_Pos) |
PS2_T::STATUS: RXBUSY Mask
Definition at line 19011 of file NUC472_442.h.
| #define PS2_STATUS_RXBUSY_Pos (4) |
PS2_T::STATUS: RXBUSY Position
Definition at line 19010 of file NUC472_442.h.
| #define PS2_STATUS_RXOV_Msk (0x1ul << PS2_STATUS_RXOV_Pos) |
PS2_T::STATUS: RXOV Mask
Definition at line 19017 of file NUC472_442.h.
| #define PS2_STATUS_RXOV_Pos (6) |
PS2_T::STATUS: RXOV Position
Definition at line 19016 of file NUC472_442.h.
| #define PS2_STATUS_RXPARITY_Msk (0x1ul << PS2_STATUS_RXPARITY_Pos) |
PS2_T::STATUS: RXPARITY Mask
Definition at line 19008 of file NUC472_442.h.
| #define PS2_STATUS_RXPARITY_Pos (3) |
PS2_T::STATUS: RXPARITY Position
Definition at line 19007 of file NUC472_442.h.
| #define PS2_STATUS_TXBUSY_Msk (0x1ul << PS2_STATUS_TXBUSY_Pos) |
PS2_T::STATUS: TXBUSY Mask
Definition at line 19014 of file NUC472_442.h.
| #define PS2_STATUS_TXBUSY_Pos (5) |
PS2_T::STATUS: TXBUSY Position
Definition at line 19013 of file NUC472_442.h.
| #define PS2_STATUS_TXEMPTY_Msk (0x1ul << PS2_STATUS_TXEMPTY_Pos) |
PS2_T::STATUS: TXEMPTY Mask
Definition at line 19020 of file NUC472_442.h.
| #define PS2_STATUS_TXEMPTY_Pos (7) |
PS2_T::STATUS: TXEMPTY Position
Definition at line 19019 of file NUC472_442.h.
| #define PS2_TXDAT0_DAT_Msk (0xfffffffful << PS2_TXDAT0_DAT_Pos) |
PS2_T::TXDAT0: DAT Mask
Definition at line 18984 of file NUC472_442.h.
| #define PS2_TXDAT0_DAT_Pos (0) |
PS2_T::TXDAT0: DAT Position
Definition at line 18983 of file NUC472_442.h.
| #define PS2_TXDAT1_DAT_Msk (0xfffffffful << PS2_TXDAT1_DAT_Pos) |
PS2_T::TXDAT1: DAT Mask
Definition at line 18987 of file NUC472_442.h.
| #define PS2_TXDAT1_DAT_Pos (0) |
PS2_T::TXDAT1: DAT Position
Definition at line 18986 of file NUC472_442.h.
| #define PS2_TXDAT2_DAT_Msk (0xfffffffful << PS2_TXDAT2_DAT_Pos) |
PS2_T::TXDAT2: DAT Mask
Definition at line 18990 of file NUC472_442.h.
| #define PS2_TXDAT2_DAT_Pos (0) |
PS2_T::TXDAT2: DAT Position
Definition at line 18989 of file NUC472_442.h.
| #define PS2_TXDAT3_DAT_Msk (0xfffffffful << PS2_TXDAT3_DAT_Pos) |
PS2_T::TXDAT3: DAT Mask
Definition at line 18993 of file NUC472_442.h.
| #define PS2_TXDAT3_DAT_Pos (0) |
PS2_T::TXDAT3: DAT Position
Definition at line 18992 of file NUC472_442.h.
| #define PWM_BRKCTL_BK1SEL_Msk (0x3ul << PWM_BRKCTL_BK1SEL_Pos) |
PWM_T::BRKCTL: BK1SEL Mask
Definition at line 19930 of file NUC472_442.h.
| #define PWM_BRKCTL_BK1SEL_Pos (12) |
PWM_T::BRKCTL: BK1SEL Position
Definition at line 19929 of file NUC472_442.h.
| #define PWM_BRKCTL_BKOD_Msk (0x3ful << PWM_BRKCTL_BKOD_Pos) |
PWM_T::BRKCTL: BKOD Mask
Definition at line 19948 of file NUC472_442.h.
| #define PWM_BRKCTL_BKOD_Pos (24) |
PWM_T::BRKCTL: BKOD Position
Definition at line 19947 of file NUC472_442.h.
| #define PWM_BRKCTL_BRK0EN_Msk (0x1ul << PWM_BRKCTL_BRK0EN_Pos) |
PWM_T::BRKCTL: BRK0EN Mask
Definition at line 19909 of file NUC472_442.h.
| #define PWM_BRKCTL_BRK0EN_Pos (0) |
PWM_T::BRKCTL: BRK0EN Position
Definition at line 19908 of file NUC472_442.h.
| #define PWM_BRKCTL_BRK0INV_Msk (0x1ul << PWM_BRKCTL_BRK0INV_Pos) |
PWM_T::BRKCTL: BRK0INV Mask
Definition at line 19915 of file NUC472_442.h.
| #define PWM_BRKCTL_BRK0INV_Pos (2) |
PWM_T::BRKCTL: BRK0INV Position
Definition at line 19914 of file NUC472_442.h.
| #define PWM_BRKCTL_BRK0NFDIS_Msk (0x1ul << PWM_BRKCTL_BRK0NFDIS_Pos) |
PWM_T::BRKCTL: BRK0NFDIS Mask
Definition at line 19912 of file NUC472_442.h.
| #define PWM_BRKCTL_BRK0NFDIS_Pos (1) |
PWM_T::BRKCTL: BRK0NFDIS Position
Definition at line 19911 of file NUC472_442.h.
| #define PWM_BRKCTL_BRK0NFSEL_Msk (0x3ul << PWM_BRKCTL_BRK0NFSEL_Pos) |
PWM_T::BRKCTL: BRK0NFSEL Mask
Definition at line 19918 of file NUC472_442.h.
| #define PWM_BRKCTL_BRK0NFSEL_Pos (6) |
PWM_T::BRKCTL: BRK0NFSEL Position
Definition at line 19917 of file NUC472_442.h.
| #define PWM_BRKCTL_BRK1EN_Msk (0x1ul << PWM_BRKCTL_BRK1EN_Pos) |
PWM_T::BRKCTL: BRK1EN Mask
Definition at line 19921 of file NUC472_442.h.
| #define PWM_BRKCTL_BRK1EN_Pos (8) |
PWM_T::BRKCTL: BRK1EN Position
Definition at line 19920 of file NUC472_442.h.
| #define PWM_BRKCTL_BRK1INV_Msk (0x1ul << PWM_BRKCTL_BRK1INV_Pos) |
PWM_T::BRKCTL: BRK1INV Mask
Definition at line 19927 of file NUC472_442.h.
| #define PWM_BRKCTL_BRK1INV_Pos (10) |
PWM_T::BRKCTL: BRK1INV Position
Definition at line 19926 of file NUC472_442.h.
| #define PWM_BRKCTL_BRK1NFDIS_Msk (0x1ul << PWM_BRKCTL_BRK1NFDIS_Pos) |
PWM_T::BRKCTL: BRK1NFDIS Mask
Definition at line 19924 of file NUC472_442.h.
| #define PWM_BRKCTL_BRK1NFDIS_Pos (9) |
PWM_T::BRKCTL: BRK1NFDIS Position
Definition at line 19923 of file NUC472_442.h.
| #define PWM_BRKCTL_BRK1NFSEL_Msk (0x3ul << PWM_BRKCTL_BRK1NFSEL_Pos) |
PWM_T::BRKCTL: BRK1NFSEL Mask
Definition at line 19933 of file NUC472_442.h.
| #define PWM_BRKCTL_BRK1NFSEL_Pos (14) |
PWM_T::BRKCTL: BRK1NFSEL Position
Definition at line 19932 of file NUC472_442.h.
| #define PWM_BRKCTL_CPO0BKEN_Msk (0x1ul << PWM_BRKCTL_CPO0BKEN_Pos) |
PWM_T::BRKCTL: CPO0BKEN Mask
Definition at line 19936 of file NUC472_442.h.
| #define PWM_BRKCTL_CPO0BKEN_Pos (16) |
PWM_T::BRKCTL: CPO0BKEN Position
Definition at line 19935 of file NUC472_442.h.
| #define PWM_BRKCTL_CPO1BKEN_Msk (0x1ul << PWM_BRKCTL_CPO1BKEN_Pos) |
PWM_T::BRKCTL: CPO1BKEN Mask
Definition at line 19939 of file NUC472_442.h.
| #define PWM_BRKCTL_CPO1BKEN_Pos (17) |
PWM_T::BRKCTL: CPO1BKEN Position
Definition at line 19938 of file NUC472_442.h.
| #define PWM_BRKCTL_CPO2BKEN_Msk (0x1ul << PWM_BRKCTL_CPO2BKEN_Pos) |
PWM_T::BRKCTL: CPO2BKEN Mask
Definition at line 19942 of file NUC472_442.h.
| #define PWM_BRKCTL_CPO2BKEN_Pos (18) |
PWM_T::BRKCTL: CPO2BKEN Position
Definition at line 19941 of file NUC472_442.h.
| #define PWM_BRKCTL_LVDBKEN_Msk (0x1ul << PWM_BRKCTL_LVDBKEN_Pos) |
PWM_T::BRKCTL: LVDBKEN Mask
Definition at line 19945 of file NUC472_442.h.
| #define PWM_BRKCTL_LVDBKEN_Pos (19) |
PWM_T::BRKCTL: LVDBKEN Position
Definition at line 19944 of file NUC472_442.h.
| #define PWM_CAPCTL_CAPEN_Msk (0x3ful << PWM_CAPCTL_CAPEN_Pos) |
PWM_T::CAPCTL: CAPEN Mask
Definition at line 20002 of file NUC472_442.h.
| #define PWM_CAPCTL_CAPEN_Pos (0) |
PWM_T::CAPCTL: CAPEN Position
Definition at line 20001 of file NUC472_442.h.
| #define PWM_CAPCTL_CAPINV_Msk (0x3ful << PWM_CAPCTL_CAPINV_Pos) |
PWM_T::CAPCTL: CAPINV Mask
Definition at line 20005 of file NUC472_442.h.
| #define PWM_CAPCTL_CAPINV_Pos (8) |
PWM_T::CAPCTL: CAPINV Position
Definition at line 20004 of file NUC472_442.h.
| #define PWM_CAPCTL_FCRLDEN_Msk (0x3ful << PWM_CAPCTL_FCRLDEN_Pos) |
PWM_T::CAPCTL: FCRLDEN Mask
Definition at line 20011 of file NUC472_442.h.
| #define PWM_CAPCTL_FCRLDEN_Pos (24) |
PWM_T::CAPCTL: FCRLDEN Position
Definition at line 20010 of file NUC472_442.h.
| #define PWM_CAPCTL_RCRLDEN_Msk (0x3ful << PWM_CAPCTL_RCRLDEN_Pos) |
PWM_T::CAPCTL: RCRLDEN Mask
Definition at line 20008 of file NUC472_442.h.
| #define PWM_CAPCTL_RCRLDEN_Pos (16) |
PWM_T::CAPCTL: RCRLDEN Position
Definition at line 20007 of file NUC472_442.h.
| #define PWM_CAPINEN_CAPINEN_Msk (0x3ful << PWM_CAPINEN_CAPINEN_Pos) |
PWM_T::CAPINEN: CAPINEN Mask
Definition at line 20014 of file NUC472_442.h.
| #define PWM_CAPINEN_CAPINEN_Pos (0) |
PWM_T::CAPINEN: CAPINEN Position
Definition at line 20013 of file NUC472_442.h.
| #define PWM_CAPSTS_CRIFOV_Msk (0x3ful << PWM_CAPSTS_CRIFOV_Pos) |
PWM_T::CAPSTS: CRIFOV Mask
Definition at line 20017 of file NUC472_442.h.
| #define PWM_CAPSTS_CRIFOV_Pos (0) |
PWM_T::CAPSTS: CRIFOV Position
Definition at line 20016 of file NUC472_442.h.
| #define PWM_CAPSTS_FLIFOV_Msk (0x3ful << PWM_CAPSTS_FLIFOV_Pos) |
PWM_T::CAPSTS: FLIFOV Mask
Definition at line 20020 of file NUC472_442.h.
| #define PWM_CAPSTS_FLIFOV_Pos (8) |
PWM_T::CAPSTS: FLIFOV Position
Definition at line 20019 of file NUC472_442.h.
| #define PWM_CLKDIV_CLKDIV0_Msk (0x7ul << PWM_CLKDIV_CLKDIV0_Pos) |
PWM_T::CLKDIV: CLKDIV0 Mask
Definition at line 19759 of file NUC472_442.h.
| #define PWM_CLKDIV_CLKDIV0_Pos (0) |
PWM_T::CLKDIV: CLKDIV0 Position
Definition at line 19758 of file NUC472_442.h.
| #define PWM_CLKDIV_CLKDIV1_Msk (0x7ul << PWM_CLKDIV_CLKDIV1_Pos) |
PWM_T::CLKDIV: CLKDIV1 Mask
Definition at line 19762 of file NUC472_442.h.
| #define PWM_CLKDIV_CLKDIV1_Pos (4) |
PWM_T::CLKDIV: CLKDIV1 Position
Definition at line 19761 of file NUC472_442.h.
| #define PWM_CLKDIV_CLKDIV2_Msk (0x7ul << PWM_CLKDIV_CLKDIV2_Pos) |
PWM_T::CLKDIV: CLKDIV2 Mask
Definition at line 19765 of file NUC472_442.h.
| #define PWM_CLKDIV_CLKDIV2_Pos (8) |
PWM_T::CLKDIV: CLKDIV2 Position
Definition at line 19764 of file NUC472_442.h.
| #define PWM_CLKDIV_CLKDIV3_Msk (0x7ul << PWM_CLKDIV_CLKDIV3_Pos) |
PWM_T::CLKDIV: CLKDIV3 Mask
Definition at line 19768 of file NUC472_442.h.
| #define PWM_CLKDIV_CLKDIV3_Pos (12) |
PWM_T::CLKDIV: CLKDIV3 Position
Definition at line 19767 of file NUC472_442.h.
| #define PWM_CLKDIV_CLKDIV4_Msk (0x7ul << PWM_CLKDIV_CLKDIV4_Pos) |
PWM_T::CLKDIV: CLKDIV4 Mask
Definition at line 19771 of file NUC472_442.h.
| #define PWM_CLKDIV_CLKDIV4_Pos (16) |
PWM_T::CLKDIV: CLKDIV4 Position
Definition at line 19770 of file NUC472_442.h.
| #define PWM_CLKDIV_CLKDIV5_Msk (0x7ul << PWM_CLKDIV_CLKDIV5_Pos) |
PWM_T::CLKDIV: CLKDIV5 Mask
Definition at line 19774 of file NUC472_442.h.
| #define PWM_CLKDIV_CLKDIV5_Pos (20) |
PWM_T::CLKDIV: CLKDIV5 Position
Definition at line 19773 of file NUC472_442.h.
| #define PWM_CLKPSC_CLKPSC01_Msk (0xfful << PWM_CLKPSC_CLKPSC01_Pos) |
PWM_T::CLKPSC: CLKPSC01 Mask
Definition at line 19750 of file NUC472_442.h.
| #define PWM_CLKPSC_CLKPSC01_Pos (0) |
@addtogroup PWM_CONST PWM Bit Field Definition Constant Definitions for PWM Controller
PWM_T::CLKPSC: CLKPSC01 Position
Definition at line 19749 of file NUC472_442.h.
| #define PWM_CLKPSC_CLKPSC23_Msk (0xfful << PWM_CLKPSC_CLKPSC23_Pos) |
PWM_T::CLKPSC: CLKPSC23 Mask
Definition at line 19753 of file NUC472_442.h.
| #define PWM_CLKPSC_CLKPSC23_Pos (8) |
PWM_T::CLKPSC: CLKPSC23 Position
Definition at line 19752 of file NUC472_442.h.
| #define PWM_CLKPSC_CLKPSC45_Msk (0xfful << PWM_CLKPSC_CLKPSC45_Pos) |
PWM_T::CLKPSC: CLKPSC45 Mask
Definition at line 19756 of file NUC472_442.h.
| #define PWM_CLKPSC_CLKPSC45_Pos (16) |
PWM_T::CLKPSC: CLKPSC45 Position
Definition at line 19755 of file NUC472_442.h.
| #define PWM_CMPDAT0_CMP_Msk (0xfffful << PWM_CMPDAT0_CMP_Pos) |
PWM_T::CMPDAT: CMP Mask
Definition at line 19822 of file NUC472_442.h.
| #define PWM_CMPDAT0_CMP_Pos (0) |
PWM_T::CMPDAT: CMP Position
Definition at line 19821 of file NUC472_442.h.
| #define PWM_CMPDAT1_CMP_Msk (0xfffful << PWM_CMPDAT1_CMP_Pos) |
PWM_T::CMPDAT: CMP Mask
Definition at line 19825 of file NUC472_442.h.
| #define PWM_CMPDAT1_CMP_Pos (0) |
PWM_T::CMPDAT: CMP Position
Definition at line 19824 of file NUC472_442.h.
| #define PWM_CMPDAT2_CMP_Msk (0xfffful << PWM_CMPDAT2_CMP_Pos) |
PWM_T::CMPDAT: CMP Mask
Definition at line 19828 of file NUC472_442.h.
| #define PWM_CMPDAT2_CMP_Pos (0) |
PWM_T::CMPDAT: CMP Position
Definition at line 19827 of file NUC472_442.h.
| #define PWM_CMPDAT3_CMP_Msk (0xfffful << PWM_CMPDAT3_CMP_Pos) |
PWM_T::CMPDAT: CMP Mask
Definition at line 19831 of file NUC472_442.h.
| #define PWM_CMPDAT3_CMP_Pos (0) |
PWM_T::CMPDAT: CMP Position
Definition at line 19830 of file NUC472_442.h.
| #define PWM_CMPDAT4_CMP_Msk (0xfffful << PWM_CMPDAT4_CMP_Pos) |
PWM_T::CMPDAT: CMP Mask
Definition at line 19834 of file NUC472_442.h.
| #define PWM_CMPDAT4_CMP_Pos (0) |
PWM_T::CMPDAT: CMP Position
Definition at line 19833 of file NUC472_442.h.
| #define PWM_CMPDAT5_CMP_Msk (0xfffful << PWM_CMPDAT5_CMP_Pos) |
PWM_T::CMPDAT: CMP Mask
Definition at line 19837 of file NUC472_442.h.
| #define PWM_CMPDAT5_CMP_Pos (0) |
PWM_T::CMPDAT: CMP Position
Definition at line 19836 of file NUC472_442.h.
| #define PWM_CNT0_CNT_Msk (0xfffful << PWM_CNT0_CNT_Pos) |
PWM_T::CNT: CNT Mask
Definition at line 19840 of file NUC472_442.h.
| #define PWM_CNT0_CNT_Pos (0) |
PWM_T::CNT: CNT Position
Definition at line 19839 of file NUC472_442.h.
| #define PWM_CNT1_CNT_Msk (0xfffful << PWM_CNT1_CNT_Pos) |
PWM_T::CNT: CNT Mask
Definition at line 19843 of file NUC472_442.h.
| #define PWM_CNT1_CNT_Pos (0) |
PWM_T::CNT: CNT Position
Definition at line 19842 of file NUC472_442.h.
| #define PWM_CNT2_CNT_Msk (0xfffful << PWM_CNT2_CNT_Pos) |
PWM_T::CNT: CNT Mask
Definition at line 19846 of file NUC472_442.h.
| #define PWM_CNT2_CNT_Pos (0) |
PWM_T::CNT: CNT Position
Definition at line 19845 of file NUC472_442.h.
| #define PWM_CNT3_CNT_Msk (0xfffful << PWM_CNT3_CNT_Pos) |
PWM_T::CNT: CNT Mask
Definition at line 19849 of file NUC472_442.h.
| #define PWM_CNT3_CNT_Pos (0) |
PWM_T::CNT: CNT Position
Definition at line 19848 of file NUC472_442.h.
| #define PWM_CNT4_CNT_Msk (0xfffful << PWM_CNT4_CNT_Pos) |
PWM_T::CNT: CNT Mask
Definition at line 19852 of file NUC472_442.h.
| #define PWM_CNT4_CNT_Pos (0) |
PWM_T::CNT: CNT Position
Definition at line 19851 of file NUC472_442.h.
| #define PWM_CNT5_CNT_Msk (0xfffful << PWM_CNT5_CNT_Pos) |
PWM_T::CNT: CNT Mask
Definition at line 19855 of file NUC472_442.h.
| #define PWM_CNT5_CNT_Pos (0) |
PWM_T::CNT: CNT Position
Definition at line 19854 of file NUC472_442.h.
| #define PWM_CNTEN_CNTEN_Msk (0x3ful << PWM_CNTEN_CNTEN_Pos) |
PWM_T::CNTEN: CNTEN Mask
Definition at line 19801 of file NUC472_442.h.
| #define PWM_CNTEN_CNTEN_Pos (0) |
PWM_T::CNTEN: CNTEN Position
Definition at line 19800 of file NUC472_442.h.
| #define PWM_CTL_CMPINV_Msk (0x3ful << PWM_CTL_CMPINV_Pos) |
PWM_T::CTL: CMPINV Mask
Definition at line 19777 of file NUC472_442.h.
| #define PWM_CTL_CMPINV_Pos (0) |
PWM_T::CTL: CMPINV Position
Definition at line 19776 of file NUC472_442.h.
| #define PWM_CTL_CNTMODE_Msk (0x3ful << PWM_CTL_CNTMODE_Pos) |
PWM_T::CTL: CNTMODE Mask
Definition at line 19792 of file NUC472_442.h.
| #define PWM_CTL_CNTMODE_Pos (16) |
PWM_T::CTL: CNTMODE Position
Definition at line 19791 of file NUC472_442.h.
| #define PWM_CTL_CNTTYPE_Msk (0x3ful << PWM_CTL_CNTTYPE_Pos) |
PWM_T::CTL: CNTTYPE Mask
Definition at line 19795 of file NUC472_442.h.
| #define PWM_CTL_CNTTYPE_Pos (24) |
PWM_T::CTL: CNTTYPE Position
Definition at line 19794 of file NUC472_442.h.
| #define PWM_CTL_DBGTRIOFF_Msk (0x1ul << PWM_CTL_DBGTRIOFF_Pos) |
PWM_T::CTL: DBGTRIOFF Mask
Definition at line 19798 of file NUC472_442.h.
| #define PWM_CTL_DBGTRIOFF_Pos (31) |
PWM_T::CTL: DBGTRIOFF Position
Definition at line 19797 of file NUC472_442.h.
| #define PWM_CTL_GROUPEN_Msk (0x1ul << PWM_CTL_GROUPEN_Pos) |
PWM_T::CTL: GROUPEN Mask
Definition at line 19783 of file NUC472_442.h.
| #define PWM_CTL_GROUPEN_Pos (7) |
PWM_T::CTL: GROUPEN Position
Definition at line 19782 of file NUC472_442.h.
| #define PWM_CTL_OUTMODE_Msk (0x1ul << PWM_CTL_OUTMODE_Pos) |
PWM_T::CTL: OUTMODE Mask
Definition at line 19780 of file NUC472_442.h.
| #define PWM_CTL_OUTMODE_Pos (6) |
PWM_T::CTL: OUTMODE Position
Definition at line 19779 of file NUC472_442.h.
| #define PWM_CTL_PINV_Msk (0x3ful << PWM_CTL_PINV_Pos) |
PWM_T::CTL: PINV Mask
Definition at line 19786 of file NUC472_442.h.
| #define PWM_CTL_PINV_Pos (8) |
PWM_T::CTL: PINV Position
Definition at line 19785 of file NUC472_442.h.
| #define PWM_CTL_SYNCEN_Msk (0x1ul << PWM_CTL_SYNCEN_Pos) |
PWM_T::CTL: SYNCEN Mask
Definition at line 19789 of file NUC472_442.h.
| #define PWM_CTL_SYNCEN_Pos (15) |
PWM_T::CTL: SYNCEN Position
Definition at line 19788 of file NUC472_442.h.
| #define PWM_DTCTL_DTCNT01_Msk (0xfful << PWM_DTCTL_DTCNT01_Pos) |
PWM_T::DTCTL: DTCNT01 Mask
Definition at line 19864 of file NUC472_442.h.
| #define PWM_DTCTL_DTCNT01_Pos (0) |
PWM_T::DTCTL: DTCNT01 Position
Definition at line 19863 of file NUC472_442.h.
| #define PWM_DTCTL_DTCNT23_Msk (0xfful << PWM_DTCTL_DTCNT23_Pos) |
PWM_T::DTCTL: DTCNT23 Mask
Definition at line 19867 of file NUC472_442.h.
| #define PWM_DTCTL_DTCNT23_Pos (8) |
PWM_T::DTCTL: DTCNT23 Position
Definition at line 19866 of file NUC472_442.h.
| #define PWM_DTCTL_DTCNT45_Msk (0xfful << PWM_DTCTL_DTCNT45_Pos) |
PWM_T::DTCTL: DTCNT45 Mask
Definition at line 19870 of file NUC472_442.h.
| #define PWM_DTCTL_DTCNT45_Pos (16) |
PWM_T::DTCTL: DTCNT45 Position
Definition at line 19869 of file NUC472_442.h.
| #define PWM_DTCTL_DTDIV_Msk (0x3ul << PWM_DTCTL_DTDIV_Pos) |
PWM_T::DTCTL: DTDIV Mask
Definition at line 19873 of file NUC472_442.h.
| #define PWM_DTCTL_DTDIV_Pos (24) |
PWM_T::DTCTL: DTDIV Position
Definition at line 19872 of file NUC472_442.h.
| #define PWM_DTCTL_DTEN01_Msk (0x1ul << PWM_DTCTL_DTEN01_Pos) |
PWM_T::DTCTL: DTEN01 Mask
Definition at line 19876 of file NUC472_442.h.
| #define PWM_DTCTL_DTEN01_Pos (28) |
PWM_T::DTCTL: DTEN01 Position
Definition at line 19875 of file NUC472_442.h.
| #define PWM_DTCTL_DTEN23_Msk (0x1ul << PWM_DTCTL_DTEN23_Pos) |
PWM_T::DTCTL: DTEN23 Mask
Definition at line 19879 of file NUC472_442.h.
| #define PWM_DTCTL_DTEN23_Pos (29) |
PWM_T::DTCTL: DTEN23 Position
Definition at line 19878 of file NUC472_442.h.
| #define PWM_DTCTL_DTEN45_Msk (0x1ul << PWM_DTCTL_DTEN45_Pos) |
PWM_T::DTCTL: DTEN45 Mask
Definition at line 19882 of file NUC472_442.h.
| #define PWM_DTCTL_DTEN45_Pos (30) |
PWM_T::DTCTL: DTEN45 Position
Definition at line 19881 of file NUC472_442.h.
| #define PWM_FCAPDAT0_FCAPDAT_Msk (0xfffful << PWM_FCAPDAT0_FCAPDAT_Pos) |
PWM_T::FCAPDAT0: FCAPDAT Mask
Definition at line 20026 of file NUC472_442.h.
| #define PWM_FCAPDAT0_FCAPDAT_Pos (0) |
PWM_T::FCAPDAT0: FCAPDAT Position
Definition at line 20025 of file NUC472_442.h.
| #define PWM_FCAPDAT1_FCAPDAT_Msk (0xfffful << PWM_FCAPDAT1_FCAPDAT_Pos) |
PWM_T::FCAPDAT1: FCAPDAT Mask
Definition at line 20032 of file NUC472_442.h.
| #define PWM_FCAPDAT1_FCAPDAT_Pos (0) |
PWM_T::FCAPDAT1: FCAPDAT Position
Definition at line 20031 of file NUC472_442.h.
| #define PWM_FCAPDAT2_FCAPDAT_Msk (0xfffful << PWM_FCAPDAT2_FCAPDAT_Pos) |
PWM_T::FCAPDAT2: FCAPDAT Mask
Definition at line 20038 of file NUC472_442.h.
| #define PWM_FCAPDAT2_FCAPDAT_Pos (0) |
PWM_T::FCAPDAT2: FCAPDAT Position
Definition at line 20037 of file NUC472_442.h.
| #define PWM_FCAPDAT3_FCAPDAT_Msk (0xfffful << PWM_FCAPDAT3_FCAPDAT_Pos) |
PWM_T::FCAPDAT3: FCAPDAT Mask
Definition at line 20044 of file NUC472_442.h.
| #define PWM_FCAPDAT3_FCAPDAT_Pos (0) |
PWM_T::FCAPDAT3: FCAPDAT Position
Definition at line 20043 of file NUC472_442.h.
| #define PWM_FCAPDAT4_FCAPDAT_Msk (0xfffful << PWM_FCAPDAT4_FCAPDAT_Pos) |
PWM_T::FCAPDAT4: FCAPDAT Mask
Definition at line 20050 of file NUC472_442.h.
| #define PWM_FCAPDAT4_FCAPDAT_Pos (0) |
PWM_T::FCAPDAT4: FCAPDAT Position
Definition at line 20049 of file NUC472_442.h.
| #define PWM_FCAPDAT5_FCAPDAT_Msk (0xfffful << PWM_FCAPDAT5_FCAPDAT_Pos) |
PWM_T::FCAPDAT5: FCAPDAT Mask
Definition at line 20056 of file NUC472_442.h.
| #define PWM_FCAPDAT5_FCAPDAT_Pos (0) |
PWM_T::FCAPDAT5: FCAPDAT Position
Definition at line 20055 of file NUC472_442.h.
| #define PWM_INTCTL_DINTTYPE_Msk (0x3ful << PWM_INTCTL_DINTTYPE_Pos) |
PWM_T::INTCTL: DINTTYPE Mask
Definition at line 19954 of file NUC472_442.h.
| #define PWM_INTCTL_DINTTYPE_Pos (8) |
PWM_T::INTCTL: DINTTYPE Position
Definition at line 19953 of file NUC472_442.h.
| #define PWM_INTCTL_PINTTYPE_Msk (0x3ful << PWM_INTCTL_PINTTYPE_Pos) |
PWM_T::INTCTL: PINTTYPE Mask
Definition at line 19951 of file NUC472_442.h.
| #define PWM_INTCTL_PINTTYPE_Pos (0) |
PWM_T::INTCTL: PINTTYPE Position
Definition at line 19950 of file NUC472_442.h.
| #define PWM_INTEN_BRKIEN_Msk (0x1ul << PWM_INTEN_BRKIEN_Pos) |
PWM_T::INTEN: BRKIEN Mask
Definition at line 19960 of file NUC472_442.h.
| #define PWM_INTEN_BRKIEN_Pos (6) |
PWM_T::INTEN: BRKIEN Position
Definition at line 19959 of file NUC472_442.h.
| #define PWM_INTEN_DIEN_Msk (0x3ful << PWM_INTEN_DIEN_Pos) |
PWM_T::INTEN: DIEN Mask
Definition at line 19963 of file NUC472_442.h.
| #define PWM_INTEN_DIEN_Pos (8) |
PWM_T::INTEN: DIEN Position
Definition at line 19962 of file NUC472_442.h.
| #define PWM_INTEN_FLIEN_Msk (0x3ful << PWM_INTEN_FLIEN_Pos) |
PWM_T::INTEN: FLIEN Mask
Definition at line 19969 of file NUC472_442.h.
| #define PWM_INTEN_FLIEN_Pos (24) |
PWM_T::INTEN: FLIEN Position
Definition at line 19968 of file NUC472_442.h.
| #define PWM_INTEN_PIEN_Msk (0x3ful << PWM_INTEN_PIEN_Pos) |
PWM_T::INTEN: PIEN Mask
Definition at line 19957 of file NUC472_442.h.
| #define PWM_INTEN_PIEN_Pos (0) |
PWM_T::INTEN: PIEN Position
Definition at line 19956 of file NUC472_442.h.
| #define PWM_INTEN_RLIEN_Msk (0x3ful << PWM_INTEN_RLIEN_Pos) |
PWM_T::INTEN: RLIEN Mask
Definition at line 19966 of file NUC472_442.h.
| #define PWM_INTEN_RLIEN_Pos (16) |
PWM_T::INTEN: RLIEN Position
Definition at line 19965 of file NUC472_442.h.
| #define PWM_INTSTS_BRKIF0_Msk (0x1ul << PWM_INTSTS_BRKIF0_Pos) |
PWM_T::INTSTS: BRKIF0 Mask
Definition at line 19975 of file NUC472_442.h.
| #define PWM_INTSTS_BRKIF0_Pos (6) |
PWM_T::INTSTS: BRKIF0 Position
Definition at line 19974 of file NUC472_442.h.
| #define PWM_INTSTS_BRKIF1_Msk (0x1ul << PWM_INTSTS_BRKIF1_Pos) |
PWM_T::INTSTS: BRKIF1 Mask
Definition at line 19978 of file NUC472_442.h.
| #define PWM_INTSTS_BRKIF1_Pos (7) |
PWM_T::INTSTS: BRKIF1 Position
Definition at line 19977 of file NUC472_442.h.
| #define PWM_INTSTS_BRKLK0_Msk (0x1ul << PWM_INTSTS_BRKLK0_Pos) |
PWM_T::INTSTS: BRKLK0 Mask
Definition at line 19984 of file NUC472_442.h.
| #define PWM_INTSTS_BRKLK0_Pos (14) |
PWM_T::INTSTS: BRKLK0 Position
Definition at line 19983 of file NUC472_442.h.
| #define PWM_INTSTS_BRKSTS0_Msk (0x1ul << PWM_INTSTS_BRKSTS0_Pos) |
PWM_T::INTSTS: BRKSTS0 Mask
Definition at line 19990 of file NUC472_442.h.
| #define PWM_INTSTS_BRKSTS0_Pos (22) |
PWM_T::INTSTS: BRKSTS0 Position
Definition at line 19989 of file NUC472_442.h.
| #define PWM_INTSTS_BRKSTS1_Msk (0x1ul << PWM_INTSTS_BRKSTS1_Pos) |
PWM_T::INTSTS: BRKSTS1 Mask
Definition at line 19993 of file NUC472_442.h.
| #define PWM_INTSTS_BRKSTS1_Pos (23) |
PWM_T::INTSTS: BRKSTS1 Position
Definition at line 19992 of file NUC472_442.h.
| #define PWM_INTSTS_CFLIF_Msk (0x3ful << PWM_INTSTS_CFLIF_Pos) |
PWM_T::INTSTS: CFLIF Mask
Definition at line 19996 of file NUC472_442.h.
| #define PWM_INTSTS_CFLIF_Pos (24) |
PWM_T::INTSTS: CFLIF Position
Definition at line 19995 of file NUC472_442.h.
| #define PWM_INTSTS_CRLIF_Msk (0x3ful << PWM_INTSTS_CRLIF_Pos) |
PWM_T::INTSTS: CRLIF Mask
Definition at line 19987 of file NUC472_442.h.
| #define PWM_INTSTS_CRLIF_Pos (16) |
PWM_T::INTSTS: CRLIF Position
Definition at line 19986 of file NUC472_442.h.
| #define PWM_INTSTS_DIF_Msk (0x3ful << PWM_INTSTS_DIF_Pos) |
PWM_T::INTSTS: DIF Mask
Definition at line 19981 of file NUC472_442.h.
| #define PWM_INTSTS_DIF_Pos (8) |
PWM_T::INTSTS: DIF Position
Definition at line 19980 of file NUC472_442.h.
| #define PWM_INTSTS_PIF_Msk (0x3ful << PWM_INTSTS_PIF_Pos) |
PWM_T::INTSTS: PIF Mask
Definition at line 19972 of file NUC472_442.h.
| #define PWM_INTSTS_PIF_Pos (0) |
PWM_T::INTSTS: PIF Position
Definition at line 19971 of file NUC472_442.h.
| #define PWM_MSK_MSKDAT_Msk (0x3ful << PWM_MSK_MSKDAT_Pos) |
PWM_T::MSK: MSKDAT Mask
Definition at line 19861 of file NUC472_442.h.
| #define PWM_MSK_MSKDAT_Pos (0) |
PWM_T::MSK: MSKDAT Position
Definition at line 19860 of file NUC472_442.h.
| #define PWM_MSKEN_MSKEN_Msk (0x3ful << PWM_MSKEN_MSKEN_Pos) |
PWM_T::MSKEN: MSKEN Mask
Definition at line 19858 of file NUC472_442.h.
| #define PWM_MSKEN_MSKEN_Pos (0) |
PWM_T::MSKEN: MSKEN Position
Definition at line 19857 of file NUC472_442.h.
| #define PWM_PERIOD0_PERIOD_Msk (0xfffful << PWM_PERIOD0_PERIOD_Pos) |
PWM_T::PERIOD: PERIOD Mask
Definition at line 19804 of file NUC472_442.h.
| #define PWM_PERIOD0_PERIOD_Pos (0) |
PWM_T::PERIOD: PERIOD Position
Definition at line 19803 of file NUC472_442.h.
| #define PWM_PERIOD1_PERIOD_Msk (0xfffful << PWM_PERIOD1_PERIOD_Pos) |
PWM_T::PERIOD: PERIOD Mask
Definition at line 19807 of file NUC472_442.h.
| #define PWM_PERIOD1_PERIOD_Pos (0) |
PWM_T::PERIOD: PERIOD Position
Definition at line 19806 of file NUC472_442.h.
| #define PWM_PERIOD2_PERIOD_Msk (0xfffful << PWM_PERIOD2_PERIOD_Pos) |
PWM_T::PERIOD: PERIOD Mask
Definition at line 19810 of file NUC472_442.h.
| #define PWM_PERIOD2_PERIOD_Pos (0) |
PWM_T::PERIOD: PERIOD Position
Definition at line 19809 of file NUC472_442.h.
| #define PWM_PERIOD3_PERIOD_Msk (0xfffful << PWM_PERIOD3_PERIOD_Pos) |
PWM_T::PERIOD: PERIOD Mask
Definition at line 19813 of file NUC472_442.h.
| #define PWM_PERIOD3_PERIOD_Pos (0) |
PWM_T::PERIOD: PERIOD Position
Definition at line 19812 of file NUC472_442.h.
| #define PWM_PERIOD4_PERIOD_Msk (0xfffful << PWM_PERIOD4_PERIOD_Pos) |
PWM_T::PERIOD: PERIOD Mask
Definition at line 19816 of file NUC472_442.h.
| #define PWM_PERIOD4_PERIOD_Pos (0) |
PWM_T::PERIOD: PERIOD Position
Definition at line 19815 of file NUC472_442.h.
| #define PWM_PERIOD5_PERIOD_Msk (0xfffful << PWM_PERIOD5_PERIOD_Pos) |
PWM_T::PERIOD: PERIOD Mask
Definition at line 19819 of file NUC472_442.h.
| #define PWM_PERIOD5_PERIOD_Pos (0) |
PWM_T::PERIOD: PERIOD Position
Definition at line 19818 of file NUC472_442.h.
| #define PWM_POEN_POEN_Msk (0x3ful << PWM_POEN_POEN_Pos) |
PWM_T::POEN: POEN Mask
Definition at line 19999 of file NUC472_442.h.
| #define PWM_POEN_POEN_Pos (0) |
PWM_T::POEN: POEN Position
Definition at line 19998 of file NUC472_442.h.
| #define PWM_RCAPDAT0_RCAPDAT_Msk (0xfffful << PWM_RCAPDAT0_RCAPDAT_Pos) |
PWM_T::RCAPDAT0: RCAPDAT Mask
Definition at line 20023 of file NUC472_442.h.
| #define PWM_RCAPDAT0_RCAPDAT_Pos (0) |
PWM_T::RCAPDAT0: RCAPDAT Position
Definition at line 20022 of file NUC472_442.h.
| #define PWM_RCAPDAT1_RCAPDAT_Msk (0xfffful << PWM_RCAPDAT1_RCAPDAT_Pos) |
PWM_T::RCAPDAT1: RCAPDAT Mask
Definition at line 20029 of file NUC472_442.h.
| #define PWM_RCAPDAT1_RCAPDAT_Pos (0) |
PWM_T::RCAPDAT1: RCAPDAT Position
Definition at line 20028 of file NUC472_442.h.
| #define PWM_RCAPDAT2_RCAPDAT_Msk (0xfffful << PWM_RCAPDAT2_RCAPDAT_Pos) |
PWM_T::RCAPDAT2: RCAPDAT Mask
Definition at line 20035 of file NUC472_442.h.
| #define PWM_RCAPDAT2_RCAPDAT_Pos (0) |
PWM_T::RCAPDAT2: RCAPDAT Position
Definition at line 20034 of file NUC472_442.h.
| #define PWM_RCAPDAT3_RCAPDAT_Msk (0xfffful << PWM_RCAPDAT3_RCAPDAT_Pos) |
PWM_T::RCAPDAT3: RCAPDAT Mask
Definition at line 20041 of file NUC472_442.h.
| #define PWM_RCAPDAT3_RCAPDAT_Pos (0) |
PWM_T::RCAPDAT3: RCAPDAT Position
Definition at line 20040 of file NUC472_442.h.
| #define PWM_RCAPDAT4_RCAPDAT_Msk (0xfffful << PWM_RCAPDAT4_RCAPDAT_Pos) |
PWM_T::RCAPDAT4: RCAPDAT Mask
Definition at line 20047 of file NUC472_442.h.
| #define PWM_RCAPDAT4_RCAPDAT_Pos (0) |
PWM_T::RCAPDAT4: RCAPDAT Position
Definition at line 20046 of file NUC472_442.h.
| #define PWM_RCAPDAT5_RCAPDAT_Msk (0xfffful << PWM_RCAPDAT5_RCAPDAT_Pos) |
PWM_T::RCAPDAT5: RCAPDAT Mask
Definition at line 20053 of file NUC472_442.h.
| #define PWM_RCAPDAT5_RCAPDAT_Pos (0) |
PWM_T::RCAPDAT5: RCAPDAT Position
Definition at line 20052 of file NUC472_442.h.
| #define PWM_SBS0_SYNCBUSY_Msk (0x1ul << PWM_SBS0_SYNCBUSY_Pos) |
PWM_T::SBS: SYNCBUSY Mask
Definition at line 20059 of file NUC472_442.h.
| #define PWM_SBS0_SYNCBUSY_Pos (0) |
PWM_T::SBS: SYNCBUSY Position
Definition at line 20058 of file NUC472_442.h.
| #define PWM_SBS1_SYNCBUSY_Msk (0x1ul << PWM_SBS1_SYNCBUSY_Pos) |
PWM_T::SBS: SYNCBUSY Mask
Definition at line 20062 of file NUC472_442.h.
| #define PWM_SBS1_SYNCBUSY_Pos (0) |
PWM_T::SBS: SYNCBUSY Position
Definition at line 20061 of file NUC472_442.h.
| #define PWM_SBS2_SYNCBUSY_Msk (0x1ul << PWM_SBS2_SYNCBUSY_Pos) |
PWM_T::SBS: SYNCBUSY Mask
Definition at line 20065 of file NUC472_442.h.
| #define PWM_SBS2_SYNCBUSY_Pos (0) |
PWM_T::SBS: SYNCBUSY Position
Definition at line 20064 of file NUC472_442.h.
| #define PWM_SBS3_SYNCBUSY_Msk (0x1ul << PWM_SBS3_SYNCBUSY_Pos) |
PWM_T::SBS: SYNCBUSY Mask
Definition at line 20068 of file NUC472_442.h.
| #define PWM_SBS3_SYNCBUSY_Pos (0) |
PWM_T::SBS: SYNCBUSY Position
Definition at line 20067 of file NUC472_442.h.
| #define PWM_SBS4_SYNCBUSY_Msk (0x1ul << PWM_SBS4_SYNCBUSY_Pos) |
PWM_T::SBS: SYNCBUSY Mask
Definition at line 20071 of file NUC472_442.h.
| #define PWM_SBS4_SYNCBUSY_Pos (0) |
PWM_T::SBS: SYNCBUSY Position
Definition at line 20070 of file NUC472_442.h.
| #define PWM_SBS5_SYNCBUSY_Msk (0x1ul << PWM_SBS5_SYNCBUSY_Pos) |
PWM_T::SBS: SYNCBUSY Mask
Definition at line 20074 of file NUC472_442.h.
| #define PWM_SBS5_SYNCBUSY_Pos (0) |
PWM_T::SBS: SYNCBUSY Position
Definition at line 20073 of file NUC472_442.h.
| #define PWM_TRGADCSTS_CTRGF_Msk (0x3ful << PWM_TRGADCSTS_CTRGF_Pos) |
PWM_T::TRGADCSTS: CTRGF Mask
Definition at line 19900 of file NUC472_442.h.
| #define PWM_TRGADCSTS_CTRGF_Pos (8) |
PWM_T::TRGADCSTS: CTRGF Position
Definition at line 19899 of file NUC472_442.h.
| #define PWM_TRGADCSTS_FTRGF_Msk (0x3ful << PWM_TRGADCSTS_FTRGF_Pos) |
PWM_T::TRGADCSTS: FTRGF Mask
Definition at line 19903 of file NUC472_442.h.
| #define PWM_TRGADCSTS_FTRGF_Pos (16) |
PWM_T::TRGADCSTS: FTRGF Position
Definition at line 19902 of file NUC472_442.h.
| #define PWM_TRGADCSTS_PTRGF_Msk (0x3ful << PWM_TRGADCSTS_PTRGF_Pos) |
PWM_T::TRGADCSTS: PTRGF Mask
Definition at line 19897 of file NUC472_442.h.
| #define PWM_TRGADCSTS_PTRGF_Pos (0) |
PWM_T::TRGADCSTS: PTRGF Position
Definition at line 19896 of file NUC472_442.h.
| #define PWM_TRGADCSTS_RTRGF_Msk (0x3ful << PWM_TRGADCSTS_RTRGF_Pos) |
PWM_T::TRGADCSTS: RTRGF Mask
Definition at line 19906 of file NUC472_442.h.
| #define PWM_TRGADCSTS_RTRGF_Pos (24) |
PWM_T::TRGADCSTS: RTRGF Position
Definition at line 19905 of file NUC472_442.h.
| #define PWM_TRGADCTL_CTRGEN_Msk (0x3ful << PWM_TRGADCTL_CTRGEN_Pos) |
PWM_T::TRGADCTL: CTRGEN Mask
Definition at line 19888 of file NUC472_442.h.
| #define PWM_TRGADCTL_CTRGEN_Pos (8) |
PWM_T::TRGADCTL: CTRGEN Position
Definition at line 19887 of file NUC472_442.h.
| #define PWM_TRGADCTL_FTRGEN_Msk (0x3ful << PWM_TRGADCTL_FTRGEN_Pos) |
PWM_T::TRGADCTL: FTRGEN Mask
Definition at line 19891 of file NUC472_442.h.
| #define PWM_TRGADCTL_FTRGEN_Pos (16) |
PWM_T::TRGADCTL: FTRGEN Position
Definition at line 19890 of file NUC472_442.h.
| #define PWM_TRGADCTL_PTRGEN_Msk (0x3ful << PWM_TRGADCTL_PTRGEN_Pos) |
PWM_T::TRGADCTL: PTRGEN Mask
Definition at line 19885 of file NUC472_442.h.
| #define PWM_TRGADCTL_PTRGEN_Pos (0) |
PWM_T::TRGADCTL: PTRGEN Position
Definition at line 19884 of file NUC472_442.h.
| #define PWM_TRGADCTL_RTRGEN_Msk (0x3ful << PWM_TRGADCTL_RTRGEN_Pos) |
PWM_T::TRGADCTL: RTRGEN Mask
Definition at line 19894 of file NUC472_442.h.
| #define PWM_TRGADCTL_RTRGEN_Pos (24) |
PWM_T::TRGADCTL: RTRGEN Position
Definition at line 19893 of file NUC472_442.h.
| #define QEI_CNT_VAL_Msk (0xfffffffful << QEI_CNT_VAL_Pos) |
QEI_T::CNT: VAL Mask
Definition at line 20296 of file NUC472_442.h.
| #define QEI_CNT_VAL_Pos (0) |
@addtogroup QEI_CONST QEI Bit Field Definition Constant Definitions for QEI Controller
QEI_T::CNT: VAL Position
Definition at line 20295 of file NUC472_442.h.
| #define QEI_CNTCMP_VAL_Msk (0xfffffffful << QEI_CNTCMP_VAL_Pos) |
QEI_T::CNTCMP: VAL Mask
Definition at line 20305 of file NUC472_442.h.
| #define QEI_CNTCMP_VAL_Pos (0) |
QEI_T::CNTCMP: VAL Position
Definition at line 20304 of file NUC472_442.h.
| #define QEI_CNTHOLD_VAL_Msk (0xfffffffful << QEI_CNTHOLD_VAL_Pos) |
QEI_T::CNTHOLD: VAL Mask
Definition at line 20299 of file NUC472_442.h.
| #define QEI_CNTHOLD_VAL_Pos (0) |
QEI_T::CNTHOLD: VAL Position
Definition at line 20298 of file NUC472_442.h.
| #define QEI_CNTLATCH_VAL_Msk (0xfffffffful << QEI_CNTLATCH_VAL_Pos) |
QEI_T::CNTLATCH: VAL Mask
Definition at line 20302 of file NUC472_442.h.
| #define QEI_CNTLATCH_VAL_Pos (0) |
QEI_T::CNTLATCH: VAL Position
Definition at line 20301 of file NUC472_442.h.
| #define QEI_CNTMAX_VAL_Msk (0xfffffffful << QEI_CNTMAX_VAL_Pos) |
QEI_T::CNTMAX: VAL Mask
Definition at line 20308 of file NUC472_442.h.
| #define QEI_CNTMAX_VAL_Pos (0) |
QEI_T::CNTMAX: VAL Position
Definition at line 20307 of file NUC472_442.h.
| #define QEI_CTR_CHAEN_Msk (0x1ul << QEI_CTR_CHAEN_Pos) |
QEI_T::CTR: CHAEN Mask
Definition at line 20317 of file NUC472_442.h.
| #define QEI_CTR_CHAEN_Pos (4) |
QEI_T::CTR: CHAEN Position
Definition at line 20316 of file NUC472_442.h.
| #define QEI_CTR_CHAINV_Msk (0x1ul << QEI_CTR_CHAINV_Pos) |
QEI_T::CTR: CHAINV Mask
Definition at line 20329 of file NUC472_442.h.
| #define QEI_CTR_CHAINV_Pos (12) |
QEI_T::CTR: CHAINV Position
Definition at line 20328 of file NUC472_442.h.
| #define QEI_CTR_CHBEN_Msk (0x1ul << QEI_CTR_CHBEN_Pos) |
QEI_T::CTR: CHBEN Mask
Definition at line 20320 of file NUC472_442.h.
| #define QEI_CTR_CHBEN_Pos (5) |
QEI_T::CTR: CHBEN Position
Definition at line 20319 of file NUC472_442.h.
| #define QEI_CTR_CHBINV_Msk (0x1ul << QEI_CTR_CHBINV_Pos) |
QEI_T::CTR: CHBINV Mask
Definition at line 20332 of file NUC472_442.h.
| #define QEI_CTR_CHBINV_Pos (13) |
QEI_T::CTR: CHBINV Position
Definition at line 20331 of file NUC472_442.h.
| #define QEI_CTR_CMPENN_Msk (0x1ul << QEI_CTR_CMPENN_Pos) |
QEI_T::CTR: CMPENN Mask
Definition at line 20371 of file NUC472_442.h.
| #define QEI_CTR_CMPENN_Pos (28) |
QEI_T::CTR: CMPENN Position
Definition at line 20370 of file NUC472_442.h.
| #define QEI_CTR_CMPIEN_Msk (0x1ul << QEI_CTR_CMPIEN_Pos) |
QEI_T::CTR: CMPIEN Mask
Definition at line 20344 of file NUC472_442.h.
| #define QEI_CTR_CMPIEN_Pos (18) |
QEI_T::CTR: CMPIEN Position
Definition at line 20343 of file NUC472_442.h.
| #define QEI_CTR_DIRIEN_Msk (0x1ul << QEI_CTR_DIRIEN_Pos) |
QEI_T::CTR: DIRIEN Mask
Definition at line 20341 of file NUC472_442.h.
| #define QEI_CTR_DIRIEN_Pos (17) |
QEI_T::CTR: DIRIEN Position
Definition at line 20340 of file NUC472_442.h.
| #define QEI_CTR_HOLDCNT_Msk (0x1ul << QEI_CTR_HOLDCNT_Pos) |
QEI_T::CTR: HOLDCNT Mask
Definition at line 20362 of file NUC472_442.h.
| #define QEI_CTR_HOLDCNT_Pos (24) |
QEI_T::CTR: HOLDCNT Position
Definition at line 20361 of file NUC472_442.h.
| #define QEI_CTR_HOLDTMR0_Msk (0x1ul << QEI_CTR_HOLDTMR0_Pos) |
QEI_T::CTR: HOLDTMR0 Mask
Definition at line 20350 of file NUC472_442.h.
| #define QEI_CTR_HOLDTMR0_Pos (20) |
QEI_T::CTR: HOLDTMR0 Position
Definition at line 20349 of file NUC472_442.h.
| #define QEI_CTR_HOLDTMR1_Msk (0x1ul << QEI_CTR_HOLDTMR1_Pos) |
QEI_T::CTR: HOLDTMR1 Mask
Definition at line 20353 of file NUC472_442.h.
| #define QEI_CTR_HOLDTMR1_Pos (21) |
QEI_T::CTR: HOLDTMR1 Position
Definition at line 20352 of file NUC472_442.h.
| #define QEI_CTR_HOLDTMR2_Msk (0x1ul << QEI_CTR_HOLDTMR2_Pos) |
QEI_T::CTR: HOLDTMR2 Mask
Definition at line 20356 of file NUC472_442.h.
| #define QEI_CTR_HOLDTMR2_Pos (22) |
QEI_T::CTR: HOLDTMR2 Position
Definition at line 20355 of file NUC472_442.h.
| #define QEI_CTR_HOLDTMR3_Msk (0x1ul << QEI_CTR_HOLDTMR3_Pos) |
QEI_T::CTR: HOLDTMR3 Mask
Definition at line 20359 of file NUC472_442.h.
| #define QEI_CTR_HOLDTMR3_Pos (23) |
QEI_T::CTR: HOLDTMR3 Position
Definition at line 20358 of file NUC472_442.h.
| #define QEI_CTR_IDXEN_Msk (0x1ul << QEI_CTR_IDXEN_Pos) |
QEI_T::CTR: IDXEN Mask
Definition at line 20323 of file NUC472_442.h.
| #define QEI_CTR_IDXEN_Pos (6) |
QEI_T::CTR: IDXEN Position
Definition at line 20322 of file NUC472_442.h.
| #define QEI_CTR_IDXIEN_Msk (0x1ul << QEI_CTR_IDXIEN_Pos) |
QEI_T::CTR: IDXIEN Mask
Definition at line 20347 of file NUC472_442.h.
| #define QEI_CTR_IDXIEN_Pos (19) |
QEI_T::CTR: IDXIEN Position
Definition at line 20346 of file NUC472_442.h.
| #define QEI_CTR_IDXINV_Msk (0x1ul << QEI_CTR_IDXINV_Pos) |
QEI_T::CTR: IDXINV Mask
Definition at line 20335 of file NUC472_442.h.
| #define QEI_CTR_IDXINV_Pos (14) |
QEI_T::CTR: IDXINV Position
Definition at line 20334 of file NUC472_442.h.
| #define QEI_CTR_IDXLATEN_Msk (0x1ul << QEI_CTR_IDXLATEN_Pos) |
QEI_T::CTR: IDXLATEN Mask
Definition at line 20365 of file NUC472_442.h.
| #define QEI_CTR_IDXLATEN_Pos (25) |
QEI_T::CTR: IDXLATEN Position
Definition at line 20364 of file NUC472_442.h.
| #define QEI_CTR_IDXRLDEN_Msk (0x1ul << QEI_CTR_IDXRLDEN_Pos) |
QEI_T::CTR: IDXRLDEN Mask
Definition at line 20368 of file NUC472_442.h.
| #define QEI_CTR_IDXRLDEN_Pos (27) |
QEI_T::CTR: IDXRLDEN Position
Definition at line 20367 of file NUC472_442.h.
| #define QEI_CTR_MODE_Msk (0x3ul << QEI_CTR_MODE_Pos) |
QEI_T::CTR: MODE Mask
Definition at line 20326 of file NUC472_442.h.
| #define QEI_CTR_MODE_Pos (8) |
QEI_T::CTR: MODE Position
Definition at line 20325 of file NUC472_442.h.
| #define QEI_CTR_NFCLKSEL_Msk (0x3ul << QEI_CTR_NFCLKSEL_Pos) |
QEI_T::CTR: NFCLKSEL Mask
Definition at line 20311 of file NUC472_442.h.
| #define QEI_CTR_NFCLKSEL_Pos (0) |
QEI_T::CTR: NFCLKSEL Position
Definition at line 20310 of file NUC472_442.h.
| #define QEI_CTR_NFDIS_Msk (0x1ul << QEI_CTR_NFDIS_Pos) |
QEI_T::CTR: NFDIS Mask
Definition at line 20314 of file NUC472_442.h.
| #define QEI_CTR_NFDIS_Pos (3) |
QEI_T::CTR: NFDIS Position
Definition at line 20313 of file NUC472_442.h.
| #define QEI_CTR_OVUNIEN_Msk (0x1ul << QEI_CTR_OVUNIEN_Pos) |
QEI_T::CTR: OVUNIEN Mask
Definition at line 20338 of file NUC472_442.h.
| #define QEI_CTR_OVUNIEN_Pos (16) |
QEI_T::CTR: OVUNIEN Position
Definition at line 20337 of file NUC472_442.h.
| #define QEI_CTR_QEIEN_Msk (0x1ul << QEI_CTR_QEIEN_Pos) |
QEI_T::CTR: QEIEN Mask
Definition at line 20374 of file NUC472_442.h.
| #define QEI_CTR_QEIEN_Pos (29) |
QEI_T::CTR: QEIEN Position
Definition at line 20373 of file NUC472_442.h.
| #define QEI_STATUS_CMPF_Msk (0x1ul << QEI_STATUS_CMPF_Pos) |
QEI_T::STATUS: CMPF Mask
Definition at line 20380 of file NUC472_442.h.
| #define QEI_STATUS_CMPF_Pos (1) |
QEI_T::STATUS: CMPF Position
Definition at line 20379 of file NUC472_442.h.
| #define QEI_STATUS_DIRCHGF_Msk (0x1ul << QEI_STATUS_DIRCHGF_Pos) |
QEI_T::STATUS: DIRCHGF Mask
Definition at line 20386 of file NUC472_442.h.
| #define QEI_STATUS_DIRCHGF_Pos (3) |
QEI_T::STATUS: DIRCHGF Position
Definition at line 20385 of file NUC472_442.h.
| #define QEI_STATUS_DIRF_Msk (0x1ul << QEI_STATUS_DIRF_Pos) |
QEI_T::STATUS: DIRF Mask
Definition at line 20389 of file NUC472_442.h.
| #define QEI_STATUS_DIRF_Pos (8) |
QEI_T::STATUS: DIRF Position
Definition at line 20388 of file NUC472_442.h.
| #define QEI_STATUS_IDXF_Msk (0x1ul << QEI_STATUS_IDXF_Pos) |
QEI_T::STATUS: IDXF Mask
Definition at line 20377 of file NUC472_442.h.
| #define QEI_STATUS_IDXF_Pos (0) |
QEI_T::STATUS: IDXF Position
Definition at line 20376 of file NUC472_442.h.
| #define QEI_STATUS_OVUNF_Msk (0x1ul << QEI_STATUS_OVUNF_Pos) |
QEI_T::STATUS: OVUNF Mask
Definition at line 20383 of file NUC472_442.h.
| #define QEI_STATUS_OVUNF_Pos (2) |
QEI_T::STATUS: OVUNF Position
Definition at line 20382 of file NUC472_442.h.
| #define RTC_CAL_DAY_Msk (0xful << RTC_CAL_DAY_Pos) |
RTC_T::CAL: DAY Mask
Definition at line 20894 of file NUC472_442.h.
| #define RTC_CAL_DAY_Pos (0) |
RTC_T::CAL: DAY Position
Definition at line 20893 of file NUC472_442.h.
| #define RTC_CAL_MON_Msk (0xful << RTC_CAL_MON_Pos) |
RTC_T::CAL: MON Mask
Definition at line 20900 of file NUC472_442.h.
| #define RTC_CAL_MON_Pos (8) |
RTC_T::CAL: MON Position
Definition at line 20899 of file NUC472_442.h.
| #define RTC_CAL_TENDAY_Msk (0x3ul << RTC_CAL_TENDAY_Pos) |
RTC_T::CAL: TENDAY Mask
Definition at line 20897 of file NUC472_442.h.
| #define RTC_CAL_TENDAY_Pos (4) |
RTC_T::CAL: TENDAY Position
Definition at line 20896 of file NUC472_442.h.
| #define RTC_CAL_TENMON_Msk (0x1ul << RTC_CAL_TENMON_Pos) |
RTC_T::CAL: TENMON Mask
Definition at line 20903 of file NUC472_442.h.
| #define RTC_CAL_TENMON_Pos (12) |
RTC_T::CAL: TENMON Position
Definition at line 20902 of file NUC472_442.h.
| #define RTC_CAL_TENYEAR_Msk (0xful << RTC_CAL_TENYEAR_Pos) |
RTC_T::CAL: TENYEAR Mask
Definition at line 20909 of file NUC472_442.h.
| #define RTC_CAL_TENYEAR_Pos (20) |
RTC_T::CAL: TENYEAR Position
Definition at line 20908 of file NUC472_442.h.
| #define RTC_CAL_YEAR_Msk (0xful << RTC_CAL_YEAR_Pos) |
RTC_T::CAL: YEAR Mask
Definition at line 20906 of file NUC472_442.h.
| #define RTC_CAL_YEAR_Pos (16) |
RTC_T::CAL: YEAR Position
Definition at line 20905 of file NUC472_442.h.
| #define RTC_CALM_DAY_Msk (0xful << RTC_CALM_DAY_Pos) |
RTC_T::CALM: DAY Mask
Definition at line 20936 of file NUC472_442.h.
| #define RTC_CALM_DAY_Pos (0) |
RTC_T::CALM: DAY Position
Definition at line 20935 of file NUC472_442.h.
| #define RTC_CALM_MON_Msk (0xful << RTC_CALM_MON_Pos) |
RTC_T::CALM: MON Mask
Definition at line 20942 of file NUC472_442.h.
| #define RTC_CALM_MON_Pos (8) |
RTC_T::CALM: MON Position
Definition at line 20941 of file NUC472_442.h.
| #define RTC_CALM_TENDAY_Msk (0x3ul << RTC_CALM_TENDAY_Pos) |
RTC_T::CALM: TENDAY Mask
Definition at line 20939 of file NUC472_442.h.
| #define RTC_CALM_TENDAY_Pos (4) |
RTC_T::CALM: TENDAY Position
Definition at line 20938 of file NUC472_442.h.
| #define RTC_CALM_TENMON_Msk (0x1ul << RTC_CALM_TENMON_Pos) |
RTC_T::CALM: TENMON Mask
Definition at line 20945 of file NUC472_442.h.
| #define RTC_CALM_TENMON_Pos (12) |
RTC_T::CALM: TENMON Position
Definition at line 20944 of file NUC472_442.h.
| #define RTC_CALM_TENYEAR_Msk (0xful << RTC_CALM_TENYEAR_Pos) |
RTC_T::CALM: TENYEAR Mask
Definition at line 20951 of file NUC472_442.h.
| #define RTC_CALM_TENYEAR_Pos (20) |
RTC_T::CALM: TENYEAR Position
Definition at line 20950 of file NUC472_442.h.
| #define RTC_CALM_YEAR_Msk (0xful << RTC_CALM_YEAR_Pos) |
RTC_T::CALM: YEAR Mask
Definition at line 20948 of file NUC472_442.h.
| #define RTC_CALM_YEAR_Pos (16) |
RTC_T::CALM: YEAR Position
Definition at line 20947 of file NUC472_442.h.
| #define RTC_CAMSK_MDAY_Msk (0x1ul << RTC_CAMSK_MDAY_Pos) |
RTC_T::CAMSK: MDAY Mask
Definition at line 21086 of file NUC472_442.h.
| #define RTC_CAMSK_MDAY_Pos (0) |
RTC_T::CAMSK: MDAY Position
Definition at line 21085 of file NUC472_442.h.
| #define RTC_CAMSK_MMON_Msk (0x1ul << RTC_CAMSK_MMON_Pos) |
RTC_T::CAMSK: MMON Mask
Definition at line 21092 of file NUC472_442.h.
| #define RTC_CAMSK_MMON_Pos (2) |
RTC_T::CAMSK: MMON Position
Definition at line 21091 of file NUC472_442.h.
| #define RTC_CAMSK_MTENDAY_Msk (0x1ul << RTC_CAMSK_MTENDAY_Pos) |
RTC_T::CAMSK: MTENDAY Mask
Definition at line 21089 of file NUC472_442.h.
| #define RTC_CAMSK_MTENDAY_Pos (1) |
RTC_T::CAMSK: MTENDAY Position
Definition at line 21088 of file NUC472_442.h.
| #define RTC_CAMSK_MTENMON_Msk (0x1ul << RTC_CAMSK_MTENMON_Pos) |
RTC_T::CAMSK: MTENMON Mask
Definition at line 21095 of file NUC472_442.h.
| #define RTC_CAMSK_MTENMON_Pos (3) |
RTC_T::CAMSK: MTENMON Position
Definition at line 21094 of file NUC472_442.h.
| #define RTC_CAMSK_MTENYEAR_Msk (0x1ul << RTC_CAMSK_MTENYEAR_Pos) |
RTC_T::CAMSK: MTENYEAR Mask
Definition at line 21101 of file NUC472_442.h.
| #define RTC_CAMSK_MTENYEAR_Pos (5) |
RTC_T::CAMSK: MTENYEAR Position
Definition at line 21100 of file NUC472_442.h.
| #define RTC_CAMSK_MYEAR_Msk (0x1ul << RTC_CAMSK_MYEAR_Pos) |
RTC_T::CAMSK: MYEAR Mask
Definition at line 21098 of file NUC472_442.h.
| #define RTC_CAMSK_MYEAR_Pos (4) |
RTC_T::CAMSK: MYEAR Position
Definition at line 21097 of file NUC472_442.h.
| #define RTC_CLKFMT_24HEN_Msk (0x1ul << RTC_CLKFMT_24HEN_Pos) |
RTC_T::CLKFMT: 24HEN Mask
Definition at line 20912 of file NUC472_442.h.
| #define RTC_CLKFMT_24HEN_Pos (0) |
RTC_T::CLKFMT: 24HEN Position
Definition at line 20911 of file NUC472_442.h.
| #define RTC_FREQADJ_FRACTION_Msk (0x3ful << RTC_FREQADJ_FRACTION_Pos) |
RTC_T::FREQADJ: FRACTION Mask
Definition at line 20870 of file NUC472_442.h.
| #define RTC_FREQADJ_FRACTION_Pos (0) |
RTC_T::FREQADJ: FRACTION Position
Definition at line 20869 of file NUC472_442.h.
| #define RTC_FREQADJ_INTEGER_Msk (0xful << RTC_FREQADJ_INTEGER_Pos) |
RTC_T::FREQADJ: INTEGER Mask
Definition at line 20873 of file NUC472_442.h.
| #define RTC_FREQADJ_INTEGER_Pos (8) |
RTC_T::FREQADJ: INTEGER Position
Definition at line 20872 of file NUC472_442.h.
| #define RTC_INIT_INIT_Active_Msk (0x1ul << RTC_INIT_INIT_Active_Pos) |
RTC_T::INIT: INIT_Active Mask
Definition at line 20858 of file NUC472_442.h.
| #define RTC_INIT_INIT_Active_Pos (0) |
@addtogroup RTC_CONST RTC Bit Field Definition Constant Definitions for RTC Controller
RTC_T::INIT: INIT_Active Position
Definition at line 20857 of file NUC472_442.h.
| #define RTC_INIT_INIT_Msk (0x7ffffffful << RTC_INIT_INIT_Pos) |
RTC_T::INIT: INIT Mask
Definition at line 20861 of file NUC472_442.h.
| #define RTC_INIT_INIT_Pos (1) |
RTC_T::INIT: INIT Position
Definition at line 20860 of file NUC472_442.h.
| #define RTC_INTEN_ALMIEN_Msk (0x1ul << RTC_INTEN_ALMIEN_Pos) |
RTC_T::INTEN: ALMIEN Mask
Definition at line 20957 of file NUC472_442.h.
| #define RTC_INTEN_ALMIEN_Pos (0) |
RTC_T::INTEN: ALMIEN Position
Definition at line 20956 of file NUC472_442.h.
| #define RTC_INTEN_TICKIEN_Msk (0x1ul << RTC_INTEN_TICKIEN_Pos) |
RTC_T::INTEN: TICKIEN Mask
Definition at line 20960 of file NUC472_442.h.
| #define RTC_INTEN_TICKIEN_Pos (1) |
RTC_T::INTEN: TICKIEN Position
Definition at line 20959 of file NUC472_442.h.
| #define RTC_INTSTS_ALMIF_Msk (0x1ul << RTC_INTSTS_ALMIF_Pos) |
RTC_T::INTSTS: ALMIF Mask
Definition at line 20963 of file NUC472_442.h.
| #define RTC_INTSTS_ALMIF_Pos (0) |
RTC_T::INTSTS: ALMIF Position
Definition at line 20962 of file NUC472_442.h.
| #define RTC_INTSTS_TICKIF_Msk (0x1ul << RTC_INTSTS_TICKIF_Pos) |
RTC_T::INTSTS: TICKIF Mask
Definition at line 20966 of file NUC472_442.h.
| #define RTC_INTSTS_TICKIF_Pos (1) |
RTC_T::INTSTS: TICKIF Position
Definition at line 20965 of file NUC472_442.h.
| #define RTC_LEAPYEAR_LEAPYEAR_Msk (0x1ul << RTC_LEAPYEAR_LEAPYEAR_Pos) |
RTC_T::LEAPYEAR: LEAPYEAR Mask
Definition at line 20954 of file NUC472_442.h.
| #define RTC_LEAPYEAR_LEAPYEAR_Pos (0) |
RTC_T::LEAPYEAR: LEAPYEAR Position
Definition at line 20953 of file NUC472_442.h.
| #define RTC_LXTIPCTL_DINOFF_Msk (0x1ul << RTC_LXTIPCTL_DINOFF_Pos) |
RTC_T::LXTIPCTL: DINOFF Mask
Definition at line 21050 of file NUC472_442.h.
| #define RTC_LXTIPCTL_DINOFF_Pos (4) |
RTC_T::LXTIPCTL: DINOFF Position
Definition at line 21049 of file NUC472_442.h.
| #define RTC_LXTIPCTL_OUTEN_Msk (0x1ul << RTC_LXTIPCTL_OUTEN_Pos) |
RTC_T::LXTIPCTL: OUTEN Mask
Definition at line 21041 of file NUC472_442.h.
| #define RTC_LXTIPCTL_OUTEN_Pos (1) |
RTC_T::LXTIPCTL: OUTEN Position
Definition at line 21040 of file NUC472_442.h.
| #define RTC_LXTIPCTL_OUTLV_Msk (0x1ul << RTC_LXTIPCTL_OUTLV_Pos) |
RTC_T::LXTIPCTL: OUTLV Mask
Definition at line 21038 of file NUC472_442.h.
| #define RTC_LXTIPCTL_OUTLV_Pos (0) |
RTC_T::LXTIPCTL: OUTLV Position
Definition at line 21037 of file NUC472_442.h.
| #define RTC_LXTIPCTL_TRIEN_Msk (0x1ul << RTC_LXTIPCTL_TRIEN_Pos) |
RTC_T::LXTIPCTL: TRIEN Mask
Definition at line 21044 of file NUC472_442.h.
| #define RTC_LXTIPCTL_TRIEN_Pos (2) |
RTC_T::LXTIPCTL: TRIEN Position
Definition at line 21043 of file NUC472_442.h.
| #define RTC_LXTIPCTL_TYPE_Msk (0x1ul << RTC_LXTIPCTL_TYPE_Pos) |
RTC_T::LXTIPCTL: TYPE Mask
Definition at line 21047 of file NUC472_442.h.
| #define RTC_LXTIPCTL_TYPE_Pos (3) |
RTC_T::LXTIPCTL: TYPE Position
Definition at line 21046 of file NUC472_442.h.
| #define RTC_LXTOPCTL_DINOFF_Msk (0x1ul << RTC_LXTOPCTL_DINOFF_Pos) |
RTC_T::LXTOPCTL: DINOFF Mask
Definition at line 21065 of file NUC472_442.h.
| #define RTC_LXTOPCTL_DINOFF_Pos (4) |
RTC_T::LXTOPCTL: DINOFF Position
Definition at line 21064 of file NUC472_442.h.
| #define RTC_LXTOPCTL_OUTEN_Msk (0x1ul << RTC_LXTOPCTL_OUTEN_Pos) |
RTC_T::LXTOPCTL: OUTEN Mask
Definition at line 21056 of file NUC472_442.h.
| #define RTC_LXTOPCTL_OUTEN_Pos (1) |
RTC_T::LXTOPCTL: OUTEN Position
Definition at line 21055 of file NUC472_442.h.
| #define RTC_LXTOPCTL_OUTLV_Msk (0x1ul << RTC_LXTOPCTL_OUTLV_Pos) |
RTC_T::LXTOPCTL: OUTLV Mask
Definition at line 21053 of file NUC472_442.h.
| #define RTC_LXTOPCTL_OUTLV_Pos (0) |
RTC_T::LXTOPCTL: OUTLV Position
Definition at line 21052 of file NUC472_442.h.
| #define RTC_LXTOPCTL_TRIEN_Msk (0x1ul << RTC_LXTOPCTL_TRIEN_Pos) |
RTC_T::LXTOPCTL: TRIEN Mask
Definition at line 21059 of file NUC472_442.h.
| #define RTC_LXTOPCTL_TRIEN_Pos (2) |
RTC_T::LXTOPCTL: TRIEN Position
Definition at line 21058 of file NUC472_442.h.
| #define RTC_LXTOPCTL_TYPE_Msk (0x1ul << RTC_LXTOPCTL_TYPE_Pos) |
RTC_T::LXTOPCTL: TYPE Mask
Definition at line 21062 of file NUC472_442.h.
| #define RTC_LXTOPCTL_TYPE_Pos (3) |
RTC_T::LXTOPCTL: TYPE Position
Definition at line 21061 of file NUC472_442.h.
| #define RTC_RWEN_RWEN_Msk (0xfffful << RTC_RWEN_RWEN_Pos) |
RTC_T::RWEN: RWEN Mask
Definition at line 20864 of file NUC472_442.h.
| #define RTC_RWEN_RWEN_Pos (0) |
RTC_T::RWEN: RWEN Position
Definition at line 20863 of file NUC472_442.h.
| #define RTC_RWEN_RWENF_Msk (0x1ul << RTC_RWEN_RWENF_Pos) |
RTC_T::RWEN: RWENF Mask
Definition at line 20867 of file NUC472_442.h.
| #define RTC_RWEN_RWENF_Pos (16) |
RTC_T::RWEN: RWENF Position
Definition at line 20866 of file NUC472_442.h.
| #define RTC_SPRCTL_SPRRWEN_Msk (0x1ul << RTC_SPRCTL_SPRRWEN_Pos) |
RTC_T::SPRCTL: SPRRWEN Mask
Definition at line 20972 of file NUC472_442.h.
| #define RTC_SPRCTL_SPRRWEN_Pos (2) |
RTC_T::SPRCTL: SPRRWEN Position
Definition at line 20971 of file NUC472_442.h.
| #define RTC_SPRCTL_SPRRWRDY_Msk (0x1ul << RTC_SPRCTL_SPRRWRDY_Pos) |
RTC_T::SPRCTL: SPRRWRDY Mask
Definition at line 20975 of file NUC472_442.h.
| #define RTC_SPRCTL_SPRRWRDY_Pos (7) |
RTC_T::SPRCTL: SPRRWRDY Position
Definition at line 20974 of file NUC472_442.h.
| #define RTC_TALM_HR_Msk (0xful << RTC_TALM_HR_Pos) |
RTC_T::TALM: HR Mask
Definition at line 20930 of file NUC472_442.h.
| #define RTC_TALM_HR_Pos (16) |
RTC_T::TALM: HR Position
Definition at line 20929 of file NUC472_442.h.
| #define RTC_TALM_MIN_Msk (0xful << RTC_TALM_MIN_Pos) |
RTC_T::TALM: MIN Mask
Definition at line 20924 of file NUC472_442.h.
| #define RTC_TALM_MIN_Pos (8) |
RTC_T::TALM: MIN Position
Definition at line 20923 of file NUC472_442.h.
| #define RTC_TALM_SEC_Msk (0xful << RTC_TALM_SEC_Pos) |
RTC_T::TALM: SEC Mask
Definition at line 20918 of file NUC472_442.h.
| #define RTC_TALM_SEC_Pos (0) |
RTC_T::TALM: SEC Position
Definition at line 20917 of file NUC472_442.h.
| #define RTC_TALM_TENHR_Msk (0x3ul << RTC_TALM_TENHR_Pos) |
RTC_T::TALM: TENHR Mask
Definition at line 20933 of file NUC472_442.h.
| #define RTC_TALM_TENHR_Pos (20) |
RTC_T::TALM: TENHR Position
Definition at line 20932 of file NUC472_442.h.
| #define RTC_TALM_TENMIN_Msk (0x7ul << RTC_TALM_TENMIN_Pos) |
RTC_T::TALM: TENMIN Mask
Definition at line 20927 of file NUC472_442.h.
| #define RTC_TALM_TENMIN_Pos (12) |
RTC_T::TALM: TENMIN Position
Definition at line 20926 of file NUC472_442.h.
| #define RTC_TALM_TENSEC_Msk (0x7ul << RTC_TALM_TENSEC_Pos) |
RTC_T::TALM: TENSEC Mask
Definition at line 20921 of file NUC472_442.h.
| #define RTC_TALM_TENSEC_Pos (4) |
RTC_T::TALM: TENSEC Position
Definition at line 20920 of file NUC472_442.h.
| #define RTC_TAMP0PCTL_DINOFF_Msk (0x1ul << RTC_TAMP0PCTL_DINOFF_Pos) |
RTC_T::TAMP0PCTL: DINOFF Mask
Definition at line 21020 of file NUC472_442.h.
| #define RTC_TAMP0PCTL_DINOFF_Pos (4) |
RTC_T::TAMP0PCTL: DINOFF Position
Definition at line 21019 of file NUC472_442.h.
| #define RTC_TAMP0PCTL_OUTEN_Msk (0x1ul << RTC_TAMP0PCTL_OUTEN_Pos) |
RTC_T::TAMP0PCTL: OUTEN Mask
Definition at line 21011 of file NUC472_442.h.
| #define RTC_TAMP0PCTL_OUTEN_Pos (1) |
RTC_T::TAMP0PCTL: OUTEN Position
Definition at line 21010 of file NUC472_442.h.
| #define RTC_TAMP0PCTL_OUTLV_Msk (0x1ul << RTC_TAMP0PCTL_OUTLV_Pos) |
RTC_T::TAMP0PCTL: OUTLV Mask
Definition at line 21008 of file NUC472_442.h.
| #define RTC_TAMP0PCTL_OUTLV_Pos (0) |
RTC_T::TAMP0PCTL: OUTLV Position
Definition at line 21007 of file NUC472_442.h.
| #define RTC_TAMP0PCTL_TRIEN_Msk (0x1ul << RTC_TAMP0PCTL_TRIEN_Pos) |
RTC_T::TAMP0PCTL: TRIEN Mask
Definition at line 21014 of file NUC472_442.h.
| #define RTC_TAMP0PCTL_TRIEN_Pos (2) |
RTC_T::TAMP0PCTL: TRIEN Position
Definition at line 21013 of file NUC472_442.h.
| #define RTC_TAMP0PCTL_TYPE_Msk (0x1ul << RTC_TAMP0PCTL_TYPE_Pos) |
RTC_T::TAMP0PCTL: TYPE Mask
Definition at line 21017 of file NUC472_442.h.
| #define RTC_TAMP0PCTL_TYPE_Pos (3) |
RTC_T::TAMP0PCTL: TYPE Position
Definition at line 21016 of file NUC472_442.h.
| #define RTC_TAMP1PCTL_DINOFF_Msk (0x1ul << RTC_TAMP1PCTL_DINOFF_Pos) |
RTC_T::TAMP1PCTL: DINOFF Mask
Definition at line 21035 of file NUC472_442.h.
| #define RTC_TAMP1PCTL_DINOFF_Pos (4) |
RTC_T::TAMP1PCTL: DINOFF Position
Definition at line 21034 of file NUC472_442.h.
| #define RTC_TAMP1PCTL_OUTEN_Msk (0x1ul << RTC_TAMP1PCTL_OUTEN_Pos) |
RTC_T::TAMP1PCTL: OUTEN Mask
Definition at line 21026 of file NUC472_442.h.
| #define RTC_TAMP1PCTL_OUTEN_Pos (1) |
RTC_T::TAMP1PCTL: OUTEN Position
Definition at line 21025 of file NUC472_442.h.
| #define RTC_TAMP1PCTL_OUTLV_Msk (0x1ul << RTC_TAMP1PCTL_OUTLV_Pos) |
RTC_T::TAMP1PCTL: OUTLV Mask
Definition at line 21023 of file NUC472_442.h.
| #define RTC_TAMP1PCTL_OUTLV_Pos (0) |
RTC_T::TAMP1PCTL: OUTLV Position
Definition at line 21022 of file NUC472_442.h.
| #define RTC_TAMP1PCTL_TRIEN_Msk (0x1ul << RTC_TAMP1PCTL_TRIEN_Pos) |
RTC_T::TAMP1PCTL: TRIEN Mask
Definition at line 21029 of file NUC472_442.h.
| #define RTC_TAMP1PCTL_TRIEN_Pos (2) |
RTC_T::TAMP1PCTL: TRIEN Position
Definition at line 21028 of file NUC472_442.h.
| #define RTC_TAMP1PCTL_TYPE_Msk (0x1ul << RTC_TAMP1PCTL_TYPE_Pos) |
RTC_T::TAMP1PCTL: TYPE Mask
Definition at line 21032 of file NUC472_442.h.
| #define RTC_TAMP1PCTL_TYPE_Pos (3) |
RTC_T::TAMP1PCTL: TYPE Position
Definition at line 21031 of file NUC472_442.h.
| #define RTC_TAMPCTL_DESTROYEN_Msk (0x1ul << RTC_TAMPCTL_DESTROYEN_Pos) |
RTC_T::TAMPCTL: DESTROYEN Mask
Definition at line 20981 of file NUC472_442.h.
| #define RTC_TAMPCTL_DESTROYEN_Pos (1) |
RTC_T::TAMPCTL: DESTROYEN Position
Definition at line 20980 of file NUC472_442.h.
| #define RTC_TAMPCTL_TAMPDBEN0_Msk (0x1ul << RTC_TAMPCTL_TAMPDBEN0_Pos) |
RTC_T::TAMPCTL: TAMPDBEN0 Mask
Definition at line 20990 of file NUC472_442.h.
| #define RTC_TAMPCTL_TAMPDBEN0_Pos (4) |
RTC_T::TAMPCTL: TAMPDBEN0 Position
Definition at line 20989 of file NUC472_442.h.
| #define RTC_TAMPCTL_TAMPDBEN1_Msk (0x1ul << RTC_TAMPCTL_TAMPDBEN1_Pos) |
RTC_T::TAMPCTL: TAMPDBEN1 Mask
Definition at line 20993 of file NUC472_442.h.
| #define RTC_TAMPCTL_TAMPDBEN1_Pos (5) |
RTC_T::TAMPCTL: TAMPDBEN1 Position
Definition at line 20992 of file NUC472_442.h.
| #define RTC_TAMPCTL_TAMPEN0_Msk (0x1ul << RTC_TAMPCTL_TAMPEN0_Pos) |
RTC_T::TAMPCTL: TAMPEN0 Mask
Definition at line 20984 of file NUC472_442.h.
| #define RTC_TAMPCTL_TAMPEN0_Pos (2) |
RTC_T::TAMPCTL: TAMPEN0 Position
Definition at line 20983 of file NUC472_442.h.
| #define RTC_TAMPCTL_TAMPEN1_Msk (0x1ul << RTC_TAMPCTL_TAMPEN1_Pos) |
RTC_T::TAMPCTL: TAMPEN1 Mask
Definition at line 20987 of file NUC472_442.h.
| #define RTC_TAMPCTL_TAMPEN1_Pos (3) |
RTC_T::TAMPCTL: TAMPEN1 Position
Definition at line 20986 of file NUC472_442.h.
| #define RTC_TAMPCTL_TAMPLV0_Msk (0x1ul << RTC_TAMPCTL_TAMPLV0_Pos) |
RTC_T::TAMPCTL: TAMPLV0 Mask
Definition at line 20996 of file NUC472_442.h.
| #define RTC_TAMPCTL_TAMPLV0_Pos (6) |
RTC_T::TAMPCTL: TAMPLV0 Position
Definition at line 20995 of file NUC472_442.h.
| #define RTC_TAMPCTL_TAMPLV1_Msk (0x1ul << RTC_TAMPCTL_TAMPLV1_Pos) |
RTC_T::TAMPCTL: TAMPLV1 Mask
Definition at line 20999 of file NUC472_442.h.
| #define RTC_TAMPCTL_TAMPLV1_Pos (7) |
RTC_T::TAMPCTL: TAMPLV1 Position
Definition at line 20998 of file NUC472_442.h.
| #define RTC_TAMPCTL_TIEN_Msk (0x1ul << RTC_TAMPCTL_TIEN_Pos) |
RTC_T::TAMPCTL: TIEN Mask
Definition at line 20978 of file NUC472_442.h.
| #define RTC_TAMPCTL_TIEN_Pos (0) |
RTC_T::TAMPCTL: TIEN Position
Definition at line 20977 of file NUC472_442.h.
| #define RTC_TAMPSTS_TAMPSTS0_Msk (0x1ul << RTC_TAMPSTS_TAMPSTS0_Pos) |
RTC_T::TAMPSTS: TAMPSTS0 Mask
Definition at line 21002 of file NUC472_442.h.
| #define RTC_TAMPSTS_TAMPSTS0_Pos (0) |
RTC_T::TAMPSTS: TAMPSTS0 Position
Definition at line 21001 of file NUC472_442.h.
| #define RTC_TAMPSTS_TAMPSTS1_Msk (0x1ul << RTC_TAMPSTS_TAMPSTS1_Pos) |
RTC_T::TAMPSTS: TAMPSTS1 Mask
Definition at line 21005 of file NUC472_442.h.
| #define RTC_TAMPSTS_TAMPSTS1_Pos (1) |
RTC_T::TAMPSTS: TAMPSTS1 Position
Definition at line 21004 of file NUC472_442.h.
| #define RTC_TAMSK_MHR_Msk (0x1ul << RTC_TAMSK_MHR_Pos) |
RTC_T::TAMSK: MHR Mask
Definition at line 21080 of file NUC472_442.h.
| #define RTC_TAMSK_MHR_Pos (4) |
RTC_T::TAMSK: MHR Position
Definition at line 21079 of file NUC472_442.h.
| #define RTC_TAMSK_MMIN_Msk (0x1ul << RTC_TAMSK_MMIN_Pos) |
RTC_T::TAMSK: MMIN Mask
Definition at line 21074 of file NUC472_442.h.
| #define RTC_TAMSK_MMIN_Pos (2) |
RTC_T::TAMSK: MMIN Position
Definition at line 21073 of file NUC472_442.h.
| #define RTC_TAMSK_MSEC_Msk (0x1ul << RTC_TAMSK_MSEC_Pos) |
RTC_T::TAMSK: MSEC Mask
Definition at line 21068 of file NUC472_442.h.
| #define RTC_TAMSK_MSEC_Pos (0) |
RTC_T::TAMSK: MSEC Position
Definition at line 21067 of file NUC472_442.h.
| #define RTC_TAMSK_MTENHR_Msk (0x1ul << RTC_TAMSK_MTENHR_Pos) |
RTC_T::TAMSK: MTENHR Mask
Definition at line 21083 of file NUC472_442.h.
| #define RTC_TAMSK_MTENHR_Pos (5) |
RTC_T::TAMSK: MTENHR Position
Definition at line 21082 of file NUC472_442.h.
| #define RTC_TAMSK_MTENMIN_Msk (0x1ul << RTC_TAMSK_MTENMIN_Pos) |
RTC_T::TAMSK: MTENMIN Mask
Definition at line 21077 of file NUC472_442.h.
| #define RTC_TAMSK_MTENMIN_Pos (3) |
RTC_T::TAMSK: MTENMIN Position
Definition at line 21076 of file NUC472_442.h.
| #define RTC_TAMSK_MTENSEC_Msk (0x1ul << RTC_TAMSK_MTENSEC_Pos) |
RTC_T::TAMSK: MTENSEC Mask
Definition at line 21071 of file NUC472_442.h.
| #define RTC_TAMSK_MTENSEC_Pos (1) |
RTC_T::TAMSK: MTENSEC Position
Definition at line 21070 of file NUC472_442.h.
| #define RTC_TICK_TICKSEL_Msk (0x7ul << RTC_TICK_TICKSEL_Pos) |
RTC_T::TICK: TICKSEL Mask
Definition at line 20969 of file NUC472_442.h.
| #define RTC_TICK_TICKSEL_Pos (0) |
RTC_T::TICK: TICKSEL Position
Definition at line 20968 of file NUC472_442.h.
| #define RTC_TIME_HR_Msk (0xful << RTC_TIME_HR_Pos) |
RTC_T::TIME: HR Mask
Definition at line 20888 of file NUC472_442.h.
| #define RTC_TIME_HR_Pos (16) |
RTC_T::TIME: HR Position
Definition at line 20887 of file NUC472_442.h.
| #define RTC_TIME_MIN_Msk (0xful << RTC_TIME_MIN_Pos) |
RTC_T::TIME: MIN Mask
Definition at line 20882 of file NUC472_442.h.
| #define RTC_TIME_MIN_Pos (8) |
RTC_T::TIME: MIN Position
Definition at line 20881 of file NUC472_442.h.
| #define RTC_TIME_SEC_Msk (0xful << RTC_TIME_SEC_Pos) |
RTC_T::TIME: SEC Mask
Definition at line 20876 of file NUC472_442.h.
| #define RTC_TIME_SEC_Pos (0) |
RTC_T::TIME: SEC Position
Definition at line 20875 of file NUC472_442.h.
| #define RTC_TIME_TENHR_Msk (0x3ul << RTC_TIME_TENHR_Pos) |
RTC_T::TIME: TENHR Mask
Definition at line 20891 of file NUC472_442.h.
| #define RTC_TIME_TENHR_Pos (20) |
RTC_T::TIME: TENHR Position
Definition at line 20890 of file NUC472_442.h.
| #define RTC_TIME_TENMIN_Msk (0x7ul << RTC_TIME_TENMIN_Pos) |
RTC_T::TIME: TENMIN Mask
Definition at line 20885 of file NUC472_442.h.
| #define RTC_TIME_TENMIN_Pos (12) |
RTC_T::TIME: TENMIN Position
Definition at line 20884 of file NUC472_442.h.
| #define RTC_TIME_TENSEC_Msk (0x7ul << RTC_TIME_TENSEC_Pos) |
RTC_T::TIME: TENSEC Mask
Definition at line 20879 of file NUC472_442.h.
| #define RTC_TIME_TENSEC_Pos (4) |
RTC_T::TIME: TENSEC Position
Definition at line 20878 of file NUC472_442.h.
| #define RTC_WEEKDAY_WEEKDAY_Msk (0x7ul << RTC_WEEKDAY_WEEKDAY_Pos) |
RTC_T::WEEKDAY: WEEKDAY Mask
Definition at line 20915 of file NUC472_442.h.
| #define RTC_WEEKDAY_WEEKDAY_Pos (0) |
RTC_T::WEEKDAY: WEEKDAY Position
Definition at line 20914 of file NUC472_442.h.
| #define SC_ALTCTL_ACTEN_Msk (0x1ul << SC_ALTCTL_ACTEN_Pos) |
SC_T::ALTCTL: ACTEN Mask
Definition at line 21809 of file NUC472_442.h.
| #define SC_ALTCTL_ACTEN_Pos (3) |
SC_T::ALTCTL: ACTEN Position
Definition at line 21808 of file NUC472_442.h.
| #define SC_ALTCTL_ACTSTS0_Msk (0x1ul << SC_ALTCTL_ACTSTS0_Pos) |
SC_T::ALTCTL: ACTSTS0 Mask
Definition at line 21833 of file NUC472_442.h.
| #define SC_ALTCTL_ACTSTS0_Pos (13) |
SC_T::ALTCTL: ACTSTS0 Position
Definition at line 21832 of file NUC472_442.h.
| #define SC_ALTCTL_ACTSTS1_Msk (0x1ul << SC_ALTCTL_ACTSTS1_Pos) |
SC_T::ALTCTL: ACTSTS1 Mask
Definition at line 21836 of file NUC472_442.h.
| #define SC_ALTCTL_ACTSTS1_Pos (14) |
SC_T::ALTCTL: ACTSTS1 Position
Definition at line 21835 of file NUC472_442.h.
| #define SC_ALTCTL_ACTSTS2_Msk (0x1ul << SC_ALTCTL_ACTSTS2_Pos) |
SC_T::ALTCTL: ACTSTS2 Mask
Definition at line 21839 of file NUC472_442.h.
| #define SC_ALTCTL_ACTSTS2_Pos (15) |
SC_T::ALTCTL: ACTSTS2 Position
Definition at line 21838 of file NUC472_442.h.
| #define SC_ALTCTL_ADACEN_Msk (0x1ul << SC_ALTCTL_ADACEN_Pos) |
SC_T::ALTCTL: ADACEN Mask
Definition at line 21827 of file NUC472_442.h.
| #define SC_ALTCTL_ADACEN_Pos (11) |
SC_T::ALTCTL: ADACEN Position
Definition at line 21826 of file NUC472_442.h.
| #define SC_ALTCTL_CNTEN0_Msk (0x1ul << SC_ALTCTL_CNTEN0_Pos) |
SC_T::ALTCTL: CNTEN0 Mask
Definition at line 21815 of file NUC472_442.h.
| #define SC_ALTCTL_CNTEN0_Pos (5) |
SC_T::ALTCTL: CNTEN0 Position
Definition at line 21814 of file NUC472_442.h.
| #define SC_ALTCTL_CNTEN1_Msk (0x1ul << SC_ALTCTL_CNTEN1_Pos) |
SC_T::ALTCTL: CNTEN1 Mask
Definition at line 21818 of file NUC472_442.h.
| #define SC_ALTCTL_CNTEN1_Pos (6) |
SC_T::ALTCTL: CNTEN1 Position
Definition at line 21817 of file NUC472_442.h.
| #define SC_ALTCTL_CNTEN2_Msk (0x1ul << SC_ALTCTL_CNTEN2_Pos) |
SC_T::ALTCTL: CNTEN2 Mask
Definition at line 21821 of file NUC472_442.h.
| #define SC_ALTCTL_CNTEN2_Pos (7) |
SC_T::ALTCTL: CNTEN2 Position
Definition at line 21820 of file NUC472_442.h.
| #define SC_ALTCTL_DACTEN_Msk (0x1ul << SC_ALTCTL_DACTEN_Pos) |
SC_T::ALTCTL: DACTEN Mask
Definition at line 21806 of file NUC472_442.h.
| #define SC_ALTCTL_DACTEN_Pos (2) |
SC_T::ALTCTL: DACTEN Position
Definition at line 21805 of file NUC472_442.h.
| #define SC_ALTCTL_INITSEL_Msk (0x3ul << SC_ALTCTL_INITSEL_Pos) |
SC_T::ALTCTL: INITSEL Mask
Definition at line 21824 of file NUC472_442.h.
| #define SC_ALTCTL_INITSEL_Pos (8) |
SC_T::ALTCTL: INITSEL Position
Definition at line 21823 of file NUC472_442.h.
| #define SC_ALTCTL_RXBGTEN_Msk (0x1ul << SC_ALTCTL_RXBGTEN_Pos) |
SC_T::ALTCTL: RXBGTEN Mask
Definition at line 21830 of file NUC472_442.h.
| #define SC_ALTCTL_RXBGTEN_Pos (12) |
SC_T::ALTCTL: RXBGTEN Position
Definition at line 21829 of file NUC472_442.h.
| #define SC_ALTCTL_RXRST_Msk (0x1ul << SC_ALTCTL_RXRST_Pos) |
SC_T::ALTCTL: RXRST Mask
Definition at line 21803 of file NUC472_442.h.
| #define SC_ALTCTL_RXRST_Pos (1) |
SC_T::ALTCTL: RXRST Position
Definition at line 21802 of file NUC472_442.h.
| #define SC_ALTCTL_TXRST_Msk (0x1ul << SC_ALTCTL_TXRST_Pos) |
SC_T::ALTCTL: TXRST Mask
Definition at line 21800 of file NUC472_442.h.
| #define SC_ALTCTL_TXRST_Pos (0) |
SC_T::ALTCTL: TXRST Position
Definition at line 21799 of file NUC472_442.h.
| #define SC_ALTCTL_WARSTEN_Msk (0x1ul << SC_ALTCTL_WARSTEN_Pos) |
SC_T::ALTCTL: WARSTEN Mask
Definition at line 21812 of file NUC472_442.h.
| #define SC_ALTCTL_WARSTEN_Pos (4) |
SC_T::ALTCTL: WARSTEN Position
Definition at line 21811 of file NUC472_442.h.
| #define SC_CTL_AUTOCEN_Msk (0x1ul << SC_CTL_AUTOCEN_Pos) |
SC_T::CTL: AUTOCEN Mask
Definition at line 21761 of file NUC472_442.h.
| #define SC_CTL_AUTOCEN_Pos (3) |
SC_T::CTL: AUTOCEN Position
Definition at line 21760 of file NUC472_442.h.
| #define SC_CTL_BGT_Msk (0x1ful << SC_CTL_BGT_Pos) |
SC_T::CTL: BGT Mask
Definition at line 21770 of file NUC472_442.h.
| #define SC_CTL_BGT_Pos (8) |
SC_T::CTL: BGT Position
Definition at line 21769 of file NUC472_442.h.
| #define SC_CTL_CDDBSEL_Msk (0x3ul << SC_CTL_CDDBSEL_Pos) |
SC_T::CTL: CDDBSEL Mask
Definition at line 21791 of file NUC472_442.h.
| #define SC_CTL_CDDBSEL_Pos (24) |
SC_T::CTL: CDDBSEL Position
Definition at line 21790 of file NUC472_442.h.
| #define SC_CTL_CDLV_Msk (0x1ul << SC_CTL_CDLV_Pos) |
SC_T::CTL: CDLV Mask
Definition at line 21794 of file NUC472_442.h.
| #define SC_CTL_CDLV_Pos (26) |
SC_T::CTL: CDLV Position
Definition at line 21793 of file NUC472_442.h.
| #define SC_CTL_CONSEL_Msk (0x3ul << SC_CTL_CONSEL_Pos) |
SC_T::CTL: CONSEL Mask
Definition at line 21764 of file NUC472_442.h.
| #define SC_CTL_CONSEL_Pos (4) |
SC_T::CTL: CONSEL Position
Definition at line 21763 of file NUC472_442.h.
| #define SC_CTL_NSB_Msk (0x1ul << SC_CTL_NSB_Pos) |
SC_T::CTL: NSB Mask
Definition at line 21776 of file NUC472_442.h.
| #define SC_CTL_NSB_Pos (15) |
SC_T::CTL: NSB Position
Definition at line 21775 of file NUC472_442.h.
| #define SC_CTL_RXOFF_Msk (0x1ul << SC_CTL_RXOFF_Pos) |
SC_T::CTL: RXOFF Mask
Definition at line 21755 of file NUC472_442.h.
| #define SC_CTL_RXOFF_Pos (1) |
SC_T::CTL: RXOFF Position
Definition at line 21754 of file NUC472_442.h.
| #define SC_CTL_RXRTY_Msk (0x7ul << SC_CTL_RXRTY_Pos) |
SC_T::CTL: RXRTY Mask
Definition at line 21779 of file NUC472_442.h.
| #define SC_CTL_RXRTY_Pos (16) |
SC_T::CTL: RXRTY Position
Definition at line 21778 of file NUC472_442.h.
| #define SC_CTL_RXRTYEN_Msk (0x1ul << SC_CTL_RXRTYEN_Pos) |
SC_T::CTL: RXRTYEN Mask
Definition at line 21782 of file NUC472_442.h.
| #define SC_CTL_RXRTYEN_Pos (19) |
SC_T::CTL: RXRTYEN Position
Definition at line 21781 of file NUC472_442.h.
| #define SC_CTL_RXTRGLV_Msk (0x3ul << SC_CTL_RXTRGLV_Pos) |
SC_T::CTL: RXTRGLV Mask
Definition at line 21767 of file NUC472_442.h.
| #define SC_CTL_RXTRGLV_Pos (6) |
SC_T::CTL: RXTRGLV Position
Definition at line 21766 of file NUC472_442.h.
| #define SC_CTL_SCEN_Msk (0x1ul << SC_CTL_SCEN_Pos) |
SC_T::CTL: SCEN Mask
Definition at line 21752 of file NUC472_442.h.
| #define SC_CTL_SCEN_Pos (0) |
SC_T::CTL: SCEN Position
Definition at line 21751 of file NUC472_442.h.
| #define SC_CTL_SYNC_Msk (0x1ul << SC_CTL_SYNC_Pos) |
SC_T::CTL: SYNC Mask
Definition at line 21797 of file NUC472_442.h.
| #define SC_CTL_SYNC_Pos (30) |
SC_T::CTL: SYNC Position
Definition at line 21796 of file NUC472_442.h.
| #define SC_CTL_TMRSEL_Msk (0x3ul << SC_CTL_TMRSEL_Pos) |
SC_T::CTL: TMRSEL Mask
Definition at line 21773 of file NUC472_442.h.
| #define SC_CTL_TMRSEL_Pos (13) |
SC_T::CTL: TMRSEL Position
Definition at line 21772 of file NUC472_442.h.
| #define SC_CTL_TXOFF_Msk (0x1ul << SC_CTL_TXOFF_Pos) |
SC_T::CTL: TXOFF Mask
Definition at line 21758 of file NUC472_442.h.
| #define SC_CTL_TXOFF_Pos (2) |
SC_T::CTL: TXOFF Position
Definition at line 21757 of file NUC472_442.h.
| #define SC_CTL_TXRTY_Msk (0x7ul << SC_CTL_TXRTY_Pos) |
SC_T::CTL: TXRTY Mask
Definition at line 21785 of file NUC472_442.h.
| #define SC_CTL_TXRTY_Pos (20) |
SC_T::CTL: TXRTY Position
Definition at line 21784 of file NUC472_442.h.
| #define SC_CTL_TXRTYEN_Msk (0x1ul << SC_CTL_TXRTYEN_Pos) |
SC_T::CTL: TXRTYEN Mask
Definition at line 21788 of file NUC472_442.h.
| #define SC_CTL_TXRTYEN_Pos (23) |
SC_T::CTL: TXRTYEN Position
Definition at line 21787 of file NUC472_442.h.
| #define SC_DAT_DAT_Msk (0xfful << SC_DAT_DAT_Pos) |
SC_T::DAT: DAT Mask
Definition at line 21749 of file NUC472_442.h.
| #define SC_DAT_DAT_Pos (0) |
@addtogroup SC_CONST SC Bit Field Definition Constant Definitions for SC Controller
SC_T::DAT: DAT Position
Definition at line 21748 of file NUC472_442.h.
| #define SC_EGT_EGT_Msk (0xfful << SC_EGT_EGT_Pos) |
SC_T::EGT: EGT Mask
Definition at line 21842 of file NUC472_442.h.
| #define SC_EGT_EGT_Pos (0) |
SC_T::EGT: EGT Position
Definition at line 21841 of file NUC472_442.h.
| #define SC_ETUCTL_CMPEN_Msk (0x1ul << SC_ETUCTL_CMPEN_Pos) |
SC_T::ETUCTL: CMPEN Mask
Definition at line 21851 of file NUC472_442.h.
| #define SC_ETUCTL_CMPEN_Pos (15) |
SC_T::ETUCTL: CMPEN Position
Definition at line 21850 of file NUC472_442.h.
| #define SC_ETUCTL_ETURDIV_Msk (0xffful << SC_ETUCTL_ETURDIV_Pos) |
SC_T::ETUCTL: ETURDIV Mask
Definition at line 21848 of file NUC472_442.h.
| #define SC_ETUCTL_ETURDIV_Pos (0) |
SC_T::ETUCTL: ETURDIV Position
Definition at line 21847 of file NUC472_442.h.
| #define SC_INTEN_ACERRIEN_Msk (0x1ul << SC_INTEN_ACERRIEN_Pos) |
SC_T::INTEN: ACERRIEN Mask
Definition at line 21884 of file NUC472_442.h.
| #define SC_INTEN_ACERRIEN_Pos (10) |
SC_T::INTEN: ACERRIEN Position
Definition at line 21883 of file NUC472_442.h.
| #define SC_INTEN_BGTIEN_Msk (0x1ul << SC_INTEN_BGTIEN_Pos) |
SC_T::INTEN: BGTIEN Mask
Definition at line 21872 of file NUC472_442.h.
| #define SC_INTEN_BGTIEN_Pos (6) |
SC_T::INTEN: BGTIEN Position
Definition at line 21871 of file NUC472_442.h.
| #define SC_INTEN_CDIEN_Msk (0x1ul << SC_INTEN_CDIEN_Pos) |
SC_T::INTEN: CDIEN Mask
Definition at line 21875 of file NUC472_442.h.
| #define SC_INTEN_CDIEN_Pos (7) |
SC_T::INTEN: CDIEN Position
Definition at line 21874 of file NUC472_442.h.
| #define SC_INTEN_INITIEN_Msk (0x1ul << SC_INTEN_INITIEN_Pos) |
SC_T::INTEN: INITIEN Mask
Definition at line 21878 of file NUC472_442.h.
| #define SC_INTEN_INITIEN_Pos (8) |
SC_T::INTEN: INITIEN Position
Definition at line 21877 of file NUC472_442.h.
| #define SC_INTEN_RDAIEN_Msk (0x1ul << SC_INTEN_RDAIEN_Pos) |
SC_T::INTEN: RDAIEN Mask
Definition at line 21854 of file NUC472_442.h.
| #define SC_INTEN_RDAIEN_Pos (0) |
SC_T::INTEN: RDAIEN Position
Definition at line 21853 of file NUC472_442.h.
| #define SC_INTEN_RXTOIF_Msk (0x1ul << SC_INTEN_RXTOIF_Pos) |
SC_T::INTEN: RXTOIF Mask
Definition at line 21881 of file NUC472_442.h.
| #define SC_INTEN_RXTOIF_Pos (9) |
SC_T::INTEN: RXTOIF Position
Definition at line 21880 of file NUC472_442.h.
| #define SC_INTEN_TBEIEN_Msk (0x1ul << SC_INTEN_TBEIEN_Pos) |
SC_T::INTEN: TBEIEN Mask
Definition at line 21857 of file NUC472_442.h.
| #define SC_INTEN_TBEIEN_Pos (1) |
SC_T::INTEN: TBEIEN Position
Definition at line 21856 of file NUC472_442.h.
| #define SC_INTEN_TERRIEN_Msk (0x1ul << SC_INTEN_TERRIEN_Pos) |
SC_T::INTEN: TERRIEN Mask
Definition at line 21860 of file NUC472_442.h.
| #define SC_INTEN_TERRIEN_Pos (2) |
SC_T::INTEN: TERRIEN Position
Definition at line 21859 of file NUC472_442.h.
| #define SC_INTEN_TMR0IEN_Msk (0x1ul << SC_INTEN_TMR0IEN_Pos) |
SC_T::INTEN: TMR0IEN Mask
Definition at line 21863 of file NUC472_442.h.
| #define SC_INTEN_TMR0IEN_Pos (3) |
SC_T::INTEN: TMR0IEN Position
Definition at line 21862 of file NUC472_442.h.
| #define SC_INTEN_TMR1IEN_Msk (0x1ul << SC_INTEN_TMR1IEN_Pos) |
SC_T::INTEN: TMR1IEN Mask
Definition at line 21866 of file NUC472_442.h.
| #define SC_INTEN_TMR1IEN_Pos (4) |
SC_T::INTEN: TMR1IEN Position
Definition at line 21865 of file NUC472_442.h.
| #define SC_INTEN_TMR2IEN_Msk (0x1ul << SC_INTEN_TMR2IEN_Pos) |
SC_T::INTEN: TMR2IEN Mask
Definition at line 21869 of file NUC472_442.h.
| #define SC_INTEN_TMR2IEN_Pos (5) |
SC_T::INTEN: TMR2IEN Position
Definition at line 21868 of file NUC472_442.h.
| #define SC_INTSTS_ACERRIF_Msk (0x1ul << SC_INTSTS_ACERRIF_Pos) |
SC_T::INTSTS: ACERRIF Mask
Definition at line 21917 of file NUC472_442.h.
| #define SC_INTSTS_ACERRIF_Pos (10) |
SC_T::INTSTS: ACERRIF Position
Definition at line 21916 of file NUC472_442.h.
| #define SC_INTSTS_BGTIF_Msk (0x1ul << SC_INTSTS_BGTIF_Pos) |
SC_T::INTSTS: BGTIF Mask
Definition at line 21905 of file NUC472_442.h.
| #define SC_INTSTS_BGTIF_Pos (6) |
SC_T::INTSTS: BGTIF Position
Definition at line 21904 of file NUC472_442.h.
| #define SC_INTSTS_CDIF_Msk (0x1ul << SC_INTSTS_CDIF_Pos) |
SC_T::INTSTS: CDIF Mask
Definition at line 21908 of file NUC472_442.h.
| #define SC_INTSTS_CDIF_Pos (7) |
SC_T::INTSTS: CDIF Position
Definition at line 21907 of file NUC472_442.h.
| #define SC_INTSTS_INITIF_Msk (0x1ul << SC_INTSTS_INITIF_Pos) |
SC_T::INTSTS: INITIF Mask
Definition at line 21911 of file NUC472_442.h.
| #define SC_INTSTS_INITIF_Pos (8) |
SC_T::INTSTS: INITIF Position
Definition at line 21910 of file NUC472_442.h.
| #define SC_INTSTS_RBTOIF_Msk (0x1ul << SC_INTSTS_RBTOIF_Pos) |
SC_T::INTSTS: RBTOIF Mask
Definition at line 21914 of file NUC472_442.h.
| #define SC_INTSTS_RBTOIF_Pos (9) |
SC_T::INTSTS: RBTOIF Position
Definition at line 21913 of file NUC472_442.h.
| #define SC_INTSTS_RDAIF_Msk (0x1ul << SC_INTSTS_RDAIF_Pos) |
SC_T::INTSTS: RDAIF Mask
Definition at line 21887 of file NUC472_442.h.
| #define SC_INTSTS_RDAIF_Pos (0) |
SC_T::INTSTS: RDAIF Position
Definition at line 21886 of file NUC472_442.h.
| #define SC_INTSTS_TBEIF_Msk (0x1ul << SC_INTSTS_TBEIF_Pos) |
SC_T::INTSTS: TBEIF Mask
Definition at line 21890 of file NUC472_442.h.
| #define SC_INTSTS_TBEIF_Pos (1) |
SC_T::INTSTS: TBEIF Position
Definition at line 21889 of file NUC472_442.h.
| #define SC_INTSTS_TERRIF_Msk (0x1ul << SC_INTSTS_TERRIF_Pos) |
SC_T::INTSTS: TERRIF Mask
Definition at line 21893 of file NUC472_442.h.
| #define SC_INTSTS_TERRIF_Pos (2) |
SC_T::INTSTS: TERRIF Position
Definition at line 21892 of file NUC472_442.h.
| #define SC_INTSTS_TMR0IF_Msk (0x1ul << SC_INTSTS_TMR0IF_Pos) |
SC_T::INTSTS: TMR0IF Mask
Definition at line 21896 of file NUC472_442.h.
| #define SC_INTSTS_TMR0IF_Pos (3) |
SC_T::INTSTS: TMR0IF Position
Definition at line 21895 of file NUC472_442.h.
| #define SC_INTSTS_TMR1IF_Msk (0x1ul << SC_INTSTS_TMR1IF_Pos) |
SC_T::INTSTS: TMR1IF Mask
Definition at line 21899 of file NUC472_442.h.
| #define SC_INTSTS_TMR1IF_Pos (4) |
SC_T::INTSTS: TMR1IF Position
Definition at line 21898 of file NUC472_442.h.
| #define SC_INTSTS_TMR2IF_Msk (0x1ul << SC_INTSTS_TMR2IF_Pos) |
SC_T::INTSTS: TMR2IF Mask
Definition at line 21902 of file NUC472_442.h.
| #define SC_INTSTS_TMR2IF_Pos (5) |
SC_T::INTSTS: TMR2IF Position
Definition at line 21901 of file NUC472_442.h.
| #define SC_PINCTL_CLKKEEP_Msk (0x1ul << SC_PINCTL_CLKKEEP_Pos) |
SC_T::PINCTL: CLKKEEP Mask
Definition at line 21986 of file NUC472_442.h.
| #define SC_PINCTL_CLKKEEP_Pos (6) |
SC_T::PINCTL: CLKKEEP Position
Definition at line 21985 of file NUC472_442.h.
| #define SC_PINCTL_DATSTS_Msk (0x1ul << SC_PINCTL_DATSTS_Pos) |
SC_T::PINCTL: DATSTS Mask
Definition at line 21995 of file NUC472_442.h.
| #define SC_PINCTL_DATSTS_Pos (16) |
SC_T::PINCTL: DATSTS Position
Definition at line 21994 of file NUC472_442.h.
| #define SC_PINCTL_PWREN_Msk (0x1ul << SC_PINCTL_PWREN_Pos) |
SC_T::PINCTL: PWREN Mask
Definition at line 21980 of file NUC472_442.h.
| #define SC_PINCTL_PWREN_Pos (0) |
SC_T::PINCTL: PWREN Position
Definition at line 21979 of file NUC472_442.h.
| #define SC_PINCTL_PWRINV_Msk (0x1ul << SC_PINCTL_PWRINV_Pos) |
SC_T::PINCTL: PWRINV Mask
Definition at line 21992 of file NUC472_442.h.
| #define SC_PINCTL_PWRINV_Pos (11) |
SC_T::PINCTL: PWRINV Position
Definition at line 21991 of file NUC472_442.h.
| #define SC_PINCTL_PWRSTS_Msk (0x1ul << SC_PINCTL_PWRSTS_Pos) |
SC_T::PINCTL: PWRSTS Mask
Definition at line 21998 of file NUC472_442.h.
| #define SC_PINCTL_PWRSTS_Pos (17) |
SC_T::PINCTL: PWRSTS Position
Definition at line 21997 of file NUC472_442.h.
| #define SC_PINCTL_RSTSTS_Msk (0x1ul << SC_PINCTL_RSTSTS_Pos) |
SC_T::PINCTL: RSTSTS Mask
Definition at line 22001 of file NUC472_442.h.
| #define SC_PINCTL_RSTSTS_Pos (18) |
SC_T::PINCTL: RSTSTS Position
Definition at line 22000 of file NUC472_442.h.
| #define SC_PINCTL_SCDOUT_Msk (0x1ul << SC_PINCTL_SCDOUT_Pos) |
SC_T::PINCTL: SCDOUT Mask
Definition at line 21989 of file NUC472_442.h.
| #define SC_PINCTL_SCDOUT_Pos (9) |
SC_T::PINCTL: SCDOUT Position
Definition at line 21988 of file NUC472_442.h.
| #define SC_PINCTL_SCRST_Msk (0x1ul << SC_PINCTL_SCRST_Pos) |
SC_T::PINCTL: SCRST Mask
Definition at line 21983 of file NUC472_442.h.
| #define SC_PINCTL_SCRST_Pos (1) |
SC_T::PINCTL: SCRST Position
Definition at line 21982 of file NUC472_442.h.
| #define SC_PINCTL_SYNC_Msk (0x1ul << SC_PINCTL_SYNC_Pos) |
SC_T::PINCTL: SYNC Mask
Definition at line 22004 of file NUC472_442.h.
| #define SC_PINCTL_SYNC_Pos (30) |
SC_T::PINCTL: SYNC Position
Definition at line 22003 of file NUC472_442.h.
| #define SC_RXTOUT_RFTM_Msk (0x1fful << SC_RXTOUT_RFTM_Pos) |
SC_T::RXTOUT: RFTM Mask
Definition at line 21845 of file NUC472_442.h.
| #define SC_RXTOUT_RFTM_Pos (0) |
SC_T::RXTOUT: RFTM Position
Definition at line 21844 of file NUC472_442.h.
| #define SC_STATUS_BEF_Msk (0x1ul << SC_STATUS_BEF_Pos) |
SC_T::STATUS: BEF Mask
Definition at line 21935 of file NUC472_442.h.
| #define SC_STATUS_BEF_Pos (6) |
SC_T::STATUS: BEF Position
Definition at line 21934 of file NUC472_442.h.
| #define SC_STATUS_CDPINSTS_Msk (0x1ul << SC_STATUS_CDPINSTS_Pos) |
SC_T::STATUS: CDPINSTS Mask
Definition at line 21953 of file NUC472_442.h.
| #define SC_STATUS_CDPINSTS_Pos (13) |
SC_T::STATUS: CDPINSTS Position
Definition at line 21952 of file NUC472_442.h.
| #define SC_STATUS_CINSERT_Msk (0x1ul << SC_STATUS_CINSERT_Pos) |
SC_T::STATUS: CINSERT Mask
Definition at line 21950 of file NUC472_442.h.
| #define SC_STATUS_CINSERT_Pos (12) |
SC_T::STATUS: CINSERT Position
Definition at line 21949 of file NUC472_442.h.
| #define SC_STATUS_CREMOVE_Msk (0x1ul << SC_STATUS_CREMOVE_Pos) |
SC_T::STATUS: CREMOVE Mask
Definition at line 21947 of file NUC472_442.h.
| #define SC_STATUS_CREMOVE_Pos (11) |
SC_T::STATUS: CREMOVE Position
Definition at line 21946 of file NUC472_442.h.
| #define SC_STATUS_FEF_Msk (0x1ul << SC_STATUS_FEF_Pos) |
SC_T::STATUS: FEF Mask
Definition at line 21932 of file NUC472_442.h.
| #define SC_STATUS_FEF_Pos (5) |
SC_T::STATUS: FEF Position
Definition at line 21931 of file NUC472_442.h.
| #define SC_STATUS_PEF_Msk (0x1ul << SC_STATUS_PEF_Pos) |
SC_T::STATUS: PEF Mask
Definition at line 21929 of file NUC472_442.h.
| #define SC_STATUS_PEF_Pos (4) |
SC_T::STATUS: PEF Position
Definition at line 21928 of file NUC472_442.h.
| #define SC_STATUS_RXACT_Msk (0x1ul << SC_STATUS_RXACT_Pos) |
SC_T::STATUS: RXACT Mask
Definition at line 21965 of file NUC472_442.h.
| #define SC_STATUS_RXACT_Pos (23) |
SC_T::STATUS: RXACT Position
Definition at line 21964 of file NUC472_442.h.
| #define SC_STATUS_RXEMPTY_Msk (0x1ul << SC_STATUS_RXEMPTY_Pos) |
SC_T::STATUS: RXEMPTY Mask
Definition at line 21923 of file NUC472_442.h.
| #define SC_STATUS_RXEMPTY_Pos (1) |
SC_T::STATUS: RXEMPTY Position
Definition at line 21922 of file NUC472_442.h.
| #define SC_STATUS_RXFULL_Msk (0x1ul << SC_STATUS_RXFULL_Pos) |
SC_T::STATUS: RXFULL Mask
Definition at line 21926 of file NUC472_442.h.
| #define SC_STATUS_RXFULL_Pos (2) |
SC_T::STATUS: RXFULL Position
Definition at line 21925 of file NUC472_442.h.
| #define SC_STATUS_RXOV_Msk (0x1ul << SC_STATUS_RXOV_Pos) |
SC_T::STATUS: RXOV Mask
Definition at line 21920 of file NUC472_442.h.
| #define SC_STATUS_RXOV_Pos (0) |
SC_T::STATUS: RXOV Position
Definition at line 21919 of file NUC472_442.h.
| #define SC_STATUS_RXOVERR_Msk (0x1ul << SC_STATUS_RXOVERR_Pos) |
SC_T::STATUS: RXOVERR Mask
Definition at line 21962 of file NUC472_442.h.
| #define SC_STATUS_RXOVERR_Pos (22) |
SC_T::STATUS: RXOVERR Position
Definition at line 21961 of file NUC472_442.h.
| #define SC_STATUS_RXPOINT_Msk (0x3ul << SC_STATUS_RXPOINT_Pos) |
SC_T::STATUS: RXPOINT Mask
Definition at line 21956 of file NUC472_442.h.
| #define SC_STATUS_RXPOINT_Pos (16) |
SC_T::STATUS: RXPOINT Position
Definition at line 21955 of file NUC472_442.h.
| #define SC_STATUS_RXRERR_Msk (0x1ul << SC_STATUS_RXRERR_Pos) |
SC_T::STATUS: RXRERR Mask
Definition at line 21959 of file NUC472_442.h.
| #define SC_STATUS_RXRERR_Pos (21) |
SC_T::STATUS: RXRERR Position
Definition at line 21958 of file NUC472_442.h.
| #define SC_STATUS_TXACT_Msk (0x1ul << SC_STATUS_TXACT_Pos) |
SC_T::STATUS: TXACT Mask
Definition at line 21977 of file NUC472_442.h.
| #define SC_STATUS_TXACT_Pos (31) |
SC_T::STATUS: TXACT Position
Definition at line 21976 of file NUC472_442.h.
| #define SC_STATUS_TXEMPTY_Msk (0x1ul << SC_STATUS_TXEMPTY_Pos) |
SC_T::STATUS: TXEMPTY Mask
Definition at line 21941 of file NUC472_442.h.
| #define SC_STATUS_TXEMPTY_Pos (9) |
SC_T::STATUS: TXEMPTY Position
Definition at line 21940 of file NUC472_442.h.
| #define SC_STATUS_TXFULL_Msk (0x1ul << SC_STATUS_TXFULL_Pos) |
SC_T::STATUS: TXFULL Mask
Definition at line 21944 of file NUC472_442.h.
| #define SC_STATUS_TXFULL_Pos (10) |
SC_T::STATUS: TXFULL Position
Definition at line 21943 of file NUC472_442.h.
| #define SC_STATUS_TXOV_Msk (0x1ul << SC_STATUS_TXOV_Pos) |
SC_T::STATUS: TXOV Mask
Definition at line 21938 of file NUC472_442.h.
| #define SC_STATUS_TXOV_Pos (8) |
SC_T::STATUS: TXOV Position
Definition at line 21937 of file NUC472_442.h.
| #define SC_STATUS_TXOVERR_Msk (0x1ul << SC_STATUS_TXOVERR_Pos) |
SC_T::STATUS: TXOVERR Mask
Definition at line 21974 of file NUC472_442.h.
| #define SC_STATUS_TXOVERR_Pos (30) |
SC_T::STATUS: TXOVERR Position
Definition at line 21973 of file NUC472_442.h.
| #define SC_STATUS_TXPOINT_Msk (0x3ul << SC_STATUS_TXPOINT_Pos) |
SC_T::STATUS: TXPOINT Mask
Definition at line 21968 of file NUC472_442.h.
| #define SC_STATUS_TXPOINT_Pos (24) |
SC_T::STATUS: TXPOINT Position
Definition at line 21967 of file NUC472_442.h.
| #define SC_STATUS_TXRERR_Msk (0x1ul << SC_STATUS_TXRERR_Pos) |
SC_T::STATUS: TXRERR Mask
Definition at line 21971 of file NUC472_442.h.
| #define SC_STATUS_TXRERR_Pos (29) |
SC_T::STATUS: TXRERR Position
Definition at line 21970 of file NUC472_442.h.
| #define SC_TMRCTL0_CNT_Msk (0xfffffful << SC_TMRCTL0_CNT_Pos) |
SC_T::TMRCTL0: CNT Mask
Definition at line 22007 of file NUC472_442.h.
| #define SC_TMRCTL0_CNT_Pos (0) |
SC_T::TMRCTL0: CNT Position
Definition at line 22006 of file NUC472_442.h.
| #define SC_TMRCTL0_OPMODE_Msk (0xful << SC_TMRCTL0_OPMODE_Pos) |
SC_T::TMRCTL0: OPMODE Mask
Definition at line 22010 of file NUC472_442.h.
| #define SC_TMRCTL0_OPMODE_Pos (24) |
SC_T::TMRCTL0: OPMODE Position
Definition at line 22009 of file NUC472_442.h.
| #define SC_TMRCTL1_CNT_Msk (0xfful << SC_TMRCTL1_CNT_Pos) |
SC_T::TMRCTL1: CNT Mask
Definition at line 22013 of file NUC472_442.h.
| #define SC_TMRCTL1_CNT_Pos (0) |
SC_T::TMRCTL1: CNT Position
Definition at line 22012 of file NUC472_442.h.
| #define SC_TMRCTL1_OPMODE_Msk (0xful << SC_TMRCTL1_OPMODE_Pos) |
SC_T::TMRCTL1: OPMODE Mask
Definition at line 22016 of file NUC472_442.h.
| #define SC_TMRCTL1_OPMODE_Pos (24) |
SC_T::TMRCTL1: OPMODE Position
Definition at line 22015 of file NUC472_442.h.
| #define SC_TMRCTL2_CNT_Msk (0xfful << SC_TMRCTL2_CNT_Pos) |
SC_T::TMRCTL2: CNT Mask
Definition at line 22019 of file NUC472_442.h.
| #define SC_TMRCTL2_CNT_Pos (0) |
SC_T::TMRCTL2: CNT Position
Definition at line 22018 of file NUC472_442.h.
| #define SC_TMRCTL2_OPMODE_Msk (0xful << SC_TMRCTL2_OPMODE_Pos) |
SC_T::TMRCTL2: OPMODE Mask
Definition at line 22022 of file NUC472_442.h.
| #define SC_TMRCTL2_OPMODE_Pos (24) |
SC_T::TMRCTL2: OPMODE Position
Definition at line 22021 of file NUC472_442.h.
| #define SC_TMRDAT0_TDR0_Msk (0xfffffful << SC_TMRDAT0_TDR0_Pos) |
SC_T::TMRDAT0: TDR0 Mask
Definition at line 22037 of file NUC472_442.h.
| #define SC_TMRDAT0_TDR0_Pos (0) |
SC_T::TMRDAT0: TDR0 Position
Definition at line 22036 of file NUC472_442.h.
| #define SC_TMRDAT1_2_TDR1_Msk (0xfful << SC_TMRDAT1_2_TDR1_Pos) |
SC_T::TMRDAT1_2: TDR1 Mask
Definition at line 22040 of file NUC472_442.h.
| #define SC_TMRDAT1_2_TDR1_Pos (0) |
SC_T::TMRDAT1_2: TDR1 Position
Definition at line 22039 of file NUC472_442.h.
| #define SC_TMRDAT1_2_TDR2_Msk (0xfful << SC_TMRDAT1_2_TDR2_Pos) |
SC_T::TMRDAT1_2: TDR2 Mask
Definition at line 22043 of file NUC472_442.h.
| #define SC_TMRDAT1_2_TDR2_Pos (8) |
SC_T::TMRDAT1_2: TDR2 Position
Definition at line 22042 of file NUC472_442.h.
| #define SC_UARTCTL_OPE_Msk (0x1ul << SC_UARTCTL_OPE_Pos) |
SC_T::UARTCTL: OPE Mask
Definition at line 22034 of file NUC472_442.h.
| #define SC_UARTCTL_OPE_Pos (7) |
SC_T::UARTCTL: OPE Position
Definition at line 22033 of file NUC472_442.h.
| #define SC_UARTCTL_PBOFF_Msk (0x1ul << SC_UARTCTL_PBOFF_Pos) |
SC_T::UARTCTL: PBOFF Mask
Definition at line 22031 of file NUC472_442.h.
| #define SC_UARTCTL_PBOFF_Pos (6) |
SC_T::UARTCTL: PBOFF Position
Definition at line 22030 of file NUC472_442.h.
| #define SC_UARTCTL_UARTEN_Msk (0x1ul << SC_UARTCTL_UARTEN_Pos) |
SC_T::UARTCTL: UARTEN Mask
Definition at line 22025 of file NUC472_442.h.
| #define SC_UARTCTL_UARTEN_Pos (0) |
SC_T::UARTCTL: UARTEN Position
Definition at line 22024 of file NUC472_442.h.
| #define SC_UARTCTL_WLS_Msk (0x3ul << SC_UARTCTL_WLS_Pos) |
SC_T::UARTCTL: WLS Mask
Definition at line 22028 of file NUC472_442.h.
| #define SC_UARTCTL_WLS_Pos (4) |
SC_T::UARTCTL: WLS Position
Definition at line 22027 of file NUC472_442.h.
| #define SDH_BLEN_BLKLEN_Msk (0x7fful << SDH_BLEN_BLKLEN_Pos) |
SDH_T::BLEN: BLKLEN Mask
Definition at line 22679 of file NUC472_442.h.
| #define SDH_BLEN_BLKLEN_Pos (0) |
SDH_T::BLEN: BLKLEN Position
Definition at line 22678 of file NUC472_442.h.
| #define SDH_CMDARG_ARGUMENT_Msk (0xfffffffful << SDH_CMDARG_ARGUMENT_Pos) |
SDH_T::CMDARG: ARGUMENT Mask
Definition at line 22592 of file NUC472_442.h.
| #define SDH_CMDARG_ARGUMENT_Pos (0) |
SDH_T::CMDARG: ARGUMENT Position
Definition at line 22591 of file NUC472_442.h.
| #define SDH_CTL_BLKCNT_Msk (0xfful << SDH_CTL_BLKCNT_Pos) |
SDH_T::CTL: BLKCNT Mask
Definition at line 22580 of file NUC472_442.h.
| #define SDH_CTL_BLKCNT_Pos (16) |
SDH_T::CTL: BLKCNT Position
Definition at line 22579 of file NUC472_442.h.
| #define SDH_CTL_CLK74OEN_Msk (0x1ul << SDH_CTL_CLK74OEN_Pos) |
SDH_T::CTL: CLK74OEN Mask
Definition at line 22562 of file NUC472_442.h.
| #define SDH_CTL_CLK74OEN_Pos (5) |
SDH_T::CTL: CLK74OEN Position
Definition at line 22561 of file NUC472_442.h.
| #define SDH_CTL_CLK8OEN_Msk (0x1ul << SDH_CTL_CLK8OEN_Pos) |
SDH_T::CTL: CLK8OEN Mask
Definition at line 22565 of file NUC472_442.h.
| #define SDH_CTL_CLK8OEN_Pos (6) |
SDH_T::CTL: CLK8OEN Position
Definition at line 22564 of file NUC472_442.h.
| #define SDH_CTL_CLKKEEP0_Msk (0x1ul << SDH_CTL_CLKKEEP0_Pos) |
SDH_T::CTL: CLKKEEP0 Mask
Definition at line 22568 of file NUC472_442.h.
| #define SDH_CTL_CLKKEEP0_Pos (7) |
SDH_T::CTL: CLKKEEP0 Position
Definition at line 22567 of file NUC472_442.h.
| #define SDH_CTL_CLKKEEP1_Msk (0x1ul << SDH_CTL_CLKKEEP1_Pos) |
SDH_T::CTL: CLKKEEP1 Mask
Definition at line 22589 of file NUC472_442.h.
| #define SDH_CTL_CLKKEEP1_Pos (31) |
SDH_T::CTL: CLKKEEP1 Position
Definition at line 22588 of file NUC472_442.h.
| #define SDH_CTL_CMDCODE_Msk (0x3ful << SDH_CTL_CMDCODE_Pos) |
SDH_T::CTL: CMDCODE Mask
Definition at line 22571 of file NUC472_442.h.
| #define SDH_CTL_CMDCODE_Pos (8) |
SDH_T::CTL: CMDCODE Position
Definition at line 22570 of file NUC472_442.h.
| #define SDH_CTL_COEN_Msk (0x1ul << SDH_CTL_COEN_Pos) |
SDH_T::CTL: COEN Mask
Definition at line 22547 of file NUC472_442.h.
| #define SDH_CTL_COEN_Pos (0) |
SDH_T::CTL: COEN Position
Definition at line 22546 of file NUC472_442.h.
| #define SDH_CTL_CTLRST_Msk (0x1ul << SDH_CTL_CTLRST_Pos) |
SDH_T::CTL: CTLRST Mask
Definition at line 22574 of file NUC472_442.h.
| #define SDH_CTL_CTLRST_Pos (14) |
SDH_T::CTL: CTLRST Position
Definition at line 22573 of file NUC472_442.h.
| #define SDH_CTL_DBW_Msk (0x1ul << SDH_CTL_DBW_Pos) |
SDH_T::CTL: DBW Mask
Definition at line 22577 of file NUC472_442.h.
| #define SDH_CTL_DBW_Pos (15) |
SDH_T::CTL: DBW Position
Definition at line 22576 of file NUC472_442.h.
| #define SDH_CTL_DIEN_Msk (0x1ul << SDH_CTL_DIEN_Pos) |
SDH_T::CTL: DIEN Mask
Definition at line 22553 of file NUC472_442.h.
| #define SDH_CTL_DIEN_Pos (2) |
SDH_T::CTL: DIEN Position
Definition at line 22552 of file NUC472_442.h.
| #define SDH_CTL_DOEN_Msk (0x1ul << SDH_CTL_DOEN_Pos) |
SDH_T::CTL: DOEN Mask
Definition at line 22556 of file NUC472_442.h.
| #define SDH_CTL_DOEN_Pos (3) |
SDH_T::CTL: DOEN Position
Definition at line 22555 of file NUC472_442.h.
| #define SDH_CTL_R2EN_Msk (0x1ul << SDH_CTL_R2EN_Pos) |
SDH_T::CTL: R2EN Mask
Definition at line 22559 of file NUC472_442.h.
| #define SDH_CTL_R2EN_Pos (4) |
SDH_T::CTL: R2EN Position
Definition at line 22558 of file NUC472_442.h.
| #define SDH_CTL_RIEN_Msk (0x1ul << SDH_CTL_RIEN_Pos) |
SDH_T::CTL: RIEN Mask
Definition at line 22550 of file NUC472_442.h.
| #define SDH_CTL_RIEN_Pos (1) |
SDH_T::CTL: RIEN Position
Definition at line 22549 of file NUC472_442.h.
| #define SDH_CTL_SDNWR_Msk (0xful << SDH_CTL_SDNWR_Pos) |
SDH_T::CTL: SDNWR Mask
Definition at line 22583 of file NUC472_442.h.
| #define SDH_CTL_SDNWR_Pos (24) |
SDH_T::CTL: SDNWR Position
Definition at line 22582 of file NUC472_442.h.
| #define SDH_CTL_SDPORT_Msk (0x3ul << SDH_CTL_SDPORT_Pos) |
SDH_T::CTL: SDPORT Mask
Definition at line 22586 of file NUC472_442.h.
| #define SDH_CTL_SDPORT_Pos (29) |
SDH_T::CTL: SDPORT Position
Definition at line 22585 of file NUC472_442.h.
| #define SDH_DMABCNT_BCNT_Msk (0x3fffffful << SDH_DMABCNT_BCNT_Pos) |
SDH_T::DMABCNT: BCNT Mask
Definition at line 22520 of file NUC472_442.h.
| #define SDH_DMABCNT_BCNT_Pos (0) |
SDH_T::DMABCNT: BCNT Position
Definition at line 22519 of file NUC472_442.h.
| #define SDH_DMACTL_DMABUSY_Msk (0x1ul << SDH_DMACTL_DMABUSY_Pos) |
SDH_T::DMACTL: DMABUSY Mask
Definition at line 22511 of file NUC472_442.h.
| #define SDH_DMACTL_DMABUSY_Pos (9) |
SDH_T::DMACTL: DMABUSY Position
Definition at line 22510 of file NUC472_442.h.
| #define SDH_DMACTL_DMAEN_Msk (0x1ul << SDH_DMACTL_DMAEN_Pos) |
SDH_T::DMACTL: DMAEN Mask
Definition at line 22502 of file NUC472_442.h.
| #define SDH_DMACTL_DMAEN_Pos (0) |
@addtogroup SDH_CONST SDH Bit Field Definition Constant Definitions for SDH Controller
SDH_T::DMACTL: DMAEN Position
Definition at line 22501 of file NUC472_442.h.
| #define SDH_DMACTL_DMARST_Msk (0x1ul << SDH_DMACTL_DMARST_Pos) |
SDH_T::DMACTL: DMARST Mask
Definition at line 22505 of file NUC472_442.h.
| #define SDH_DMACTL_DMARST_Pos (1) |
SDH_T::DMACTL: DMARST Position
Definition at line 22504 of file NUC472_442.h.
| #define SDH_DMACTL_SGEN_Msk (0x1ul << SDH_DMACTL_SGEN_Pos) |
SDH_T::DMACTL: SGEN Mask
Definition at line 22508 of file NUC472_442.h.
| #define SDH_DMACTL_SGEN_Pos (3) |
SDH_T::DMACTL: SGEN Position
Definition at line 22507 of file NUC472_442.h.
| #define SDH_DMAINTEN_ABORTIEN_Msk (0x1ul << SDH_DMAINTEN_ABORTIEN_Pos) |
SDH_T::DMAINTEN: ABORTIEN Mask
Definition at line 22523 of file NUC472_442.h.
| #define SDH_DMAINTEN_ABORTIEN_Pos (0) |
SDH_T::DMAINTEN: ABORTIEN Position
Definition at line 22522 of file NUC472_442.h.
| #define SDH_DMAINTEN_WEOTIEN_Msk (0x1ul << SDH_DMAINTEN_WEOTIEN_Pos) |
SDH_T::DMAINTEN: WEOTIEN Mask
Definition at line 22526 of file NUC472_442.h.
| #define SDH_DMAINTEN_WEOTIEN_Pos (1) |
SDH_T::DMAINTEN: WEOTIEN Position
Definition at line 22525 of file NUC472_442.h.
| #define SDH_DMAINTSTS_ABORTIF_Msk (0x1ul << SDH_DMAINTSTS_ABORTIF_Pos) |
SDH_T::DMAINTSTS: ABORTIF Mask
Definition at line 22529 of file NUC472_442.h.
| #define SDH_DMAINTSTS_ABORTIF_Pos (0) |
SDH_T::DMAINTSTS: ABORTIF Position
Definition at line 22528 of file NUC472_442.h.
| #define SDH_DMAINTSTS_WEOTIF_Msk (0x1ul << SDH_DMAINTSTS_WEOTIF_Pos) |
SDH_T::DMAINTSTS: WEOTIF Mask
Definition at line 22532 of file NUC472_442.h.
| #define SDH_DMAINTSTS_WEOTIF_Pos (1) |
SDH_T::DMAINTSTS: WEOTIF Position
Definition at line 22531 of file NUC472_442.h.
| #define SDH_DMASA_DMASA_Msk (0x7ffffffful << SDH_DMASA_DMASA_Pos) |
SDH_T::DMASA: DMASA Mask
Definition at line 22517 of file NUC472_442.h.
| #define SDH_DMASA_DMASA_Pos (1) |
SDH_T::DMASA: DMASA Position
Definition at line 22516 of file NUC472_442.h.
| #define SDH_DMASA_ORDER_Msk (0x1ul << SDH_DMASA_ORDER_Pos) |
SDH_T::DMASA: ORDER Mask
Definition at line 22514 of file NUC472_442.h.
| #define SDH_DMASA_ORDER_Pos (0) |
SDH_T::DMASA: ORDER Position
Definition at line 22513 of file NUC472_442.h.
| #define SDH_GCTL_GCTLRST_Msk (0x1ul << SDH_GCTL_GCTLRST_Pos) |
SDH_T::GCTL: GCTLRST Mask
Definition at line 22535 of file NUC472_442.h.
| #define SDH_GCTL_GCTLRST_Pos (0) |
SDH_T::GCTL: GCTLRST Position
Definition at line 22534 of file NUC472_442.h.
| #define SDH_GCTL_SDEN_Msk (0x1ul << SDH_GCTL_SDEN_Pos) |
SDH_T::GCTL: SDEN Mask
Definition at line 22538 of file NUC472_442.h.
| #define SDH_GCTL_SDEN_Pos (1) |
SDH_T::GCTL: SDEN Position
Definition at line 22537 of file NUC472_442.h.
| #define SDH_GINTEN_DTAIEN_Msk (0x1ul << SDH_GINTEN_DTAIEN_Pos) |
SDH_T::GINTEN: DTAIEN Mask
Definition at line 22541 of file NUC472_442.h.
| #define SDH_GINTEN_DTAIEN_Pos (0) |
SDH_T::GINTEN: DTAIEN Position
Definition at line 22540 of file NUC472_442.h.
| #define SDH_GINTSTS_DTAIF_Msk (0x1ul << SDH_GINTSTS_DTAIF_Pos) |
SDH_T::GINTSTS: DTAIF Mask
Definition at line 22544 of file NUC472_442.h.
| #define SDH_GINTSTS_DTAIF_Pos (0) |
SDH_T::GINTSTS: DTAIF Position
Definition at line 22543 of file NUC472_442.h.
| #define SDH_INTEN_BLKDIEN_Msk (0x1ul << SDH_INTEN_BLKDIEN_Pos) |
SDH_T::INTEN: BLKDIEN Mask
Definition at line 22595 of file NUC472_442.h.
| #define SDH_INTEN_BLKDIEN_Pos (0) |
SDH_T::INTEN: BLKDIEN Position
Definition at line 22594 of file NUC472_442.h.
| #define SDH_INTEN_CDIEN0_Msk (0x1ul << SDH_INTEN_CDIEN0_Pos) |
SDH_T::INTEN: CDIEN0 Mask
Definition at line 22601 of file NUC472_442.h.
| #define SDH_INTEN_CDIEN0_Pos (8) |
SDH_T::INTEN: CDIEN0 Position
Definition at line 22600 of file NUC472_442.h.
| #define SDH_INTEN_CDIEN1_Msk (0x1ul << SDH_INTEN_CDIEN1_Pos) |
SDH_T::INTEN: CDIEN1 Mask
Definition at line 22604 of file NUC472_442.h.
| #define SDH_INTEN_CDIEN1_Pos (9) |
SDH_T::INTEN: CDIEN1 Position
Definition at line 22603 of file NUC472_442.h.
| #define SDH_INTEN_CDSRC0_Msk (0x1ul << SDH_INTEN_CDSRC0_Pos) |
SDH_T::INTEN: CDSRC0 Mask
Definition at line 22622 of file NUC472_442.h.
| #define SDH_INTEN_CDSRC0_Pos (30) |
SDH_T::INTEN: CDSRC0 Position
Definition at line 22621 of file NUC472_442.h.
| #define SDH_INTEN_CDSRC1_Msk (0x1ul << SDH_INTEN_CDSRC1_Pos) |
SDH_T::INTEN: CDSRC1 Mask
Definition at line 22625 of file NUC472_442.h.
| #define SDH_INTEN_CDSRC1_Pos (31) |
SDH_T::INTEN: CDSRC1 Position
Definition at line 22624 of file NUC472_442.h.
| #define SDH_INTEN_CRCIEN_Msk (0x1ul << SDH_INTEN_CRCIEN_Pos) |
SDH_T::INTEN: CRCIEN Mask
Definition at line 22598 of file NUC472_442.h.
| #define SDH_INTEN_CRCIEN_Pos (1) |
SDH_T::INTEN: CRCIEN Position
Definition at line 22597 of file NUC472_442.h.
| #define SDH_INTEN_DITOIEN_Msk (0x1ul << SDH_INTEN_DITOIEN_Pos) |
SDH_T::INTEN: DITOIEN Mask
Definition at line 22616 of file NUC472_442.h.
| #define SDH_INTEN_DITOIEN_Pos (13) |
SDH_T::INTEN: DITOIEN Position
Definition at line 22615 of file NUC472_442.h.
| #define SDH_INTEN_RTOIEN_Msk (0x1ul << SDH_INTEN_RTOIEN_Pos) |
SDH_T::INTEN: RTOIEN Mask
Definition at line 22613 of file NUC472_442.h.
| #define SDH_INTEN_RTOIEN_Pos (12) |
SDH_T::INTEN: RTOIEN Position
Definition at line 22612 of file NUC472_442.h.
| #define SDH_INTEN_SDHOST0IEN_Msk (0x1ul << SDH_INTEN_SDHOST0IEN_Pos) |
SDH_T::INTSTS: SDHOST0IEN Mask
Definition at line 22607 of file NUC472_442.h.
| #define SDH_INTEN_SDHOST0IEN_Pos (10) |
SDH_T::INTSTS: SDHOST0IEN Position
Definition at line 22606 of file NUC472_442.h.
| #define SDH_INTEN_SDHOST1IEN_Msk (0x1ul << SDH_INTEN_SDHOST1IEN_Pos) |
SDH_T::INTSTS: SDHOST1IEN Mask
Definition at line 22610 of file NUC472_442.h.
| #define SDH_INTEN_SDHOST1IEN_Pos (11) |
SDH_T::INTSTS: SDHOST1IEN Position
Definition at line 22609 of file NUC472_442.h.
| #define SDH_INTEN_WKIEN_Msk (0x1ul << SDH_INTEN_WKIEN_Pos) |
SDH_T::INTEN: WKIEN Mask
Definition at line 22619 of file NUC472_442.h.
| #define SDH_INTEN_WKIEN_Pos (14) |
SDH_T::INTEN: WKIEN Position
Definition at line 22618 of file NUC472_442.h.
| #define SDH_INTSTS_BLKDIF_Msk (0x1ul << SDH_INTSTS_BLKDIF_Pos) |
SDH_T::INTSTS: BLKDIF Mask
Definition at line 22628 of file NUC472_442.h.
| #define SDH_INTSTS_BLKDIF_Pos (0) |
SDH_T::INTSTS: BLKDIF Position
Definition at line 22627 of file NUC472_442.h.
| #define SDH_INTSTS_CDIF0_Msk (0x1ul << SDH_INTSTS_CDIF0_Pos) |
SDH_T::INTSTS: CDIF0 Mask
Definition at line 22646 of file NUC472_442.h.
| #define SDH_INTSTS_CDIF0_Pos (8) |
SDH_T::INTSTS: CDIF0 Position
Definition at line 22645 of file NUC472_442.h.
| #define SDH_INTSTS_CDIF1_Msk (0x1ul << SDH_INTSTS_CDIF1_Pos) |
SDH_T::INTSTS: CDIF1 Mask
Definition at line 22649 of file NUC472_442.h.
| #define SDH_INTSTS_CDIF1_Pos (9) |
SDH_T::INTSTS: CDIF1 Position
Definition at line 22648 of file NUC472_442.h.
| #define SDH_INTSTS_CDSTS0_Msk (0x1ul << SDH_INTSTS_CDSTS0_Pos) |
SDH_T::INTSTS: CDSTS0 Mask
Definition at line 22664 of file NUC472_442.h.
| #define SDH_INTSTS_CDSTS0_Pos (16) |
SDH_T::INTSTS: CDSTS0 Position
Definition at line 22663 of file NUC472_442.h.
| #define SDH_INTSTS_CDSTS1_Msk (0x1ul << SDH_INTSTS_CDSTS1_Pos) |
SDH_T::INTSTS: CDSTS1 Mask
Definition at line 22667 of file NUC472_442.h.
| #define SDH_INTSTS_CDSTS1_Pos (17) |
SDH_T::INTSTS: CDSTS1 Position
Definition at line 22666 of file NUC472_442.h.
| #define SDH_INTSTS_CRC16_Msk (0x1ul << SDH_INTSTS_CRC16_Pos) |
SDH_T::INTSTS: CRC16 Mask
Definition at line 22637 of file NUC472_442.h.
| #define SDH_INTSTS_CRC16_Pos (3) |
SDH_T::INTSTS: CRC16 Position
Definition at line 22636 of file NUC472_442.h.
| #define SDH_INTSTS_CRC7_Msk (0x1ul << SDH_INTSTS_CRC7_Pos) |
SDH_T::INTSTS: CRC7 Mask
Definition at line 22634 of file NUC472_442.h.
| #define SDH_INTSTS_CRC7_Pos (2) |
SDH_T::INTSTS: CRC7 Position
Definition at line 22633 of file NUC472_442.h.
| #define SDH_INTSTS_CRCIF_Msk (0x1ul << SDH_INTSTS_CRCIF_Pos) |
SDH_T::INTSTS: CRCIF Mask
Definition at line 22631 of file NUC472_442.h.
| #define SDH_INTSTS_CRCIF_Pos (1) |
SDH_T::INTSTS: CRCIF Position
Definition at line 22630 of file NUC472_442.h.
| #define SDH_INTSTS_CRCSTS_Msk (0x7ul << SDH_INTSTS_CRCSTS_Pos) |
SDH_T::INTSTS: CRCSTS Mask
Definition at line 22640 of file NUC472_442.h.
| #define SDH_INTSTS_CRCSTS_Pos (4) |
SDH_T::INTSTS: CRCSTS Position
Definition at line 22639 of file NUC472_442.h.
| #define SDH_INTSTS_DAT0STS_Msk (0x1ul << SDH_INTSTS_DAT0STS_Pos) |
SDH_T::INTSTS: DAT0STS Mask
Definition at line 22643 of file NUC472_442.h.
| #define SDH_INTSTS_DAT0STS_Pos (7) |
SDH_T::INTSTS: DAT0STS Position
Definition at line 22642 of file NUC472_442.h.
| #define SDH_INTSTS_DAT1STS_Msk (0x1ul << SDH_INTSTS_DAT1STS_Pos) |
SDH_T::INTSTS: DAT1STS Mask
Definition at line 22670 of file NUC472_442.h.
| #define SDH_INTSTS_DAT1STS_Pos (18) |
SDH_T::INTSTS: DAT1STS Position
Definition at line 22669 of file NUC472_442.h.
| #define SDH_INTSTS_DINTOIF_Msk (0x1ul << SDH_INTSTS_DINTOIF_Pos) |
SDH_T::INTSTS: DINTOIF Mask
Definition at line 22661 of file NUC472_442.h.
| #define SDH_INTSTS_DINTOIF_Pos (13) |
SDH_T::INTSTS: DINTOIF Position
Definition at line 22660 of file NUC472_442.h.
| #define SDH_INTSTS_RTOIF_Msk (0x1ul << SDH_INTSTS_RTOIF_Pos) |
SDH_T::INTSTS: RTOIF Mask
Definition at line 22658 of file NUC472_442.h.
| #define SDH_INTSTS_RTOIF_Pos (12) |
SDH_T::INTSTS: RTOIF Position
Definition at line 22657 of file NUC472_442.h.
| #define SDH_INTSTS_SDHOST0IF_Msk (0x1ul << SDH_INTSTS_SDHOST0IF_Pos) |
SDH_T::INTSTS: SDHOST0IF Mask
Definition at line 22652 of file NUC472_442.h.
| #define SDH_INTSTS_SDHOST0IF_Pos (10) |
SDH_T::INTSTS: SDHOST0IF Position
Definition at line 22651 of file NUC472_442.h.
| #define SDH_INTSTS_SDHOST1IF_Msk (0x1ul << SDH_INTSTS_SDHOST1IF_Pos) |
SDH_T::INTSTS: SDHOST1IF Mask
Definition at line 22655 of file NUC472_442.h.
| #define SDH_INTSTS_SDHOST1IF_Pos (11) |
SDH_T::INTSTS: SDHOST1IF Position
Definition at line 22654 of file NUC472_442.h.
| #define SDH_RESP0_RESPTK0_Msk (0xfffffffful << SDH_RESP0_RESPTK0_Pos) |
SDH_T::RESP0: RESPTK0 Mask
Definition at line 22673 of file NUC472_442.h.
| #define SDH_RESP0_RESPTK0_Pos (0) |
SDH_T::RESP0: RESPTK0 Position
Definition at line 22672 of file NUC472_442.h.
| #define SDH_RESP1_RESPTK1_Msk (0xfful << SDH_RESP1_RESPTK1_Pos) |
SDH_T::RESP1: RESPTK1 Mask
Definition at line 22676 of file NUC472_442.h.
| #define SDH_RESP1_RESPTK1_Pos (0) |
SDH_T::RESP1: RESPTK1 Position
Definition at line 22675 of file NUC472_442.h.
| #define SDH_TOUT_TOUT_Msk (0xfffffful << SDH_TOUT_TOUT_Pos) |
SDH_T::TOUT: TOUT Mask
Definition at line 22682 of file NUC472_442.h.
| #define SDH_TOUT_TOUT_Pos (0) |
SDH_T::TOUT: TOUT Position
Definition at line 22681 of file NUC472_442.h.
| #define SPI_CLKDIV_DIVIDER_Msk (0xfful << SPI_CLKDIV_DIVIDER_Pos) |
SPI_T::CLKDIV: DIVIDER Mask
Definition at line 23109 of file NUC472_442.h.
| #define SPI_CLKDIV_DIVIDER_Pos (0) |
SPI_T::CLKDIV: DIVIDER Position
Definition at line 23108 of file NUC472_442.h.
| #define SPI_CTL_CLKPOL_Msk (0x1ul << SPI_CTL_CLKPOL_Pos) |
SPI_T::CTL: CLKPOL Mask
Definition at line 23076 of file NUC472_442.h.
| #define SPI_CTL_CLKPOL_Pos (3) |
SPI_T::CTL: CLKPOL Position
Definition at line 23075 of file NUC472_442.h.
| #define SPI_CTL_DUALIOEN_Msk (0x1ul << SPI_CTL_DUALIOEN_Pos) |
SPI_T::CTL: DUALIOEN Mask
Definition at line 23103 of file NUC472_442.h.
| #define SPI_CTL_DUALIOEN_Pos (21) |
SPI_T::CTL: DUALIOEN Position
Definition at line 23102 of file NUC472_442.h.
| #define SPI_CTL_DWIDTH_Msk (0x1ful << SPI_CTL_DWIDTH_Pos) |
SPI_T::CTL: DWIDTH Mask
Definition at line 23082 of file NUC472_442.h.
| #define SPI_CTL_DWIDTH_Pos (8) |
SPI_T::CTL: DWIDTH Position
Definition at line 23081 of file NUC472_442.h.
| #define SPI_CTL_LSB_Msk (0x1ul << SPI_CTL_LSB_Pos) |
SPI_T::CTL: LSB Mask
Definition at line 23085 of file NUC472_442.h.
| #define SPI_CTL_LSB_Pos (13) |
SPI_T::CTL: LSB Position
Definition at line 23084 of file NUC472_442.h.
| #define SPI_CTL_QDIODIR_Msk (0x1ul << SPI_CTL_QDIODIR_Pos) |
SPI_T::CTL: QDIODIR Mask
Definition at line 23100 of file NUC472_442.h.
| #define SPI_CTL_QDIODIR_Pos (20) |
SPI_T::CTL: QDIODIR Position
Definition at line 23099 of file NUC472_442.h.
| #define SPI_CTL_QUADIOEN_Msk (0x1ul << SPI_CTL_QUADIOEN_Pos) |
SPI_T::CTL: QUADIOEN Mask
Definition at line 23106 of file NUC472_442.h.
| #define SPI_CTL_QUADIOEN_Pos (22) |
SPI_T::CTL: QUADIOEN Position
Definition at line 23105 of file NUC472_442.h.
| #define SPI_CTL_REORDER_Msk (0x1ul << SPI_CTL_REORDER_Pos) |
SPI_T::CTL: REORDER Mask
Definition at line 23097 of file NUC472_442.h.
| #define SPI_CTL_REORDER_Pos (19) |
SPI_T::CTL: REORDER Position
Definition at line 23096 of file NUC472_442.h.
| #define SPI_CTL_RXNEG_Msk (0x1ul << SPI_CTL_RXNEG_Pos) |
SPI_T::CTL: RXNEG Mask
Definition at line 23070 of file NUC472_442.h.
| #define SPI_CTL_RXNEG_Pos (1) |
SPI_T::CTL: RXNEG Position
Definition at line 23069 of file NUC472_442.h.
| #define SPI_CTL_SLAVE_Msk (0x1ul << SPI_CTL_SLAVE_Pos) |
SPI_T::CTL: SLAVE Mask
Definition at line 23094 of file NUC472_442.h.
| #define SPI_CTL_SLAVE_Pos (18) |
SPI_T::CTL: SLAVE Position
Definition at line 23093 of file NUC472_442.h.
| #define SPI_CTL_SPIEN_Msk (0x1ul << SPI_CTL_SPIEN_Pos) |
SPI_T::CTL: SPIEN Mask
Definition at line 23067 of file NUC472_442.h.
| #define SPI_CTL_SPIEN_Pos (0) |
@addtogroup SPI_CONST SPI Bit Field Definition Constant Definitions for SPI Controller
SPI_T::CTL: SPIEN Position
Definition at line 23066 of file NUC472_442.h.
| #define SPI_CTL_SUSPITV_Msk (0xful << SPI_CTL_SUSPITV_Pos) |
SPI_T::CTL: SUSPITV Mask
Definition at line 23079 of file NUC472_442.h.
| #define SPI_CTL_SUSPITV_Pos (4) |
SPI_T::CTL: SUSPITV Position
Definition at line 23078 of file NUC472_442.h.
| #define SPI_CTL_TWOBIT_Msk (0x1ul << SPI_CTL_TWOBIT_Pos) |
SPI_T::CTL: TWOBIT Mask
Definition at line 23088 of file NUC472_442.h.
| #define SPI_CTL_TWOBIT_Pos (16) |
SPI_T::CTL: TWOBIT Position
Definition at line 23087 of file NUC472_442.h.
| #define SPI_CTL_TXNEG_Msk (0x1ul << SPI_CTL_TXNEG_Pos) |
SPI_T::CTL: TXNEG Mask
Definition at line 23073 of file NUC472_442.h.
| #define SPI_CTL_TXNEG_Pos (2) |
SPI_T::CTL: TXNEG Position
Definition at line 23072 of file NUC472_442.h.
| #define SPI_CTL_UNITIEN_Msk (0x1ul << SPI_CTL_UNITIEN_Pos) |
SPI_T::CTL: UNITIEN Mask
Definition at line 23091 of file NUC472_442.h.
| #define SPI_CTL_UNITIEN_Pos (17) |
SPI_T::CTL: UNITIEN Position
Definition at line 23090 of file NUC472_442.h.
| #define SPI_FIFOCTL_RXOVIEN_Msk (0x1ul << SPI_FIFOCTL_RXOVIEN_Pos) |
SPI_T::FIFOCTL: RXOVIEN Mask
Definition at line 23169 of file NUC472_442.h.
| #define SPI_FIFOCTL_RXOVIEN_Pos (5) |
SPI_T::FIFOCTL: RXOVIEN Position
Definition at line 23168 of file NUC472_442.h.
| #define SPI_FIFOCTL_RXRST_Msk (0x1ul << SPI_FIFOCTL_RXRST_Pos) |
SPI_T::FIFOCTL: RXRST Mask
Definition at line 23154 of file NUC472_442.h.
| #define SPI_FIFOCTL_RXRST_Pos (0) |
SPI_T::FIFOCTL: RXRST Position
Definition at line 23153 of file NUC472_442.h.
| #define SPI_FIFOCTL_RXTH_Msk (0x7ul << SPI_FIFOCTL_RXTH_Pos) |
SPI_T::FIFOCTL: RXTH Mask
Definition at line 23178 of file NUC472_442.h.
| #define SPI_FIFOCTL_RXTH_Pos (24) |
SPI_T::FIFOCTL: RXTH Position
Definition at line 23177 of file NUC472_442.h.
| #define SPI_FIFOCTL_RXTHIEN_Msk (0x1ul << SPI_FIFOCTL_RXTHIEN_Pos) |
SPI_T::FIFOCTL: RXTHIEN Mask
Definition at line 23160 of file NUC472_442.h.
| #define SPI_FIFOCTL_RXTHIEN_Pos (2) |
SPI_T::FIFOCTL: RXTHIEN Position
Definition at line 23159 of file NUC472_442.h.
| #define SPI_FIFOCTL_RXTOIEN_Msk (0x1ul << SPI_FIFOCTL_RXTOIEN_Pos) |
SPI_T::FIFOCTL: RXTOIEN Mask
Definition at line 23166 of file NUC472_442.h.
| #define SPI_FIFOCTL_RXTOIEN_Pos (4) |
SPI_T::FIFOCTL: RXTOIEN Position
Definition at line 23165 of file NUC472_442.h.
| #define SPI_FIFOCTL_TXRST_Msk (0x1ul << SPI_FIFOCTL_TXRST_Pos) |
SPI_T::FIFOCTL: TXRST Mask
Definition at line 23157 of file NUC472_442.h.
| #define SPI_FIFOCTL_TXRST_Pos (1) |
SPI_T::FIFOCTL: TXRST Position
Definition at line 23156 of file NUC472_442.h.
| #define SPI_FIFOCTL_TXTH_Msk (0x7ul << SPI_FIFOCTL_TXTH_Pos) |
SPI_T::FIFOCTL: TXTH Mask
Definition at line 23181 of file NUC472_442.h.
| #define SPI_FIFOCTL_TXTH_Pos (28) |
SPI_T::FIFOCTL: TXTH Position
Definition at line 23180 of file NUC472_442.h.
| #define SPI_FIFOCTL_TXTHIEN_Msk (0x1ul << SPI_FIFOCTL_TXTHIEN_Pos) |
SPI_T::FIFOCTL: TXTHIEN Mask
Definition at line 23163 of file NUC472_442.h.
| #define SPI_FIFOCTL_TXTHIEN_Pos (3) |
SPI_T::FIFOCTL: TXTHIEN Position
Definition at line 23162 of file NUC472_442.h.
| #define SPI_FIFOCTL_TXUFIEN_Msk (0x1ul << SPI_FIFOCTL_TXUFIEN_Pos) |
SPI_T::FIFOCTL: TXUFIEN Mask
Definition at line 23175 of file NUC472_442.h.
| #define SPI_FIFOCTL_TXUFIEN_Pos (7) |
SPI_T::FIFOCTL: TXUFIEN Position
Definition at line 23174 of file NUC472_442.h.
| #define SPI_FIFOCTL_TXUFPOL_Msk (0x1ul << SPI_FIFOCTL_TXUFPOL_Pos) |
SPI_T::FIFOCTL: TXUFPOL Mask
Definition at line 23172 of file NUC472_442.h.
| #define SPI_FIFOCTL_TXUFPOL_Pos (6) |
SPI_T::FIFOCTL: TXUFPOL Position
Definition at line 23171 of file NUC472_442.h.
| #define SPI_PDMACTL_PDMARST_Msk (0x1ul << SPI_PDMACTL_PDMARST_Pos) |
SPI_T::PDMACTL: PDMARST Mask
Definition at line 23151 of file NUC472_442.h.
| #define SPI_PDMACTL_PDMARST_Pos (2) |
SPI_T::PDMACTL: PDMARST Position
Definition at line 23150 of file NUC472_442.h.
| #define SPI_PDMACTL_RXPDMAEN_Msk (0x1ul << SPI_PDMACTL_RXPDMAEN_Pos) |
SPI_T::PDMACTL: RXPDMAEN Mask
Definition at line 23148 of file NUC472_442.h.
| #define SPI_PDMACTL_RXPDMAEN_Pos (1) |
SPI_T::PDMACTL: RXPDMAEN Position
Definition at line 23147 of file NUC472_442.h.
| #define SPI_PDMACTL_TXPDMAEN_Msk (0x1ul << SPI_PDMACTL_TXPDMAEN_Pos) |
SPI_T::PDMACTL: TXPDMAEN Mask
Definition at line 23145 of file NUC472_442.h.
| #define SPI_PDMACTL_TXPDMAEN_Pos (0) |
SPI_T::PDMACTL: TXPDMAEN Position
Definition at line 23144 of file NUC472_442.h.
| #define SPI_RX_RX_Msk (0xfffffffful << SPI_RX_RX_Pos) |
SPI_T::RX: RX Mask
Definition at line 23250 of file NUC472_442.h.
| #define SPI_RX_RX_Pos (0) |
SPI_T::RX: RX Position
Definition at line 23249 of file NUC472_442.h.
| #define SPI_SSCTL_AUTOSS_Msk (0x1ul << SPI_SSCTL_AUTOSS_Pos) |
SPI_T::SSCTL: AUTOSS Mask
Definition at line 23118 of file NUC472_442.h.
| #define SPI_SSCTL_AUTOSS_Pos (3) |
SPI_T::SSCTL: AUTOSS Position
Definition at line 23117 of file NUC472_442.h.
| #define SPI_SSCTL_SLV3WIRE_Msk (0x1ul << SPI_SSCTL_SLV3WIRE_Pos) |
SPI_T::SSCTL: SLV3WIRE Mask
Definition at line 23121 of file NUC472_442.h.
| #define SPI_SSCTL_SLV3WIRE_Pos (4) |
SPI_T::SSCTL: SLV3WIRE Position
Definition at line 23120 of file NUC472_442.h.
| #define SPI_SSCTL_SLVBEIEN_Msk (0x1ul << SPI_SSCTL_SLVBEIEN_Pos) |
SPI_T::SSCTL: SLVBEIEN Mask
Definition at line 23130 of file NUC472_442.h.
| #define SPI_SSCTL_SLVBEIEN_Pos (8) |
SPI_T::SSCTL: SLVBEIEN Position
Definition at line 23129 of file NUC472_442.h.
| #define SPI_SSCTL_SLVTOCNT_Msk (0xfffful << SPI_SSCTL_SLVTOCNT_Pos) |
SPI_T::SSCTL: SLVTOCNT Mask
Definition at line 23142 of file NUC472_442.h.
| #define SPI_SSCTL_SLVTOCNT_Pos (16) |
SPI_T::SSCTL: SLVTOCNT Position
Definition at line 23141 of file NUC472_442.h.
| #define SPI_SSCTL_SLVTOIEN_Msk (0x1ul << SPI_SSCTL_SLVTOIEN_Pos) |
SPI_T::SSCTL: SLVTOIEN Mask
Definition at line 23124 of file NUC472_442.h.
| #define SPI_SSCTL_SLVTOIEN_Pos (5) |
SPI_T::SSCTL: SLVTOIEN Position
Definition at line 23123 of file NUC472_442.h.
| #define SPI_SSCTL_SLVTORST_Msk (0x1ul << SPI_SSCTL_SLVTORST_Pos) |
SPI_T::SSCTL: SLVTORST Mask
Definition at line 23127 of file NUC472_442.h.
| #define SPI_SSCTL_SLVTORST_Pos (6) |
SPI_T::SSCTL: SLVTORST Position
Definition at line 23126 of file NUC472_442.h.
| #define SPI_SSCTL_SLVURIEN_Msk (0x1ul << SPI_SSCTL_SLVURIEN_Pos) |
SPI_T::SSCTL: SLVURIEN Mask
Definition at line 23133 of file NUC472_442.h.
| #define SPI_SSCTL_SLVURIEN_Pos (9) |
SPI_T::SSCTL: SLVURIEN Position
Definition at line 23132 of file NUC472_442.h.
| #define SPI_SSCTL_SS_Msk (0x3ul << SPI_SSCTL_SS_Pos) |
SPI_T::SSCTL: SS Mask
Definition at line 23112 of file NUC472_442.h.
| #define SPI_SSCTL_SS_Pos (0) |
SPI_T::SSCTL: SS Position
Definition at line 23111 of file NUC472_442.h.
| #define SPI_SSCTL_SSACTIEN_Msk (0x1ul << SPI_SSCTL_SSACTIEN_Pos) |
SPI_T::SSCTL: SSACTIEN Mask
Definition at line 23136 of file NUC472_442.h.
| #define SPI_SSCTL_SSACTIEN_Pos (12) |
SPI_T::SSCTL: SSACTIEN Position
Definition at line 23135 of file NUC472_442.h.
| #define SPI_SSCTL_SSACTPOL_Msk (0x1ul << SPI_SSCTL_SSACTPOL_Pos) |
SPI_T::SSCTL: SSACTPOL Mask
Definition at line 23115 of file NUC472_442.h.
| #define SPI_SSCTL_SSACTPOL_Pos (2) |
SPI_T::SSCTL: SSACTPOL Position
Definition at line 23114 of file NUC472_442.h.
| #define SPI_SSCTL_SSINAIEN_Msk (0x1ul << SPI_SSCTL_SSINAIEN_Pos) |
SPI_T::SSCTL: SSINAIEN Mask
Definition at line 23139 of file NUC472_442.h.
| #define SPI_SSCTL_SSINAIEN_Pos (13) |
SPI_T::SSCTL: SSINAIEN Position
Definition at line 23138 of file NUC472_442.h.
| #define SPI_STATUS_BUSY_Msk (0x1ul << SPI_STATUS_BUSY_Pos) |
SPI_T::STATUS: BUSY Mask
Definition at line 23184 of file NUC472_442.h.
| #define SPI_STATUS_BUSY_Pos (0) |
SPI_T::STATUS: BUSY Position
Definition at line 23183 of file NUC472_442.h.
| #define SPI_STATUS_RXCNT_Msk (0xful << SPI_STATUS_RXCNT_Pos) |
SPI_T::STATUS: RXCNT Mask
Definition at line 23241 of file NUC472_442.h.
| #define SPI_STATUS_RXCNT_Pos (24) |
SPI_T::STATUS: RXCNT Position
Definition at line 23240 of file NUC472_442.h.
| #define SPI_STATUS_RXEMPTY_Msk (0x1ul << SPI_STATUS_RXEMPTY_Pos) |
SPI_T::STATUS: RXEMPTY Mask
Definition at line 23208 of file NUC472_442.h.
| #define SPI_STATUS_RXEMPTY_Pos (8) |
SPI_T::STATUS: RXEMPTY Position
Definition at line 23207 of file NUC472_442.h.
| #define SPI_STATUS_RXFULL_Msk (0x1ul << SPI_STATUS_RXFULL_Pos) |
SPI_T::STATUS: RXFULL Mask
Definition at line 23211 of file NUC472_442.h.
| #define SPI_STATUS_RXFULL_Pos (9) |
SPI_T::STATUS: RXFULL Position
Definition at line 23210 of file NUC472_442.h.
| #define SPI_STATUS_RXOVIF_Msk (0x1ul << SPI_STATUS_RXOVIF_Pos) |
SPI_T::STATUS: RXOVIF Mask
Definition at line 23217 of file NUC472_442.h.
| #define SPI_STATUS_RXOVIF_Pos (11) |
SPI_T::STATUS: RXOVIF Position
Definition at line 23216 of file NUC472_442.h.
| #define SPI_STATUS_RXTHIF_Msk (0x1ul << SPI_STATUS_RXTHIF_Pos) |
SPI_T::STATUS: RXTHIF Mask
Definition at line 23214 of file NUC472_442.h.
| #define SPI_STATUS_RXTHIF_Pos (10) |
SPI_T::STATUS: RXTHIF Position
Definition at line 23213 of file NUC472_442.h.
| #define SPI_STATUS_RXTOIF_Msk (0x1ul << SPI_STATUS_RXTOIF_Pos) |
SPI_T::STATUS: RXTOIF Mask
Definition at line 23220 of file NUC472_442.h.
| #define SPI_STATUS_RXTOIF_Pos (12) |
SPI_T::STATUS: RXTOIF Position
Definition at line 23219 of file NUC472_442.h.
| #define SPI_STATUS_SLVBEIF_Msk (0x1ul << SPI_STATUS_SLVBEIF_Pos) |
SPI_T::STATUS: SLVBEIF Mask
Definition at line 23202 of file NUC472_442.h.
| #define SPI_STATUS_SLVBEIF_Pos (6) |
SPI_T::STATUS: SLVBEIF Position
Definition at line 23201 of file NUC472_442.h.
| #define SPI_STATUS_SLVTOIF_Msk (0x1ul << SPI_STATUS_SLVTOIF_Pos) |
SPI_T::STATUS: SLVTOIF Mask
Definition at line 23199 of file NUC472_442.h.
| #define SPI_STATUS_SLVTOIF_Pos (5) |
SPI_T::STATUS: SLVTOIF Position
Definition at line 23198 of file NUC472_442.h.
| #define SPI_STATUS_SLVUDRIF_Msk (0x1ul << SPI_STATUS_SLVUDRIF_Pos) |
SPI_T::STATUS: SLVUDRIF Mask
Definition at line 23205 of file NUC472_442.h.
| #define SPI_STATUS_SLVUDRIF_Pos (7) |
SPI_T::STATUS: SLVUDRIF Position
Definition at line 23204 of file NUC472_442.h.
| #define SPI_STATUS_SPIENSTS_Msk (0x1ul << SPI_STATUS_SPIENSTS_Pos) |
SPI_T::STATUS: SPIENSTS Mask
Definition at line 23223 of file NUC472_442.h.
| #define SPI_STATUS_SPIENSTS_Pos (15) |
SPI_T::STATUS: SPIENSTS Position
Definition at line 23222 of file NUC472_442.h.
| #define SPI_STATUS_SSACTIF_Msk (0x1ul << SPI_STATUS_SSACTIF_Pos) |
SPI_T::STATUS: SSACTIF Mask
Definition at line 23190 of file NUC472_442.h.
| #define SPI_STATUS_SSACTIF_Pos (2) |
SPI_T::STATUS: SSACTIF Position
Definition at line 23189 of file NUC472_442.h.
| #define SPI_STATUS_SSINAIF_Msk (0x1ul << SPI_STATUS_SSINAIF_Pos) |
SPI_T::STATUS: SSINAIF Mask
Definition at line 23193 of file NUC472_442.h.
| #define SPI_STATUS_SSINAIF_Pos (3) |
SPI_T::STATUS: SSINAIF Position
Definition at line 23192 of file NUC472_442.h.
| #define SPI_STATUS_SSLINE_Msk (0x1ul << SPI_STATUS_SSLINE_Pos) |
SPI_T::STATUS: SSLINE Mask
Definition at line 23196 of file NUC472_442.h.
| #define SPI_STATUS_SSLINE_Pos (4) |
SPI_T::STATUS: SSLINE Position
Definition at line 23195 of file NUC472_442.h.
| #define SPI_STATUS_TXCNT_Msk (0xful << SPI_STATUS_TXCNT_Pos) |
SPI_T::STATUS: TXCNT Mask
Definition at line 23244 of file NUC472_442.h.
| #define SPI_STATUS_TXCNT_Pos (28) |
SPI_T::STATUS: TXCNT Position
Definition at line 23243 of file NUC472_442.h.
| #define SPI_STATUS_TXEMPTY_Msk (0x1ul << SPI_STATUS_TXEMPTY_Pos) |
SPI_T::STATUS: TXEMPTY Mask
Definition at line 23226 of file NUC472_442.h.
| #define SPI_STATUS_TXEMPTY_Pos (16) |
SPI_T::STATUS: TXEMPTY Position
Definition at line 23225 of file NUC472_442.h.
| #define SPI_STATUS_TXFULL_Msk (0x1ul << SPI_STATUS_TXFULL_Pos) |
SPI_T::STATUS: TXFULL Mask
Definition at line 23229 of file NUC472_442.h.
| #define SPI_STATUS_TXFULL_Pos (17) |
SPI_T::STATUS: TXFULL Position
Definition at line 23228 of file NUC472_442.h.
| #define SPI_STATUS_TXRXRST_Msk (0x1ul << SPI_STATUS_TXRXRST_Pos) |
SPI_T::STATUS: TXRXRST Mask
Definition at line 23238 of file NUC472_442.h.
| #define SPI_STATUS_TXRXRST_Pos (23) |
SPI_T::STATUS: TXRXRST Position
Definition at line 23237 of file NUC472_442.h.
| #define SPI_STATUS_TXTHIF_Msk (0x1ul << SPI_STATUS_TXTHIF_Pos) |
SPI_T::STATUS: TXTHIF Mask
Definition at line 23232 of file NUC472_442.h.
| #define SPI_STATUS_TXTHIF_Pos (18) |
SPI_T::STATUS: TXTHIF Position
Definition at line 23231 of file NUC472_442.h.
| #define SPI_STATUS_TXUFIF_Msk (0x1ul << SPI_STATUS_TXUFIF_Pos) |
SPI_T::STATUS: TXUFIF Mask
Definition at line 23235 of file NUC472_442.h.
| #define SPI_STATUS_TXUFIF_Pos (19) |
SPI_T::STATUS: TXUFIF Position
Definition at line 23234 of file NUC472_442.h.
| #define SPI_STATUS_UNITIF_Msk (0x1ul << SPI_STATUS_UNITIF_Pos) |
SPI_T::STATUS: UNITIF Mask
Definition at line 23187 of file NUC472_442.h.
| #define SPI_STATUS_UNITIF_Pos (1) |
SPI_T::STATUS: UNITIF Position
Definition at line 23186 of file NUC472_442.h.
| #define SPI_TX_TX_Msk (0xfffffffful << SPI_TX_TX_Pos) |
SPI_T::TX: TX Mask
Definition at line 23247 of file NUC472_442.h.
| #define SPI_TX_TX_Pos (0) |
SPI_T::TX: TX Position
Definition at line 23246 of file NUC472_442.h.
| #define SYS_BODCTL_BODEN_Msk (0x1ul << SYS_BODCTL_BODEN_Pos) |
SYS_T::BODCTL: BODEN Mask
Definition at line 24354 of file NUC472_442.h.
| #define SYS_BODCTL_BODEN_Pos (0) |
SYS_T::BODCTL: BODEN Position
Definition at line 24353 of file NUC472_442.h.
| #define SYS_BODCTL_BODINTF_Msk (0x1ul << SYS_BODCTL_BODINTF_Pos) |
SYS_T::BODCTL: BODINTF Mask
Definition at line 24363 of file NUC472_442.h.
| #define SYS_BODCTL_BODINTF_Pos (4) |
SYS_T::BODCTL: BODINTF Position
Definition at line 24362 of file NUC472_442.h.
| #define SYS_BODCTL_BODLPM_Msk (0x1ul << SYS_BODCTL_BODLPM_Pos) |
SYS_T::BODCTL: BODLPM Mask
Definition at line 24366 of file NUC472_442.h.
| #define SYS_BODCTL_BODLPM_Pos (5) |
SYS_T::BODCTL: BODLPM Position
Definition at line 24365 of file NUC472_442.h.
| #define SYS_BODCTL_BODOUT_Msk (0x1ul << SYS_BODCTL_BODOUT_Pos) |
SYS_T::BODCTL: BODOUT Mask
Definition at line 24369 of file NUC472_442.h.
| #define SYS_BODCTL_BODOUT_Pos (6) |
SYS_T::BODCTL: BODOUT Position
Definition at line 24368 of file NUC472_442.h.
| #define SYS_BODCTL_BODRSTEN_Msk (0x1ul << SYS_BODCTL_BODRSTEN_Pos) |
SYS_T::BODCTL: BODRSTEN Mask
Definition at line 24360 of file NUC472_442.h.
| #define SYS_BODCTL_BODRSTEN_Pos (3) |
SYS_T::BODCTL: BODRSTEN Position
Definition at line 24359 of file NUC472_442.h.
| #define SYS_BODCTL_BODVL_Msk (0x3ul << SYS_BODCTL_BODVL_Pos) |
SYS_T::BODCTL: BODVL Mask
Definition at line 24357 of file NUC472_442.h.
| #define SYS_BODCTL_BODVL_Pos (1) |
SYS_T::BODCTL: BODVL Position
Definition at line 24356 of file NUC472_442.h.
| #define SYS_BODCTL_LVREN_Msk (0x1ul << SYS_BODCTL_LVREN_Pos) |
SYS_T::BODCTL: LVREN Mask
Definition at line 24372 of file NUC472_442.h.
| #define SYS_BODCTL_LVREN_Pos (7) |
SYS_T::BODCTL: LVREN Position
Definition at line 24371 of file NUC472_442.h.
| #define SYS_GPA_MFPH_PA10MFP_Msk (0xful << SYS_GPA_MFPH_PA10MFP_Pos) |
SYS_T::GPA_MFPH: PA10MFP Mask
Definition at line 24429 of file NUC472_442.h.
| #define SYS_GPA_MFPH_PA10MFP_Pos (8) |
SYS_T::GPA_MFPH: PA10MFP Position
Definition at line 24428 of file NUC472_442.h.
| #define SYS_GPA_MFPH_PA11MFP_Msk (0xful << SYS_GPA_MFPH_PA11MFP_Pos) |
SYS_T::GPA_MFPH: PA11MFP Mask
Definition at line 24432 of file NUC472_442.h.
| #define SYS_GPA_MFPH_PA11MFP_Pos (12) |
SYS_T::GPA_MFPH: PA11MFP Position
Definition at line 24431 of file NUC472_442.h.
| #define SYS_GPA_MFPH_PA12MFP_Msk (0xful << SYS_GPA_MFPH_PA12MFP_Pos) |
SYS_T::GPA_MFPH: PA12MFP Mask
Definition at line 24435 of file NUC472_442.h.
| #define SYS_GPA_MFPH_PA12MFP_Pos (16) |
SYS_T::GPA_MFPH: PA12MFP Position
Definition at line 24434 of file NUC472_442.h.
| #define SYS_GPA_MFPH_PA13MFP_Msk (0xful << SYS_GPA_MFPH_PA13MFP_Pos) |
SYS_T::GPA_MFPH: PA13MFP Mask
Definition at line 24438 of file NUC472_442.h.
| #define SYS_GPA_MFPH_PA13MFP_Pos (20) |
SYS_T::GPA_MFPH: PA13MFP Position
Definition at line 24437 of file NUC472_442.h.
| #define SYS_GPA_MFPH_PA14MFP_Msk (0xful << SYS_GPA_MFPH_PA14MFP_Pos) |
SYS_T::GPA_MFPH: PA14MFP Mask
Definition at line 24441 of file NUC472_442.h.
| #define SYS_GPA_MFPH_PA14MFP_Pos (24) |
SYS_T::GPA_MFPH: PA14MFP Position
Definition at line 24440 of file NUC472_442.h.
| #define SYS_GPA_MFPH_PA15MFP_Msk (0xful << SYS_GPA_MFPH_PA15MFP_Pos) |
SYS_T::GPA_MFPH: PA15MFP Mask
Definition at line 24444 of file NUC472_442.h.
| #define SYS_GPA_MFPH_PA15MFP_Pos (28) |
SYS_T::GPA_MFPH: PA15MFP Position
Definition at line 24443 of file NUC472_442.h.
| #define SYS_GPA_MFPH_PA8MFP_Msk (0xful << SYS_GPA_MFPH_PA8MFP_Pos) |
SYS_T::GPA_MFPH: PA8MFP Mask
Definition at line 24423 of file NUC472_442.h.
| #define SYS_GPA_MFPH_PA8MFP_Pos (0) |
SYS_T::GPA_MFPH: PA8MFP Position
Definition at line 24422 of file NUC472_442.h.
| #define SYS_GPA_MFPH_PA9MFP_Msk (0xful << SYS_GPA_MFPH_PA9MFP_Pos) |
SYS_T::GPA_MFPH: PA9MFP Mask
Definition at line 24426 of file NUC472_442.h.
| #define SYS_GPA_MFPH_PA9MFP_Pos (4) |
SYS_T::GPA_MFPH: PA9MFP Position
Definition at line 24425 of file NUC472_442.h.
| #define SYS_GPA_MFPL_PA0MFP_Msk (0xful << SYS_GPA_MFPL_PA0MFP_Pos) |
SYS_T::GPA_MFPL: PA0MFP Mask
Definition at line 24399 of file NUC472_442.h.
| #define SYS_GPA_MFPL_PA0MFP_Pos (0) |
SYS_T::GPA_MFPL: PA0MFP Position
Definition at line 24398 of file NUC472_442.h.
| #define SYS_GPA_MFPL_PA1MFP_Msk (0xful << SYS_GPA_MFPL_PA1MFP_Pos) |
SYS_T::GPA_MFPL: PA1MFP Mask
Definition at line 24402 of file NUC472_442.h.
| #define SYS_GPA_MFPL_PA1MFP_Pos (4) |
SYS_T::GPA_MFPL: PA1MFP Position
Definition at line 24401 of file NUC472_442.h.
| #define SYS_GPA_MFPL_PA2MFP_Msk (0xful << SYS_GPA_MFPL_PA2MFP_Pos) |
SYS_T::GPA_MFPL: PA2MFP Mask
Definition at line 24405 of file NUC472_442.h.
| #define SYS_GPA_MFPL_PA2MFP_Pos (8) |
SYS_T::GPA_MFPL: PA2MFP Position
Definition at line 24404 of file NUC472_442.h.
| #define SYS_GPA_MFPL_PA3MFP_Msk (0xful << SYS_GPA_MFPL_PA3MFP_Pos) |
SYS_T::GPA_MFPL: PA3MFP Mask
Definition at line 24408 of file NUC472_442.h.
| #define SYS_GPA_MFPL_PA3MFP_Pos (12) |
SYS_T::GPA_MFPL: PA3MFP Position
Definition at line 24407 of file NUC472_442.h.
| #define SYS_GPA_MFPL_PA4MFP_Msk (0xful << SYS_GPA_MFPL_PA4MFP_Pos) |
SYS_T::GPA_MFPL: PA4MFP Mask
Definition at line 24411 of file NUC472_442.h.
| #define SYS_GPA_MFPL_PA4MFP_Pos (16) |
SYS_T::GPA_MFPL: PA4MFP Position
Definition at line 24410 of file NUC472_442.h.
| #define SYS_GPA_MFPL_PA5MFP_Msk (0xful << SYS_GPA_MFPL_PA5MFP_Pos) |
SYS_T::GPA_MFPL: PA5MFP Mask
Definition at line 24414 of file NUC472_442.h.
| #define SYS_GPA_MFPL_PA5MFP_Pos (20) |
SYS_T::GPA_MFPL: PA5MFP Position
Definition at line 24413 of file NUC472_442.h.
| #define SYS_GPA_MFPL_PA6MFP_Msk (0xful << SYS_GPA_MFPL_PA6MFP_Pos) |
SYS_T::GPA_MFPL: PA6MFP Mask
Definition at line 24417 of file NUC472_442.h.
| #define SYS_GPA_MFPL_PA6MFP_Pos (24) |
SYS_T::GPA_MFPL: PA6MFP Position
Definition at line 24416 of file NUC472_442.h.
| #define SYS_GPA_MFPL_PA7MFP_Msk (0xful << SYS_GPA_MFPL_PA7MFP_Pos) |
SYS_T::GPA_MFPL: PA7MFP Mask
Definition at line 24420 of file NUC472_442.h.
| #define SYS_GPA_MFPL_PA7MFP_Pos (28) |
SYS_T::GPA_MFPL: PA7MFP Position
Definition at line 24419 of file NUC472_442.h.
| #define SYS_GPB_MFPH_PB10MFP_Msk (0xful << SYS_GPB_MFPH_PB10MFP_Pos) |
SYS_T::GPB_MFPH: PB10MFP Mask
Definition at line 24477 of file NUC472_442.h.
| #define SYS_GPB_MFPH_PB10MFP_Pos (8) |
SYS_T::GPB_MFPH: PB10MFP Position
Definition at line 24476 of file NUC472_442.h.
| #define SYS_GPB_MFPH_PB11MFP_Msk (0xful << SYS_GPB_MFPH_PB11MFP_Pos) |
SYS_T::GPB_MFPH: PB11MFP Mask
Definition at line 24480 of file NUC472_442.h.
| #define SYS_GPB_MFPH_PB11MFP_Pos (12) |
SYS_T::GPB_MFPH: PB11MFP Position
Definition at line 24479 of file NUC472_442.h.
| #define SYS_GPB_MFPH_PB12MFP_Msk (0xful << SYS_GPB_MFPH_PB12MFP_Pos) |
SYS_T::GPB_MFPH: PB12MFP Mask
Definition at line 24483 of file NUC472_442.h.
| #define SYS_GPB_MFPH_PB12MFP_Pos (16) |
SYS_T::GPB_MFPH: PB12MFP Position
Definition at line 24482 of file NUC472_442.h.
| #define SYS_GPB_MFPH_PB13MFP_Msk (0xful << SYS_GPB_MFPH_PB13MFP_Pos) |
SYS_T::GPB_MFPH: PB13MFP Mask
Definition at line 24486 of file NUC472_442.h.
| #define SYS_GPB_MFPH_PB13MFP_Pos (20) |
SYS_T::GPB_MFPH: PB13MFP Position
Definition at line 24485 of file NUC472_442.h.
| #define SYS_GPB_MFPH_PB14MFP_Msk (0xful << SYS_GPB_MFPH_PB14MFP_Pos) |
SYS_T::GPB_MFPH: PB14MFP Mask
Definition at line 24489 of file NUC472_442.h.
| #define SYS_GPB_MFPH_PB14MFP_Pos (24) |
SYS_T::GPB_MFPH: PB14MFP Position
Definition at line 24488 of file NUC472_442.h.
| #define SYS_GPB_MFPH_PB15MFP_Msk (0xful << SYS_GPB_MFPH_PB15MFP_Pos) |
SYS_T::GPB_MFPH: PB15MFP Mask
Definition at line 24492 of file NUC472_442.h.
| #define SYS_GPB_MFPH_PB15MFP_Pos (28) |
SYS_T::GPB_MFPH: PB15MFP Position
Definition at line 24491 of file NUC472_442.h.
| #define SYS_GPB_MFPH_PB8MFP_Msk (0xful << SYS_GPB_MFPH_PB8MFP_Pos) |
SYS_T::GPB_MFPH: PB8MFP Mask
Definition at line 24471 of file NUC472_442.h.
| #define SYS_GPB_MFPH_PB8MFP_Pos (0) |
SYS_T::GPB_MFPH: PB8MFP Position
Definition at line 24470 of file NUC472_442.h.
| #define SYS_GPB_MFPH_PB9MFP_Msk (0xful << SYS_GPB_MFPH_PB9MFP_Pos) |
SYS_T::GPB_MFPH: PB9MFP Mask
Definition at line 24474 of file NUC472_442.h.
| #define SYS_GPB_MFPH_PB9MFP_Pos (4) |
SYS_T::GPB_MFPH: PB9MFP Position
Definition at line 24473 of file NUC472_442.h.
| #define SYS_GPB_MFPL_PB0MFP_Msk (0xful << SYS_GPB_MFPL_PB0MFP_Pos) |
SYS_T::GPB_MFPL: PB0MFP Mask
Definition at line 24447 of file NUC472_442.h.
| #define SYS_GPB_MFPL_PB0MFP_Pos (0) |
SYS_T::GPB_MFPL: PB0MFP Position
Definition at line 24446 of file NUC472_442.h.
| #define SYS_GPB_MFPL_PB1MFP_Msk (0xful << SYS_GPB_MFPL_PB1MFP_Pos) |
SYS_T::GPB_MFPL: PB1MFP Mask
Definition at line 24450 of file NUC472_442.h.
| #define SYS_GPB_MFPL_PB1MFP_Pos (4) |
SYS_T::GPB_MFPL: PB1MFP Position
Definition at line 24449 of file NUC472_442.h.
| #define SYS_GPB_MFPL_PB2MFP_Msk (0xful << SYS_GPB_MFPL_PB2MFP_Pos) |
SYS_T::GPB_MFPL: PB2MFP Mask
Definition at line 24453 of file NUC472_442.h.
| #define SYS_GPB_MFPL_PB2MFP_Pos (8) |
SYS_T::GPB_MFPL: PB2MFP Position
Definition at line 24452 of file NUC472_442.h.
| #define SYS_GPB_MFPL_PB3MFP_Msk (0xful << SYS_GPB_MFPL_PB3MFP_Pos) |
SYS_T::GPB_MFPL: PB3MFP Mask
Definition at line 24456 of file NUC472_442.h.
| #define SYS_GPB_MFPL_PB3MFP_Pos (12) |
SYS_T::GPB_MFPL: PB3MFP Position
Definition at line 24455 of file NUC472_442.h.
| #define SYS_GPB_MFPL_PB4MFP_Msk (0xful << SYS_GPB_MFPL_PB4MFP_Pos) |
SYS_T::GPB_MFPL: PB4MFP Mask
Definition at line 24459 of file NUC472_442.h.
| #define SYS_GPB_MFPL_PB4MFP_Pos (16) |
SYS_T::GPB_MFPL: PB4MFP Position
Definition at line 24458 of file NUC472_442.h.
| #define SYS_GPB_MFPL_PB5MFP_Msk (0xful << SYS_GPB_MFPL_PB5MFP_Pos) |
SYS_T::GPB_MFPL: PB5MFP Mask
Definition at line 24462 of file NUC472_442.h.
| #define SYS_GPB_MFPL_PB5MFP_Pos (20) |
SYS_T::GPB_MFPL: PB5MFP Position
Definition at line 24461 of file NUC472_442.h.
| #define SYS_GPB_MFPL_PB6MFP_Msk (0xful << SYS_GPB_MFPL_PB6MFP_Pos) |
SYS_T::GPB_MFPL: PB6MFP Mask
Definition at line 24465 of file NUC472_442.h.
| #define SYS_GPB_MFPL_PB6MFP_Pos (24) |
SYS_T::GPB_MFPL: PB6MFP Position
Definition at line 24464 of file NUC472_442.h.
| #define SYS_GPB_MFPL_PB7MFP_Msk (0xful << SYS_GPB_MFPL_PB7MFP_Pos) |
SYS_T::GPB_MFPL: PB7MFP Mask
Definition at line 24468 of file NUC472_442.h.
| #define SYS_GPB_MFPL_PB7MFP_Pos (28) |
SYS_T::GPB_MFPL: PB7MFP Position
Definition at line 24467 of file NUC472_442.h.
| #define SYS_GPC_MFPH_PC10MFP_Msk (0xful << SYS_GPC_MFPH_PC10MFP_Pos) |
SYS_T::GPC_MFPH: PC10MFP Mask
Definition at line 24525 of file NUC472_442.h.
| #define SYS_GPC_MFPH_PC10MFP_Pos (8) |
SYS_T::GPC_MFPH: PC10MFP Position
Definition at line 24524 of file NUC472_442.h.
| #define SYS_GPC_MFPH_PC11MFP_Msk (0xful << SYS_GPC_MFPH_PC11MFP_Pos) |
SYS_T::GPC_MFPH: PC11MFP Mask
Definition at line 24528 of file NUC472_442.h.
| #define SYS_GPC_MFPH_PC11MFP_Pos (12) |
SYS_T::GPC_MFPH: PC11MFP Position
Definition at line 24527 of file NUC472_442.h.
| #define SYS_GPC_MFPH_PC12MFP_Msk (0xful << SYS_GPC_MFPH_PC12MFP_Pos) |
SYS_T::GPC_MFPH: PC12MFP Mask
Definition at line 24531 of file NUC472_442.h.
| #define SYS_GPC_MFPH_PC12MFP_Pos (16) |
SYS_T::GPC_MFPH: PC12MFP Position
Definition at line 24530 of file NUC472_442.h.
| #define SYS_GPC_MFPH_PC13MFP_Msk (0xful << SYS_GPC_MFPH_PC13MFP_Pos) |
SYS_T::GPC_MFPH: PC13MFP Mask
Definition at line 24534 of file NUC472_442.h.
| #define SYS_GPC_MFPH_PC13MFP_Pos (20) |
SYS_T::GPC_MFPH: PC13MFP Position
Definition at line 24533 of file NUC472_442.h.
| #define SYS_GPC_MFPH_PC14MFP_Msk (0xful << SYS_GPC_MFPH_PC14MFP_Pos) |
SYS_T::GPC_MFPH: PC14MFP Mask
Definition at line 24537 of file NUC472_442.h.
| #define SYS_GPC_MFPH_PC14MFP_Pos (24) |
SYS_T::GPC_MFPH: PC14MFP Position
Definition at line 24536 of file NUC472_442.h.
| #define SYS_GPC_MFPH_PC15MFP_Msk (0xful << SYS_GPC_MFPH_PC15MFP_Pos) |
SYS_T::GPC_MFPH: PC15MFP Mask
Definition at line 24540 of file NUC472_442.h.
| #define SYS_GPC_MFPH_PC15MFP_Pos (28) |
SYS_T::GPC_MFPH: PC15MFP Position
Definition at line 24539 of file NUC472_442.h.
| #define SYS_GPC_MFPH_PC8MFP_Msk (0xful << SYS_GPC_MFPH_PC8MFP_Pos) |
SYS_T::GPC_MFPH: PC8MFP Mask
Definition at line 24519 of file NUC472_442.h.
| #define SYS_GPC_MFPH_PC8MFP_Pos (0) |
SYS_T::GPC_MFPH: PC8MFP Position
Definition at line 24518 of file NUC472_442.h.
| #define SYS_GPC_MFPH_PC9MFP_Msk (0xful << SYS_GPC_MFPH_PC9MFP_Pos) |
SYS_T::GPC_MFPH: PC9MFP Mask
Definition at line 24522 of file NUC472_442.h.
| #define SYS_GPC_MFPH_PC9MFP_Pos (4) |
SYS_T::GPC_MFPH: PC9MFP Position
Definition at line 24521 of file NUC472_442.h.
| #define SYS_GPC_MFPL_PC0MFP_Msk (0xful << SYS_GPC_MFPL_PC0MFP_Pos) |
SYS_T::GPC_MFPL: PC0MFP Mask
Definition at line 24495 of file NUC472_442.h.
| #define SYS_GPC_MFPL_PC0MFP_Pos (0) |
SYS_T::GPC_MFPL: PC0MFP Position
Definition at line 24494 of file NUC472_442.h.
| #define SYS_GPC_MFPL_PC1MFP_Msk (0xful << SYS_GPC_MFPL_PC1MFP_Pos) |
SYS_T::GPC_MFPL: PC1MFP Mask
Definition at line 24498 of file NUC472_442.h.
| #define SYS_GPC_MFPL_PC1MFP_Pos (4) |
SYS_T::GPC_MFPL: PC1MFP Position
Definition at line 24497 of file NUC472_442.h.
| #define SYS_GPC_MFPL_PC2MFP_Msk (0xful << SYS_GPC_MFPL_PC2MFP_Pos) |
SYS_T::GPC_MFPL: PC2MFP Mask
Definition at line 24501 of file NUC472_442.h.
| #define SYS_GPC_MFPL_PC2MFP_Pos (8) |
SYS_T::GPC_MFPL: PC2MFP Position
Definition at line 24500 of file NUC472_442.h.
| #define SYS_GPC_MFPL_PC3MFP_Msk (0xful << SYS_GPC_MFPL_PC3MFP_Pos) |
SYS_T::GPC_MFPL: PC3MFP Mask
Definition at line 24504 of file NUC472_442.h.
| #define SYS_GPC_MFPL_PC3MFP_Pos (12) |
SYS_T::GPC_MFPL: PC3MFP Position
Definition at line 24503 of file NUC472_442.h.
| #define SYS_GPC_MFPL_PC4MFP_Msk (0xful << SYS_GPC_MFPL_PC4MFP_Pos) |
SYS_T::GPC_MFPL: PC4MFP Mask
Definition at line 24507 of file NUC472_442.h.
| #define SYS_GPC_MFPL_PC4MFP_Pos (16) |
SYS_T::GPC_MFPL: PC4MFP Position
Definition at line 24506 of file NUC472_442.h.
| #define SYS_GPC_MFPL_PC5MFP_Msk (0xful << SYS_GPC_MFPL_PC5MFP_Pos) |
SYS_T::GPC_MFPL: PC5MFP Mask
Definition at line 24510 of file NUC472_442.h.
| #define SYS_GPC_MFPL_PC5MFP_Pos (20) |
SYS_T::GPC_MFPL: PC5MFP Position
Definition at line 24509 of file NUC472_442.h.
| #define SYS_GPC_MFPL_PC6MFP_Msk (0xful << SYS_GPC_MFPL_PC6MFP_Pos) |
SYS_T::GPC_MFPL: PC6MFP Mask
Definition at line 24513 of file NUC472_442.h.
| #define SYS_GPC_MFPL_PC6MFP_Pos (24) |
SYS_T::GPC_MFPL: PC6MFP Position
Definition at line 24512 of file NUC472_442.h.
| #define SYS_GPC_MFPL_PC7MFP_Msk (0xful << SYS_GPC_MFPL_PC7MFP_Pos) |
SYS_T::GPC_MFPL: PC7MFP Mask
Definition at line 24516 of file NUC472_442.h.
| #define SYS_GPC_MFPL_PC7MFP_Pos (28) |
SYS_T::GPC_MFPL: PC7MFP Position
Definition at line 24515 of file NUC472_442.h.
| #define SYS_GPD_MFPH_PD10MFP_Msk (0xful << SYS_GPD_MFPH_PD10MFP_Pos) |
SYS_T::GPD_MFPH: PD10MFP Mask
Definition at line 24573 of file NUC472_442.h.
| #define SYS_GPD_MFPH_PD10MFP_Pos (8) |
SYS_T::GPD_MFPH: PD10MFP Position
Definition at line 24572 of file NUC472_442.h.
| #define SYS_GPD_MFPH_PD11MFP_Msk (0xful << SYS_GPD_MFPH_PD11MFP_Pos) |
SYS_T::GPD_MFPH: PD11MFP Mask
Definition at line 24576 of file NUC472_442.h.
| #define SYS_GPD_MFPH_PD11MFP_Pos (12) |
SYS_T::GPD_MFPH: PD11MFP Position
Definition at line 24575 of file NUC472_442.h.
| #define SYS_GPD_MFPH_PD12MFP_Msk (0xful << SYS_GPD_MFPH_PD12MFP_Pos) |
SYS_T::GPD_MFPH: PD12MFP Mask
Definition at line 24579 of file NUC472_442.h.
| #define SYS_GPD_MFPH_PD12MFP_Pos (16) |
SYS_T::GPD_MFPH: PD12MFP Position
Definition at line 24578 of file NUC472_442.h.
| #define SYS_GPD_MFPH_PD13MFP_Msk (0xful << SYS_GPD_MFPH_PD13MFP_Pos) |
SYS_T::GPD_MFPH: PD13MFP Mask
Definition at line 24582 of file NUC472_442.h.
| #define SYS_GPD_MFPH_PD13MFP_Pos (20) |
SYS_T::GPD_MFPH: PD13MFP Position
Definition at line 24581 of file NUC472_442.h.
| #define SYS_GPD_MFPH_PD14MFP_Msk (0xful << SYS_GPD_MFPH_PD14MFP_Pos) |
SYS_T::GPD_MFPH: PD14MFP Mask
Definition at line 24585 of file NUC472_442.h.
| #define SYS_GPD_MFPH_PD14MFP_Pos (24) |
SYS_T::GPD_MFPH: PD14MFP Position
Definition at line 24584 of file NUC472_442.h.
| #define SYS_GPD_MFPH_PD15MFP_Msk (0xful << SYS_GPD_MFPH_PD15MFP_Pos) |
SYS_T::GPD_MFPH: PD15MFP Mask
Definition at line 24588 of file NUC472_442.h.
| #define SYS_GPD_MFPH_PD15MFP_Pos (28) |
SYS_T::GPD_MFPH: PD15MFP Position
Definition at line 24587 of file NUC472_442.h.
| #define SYS_GPD_MFPH_PD8MFP_Msk (0xful << SYS_GPD_MFPH_PD8MFP_Pos) |
SYS_T::GPD_MFPH: PD8MFP Mask
Definition at line 24567 of file NUC472_442.h.
| #define SYS_GPD_MFPH_PD8MFP_Pos (0) |
SYS_T::GPD_MFPH: PD8MFP Position
Definition at line 24566 of file NUC472_442.h.
| #define SYS_GPD_MFPH_PD9MFP_Msk (0xful << SYS_GPD_MFPH_PD9MFP_Pos) |
SYS_T::GPD_MFPH: PD9MFP Mask
Definition at line 24570 of file NUC472_442.h.
| #define SYS_GPD_MFPH_PD9MFP_Pos (4) |
SYS_T::GPD_MFPH: PD9MFP Position
Definition at line 24569 of file NUC472_442.h.
| #define SYS_GPD_MFPL_PD0MFP_Msk (0xful << SYS_GPD_MFPL_PD0MFP_Pos) |
SYS_T::GPD_MFPL: PD0MFP Mask
Definition at line 24543 of file NUC472_442.h.
| #define SYS_GPD_MFPL_PD0MFP_Pos (0) |
SYS_T::GPD_MFPL: PD0MFP Position
Definition at line 24542 of file NUC472_442.h.
| #define SYS_GPD_MFPL_PD1MFP_Msk (0xful << SYS_GPD_MFPL_PD1MFP_Pos) |
SYS_T::GPD_MFPL: PD1MFP Mask
Definition at line 24546 of file NUC472_442.h.
| #define SYS_GPD_MFPL_PD1MFP_Pos (4) |
SYS_T::GPD_MFPL: PD1MFP Position
Definition at line 24545 of file NUC472_442.h.
| #define SYS_GPD_MFPL_PD2MFP_Msk (0xful << SYS_GPD_MFPL_PD2MFP_Pos) |
SYS_T::GPD_MFPL: PD2MFP Mask
Definition at line 24549 of file NUC472_442.h.
| #define SYS_GPD_MFPL_PD2MFP_Pos (8) |
SYS_T::GPD_MFPL: PD2MFP Position
Definition at line 24548 of file NUC472_442.h.
| #define SYS_GPD_MFPL_PD3MFP_Msk (0xful << SYS_GPD_MFPL_PD3MFP_Pos) |
SYS_T::GPD_MFPL: PD3MFP Mask
Definition at line 24552 of file NUC472_442.h.
| #define SYS_GPD_MFPL_PD3MFP_Pos (12) |
SYS_T::GPD_MFPL: PD3MFP Position
Definition at line 24551 of file NUC472_442.h.
| #define SYS_GPD_MFPL_PD4MFP_Msk (0xful << SYS_GPD_MFPL_PD4MFP_Pos) |
SYS_T::GPD_MFPL: PD4MFP Mask
Definition at line 24555 of file NUC472_442.h.
| #define SYS_GPD_MFPL_PD4MFP_Pos (16) |
SYS_T::GPD_MFPL: PD4MFP Position
Definition at line 24554 of file NUC472_442.h.
| #define SYS_GPD_MFPL_PD5MFP_Msk (0xful << SYS_GPD_MFPL_PD5MFP_Pos) |
SYS_T::GPD_MFPL: PD5MFP Mask
Definition at line 24558 of file NUC472_442.h.
| #define SYS_GPD_MFPL_PD5MFP_Pos (20) |
SYS_T::GPD_MFPL: PD5MFP Position
Definition at line 24557 of file NUC472_442.h.
| #define SYS_GPD_MFPL_PD6MFP_Msk (0xful << SYS_GPD_MFPL_PD6MFP_Pos) |
SYS_T::GPD_MFPL: PD6MFP Mask
Definition at line 24561 of file NUC472_442.h.
| #define SYS_GPD_MFPL_PD6MFP_Pos (24) |
SYS_T::GPD_MFPL: PD6MFP Position
Definition at line 24560 of file NUC472_442.h.
| #define SYS_GPD_MFPL_PD7MFP_Msk (0xful << SYS_GPD_MFPL_PD7MFP_Pos) |
SYS_T::GPD_MFPL: PD7MFP Mask
Definition at line 24564 of file NUC472_442.h.
| #define SYS_GPD_MFPL_PD7MFP_Pos (28) |
SYS_T::GPD_MFPL: PD7MFP Position
Definition at line 24563 of file NUC472_442.h.
| #define SYS_GPE_MFPH_PE10MFP_Msk (0xful << SYS_GPE_MFPH_PE10MFP_Pos) |
SYS_T::GPE_MFPH: PE10MFP Mask
Definition at line 24621 of file NUC472_442.h.
| #define SYS_GPE_MFPH_PE10MFP_Pos (8) |
SYS_T::GPE_MFPH: PE10MFP Position
Definition at line 24620 of file NUC472_442.h.
| #define SYS_GPE_MFPH_PE11MFP_Msk (0xful << SYS_GPE_MFPH_PE11MFP_Pos) |
SYS_T::GPE_MFPH: PE11MFP Mask
Definition at line 24624 of file NUC472_442.h.
| #define SYS_GPE_MFPH_PE11MFP_Pos (12) |
SYS_T::GPE_MFPH: PE11MFP Position
Definition at line 24623 of file NUC472_442.h.
| #define SYS_GPE_MFPH_PE12MFP_Msk (0xful << SYS_GPE_MFPH_PE12MFP_Pos) |
SYS_T::GPE_MFPH: PE12MFP Mask
Definition at line 24627 of file NUC472_442.h.
| #define SYS_GPE_MFPH_PE12MFP_Pos (16) |
SYS_T::GPE_MFPH: PE12MFP Position
Definition at line 24626 of file NUC472_442.h.
| #define SYS_GPE_MFPH_PE13MFP_Msk (0xful << SYS_GPE_MFPH_PE13MFP_Pos) |
SYS_T::GPE_MFPH: PE13MFP Mask
Definition at line 24630 of file NUC472_442.h.
| #define SYS_GPE_MFPH_PE13MFP_Pos (20) |
SYS_T::GPE_MFPH: PE13MFP Position
Definition at line 24629 of file NUC472_442.h.
| #define SYS_GPE_MFPH_PE14MFP_Msk (0xful << SYS_GPE_MFPH_PE14MFP_Pos) |
SYS_T::GPE_MFPH: PE14MFP Mask
Definition at line 24633 of file NUC472_442.h.
| #define SYS_GPE_MFPH_PE14MFP_Pos (24) |
SYS_T::GPE_MFPH: PE14MFP Position
Definition at line 24632 of file NUC472_442.h.
| #define SYS_GPE_MFPH_PE15MFP_Msk (0xful << SYS_GPE_MFPH_PE15MFP_Pos) |
SYS_T::GPE_MFPH: PE15MFP Mask
Definition at line 24636 of file NUC472_442.h.
| #define SYS_GPE_MFPH_PE15MFP_Pos (28) |
SYS_T::GPE_MFPH: PE15MFP Position
Definition at line 24635 of file NUC472_442.h.
| #define SYS_GPE_MFPH_PE8MFP_Msk (0xful << SYS_GPE_MFPH_PE8MFP_Pos) |
SYS_T::GPE_MFPH: PE8MFP Mask
Definition at line 24615 of file NUC472_442.h.
| #define SYS_GPE_MFPH_PE8MFP_Pos (0) |
SYS_T::GPE_MFPH: PE8MFP Position
Definition at line 24614 of file NUC472_442.h.
| #define SYS_GPE_MFPH_PE9MFP_Msk (0xful << SYS_GPE_MFPH_PE9MFP_Pos) |
SYS_T::GPE_MFPH: PE9MFP Mask
Definition at line 24618 of file NUC472_442.h.
| #define SYS_GPE_MFPH_PE9MFP_Pos (4) |
SYS_T::GPE_MFPH: PE9MFP Position
Definition at line 24617 of file NUC472_442.h.
| #define SYS_GPE_MFPL_PE0MFP_Msk (0xful << SYS_GPE_MFPL_PE0MFP_Pos) |
SYS_T::GPE_MFPL: PE0MFP Mask
Definition at line 24591 of file NUC472_442.h.
| #define SYS_GPE_MFPL_PE0MFP_Pos (0) |
SYS_T::GPE_MFPL: PE0MFP Position
Definition at line 24590 of file NUC472_442.h.
| #define SYS_GPE_MFPL_PE1MFP_Msk (0xful << SYS_GPE_MFPL_PE1MFP_Pos) |
SYS_T::GPE_MFPL: PE1MFP Mask
Definition at line 24594 of file NUC472_442.h.
| #define SYS_GPE_MFPL_PE1MFP_Pos (4) |
SYS_T::GPE_MFPL: PE1MFP Position
Definition at line 24593 of file NUC472_442.h.
| #define SYS_GPE_MFPL_PE2MFP_Msk (0xful << SYS_GPE_MFPL_PE2MFP_Pos) |
SYS_T::GPE_MFPL: PE2MFP Mask
Definition at line 24597 of file NUC472_442.h.
| #define SYS_GPE_MFPL_PE2MFP_Pos (8) |
SYS_T::GPE_MFPL: PE2MFP Position
Definition at line 24596 of file NUC472_442.h.
| #define SYS_GPE_MFPL_PE3MFP_Msk (0xful << SYS_GPE_MFPL_PE3MFP_Pos) |
SYS_T::GPE_MFPL: PE3MFP Mask
Definition at line 24600 of file NUC472_442.h.
| #define SYS_GPE_MFPL_PE3MFP_Pos (12) |
SYS_T::GPE_MFPL: PE3MFP Position
Definition at line 24599 of file NUC472_442.h.
| #define SYS_GPE_MFPL_PE4MFP_Msk (0xful << SYS_GPE_MFPL_PE4MFP_Pos) |
SYS_T::GPE_MFPL: PE4MFP Mask
Definition at line 24603 of file NUC472_442.h.
| #define SYS_GPE_MFPL_PE4MFP_Pos (16) |
SYS_T::GPE_MFPL: PE4MFP Position
Definition at line 24602 of file NUC472_442.h.
| #define SYS_GPE_MFPL_PE5MFP_Msk (0xful << SYS_GPE_MFPL_PE5MFP_Pos) |
SYS_T::GPE_MFPL: PE5MFP Mask
Definition at line 24606 of file NUC472_442.h.
| #define SYS_GPE_MFPL_PE5MFP_Pos (20) |
SYS_T::GPE_MFPL: PE5MFP Position
Definition at line 24605 of file NUC472_442.h.
| #define SYS_GPE_MFPL_PE6MFP_Msk (0xful << SYS_GPE_MFPL_PE6MFP_Pos) |
SYS_T::GPE_MFPL: PE6MFP Mask
Definition at line 24609 of file NUC472_442.h.
| #define SYS_GPE_MFPL_PE6MFP_Pos (24) |
SYS_T::GPE_MFPL: PE6MFP Position
Definition at line 24608 of file NUC472_442.h.
| #define SYS_GPE_MFPL_PE7MFP_Msk (0xful << SYS_GPE_MFPL_PE7MFP_Pos) |
SYS_T::GPE_MFPL: PE7MFP Mask
Definition at line 24612 of file NUC472_442.h.
| #define SYS_GPE_MFPL_PE7MFP_Pos (28) |
SYS_T::GPE_MFPL: PE7MFP Position
Definition at line 24611 of file NUC472_442.h.
| #define SYS_GPF_MFPH_PF10MFP_Msk (0xful << SYS_GPF_MFPH_PF10MFP_Pos) |
SYS_T::GPF_MFPH: PF10MFP Mask
Definition at line 24669 of file NUC472_442.h.
| #define SYS_GPF_MFPH_PF10MFP_Pos (8) |
SYS_T::GPF_MFPH: PF10MFP Position
Definition at line 24668 of file NUC472_442.h.
| #define SYS_GPF_MFPH_PF11MFP_Msk (0xful << SYS_GPF_MFPH_PF11MFP_Pos) |
SYS_T::GPF_MFPH: PF11MFP Mask
Definition at line 24672 of file NUC472_442.h.
| #define SYS_GPF_MFPH_PF11MFP_Pos (12) |
SYS_T::GPF_MFPH: PF11MFP Position
Definition at line 24671 of file NUC472_442.h.
| #define SYS_GPF_MFPH_PF12MFP_Msk (0xful << SYS_GPF_MFPH_PF12MFP_Pos) |
SYS_T::GPF_MFPH: PF12MFP Mask
Definition at line 24675 of file NUC472_442.h.
| #define SYS_GPF_MFPH_PF12MFP_Pos (16) |
SYS_T::GPF_MFPH: PF12MFP Position
Definition at line 24674 of file NUC472_442.h.
| #define SYS_GPF_MFPH_PF13MFP_Msk (0xful << SYS_GPF_MFPH_PF13MFP_Pos) |
SYS_T::GPF_MFPH: PF13MFP Mask
Definition at line 24678 of file NUC472_442.h.
| #define SYS_GPF_MFPH_PF13MFP_Pos (20) |
SYS_T::GPF_MFPH: PF13MFP Position
Definition at line 24677 of file NUC472_442.h.
| #define SYS_GPF_MFPH_PF14MFP_Msk (0xful << SYS_GPF_MFPH_PF14MFP_Pos) |
SYS_T::GPF_MFPH: PF14MFP Mask
Definition at line 24681 of file NUC472_442.h.
| #define SYS_GPF_MFPH_PF14MFP_Pos (24) |
SYS_T::GPF_MFPH: PF14MFP Position
Definition at line 24680 of file NUC472_442.h.
| #define SYS_GPF_MFPH_PF15MFP_Msk (0xful << SYS_GPF_MFPH_PF15MFP_Pos) |
SYS_T::GPF_MFPH: PF15MFP Mask
Definition at line 24684 of file NUC472_442.h.
| #define SYS_GPF_MFPH_PF15MFP_Pos (28) |
SYS_T::GPF_MFPH: PF15MFP Position
Definition at line 24683 of file NUC472_442.h.
| #define SYS_GPF_MFPH_PF8MFP_Msk (0xful << SYS_GPF_MFPH_PF8MFP_Pos) |
SYS_T::GPF_MFPH: PF8MFP Mask
Definition at line 24663 of file NUC472_442.h.
| #define SYS_GPF_MFPH_PF8MFP_Pos (0) |
SYS_T::GPF_MFPH: PF8MFP Position
Definition at line 24662 of file NUC472_442.h.
| #define SYS_GPF_MFPH_PF9MFP_Msk (0xful << SYS_GPF_MFPH_PF9MFP_Pos) |
SYS_T::GPF_MFPH: PF9MFP Mask
Definition at line 24666 of file NUC472_442.h.
| #define SYS_GPF_MFPH_PF9MFP_Pos (4) |
SYS_T::GPF_MFPH: PF9MFP Position
Definition at line 24665 of file NUC472_442.h.
| #define SYS_GPF_MFPL_PF0MFP_Msk (0xful << SYS_GPF_MFPL_PF0MFP_Pos) |
SYS_T::GPF_MFPL: PF0MFP Mask
Definition at line 24639 of file NUC472_442.h.
| #define SYS_GPF_MFPL_PF0MFP_Pos (0) |
SYS_T::GPF_MFPL: PF0MFP Position
Definition at line 24638 of file NUC472_442.h.
| #define SYS_GPF_MFPL_PF1MFP_Msk (0xful << SYS_GPF_MFPL_PF1MFP_Pos) |
SYS_T::GPF_MFPL: PF1MFP Mask
Definition at line 24642 of file NUC472_442.h.
| #define SYS_GPF_MFPL_PF1MFP_Pos (4) |
SYS_T::GPF_MFPL: PF1MFP Position
Definition at line 24641 of file NUC472_442.h.
| #define SYS_GPF_MFPL_PF2MFP_Msk (0xful << SYS_GPF_MFPL_PF2MFP_Pos) |
SYS_T::GPF_MFPL: PF2MFP Mask
Definition at line 24645 of file NUC472_442.h.
| #define SYS_GPF_MFPL_PF2MFP_Pos (8) |
SYS_T::GPF_MFPL: PF2MFP Position
Definition at line 24644 of file NUC472_442.h.
| #define SYS_GPF_MFPL_PF3MFP_Msk (0xful << SYS_GPF_MFPL_PF3MFP_Pos) |
SYS_T::GPF_MFPL: PF3MFP Mask
Definition at line 24648 of file NUC472_442.h.
| #define SYS_GPF_MFPL_PF3MFP_Pos (12) |
SYS_T::GPF_MFPL: PF3MFP Position
Definition at line 24647 of file NUC472_442.h.
| #define SYS_GPF_MFPL_PF4MFP_Msk (0xful << SYS_GPF_MFPL_PF4MFP_Pos) |
SYS_T::GPF_MFPL: PF4MFP Mask
Definition at line 24651 of file NUC472_442.h.
| #define SYS_GPF_MFPL_PF4MFP_Pos (16) |
SYS_T::GPF_MFPL: PF4MFP Position
Definition at line 24650 of file NUC472_442.h.
| #define SYS_GPF_MFPL_PF5MFP_Msk (0xful << SYS_GPF_MFPL_PF5MFP_Pos) |
SYS_T::GPF_MFPL: PF5MFP Mask
Definition at line 24654 of file NUC472_442.h.
| #define SYS_GPF_MFPL_PF5MFP_Pos (20) |
SYS_T::GPF_MFPL: PF5MFP Position
Definition at line 24653 of file NUC472_442.h.
| #define SYS_GPF_MFPL_PF6MFP_Msk (0xful << SYS_GPF_MFPL_PF6MFP_Pos) |
SYS_T::GPF_MFPL: PF6MFP Mask
Definition at line 24657 of file NUC472_442.h.
| #define SYS_GPF_MFPL_PF6MFP_Pos (24) |
SYS_T::GPF_MFPL: PF6MFP Position
Definition at line 24656 of file NUC472_442.h.
| #define SYS_GPF_MFPL_PF7MFP_Msk (0xful << SYS_GPF_MFPL_PF7MFP_Pos) |
SYS_T::GPF_MFPL: PF7MFP Mask
Definition at line 24660 of file NUC472_442.h.
| #define SYS_GPF_MFPL_PF7MFP_Pos (28) |
SYS_T::GPF_MFPL: PF7MFP Position
Definition at line 24659 of file NUC472_442.h.
| #define SYS_GPG_MFPH_PG10MFP_Msk (0xful << SYS_GPG_MFPH_PG10MFP_Pos) |
SYS_T::GPG_MFPH: PG10MFP Mask
Definition at line 24717 of file NUC472_442.h.
| #define SYS_GPG_MFPH_PG10MFP_Pos (8) |
SYS_T::GPG_MFPH: PG10MFP Position
Definition at line 24716 of file NUC472_442.h.
| #define SYS_GPG_MFPH_PG11MFP_Msk (0xful << SYS_GPG_MFPH_PG11MFP_Pos) |
SYS_T::GPG_MFPH: PG11MFP Mask
Definition at line 24720 of file NUC472_442.h.
| #define SYS_GPG_MFPH_PG11MFP_Pos (12) |
SYS_T::GPG_MFPH: PG11MFP Position
Definition at line 24719 of file NUC472_442.h.
| #define SYS_GPG_MFPH_PG12MFP_Msk (0xful << SYS_GPG_MFPH_PG12MFP_Pos) |
SYS_T::GPG_MFPH: PG12MFP Mask
Definition at line 24723 of file NUC472_442.h.
| #define SYS_GPG_MFPH_PG12MFP_Pos (16) |
SYS_T::GPG_MFPH: PG12MFP Position
Definition at line 24722 of file NUC472_442.h.
| #define SYS_GPG_MFPH_PG13MFP_Msk (0xful << SYS_GPG_MFPH_PG13MFP_Pos) |
SYS_T::GPG_MFPH: PG13MFP Mask
Definition at line 24726 of file NUC472_442.h.
| #define SYS_GPG_MFPH_PG13MFP_Pos (20) |
SYS_T::GPG_MFPH: PG13MFP Position
Definition at line 24725 of file NUC472_442.h.
| #define SYS_GPG_MFPH_PG14MFP_Msk (0xful << SYS_GPG_MFPH_PG14MFP_Pos) |
SYS_T::GPG_MFPH: PG14MFP Mask
Definition at line 24729 of file NUC472_442.h.
| #define SYS_GPG_MFPH_PG14MFP_Pos (24) |
SYS_T::GPG_MFPH: PG14MFP Position
Definition at line 24728 of file NUC472_442.h.
| #define SYS_GPG_MFPH_PG15MFP_Msk (0xful << SYS_GPG_MFPH_PG15MFP_Pos) |
SYS_T::GPG_MFPH: PG15MFP Mask
Definition at line 24732 of file NUC472_442.h.
| #define SYS_GPG_MFPH_PG15MFP_Pos (28) |
SYS_T::GPG_MFPH: PG15MFP Position
Definition at line 24731 of file NUC472_442.h.
| #define SYS_GPG_MFPH_PG8MFP_Msk (0xful << SYS_GPG_MFPH_PG8MFP_Pos) |
SYS_T::GPG_MFPH: PG8MFP Mask
Definition at line 24711 of file NUC472_442.h.
| #define SYS_GPG_MFPH_PG8MFP_Pos (0) |
SYS_T::GPG_MFPH: PG8MFP Position
Definition at line 24710 of file NUC472_442.h.
| #define SYS_GPG_MFPH_PG9MFP_Msk (0xful << SYS_GPG_MFPH_PG9MFP_Pos) |
SYS_T::GPG_MFPH: PG9MFP Mask
Definition at line 24714 of file NUC472_442.h.
| #define SYS_GPG_MFPH_PG9MFP_Pos (4) |
SYS_T::GPG_MFPH: PG9MFP Position
Definition at line 24713 of file NUC472_442.h.
| #define SYS_GPG_MFPL_PG0MFP_Msk (0xful << SYS_GPG_MFPL_PG0MFP_Pos) |
SYS_T::GPG_MFPL: PG0MFP Mask
Definition at line 24687 of file NUC472_442.h.
| #define SYS_GPG_MFPL_PG0MFP_Pos (0) |
SYS_T::GPG_MFPL: PG0MFP Position
Definition at line 24686 of file NUC472_442.h.
| #define SYS_GPG_MFPL_PG1MFP_Msk (0xful << SYS_GPG_MFPL_PG1MFP_Pos) |
SYS_T::GPG_MFPL: PG1MFP Mask
Definition at line 24690 of file NUC472_442.h.
| #define SYS_GPG_MFPL_PG1MFP_Pos (4) |
SYS_T::GPG_MFPL: PG1MFP Position
Definition at line 24689 of file NUC472_442.h.
| #define SYS_GPG_MFPL_PG2MFP_Msk (0xful << SYS_GPG_MFPL_PG2MFP_Pos) |
SYS_T::GPG_MFPL: PG2MFP Mask
Definition at line 24693 of file NUC472_442.h.
| #define SYS_GPG_MFPL_PG2MFP_Pos (8) |
SYS_T::GPG_MFPL: PG2MFP Position
Definition at line 24692 of file NUC472_442.h.
| #define SYS_GPG_MFPL_PG3MFP_Msk (0xful << SYS_GPG_MFPL_PG3MFP_Pos) |
SYS_T::GPG_MFPL: PG3MFP Mask
Definition at line 24696 of file NUC472_442.h.
| #define SYS_GPG_MFPL_PG3MFP_Pos (12) |
SYS_T::GPG_MFPL: PG3MFP Position
Definition at line 24695 of file NUC472_442.h.
| #define SYS_GPG_MFPL_PG4MFP_Msk (0xful << SYS_GPG_MFPL_PG4MFP_Pos) |
SYS_T::GPG_MFPL: PG4MFP Mask
Definition at line 24699 of file NUC472_442.h.
| #define SYS_GPG_MFPL_PG4MFP_Pos (16) |
SYS_T::GPG_MFPL: PG4MFP Position
Definition at line 24698 of file NUC472_442.h.
| #define SYS_GPG_MFPL_PG5MFP_Msk (0xful << SYS_GPG_MFPL_PG5MFP_Pos) |
SYS_T::GPG_MFPL: PG5MFP Mask
Definition at line 24702 of file NUC472_442.h.
| #define SYS_GPG_MFPL_PG5MFP_Pos (20) |
SYS_T::GPG_MFPL: PG5MFP Position
Definition at line 24701 of file NUC472_442.h.
| #define SYS_GPG_MFPL_PG6MFP_Msk (0xful << SYS_GPG_MFPL_PG6MFP_Pos) |
SYS_T::GPG_MFPL: PG6MFP Mask
Definition at line 24705 of file NUC472_442.h.
| #define SYS_GPG_MFPL_PG6MFP_Pos (24) |
SYS_T::GPG_MFPL: PG6MFP Position
Definition at line 24704 of file NUC472_442.h.
| #define SYS_GPG_MFPL_PG7MFP_Msk (0xful << SYS_GPG_MFPL_PG7MFP_Pos) |
SYS_T::GPG_MFPL: PG7MFP Mask
Definition at line 24708 of file NUC472_442.h.
| #define SYS_GPG_MFPL_PG7MFP_Pos (28) |
SYS_T::GPG_MFPL: PG7MFP Position
Definition at line 24707 of file NUC472_442.h.
| #define SYS_GPH_MFPH_PH10MFP_Msk (0xful << SYS_GPH_MFPH_PH10MFP_Pos) |
SYS_T::GPH_MFPH: PH10MFP Mask
Definition at line 24765 of file NUC472_442.h.
| #define SYS_GPH_MFPH_PH10MFP_Pos (8) |
SYS_T::GPH_MFPH: PH10MFP Position
Definition at line 24764 of file NUC472_442.h.
| #define SYS_GPH_MFPH_PH11MFP_Msk (0xful << SYS_GPH_MFPH_PH11MFP_Pos) |
SYS_T::GPH_MFPH: PH11MFP Mask
Definition at line 24768 of file NUC472_442.h.
| #define SYS_GPH_MFPH_PH11MFP_Pos (12) |
SYS_T::GPH_MFPH: PH11MFP Position
Definition at line 24767 of file NUC472_442.h.
| #define SYS_GPH_MFPH_PH12MFP_Msk (0xful << SYS_GPH_MFPH_PH12MFP_Pos) |
SYS_T::GPH_MFPH: PH12MFP Mask
Definition at line 24771 of file NUC472_442.h.
| #define SYS_GPH_MFPH_PH12MFP_Pos (16) |
SYS_T::GPH_MFPH: PH12MFP Position
Definition at line 24770 of file NUC472_442.h.
| #define SYS_GPH_MFPH_PH13MFP_Msk (0xful << SYS_GPH_MFPH_PH13MFP_Pos) |
SYS_T::GPH_MFPH: PH13MFP Mask
Definition at line 24774 of file NUC472_442.h.
| #define SYS_GPH_MFPH_PH13MFP_Pos (20) |
SYS_T::GPH_MFPH: PH13MFP Position
Definition at line 24773 of file NUC472_442.h.
| #define SYS_GPH_MFPH_PH14MFP_Msk (0xful << SYS_GPH_MFPH_PH14MFP_Pos) |
SYS_T::GPH_MFPH: PH14MFP Mask
Definition at line 24777 of file NUC472_442.h.
| #define SYS_GPH_MFPH_PH14MFP_Pos (24) |
SYS_T::GPH_MFPH: PH14MFP Position
Definition at line 24776 of file NUC472_442.h.
| #define SYS_GPH_MFPH_PH15MFP_Msk (0xful << SYS_GPH_MFPH_PH15MFP_Pos) |
SYS_T::GPH_MFPH: PH15MFP Mask
Definition at line 24780 of file NUC472_442.h.
| #define SYS_GPH_MFPH_PH15MFP_Pos (28) |
SYS_T::GPH_MFPH: PH15MFP Position
Definition at line 24779 of file NUC472_442.h.
| #define SYS_GPH_MFPH_PH8MFP_Msk (0xful << SYS_GPH_MFPH_PH8MFP_Pos) |
SYS_T::GPH_MFPH: PH8MFP Mask
Definition at line 24759 of file NUC472_442.h.
| #define SYS_GPH_MFPH_PH8MFP_Pos (0) |
SYS_T::GPH_MFPH: PH8MFP Position
Definition at line 24758 of file NUC472_442.h.
| #define SYS_GPH_MFPH_PH9MFP_Msk (0xful << SYS_GPH_MFPH_PH9MFP_Pos) |
SYS_T::GPH_MFPH: PH9MFP Mask
Definition at line 24762 of file NUC472_442.h.
| #define SYS_GPH_MFPH_PH9MFP_Pos (4) |
SYS_T::GPH_MFPH: PH9MFP Position
Definition at line 24761 of file NUC472_442.h.
| #define SYS_GPH_MFPL_PH0MFP_Msk (0xful << SYS_GPH_MFPL_PH0MFP_Pos) |
SYS_T::GPH_MFPL: PH0MFP Mask
Definition at line 24735 of file NUC472_442.h.
| #define SYS_GPH_MFPL_PH0MFP_Pos (0) |
SYS_T::GPH_MFPL: PH0MFP Position
Definition at line 24734 of file NUC472_442.h.
| #define SYS_GPH_MFPL_PH1MFP_Msk (0xful << SYS_GPH_MFPL_PH1MFP_Pos) |
SYS_T::GPH_MFPL: PH1MFP Mask
Definition at line 24738 of file NUC472_442.h.
| #define SYS_GPH_MFPL_PH1MFP_Pos (4) |
SYS_T::GPH_MFPL: PH1MFP Position
Definition at line 24737 of file NUC472_442.h.
| #define SYS_GPH_MFPL_PH2MFP_Msk (0xful << SYS_GPH_MFPL_PH2MFP_Pos) |
SYS_T::GPH_MFPL: PH2MFP Mask
Definition at line 24741 of file NUC472_442.h.
| #define SYS_GPH_MFPL_PH2MFP_Pos (8) |
SYS_T::GPH_MFPL: PH2MFP Position
Definition at line 24740 of file NUC472_442.h.
| #define SYS_GPH_MFPL_PH3MFP_Msk (0xful << SYS_GPH_MFPL_PH3MFP_Pos) |
SYS_T::GPH_MFPL: PH3MFP Mask
Definition at line 24744 of file NUC472_442.h.
| #define SYS_GPH_MFPL_PH3MFP_Pos (12) |
SYS_T::GPH_MFPL: PH3MFP Position
Definition at line 24743 of file NUC472_442.h.
| #define SYS_GPH_MFPL_PH4MFP_Msk (0xful << SYS_GPH_MFPL_PH4MFP_Pos) |
SYS_T::GPH_MFPL: PH4MFP Mask
Definition at line 24747 of file NUC472_442.h.
| #define SYS_GPH_MFPL_PH4MFP_Pos (16) |
SYS_T::GPH_MFPL: PH4MFP Position
Definition at line 24746 of file NUC472_442.h.
| #define SYS_GPH_MFPL_PH5MFP_Msk (0xful << SYS_GPH_MFPL_PH5MFP_Pos) |
SYS_T::GPH_MFPL: PH5MFP Mask
Definition at line 24750 of file NUC472_442.h.
| #define SYS_GPH_MFPL_PH5MFP_Pos (20) |
SYS_T::GPH_MFPL: PH5MFP Position
Definition at line 24749 of file NUC472_442.h.
| #define SYS_GPH_MFPL_PH6MFP_Msk (0xful << SYS_GPH_MFPL_PH6MFP_Pos) |
SYS_T::GPH_MFPL: PH6MFP Mask
Definition at line 24753 of file NUC472_442.h.
| #define SYS_GPH_MFPL_PH6MFP_Pos (24) |
SYS_T::GPH_MFPL: PH6MFP Position
Definition at line 24752 of file NUC472_442.h.
| #define SYS_GPH_MFPL_PH7MFP_Msk (0xful << SYS_GPH_MFPL_PH7MFP_Pos) |
SYS_T::GPH_MFPL: PH7MFP Mask
Definition at line 24756 of file NUC472_442.h.
| #define SYS_GPH_MFPL_PH7MFP_Pos (28) |
SYS_T::GPH_MFPL: PH7MFP Position
Definition at line 24755 of file NUC472_442.h.
| #define SYS_GPI_MFPH_PI10MFP_Msk (0xful << SYS_GPI_MFPH_PI10MFP_Pos) |
SYS_T::GPI_MFPH: PI10MFP Mask
Definition at line 24813 of file NUC472_442.h.
| #define SYS_GPI_MFPH_PI10MFP_Pos (8) |
SYS_T::GPI_MFPH: PI10MFP Position
Definition at line 24812 of file NUC472_442.h.
| #define SYS_GPI_MFPH_PI11MFP_Msk (0xful << SYS_GPI_MFPH_PI11MFP_Pos) |
SYS_T::GPI_MFPH: PI11MFP Mask
Definition at line 24816 of file NUC472_442.h.
| #define SYS_GPI_MFPH_PI11MFP_Pos (12) |
SYS_T::GPI_MFPH: PI11MFP Position
Definition at line 24815 of file NUC472_442.h.
| #define SYS_GPI_MFPH_PI12MFP_Msk (0xful << SYS_GPI_MFPH_PI12MFP_Pos) |
SYS_T::GPI_MFPH: PI12MFP Mask
Definition at line 24819 of file NUC472_442.h.
| #define SYS_GPI_MFPH_PI12MFP_Pos (16) |
SYS_T::GPI_MFPH: PI12MFP Position
Definition at line 24818 of file NUC472_442.h.
| #define SYS_GPI_MFPH_PI13MFP_Msk (0xful << SYS_GPI_MFPH_PI13MFP_Pos) |
SYS_T::GPI_MFPH: PI13MFP Mask
Definition at line 24822 of file NUC472_442.h.
| #define SYS_GPI_MFPH_PI13MFP_Pos (20) |
SYS_T::GPI_MFPH: PI13MFP Position
Definition at line 24821 of file NUC472_442.h.
| #define SYS_GPI_MFPH_PI14MFP_Msk (0xful << SYS_GPI_MFPH_PI14MFP_Pos) |
SYS_T::GPI_MFPH: PI14MFP Mask
Definition at line 24825 of file NUC472_442.h.
| #define SYS_GPI_MFPH_PI14MFP_Pos (24) |
SYS_T::GPI_MFPH: PI14MFP Position
Definition at line 24824 of file NUC472_442.h.
| #define SYS_GPI_MFPH_PI15MFP_Msk (0xful << SYS_GPI_MFPH_PI15MFP_Pos) |
SYS_T::GPI_MFPH: PI15MFP Mask
Definition at line 24828 of file NUC472_442.h.
| #define SYS_GPI_MFPH_PI15MFP_Pos (28) |
SYS_T::GPI_MFPH: PI15MFP Position
Definition at line 24827 of file NUC472_442.h.
| #define SYS_GPI_MFPH_PI8MFP_Msk (0xful << SYS_GPI_MFPH_PI8MFP_Pos) |
SYS_T::GPI_MFPH: PI8MFP Mask
Definition at line 24807 of file NUC472_442.h.
| #define SYS_GPI_MFPH_PI8MFP_Pos (0) |
SYS_T::GPI_MFPH: PI8MFP Position
Definition at line 24806 of file NUC472_442.h.
| #define SYS_GPI_MFPH_PI9MFP_Msk (0xful << SYS_GPI_MFPH_PI9MFP_Pos) |
SYS_T::GPI_MFPH: PI9MFP Mask
Definition at line 24810 of file NUC472_442.h.
| #define SYS_GPI_MFPH_PI9MFP_Pos (4) |
SYS_T::GPI_MFPH: PI9MFP Position
Definition at line 24809 of file NUC472_442.h.
| #define SYS_GPI_MFPL_PI0MFP_Msk (0xful << SYS_GPI_MFPL_PI0MFP_Pos) |
SYS_T::GPI_MFPL: PI0MFP Mask
Definition at line 24783 of file NUC472_442.h.
| #define SYS_GPI_MFPL_PI0MFP_Pos (0) |
SYS_T::GPI_MFPL: PI0MFP Position
Definition at line 24782 of file NUC472_442.h.
| #define SYS_GPI_MFPL_PI1MFP_Msk (0xful << SYS_GPI_MFPL_PI1MFP_Pos) |
SYS_T::GPI_MFPL: PI1MFP Mask
Definition at line 24786 of file NUC472_442.h.
| #define SYS_GPI_MFPL_PI1MFP_Pos (4) |
SYS_T::GPI_MFPL: PI1MFP Position
Definition at line 24785 of file NUC472_442.h.
| #define SYS_GPI_MFPL_PI2MFP_Msk (0xful << SYS_GPI_MFPL_PI2MFP_Pos) |
SYS_T::GPI_MFPL: PI2MFP Mask
Definition at line 24789 of file NUC472_442.h.
| #define SYS_GPI_MFPL_PI2MFP_Pos (8) |
SYS_T::GPI_MFPL: PI2MFP Position
Definition at line 24788 of file NUC472_442.h.
| #define SYS_GPI_MFPL_PI3MFP_Msk (0xful << SYS_GPI_MFPL_PI3MFP_Pos) |
SYS_T::GPI_MFPL: PI3MFP Mask
Definition at line 24792 of file NUC472_442.h.
| #define SYS_GPI_MFPL_PI3MFP_Pos (12) |
SYS_T::GPI_MFPL: PI3MFP Position
Definition at line 24791 of file NUC472_442.h.
| #define SYS_GPI_MFPL_PI4MFP_Msk (0xful << SYS_GPI_MFPL_PI4MFP_Pos) |
SYS_T::GPI_MFPL: PI4MFP Mask
Definition at line 24795 of file NUC472_442.h.
| #define SYS_GPI_MFPL_PI4MFP_Pos (16) |
SYS_T::GPI_MFPL: PI4MFP Position
Definition at line 24794 of file NUC472_442.h.
| #define SYS_GPI_MFPL_PI5MFP_Msk (0xful << SYS_GPI_MFPL_PI5MFP_Pos) |
SYS_T::GPI_MFPL: PI5MFP Mask
Definition at line 24798 of file NUC472_442.h.
| #define SYS_GPI_MFPL_PI5MFP_Pos (20) |
SYS_T::GPI_MFPL: PI5MFP Position
Definition at line 24797 of file NUC472_442.h.
| #define SYS_GPI_MFPL_PI6MFP_Msk (0xful << SYS_GPI_MFPL_PI6MFP_Pos) |
SYS_T::GPI_MFPL: PI6MFP Mask
Definition at line 24801 of file NUC472_442.h.
| #define SYS_GPI_MFPL_PI6MFP_Pos (24) |
SYS_T::GPI_MFPL: PI6MFP Position
Definition at line 24800 of file NUC472_442.h.
| #define SYS_GPI_MFPL_PI7MFP_Msk (0xful << SYS_GPI_MFPL_PI7MFP_Pos) |
SYS_T::GPI_MFPL: PI7MFP Mask
Definition at line 24804 of file NUC472_442.h.
| #define SYS_GPI_MFPL_PI7MFP_Pos (28) |
SYS_T::GPI_MFPL: PI7MFP Position
Definition at line 24803 of file NUC472_442.h.
| #define SYS_IPRST0_CAPRST_Msk (0x1ul << SYS_IPRST0_CAPRST_Pos) |
SYS_T::IPRST0: CAPRST Mask
Definition at line 24234 of file NUC472_442.h.
| #define SYS_IPRST0_CAPRST_Pos (8) |
SYS_T::IPRST0: CAPRST Position
Definition at line 24233 of file NUC472_442.h.
| #define SYS_IPRST0_CHIPRST_Msk (0x1ul << SYS_IPRST0_CHIPRST_Pos) |
SYS_T::IPRST0: CHIPRST Mask
Definition at line 24210 of file NUC472_442.h.
| #define SYS_IPRST0_CHIPRST_Pos (0) |
SYS_T::IPRST0: CHIPRST Position
Definition at line 24209 of file NUC472_442.h.
| #define SYS_IPRST0_CPURST_Msk (0x1ul << SYS_IPRST0_CPURST_Pos) |
SYS_T::IPRST0: CPURST Mask
Definition at line 24213 of file NUC472_442.h.
| #define SYS_IPRST0_CPURST_Pos (1) |
SYS_T::IPRST0: CPURST Position
Definition at line 24212 of file NUC472_442.h.
| #define SYS_IPRST0_CRCRST_Msk (0x1ul << SYS_IPRST0_CRCRST_Pos) |
SYS_T::IPRST0: CRCRST Mask
Definition at line 24231 of file NUC472_442.h.
| #define SYS_IPRST0_CRCRST_Pos (7) |
SYS_T::IPRST0: CRCRST Position
Definition at line 24230 of file NUC472_442.h.
| #define SYS_IPRST0_CRPTRST_Msk (0x1ul << SYS_IPRST0_CRPTRST_Pos) |
SYS_T::IPRST0: CRPTRST Mask
Definition at line 24237 of file NUC472_442.h.
| #define SYS_IPRST0_CRPTRST_Pos (12) |
SYS_T::IPRST0: CRPTRST Position
Definition at line 24236 of file NUC472_442.h.
| #define SYS_IPRST0_EBIRST_Msk (0x1ul << SYS_IPRST0_EBIRST_Pos) |
SYS_T::IPRST0: EBIRST Mask
Definition at line 24219 of file NUC472_442.h.
| #define SYS_IPRST0_EBIRST_Pos (3) |
SYS_T::IPRST0: EBIRST Position
Definition at line 24218 of file NUC472_442.h.
| #define SYS_IPRST0_EMACRST_Msk (0x1ul << SYS_IPRST0_EMACRST_Pos) |
SYS_T::IPRST0: EMACRST Mask
Definition at line 24225 of file NUC472_442.h.
| #define SYS_IPRST0_EMACRST_Pos (5) |
SYS_T::IPRST0: EMACRST Position
Definition at line 24224 of file NUC472_442.h.
| #define SYS_IPRST0_PDMARST_Msk (0x1ul << SYS_IPRST0_PDMARST_Pos) |
SYS_T::IPRST0: PDMARST Mask
Definition at line 24216 of file NUC472_442.h.
| #define SYS_IPRST0_PDMARST_Pos (2) |
SYS_T::IPRST0: PDMARST Position
Definition at line 24215 of file NUC472_442.h.
| #define SYS_IPRST0_SDHRST_Msk (0x1ul << SYS_IPRST0_SDHRST_Pos) |
SYS_T::IPRST0: SDHRST Mask
Definition at line 24228 of file NUC472_442.h.
| #define SYS_IPRST0_SDHRST_Pos (6) |
SYS_T::IPRST0: SDHRST Position
Definition at line 24227 of file NUC472_442.h.
| #define SYS_IPRST0_USBHRST_Msk (0x1ul << SYS_IPRST0_USBHRST_Pos) |
SYS_T::IPRST0: USBHRST Mask
Definition at line 24222 of file NUC472_442.h.
| #define SYS_IPRST0_USBHRST_Pos (4) |
SYS_T::IPRST0: USBHRST Position
Definition at line 24221 of file NUC472_442.h.
| #define SYS_IPRST1_ACMPRST_Msk (0x1ul << SYS_IPRST1_ACMPRST_Pos) |
SYS_T::IPRST1: ACMPRST Mask
Definition at line 24255 of file NUC472_442.h.
| #define SYS_IPRST1_ACMPRST_Pos (7) |
SYS_T::IPRST1: ACMPRST Position
Definition at line 24254 of file NUC472_442.h.
| #define SYS_IPRST1_ADCRST_Msk (0x1ul << SYS_IPRST1_ADCRST_Pos) |
SYS_T::IPRST1: ADCRST Mask
Definition at line 24309 of file NUC472_442.h.
| #define SYS_IPRST1_ADCRST_Pos (28) |
SYS_T::IPRST1: ADCRST Position
Definition at line 24308 of file NUC472_442.h.
| #define SYS_IPRST1_CAN0RST_Msk (0x1ul << SYS_IPRST1_CAN0RST_Pos) |
SYS_T::IPRST1: CAN0RST Mask
Definition at line 24300 of file NUC472_442.h.
| #define SYS_IPRST1_CAN0RST_Pos (24) |
SYS_T::IPRST1: CAN0RST Position
Definition at line 24299 of file NUC472_442.h.
| #define SYS_IPRST1_CAN1RST_Msk (0x1ul << SYS_IPRST1_CAN1RST_Pos) |
SYS_T::IPRST1: CAN1RST Mask
Definition at line 24303 of file NUC472_442.h.
| #define SYS_IPRST1_CAN1RST_Pos (25) |
SYS_T::IPRST1: CAN1RST Position
Definition at line 24302 of file NUC472_442.h.
| #define SYS_IPRST1_GPIORST_Msk (0x1ul << SYS_IPRST1_GPIORST_Pos) |
SYS_T::IPRST1: GPIORST Mask
Definition at line 24240 of file NUC472_442.h.
| #define SYS_IPRST1_GPIORST_Pos (1) |
SYS_T::IPRST1: GPIORST Position
Definition at line 24239 of file NUC472_442.h.
| #define SYS_IPRST1_I2C0RST_Msk (0x1ul << SYS_IPRST1_I2C0RST_Pos) |
SYS_T::IPRST1: I2C0RST Mask
Definition at line 24258 of file NUC472_442.h.
| #define SYS_IPRST1_I2C0RST_Pos (8) |
SYS_T::IPRST1: I2C0RST Position
Definition at line 24257 of file NUC472_442.h.
| #define SYS_IPRST1_I2C1RST_Msk (0x1ul << SYS_IPRST1_I2C1RST_Pos) |
SYS_T::IPRST1: I2C1RST Mask
Definition at line 24261 of file NUC472_442.h.
| #define SYS_IPRST1_I2C1RST_Pos (9) |
SYS_T::IPRST1: I2C1RST Position
Definition at line 24260 of file NUC472_442.h.
| #define SYS_IPRST1_I2C2RST_Msk (0x1ul << SYS_IPRST1_I2C2RST_Pos) |
SYS_T::IPRST1: I2C2RST Mask
Definition at line 24264 of file NUC472_442.h.
| #define SYS_IPRST1_I2C2RST_Pos (10) |
SYS_T::IPRST1: I2C2RST Position
Definition at line 24263 of file NUC472_442.h.
| #define SYS_IPRST1_I2C3RST_Msk (0x1ul << SYS_IPRST1_I2C3RST_Pos) |
SYS_T::IPRST1: I2C3RST Mask
Definition at line 24267 of file NUC472_442.h.
| #define SYS_IPRST1_I2C3RST_Pos (11) |
SYS_T::IPRST1: I2C3RST Position
Definition at line 24266 of file NUC472_442.h.
| #define SYS_IPRST1_I2S0RST_Msk (0x1ul << SYS_IPRST1_I2S0RST_Pos) |
SYS_T::IPRST1: I2SRST Mask
Definition at line 24312 of file NUC472_442.h.
| #define SYS_IPRST1_I2S0RST_Pos (29) |
SYS_T::IPRST1: I2SRST Position
Definition at line 24311 of file NUC472_442.h.
| #define SYS_IPRST1_I2S1RST_Msk (0x1ul << SYS_IPRST1_I2S1RST_Pos) |
SYS_T::IPRST1: I2S1RST Mask
Definition at line 24315 of file NUC472_442.h.
| #define SYS_IPRST1_I2S1RST_Pos (30) |
SYS_T::IPRST1: I2S1RST Position
Definition at line 24314 of file NUC472_442.h.
| #define SYS_IPRST1_PS2RST_Msk (0x1ul << SYS_IPRST1_PS2RST_Pos) |
SYS_T::IPRST1: PS2RST Mask
Definition at line 24318 of file NUC472_442.h.
| #define SYS_IPRST1_PS2RST_Pos (31) |
SYS_T::IPRST1: PS2RST Position
Definition at line 24317 of file NUC472_442.h.
| #define SYS_IPRST1_SPI0RST_Msk (0x1ul << SYS_IPRST1_SPI0RST_Pos) |
SYS_T::IPRST1: SPI0RST Mask
Definition at line 24270 of file NUC472_442.h.
| #define SYS_IPRST1_SPI0RST_Pos (12) |
SYS_T::IPRST1: SPI0RST Position
Definition at line 24269 of file NUC472_442.h.
| #define SYS_IPRST1_SPI1RST_Msk (0x1ul << SYS_IPRST1_SPI1RST_Pos) |
SYS_T::IPRST1: SPI1RST Mask
Definition at line 24273 of file NUC472_442.h.
| #define SYS_IPRST1_SPI1RST_Pos (13) |
SYS_T::IPRST1: SPI1RST Position
Definition at line 24272 of file NUC472_442.h.
| #define SYS_IPRST1_SPI2RST_Msk (0x1ul << SYS_IPRST1_SPI2RST_Pos) |
SYS_T::IPRST1: SPI2RST Mask
Definition at line 24276 of file NUC472_442.h.
| #define SYS_IPRST1_SPI2RST_Pos (14) |
SYS_T::IPRST1: SPI2RST Position
Definition at line 24275 of file NUC472_442.h.
| #define SYS_IPRST1_SPI3RST_Msk (0x1ul << SYS_IPRST1_SPI3RST_Pos) |
SYS_T::IPRST1: SPI3RST Mask
Definition at line 24279 of file NUC472_442.h.
| #define SYS_IPRST1_SPI3RST_Pos (15) |
SYS_T::IPRST1: SPI3RST Position
Definition at line 24278 of file NUC472_442.h.
| #define SYS_IPRST1_TMR0RST_Msk (0x1ul << SYS_IPRST1_TMR0RST_Pos) |
SYS_T::IPRST1: TMR0RST Mask
Definition at line 24243 of file NUC472_442.h.
| #define SYS_IPRST1_TMR0RST_Pos (2) |
SYS_T::IPRST1: TMR0RST Position
Definition at line 24242 of file NUC472_442.h.
| #define SYS_IPRST1_TMR1RST_Msk (0x1ul << SYS_IPRST1_TMR1RST_Pos) |
SYS_T::IPRST1: TMR1RST Mask
Definition at line 24246 of file NUC472_442.h.
| #define SYS_IPRST1_TMR1RST_Pos (3) |
SYS_T::IPRST1: TMR1RST Position
Definition at line 24245 of file NUC472_442.h.
| #define SYS_IPRST1_TMR2RST_Msk (0x1ul << SYS_IPRST1_TMR2RST_Pos) |
SYS_T::IPRST1: TMR2RST Mask
Definition at line 24249 of file NUC472_442.h.
| #define SYS_IPRST1_TMR2RST_Pos (4) |
SYS_T::IPRST1: TMR2RST Position
Definition at line 24248 of file NUC472_442.h.
| #define SYS_IPRST1_TMR3RST_Msk (0x1ul << SYS_IPRST1_TMR3RST_Pos) |
SYS_T::IPRST1: TMR3RST Mask
Definition at line 24252 of file NUC472_442.h.
| #define SYS_IPRST1_TMR3RST_Pos (5) |
SYS_T::IPRST1: TMR3RST Position
Definition at line 24251 of file NUC472_442.h.
| #define SYS_IPRST1_UART0RST_Msk (0x1ul << SYS_IPRST1_UART0RST_Pos) |
SYS_T::IPRST1: UART0RST Mask
Definition at line 24282 of file NUC472_442.h.
| #define SYS_IPRST1_UART0RST_Pos (16) |
SYS_T::IPRST1: UART0RST Position
Definition at line 24281 of file NUC472_442.h.
| #define SYS_IPRST1_UART1RST_Msk (0x1ul << SYS_IPRST1_UART1RST_Pos) |
SYS_T::IPRST1: UART1RST Mask
Definition at line 24285 of file NUC472_442.h.
| #define SYS_IPRST1_UART1RST_Pos (17) |
SYS_T::IPRST1: UART1RST Position
Definition at line 24284 of file NUC472_442.h.
| #define SYS_IPRST1_UART2RST_Msk (0x1ul << SYS_IPRST1_UART2RST_Pos) |
SYS_T::IPRST1: UART2RST Mask
Definition at line 24288 of file NUC472_442.h.
| #define SYS_IPRST1_UART2RST_Pos (18) |
SYS_T::IPRST1: UART2RST Position
Definition at line 24287 of file NUC472_442.h.
| #define SYS_IPRST1_UART3RST_Msk (0x1ul << SYS_IPRST1_UART3RST_Pos) |
SYS_T::IPRST1: UART3RST Mask
Definition at line 24291 of file NUC472_442.h.
| #define SYS_IPRST1_UART3RST_Pos (19) |
SYS_T::IPRST1: UART3RST Position
Definition at line 24290 of file NUC472_442.h.
| #define SYS_IPRST1_UART4RST_Msk (0x1ul << SYS_IPRST1_UART4RST_Pos) |
SYS_T::IPRST1: UART4RST Mask
Definition at line 24294 of file NUC472_442.h.
| #define SYS_IPRST1_UART4RST_Pos (20) |
SYS_T::IPRST1: UART4RST Position
Definition at line 24293 of file NUC472_442.h.
| #define SYS_IPRST1_UART5RST_Msk (0x1ul << SYS_IPRST1_UART5RST_Pos) |
SYS_T::IPRST1: UART5RST Mask
Definition at line 24297 of file NUC472_442.h.
| #define SYS_IPRST1_UART5RST_Pos (21) |
SYS_T::IPRST1: UART5RST Position
Definition at line 24296 of file NUC472_442.h.
| #define SYS_IPRST1_USBDRST_Msk (0x1ul << SYS_IPRST1_USBDRST_Pos) |
SYS_T::IPRST1: USBDRST Mask
Definition at line 24306 of file NUC472_442.h.
| #define SYS_IPRST1_USBDRST_Pos (27) |
SYS_T::IPRST1: USBDRST Position
Definition at line 24305 of file NUC472_442.h.
| #define SYS_IPRST2_I2C4RST_Msk (0x1ul << SYS_IPRST2_I2C4RST_Pos) |
SYS_T::IPRST2: I2C4RST Mask
Definition at line 24339 of file NUC472_442.h.
| #define SYS_IPRST2_I2C4RST_Pos (8) |
SYS_T::IPRST2: I2C4RST Position
Definition at line 24338 of file NUC472_442.h.
| #define SYS_IPRST2_PWM0RST_Msk (0x1ul << SYS_IPRST2_PWM0RST_Pos) |
SYS_T::IPRST2: PWM0RST Mask
Definition at line 24342 of file NUC472_442.h.
| #define SYS_IPRST2_PWM0RST_Pos (16) |
SYS_T::IPRST2: PWM0RST Position
Definition at line 24341 of file NUC472_442.h.
| #define SYS_IPRST2_PWM1RST_Msk (0x1ul << SYS_IPRST2_PWM1RST_Pos) |
SYS_T::IPRST2: PWM1RST Mask
Definition at line 24345 of file NUC472_442.h.
| #define SYS_IPRST2_PWM1RST_Pos (17) |
SYS_T::IPRST2: PWM1RST Position
Definition at line 24344 of file NUC472_442.h.
| #define SYS_IPRST2_QEI0RST_Msk (0x1ul << SYS_IPRST2_QEI0RST_Pos) |
SYS_T::IPRST2: QEI0RST Mask
Definition at line 24348 of file NUC472_442.h.
| #define SYS_IPRST2_QEI0RST_Pos (22) |
SYS_T::IPRST2: QEI0RST Position
Definition at line 24347 of file NUC472_442.h.
| #define SYS_IPRST2_QEI1RST_Msk (0x1ul << SYS_IPRST2_QEI1RST_Pos) |
SYS_T::IPRST2: QEI1RST Mask
Definition at line 24351 of file NUC472_442.h.
| #define SYS_IPRST2_QEI1RST_Pos (23) |
SYS_T::IPRST2: QEI1RST Position
Definition at line 24350 of file NUC472_442.h.
| #define SYS_IPRST2_SC0RST_Msk (0x1ul << SYS_IPRST2_SC0RST_Pos) |
SYS_T::IPRST2: SC0RST Mask
Definition at line 24321 of file NUC472_442.h.
| #define SYS_IPRST2_SC0RST_Pos (0) |
SYS_T::IPRST2: SC0RST Position
Definition at line 24320 of file NUC472_442.h.
| #define SYS_IPRST2_SC1RST_Msk (0x1ul << SYS_IPRST2_SC1RST_Pos) |
SYS_T::IPRST2: SC1RST Mask
Definition at line 24324 of file NUC472_442.h.
| #define SYS_IPRST2_SC1RST_Pos (1) |
SYS_T::IPRST2: SC1RST Position
Definition at line 24323 of file NUC472_442.h.
| #define SYS_IPRST2_SC2RST_Msk (0x1ul << SYS_IPRST2_SC2RST_Pos) |
SYS_T::IPRST2: SC2RST Mask
Definition at line 24327 of file NUC472_442.h.
| #define SYS_IPRST2_SC2RST_Pos (2) |
SYS_T::IPRST2: SC2RST Position
Definition at line 24326 of file NUC472_442.h.
| #define SYS_IPRST2_SC3RST_Msk (0x1ul << SYS_IPRST2_SC3RST_Pos) |
SYS_T::IPRST2: SC3RST Mask
Definition at line 24330 of file NUC472_442.h.
| #define SYS_IPRST2_SC3RST_Pos (3) |
SYS_T::IPRST2: SC3RST Position
Definition at line 24329 of file NUC472_442.h.
| #define SYS_IPRST2_SC4RST_Msk (0x1ul << SYS_IPRST2_SC4RST_Pos) |
SYS_T::IPRST2: SC4RST Mask
Definition at line 24333 of file NUC472_442.h.
| #define SYS_IPRST2_SC4RST_Pos (4) |
SYS_T::IPRST2: SC4RST Position
Definition at line 24332 of file NUC472_442.h.
| #define SYS_IPRST2_SC5RST_Msk (0x1ul << SYS_IPRST2_SC5RST_Pos) |
SYS_T::IPRST2: SC5RST Mask
Definition at line 24336 of file NUC472_442.h.
| #define SYS_IPRST2_SC5RST_Pos (5) |
SYS_T::IPRST2: SC5RST Position
Definition at line 24335 of file NUC472_442.h.
| #define SYS_IRCTCTL_CALCLOOP_Msk (0x3ul << SYS_IRCTCTL_CALCLOOP_Pos) |
SYS_T::IRCTCTL: CALCLOOP Mask
Definition at line 24849 of file NUC472_442.h.
| #define SYS_IRCTCTL_CALCLOOP_Pos (4) |
SYS_T::IRCTCTL: CALCLOOP Position
Definition at line 24848 of file NUC472_442.h.
| #define SYS_IRCTCTL_CESTOPEN_Msk (0x1ul << SYS_IRCTCTL_CESTOPEN_Pos) |
SYS_T::IRCTCTL: CESTOPEN Mask
Definition at line 24855 of file NUC472_442.h.
| #define SYS_IRCTCTL_CESTOPEN_Pos (8) |
SYS_T::IRCTCTL: CESTOPEN Position
Definition at line 24854 of file NUC472_442.h.
| #define SYS_IRCTCTL_FREQSEL_Msk (0x3ul << SYS_IRCTCTL_FREQSEL_Pos) |
SYS_T::IRCTCTL: FREQSEL Mask
Definition at line 24846 of file NUC472_442.h.
| #define SYS_IRCTCTL_FREQSEL_Pos (0) |
SYS_T::IRCTCTL: FREQSEL Position
Definition at line 24845 of file NUC472_442.h.
| #define SYS_IRCTCTL_RETRYCNT_Msk (0x3ul << SYS_IRCTCTL_RETRYCNT_Pos) |
SYS_T::IRCTCTL: RETRYCNT Mask
Definition at line 24852 of file NUC472_442.h.
| #define SYS_IRCTCTL_RETRYCNT_Pos (6) |
SYS_T::IRCTCTL: RETRYCNT Position
Definition at line 24851 of file NUC472_442.h.
| #define SYS_IRCTIEN_CLKEIEN_Msk (0x1ul << SYS_IRCTIEN_CLKEIEN_Pos) |
SYS_T::IRCTIEN: CLKEIEN Mask
Definition at line 24861 of file NUC472_442.h.
| #define SYS_IRCTIEN_CLKEIEN_Pos (2) |
SYS_T::IRCTIEN: CLKEIEN Position
Definition at line 24860 of file NUC472_442.h.
| #define SYS_IRCTIEN_TFAILIEN_Msk (0x1ul << SYS_IRCTIEN_TFAILIEN_Pos) |
SYS_T::IRCTIEN: TFAILIEN Mask
Definition at line 24858 of file NUC472_442.h.
| #define SYS_IRCTIEN_TFAILIEN_Pos (1) |
SYS_T::IRCTIEN: TFAILIEN Position
Definition at line 24857 of file NUC472_442.h.
| #define SYS_IRCTISTS_CLKERRIF_Msk (0x1ul << SYS_IRCTISTS_CLKERRIF_Pos) |
SYS_T::IRCTISTS: CLKERRIF Mask
Definition at line 24870 of file NUC472_442.h.
| #define SYS_IRCTISTS_CLKERRIF_Pos (2) |
SYS_T::IRCTISTS: CLKERRIF Position
Definition at line 24869 of file NUC472_442.h.
| #define SYS_IRCTISTS_FREQLOCK_Msk (0x1ul << SYS_IRCTISTS_FREQLOCK_Pos) |
SYS_T::IRCTISTS: FREQLOCK Mask
Definition at line 24864 of file NUC472_442.h.
| #define SYS_IRCTISTS_FREQLOCK_Pos (0) |
SYS_T::IRCTISTS: FREQLOCK Position
Definition at line 24863 of file NUC472_442.h.
| #define SYS_IRCTISTS_TFAILIF_Msk (0x1ul << SYS_IRCTISTS_TFAILIF_Pos) |
SYS_T::IRCTISTS: TFAILIF Mask
Definition at line 24867 of file NUC472_442.h.
| #define SYS_IRCTISTS_TFAILIF_Pos (1) |
SYS_T::IRCTISTS: TFAILIF Position
Definition at line 24866 of file NUC472_442.h.
| #define SYS_PDID_SYS_PDID_Msk (0xfffffffful << SYS_PDID_SYS_PDID_Pos) |
SYS_T::PDID: SYS_PDID Mask
Definition at line 24186 of file NUC472_442.h.
| #define SYS_PDID_SYS_PDID_Pos (0) |
@addtogroup SYS_CONST SYS Bit Field Definition Constant Definitions for SYS Controller
SYS_T::PDID: SYS_PDID Position
Definition at line 24185 of file NUC472_442.h.
| #define SYS_PORCTL_POROFF_Msk (0xfffful << SYS_PORCTL_POROFF_Pos) |
SYS_T::PORCTL: POROFF Mask
Definition at line 24381 of file NUC472_442.h.
| #define SYS_PORCTL_POROFF_Pos (0) |
SYS_T::PORCTL: POROFF Position
Definition at line 24380 of file NUC472_442.h.
| #define SYS_REGLCTL_REGLCTL_Msk (0x1ul << SYS_REGLCTL_REGLCTL_Pos) |
SYS_T::REGLCTL: REGLCTL Mask
Definition at line 24873 of file NUC472_442.h.
| #define SYS_REGLCTL_REGLCTL_Pos (0) |
SYS_T::REGLCTL: REGLCTL Position
Definition at line 24872 of file NUC472_442.h.
| #define SYS_REGLCTL_SYS_REGLCTL_Msk (0xfful << SYS_REGLCTL_SYS_REGLCTL_Pos) |
SYS_T::REGLCTL: SYS_REGLCTL Mask
Definition at line 24876 of file NUC472_442.h.
| #define SYS_REGLCTL_SYS_REGLCTL_Pos (0) |
SYS_T::REGLCTL: SYS_REGLCTL Position
Definition at line 24875 of file NUC472_442.h.
| #define SYS_RSTSTS_BODRF_Msk (0x1ul << SYS_RSTSTS_BODRF_Pos) |
SYS_T::RSTSTS: BODRF Mask
Definition at line 24201 of file NUC472_442.h.
| #define SYS_RSTSTS_BODRF_Pos (4) |
SYS_T::RSTSTS: BODRF Position
Definition at line 24200 of file NUC472_442.h.
| #define SYS_RSTSTS_CPURF_Msk (0x1ul << SYS_RSTSTS_CPURF_Pos) |
SYS_T::RSTSTS: CPURF Mask
Definition at line 24207 of file NUC472_442.h.
| #define SYS_RSTSTS_CPURF_Pos (7) |
SYS_T::RSTSTS: CPURF Position
Definition at line 24206 of file NUC472_442.h.
| #define SYS_RSTSTS_LVRF_Msk (0x1ul << SYS_RSTSTS_LVRF_Pos) |
SYS_T::RSTSTS: LVRF Mask
Definition at line 24198 of file NUC472_442.h.
| #define SYS_RSTSTS_LVRF_Pos (3) |
SYS_T::RSTSTS: LVRF Position
Definition at line 24197 of file NUC472_442.h.
| #define SYS_RSTSTS_PINRF_Msk (0x1ul << SYS_RSTSTS_PINRF_Pos) |
SYS_T::RSTSTS: PINRF Mask
Definition at line 24192 of file NUC472_442.h.
| #define SYS_RSTSTS_PINRF_Pos (1) |
SYS_T::RSTSTS: PINRF Position
Definition at line 24191 of file NUC472_442.h.
| #define SYS_RSTSTS_PORF_Msk (0x1ul << SYS_RSTSTS_PORF_Pos) |
SYS_T::RSTSTS: PORF Mask
Definition at line 24189 of file NUC472_442.h.
| #define SYS_RSTSTS_PORF_Pos (0) |
SYS_T::RSTSTS: PORF Position
Definition at line 24188 of file NUC472_442.h.
| #define SYS_RSTSTS_SYSRF_Msk (0x1ul << SYS_RSTSTS_SYSRF_Pos) |
SYS_T::RSTSTS: SYSRF Mask
Definition at line 24204 of file NUC472_442.h.
| #define SYS_RSTSTS_SYSRF_Pos (5) |
SYS_T::RSTSTS: SYSRF Position
Definition at line 24203 of file NUC472_442.h.
| #define SYS_RSTSTS_WDTRF_Msk (0x1ul << SYS_RSTSTS_WDTRF_Pos) |
SYS_T::RSTSTS: WDTRF Mask
Definition at line 24195 of file NUC472_442.h.
| #define SYS_RSTSTS_WDTRF_Pos (2) |
SYS_T::RSTSTS: WDTRF Position
Definition at line 24194 of file NUC472_442.h.
| #define SYS_SRAM0_ERRADDR_PERRADDR_Msk (0xfffffffful << SYS_SRAM0_ERRADDR_PERRADDR_Pos) |
SYS_T::SRAM0_ERRADDR: PERRADDR Mask
Definition at line 24840 of file NUC472_442.h.
| #define SYS_SRAM0_ERRADDR_PERRADDR_Pos (0) |
SYS_T::SRAM0_ERRADDR: PERRADDR Position
Definition at line 24839 of file NUC472_442.h.
| #define SYS_SRAM1_ERRADDR_PERRADDR_Msk (0xfffffffful << SYS_SRAM1_ERRADDR_PERRADDR_Pos) |
SYS_T::SRAM1_ERRADDR: PERRADDR Mask
Definition at line 24843 of file NUC472_442.h.
| #define SYS_SRAM1_ERRADDR_PERRADDR_Pos (0) |
SYS_T::SRAM1_ERRADDR: PERRADDR Position
Definition at line 24842 of file NUC472_442.h.
| #define SYS_SRAM_INTCTL_PERRIEN_Msk (0x1ul << SYS_SRAM_INTCTL_PERRIEN_Pos) |
SYS_T::SRAM_INTCTL: PERRIEN Mask
Definition at line 24831 of file NUC472_442.h.
| #define SYS_SRAM_INTCTL_PERRIEN_Pos (0) |
SYS_T::SRAM_INTCTL: PERRIEN Position
Definition at line 24830 of file NUC472_442.h.
| #define SYS_SRAM_STATUS_PERRIF0_Msk (0x1ul << SYS_SRAM_STATUS_PERRIF0_Pos) |
SYS_T::SRAM_STATUS: PERRIF0 Mask
Definition at line 24834 of file NUC472_442.h.
| #define SYS_SRAM_STATUS_PERRIF0_Pos (0) |
SYS_T::SRAM_STATUS: PERRIF0 Position
Definition at line 24833 of file NUC472_442.h.
| #define SYS_SRAM_STATUS_PERRIF1_Msk (0x1ul << SYS_SRAM_STATUS_PERRIF1_Pos) |
SYS_T::SRAM_STATUS: PERRIF1 Mask
Definition at line 24837 of file NUC472_442.h.
| #define SYS_SRAM_STATUS_PERRIF1_Pos (1) |
SYS_T::SRAM_STATUS: PERRIF1 Position
Definition at line 24836 of file NUC472_442.h.
| #define SYS_TEMPCTL_VTEMPEN_Msk (0x1ul << SYS_TEMPCTL_VTEMPEN_Pos) |
SYS_T::TEMPCTL: VTEMPEN Mask
Definition at line 24375 of file NUC472_442.h.
| #define SYS_TEMPCTL_VTEMPEN_Pos (0) |
SYS_T::TEMPCTL: VTEMPEN Position
Definition at line 24374 of file NUC472_442.h.
| #define SYS_USBPHY_LDO33EN_Msk (0x1ul << SYS_USBPHY_LDO33EN_Pos) |
SYS_T::USBPHY: LDO33EN Mask
Definition at line 24396 of file NUC472_442.h.
| #define SYS_USBPHY_LDO33EN_Pos (8) |
SYS_T::USBPHY: LDO33EN Position
Definition at line 24395 of file NUC472_442.h.
| #define SYS_USBPHY_USBROLE_Msk (0x3ul << SYS_USBPHY_USBROLE_Pos) |
SYS_T::USBPHY: USBROLE Mask
Definition at line 24393 of file NUC472_442.h.
| #define SYS_USBPHY_USBROLE_Pos (0) |
SYS_T::USBPHY: USBROLE Position
Definition at line 24392 of file NUC472_442.h.
| #define SYS_VCID_VCID_Msk (0xfffful << SYS_VCID_VCID_Pos) |
SYS_T::VCID: VCID Mask
Definition at line 24378 of file NUC472_442.h.
| #define SYS_VCID_VCID_Pos (0) |
SYS_T::VCID: VCID Position
Definition at line 24377 of file NUC472_442.h.
| #define SYS_VREFCTL_ADCMODESEL_Msk (0x1ul << SYS_VREFCTL_ADCMODESEL_Pos) |
SYS_T::VREFCTL: ADCMODESEL Mask
Definition at line 24387 of file NUC472_442.h.
| #define SYS_VREFCTL_ADCMODESEL_Pos (8) |
SYS_T::VREFCTL: ADCMODESEL Position
Definition at line 24386 of file NUC472_442.h.
| #define SYS_VREFCTL_PWMSYNCMODE_Msk (0x1ul << SYS_VREFCTL_PWMSYNCMODE_Pos) |
SYS_T::VREFCTL: PWMSYNCMODE Mask
Definition at line 24390 of file NUC472_442.h.
| #define SYS_VREFCTL_PWMSYNCMODE_Pos (9) |
SYS_T::VREFCTL: PWMSYNCMODE Position
Definition at line 24389 of file NUC472_442.h.
| #define SYS_VREFCTL_VREFCTL_Msk (0x1ful << SYS_VREFCTL_VREFCTL_Pos) |
SYS_T::VREFCTL: VREFCTL Mask
Definition at line 24384 of file NUC472_442.h.
| #define SYS_VREFCTL_VREFCTL_Pos (0) |
SYS_T::VREFCTL: VREFCTL Position
Definition at line 24383 of file NUC472_442.h.
| #define TIMER_CAP_CAPDAT_Msk (0xfffffful << TIMER_CAP_CAPDAT_Pos) |
TIMER_T::CAP: CAPDAT Mask
Definition at line 25132 of file NUC472_442.h.
| #define TIMER_CAP_CAPDAT_Pos (0) |
TIMER_T::CAP: CAPDAT Position
Definition at line 25131 of file NUC472_442.h.
| #define TIMER_CMP_CMPDAT_Msk (0xfffffful << TIMER_CMP_CMPDAT_Pos) |
TIMER_T::CMP: CMPDAT Mask
Definition at line 25120 of file NUC472_442.h.
| #define TIMER_CMP_CMPDAT_Pos (0) |
TIMER_T::CMP: CMPDAT Position
Definition at line 25119 of file NUC472_442.h.
| #define TIMER_CNT_TIMER_CNT_Msk (0xfffffful << TIMER_CNT_TIMER_CNT_Pos) |
TIMER_T::CNT: TIMER_CNT Mask
Definition at line 25129 of file NUC472_442.h.
| #define TIMER_CNT_TIMER_CNT_Pos (0) |
TIMER_T::CNT: TIMER_CNT Position
Definition at line 25128 of file NUC472_442.h.
| #define TIMER_CTL_ACTSTS_Msk (0x1ul << TIMER_CTL_ACTSTS_Pos) |
TIMER_T::CTL: ACTSTS Mask
Definition at line 25102 of file NUC472_442.h.
| #define TIMER_CTL_ACTSTS_Pos (25) |
TIMER_T::CTL: ACTSTS Position
Definition at line 25101 of file NUC472_442.h.
| #define TIMER_CTL_CNTDATEN_Msk (0x1ul << TIMER_CTL_CNTDATEN_Pos) |
TIMER_T::CTL: CNTDATEN Mask
Definition at line 25087 of file NUC472_442.h.
| #define TIMER_CTL_CNTDATEN_Pos (16) |
TIMER_T::CTL: CNTDATEN Position
Definition at line 25086 of file NUC472_442.h.
| #define TIMER_CTL_CNTEN_Msk (0x1ul << TIMER_CTL_CNTEN_Pos) |
TIMER_T::CTL: CNTEN Mask
Definition at line 25114 of file NUC472_442.h.
| #define TIMER_CTL_CNTEN_Pos (30) |
TIMER_T::CTL: CNTEN Position
Definition at line 25113 of file NUC472_442.h.
| #define TIMER_CTL_EXTCNTEN_Msk (0x1ul << TIMER_CTL_EXTCNTEN_Pos) |
TIMER_T::CTL: EXTCNTEN Mask
Definition at line 25099 of file NUC472_442.h.
| #define TIMER_CTL_EXTCNTEN_Pos (24) |
TIMER_T::CTL: EXTCNTEN Position
Definition at line 25098 of file NUC472_442.h.
| #define TIMER_CTL_ICEDEBUG_Msk (0x1ul << TIMER_CTL_ICEDEBUG_Pos) |
TIMER_T::CTL: ICEDEBUG Mask
Definition at line 25117 of file NUC472_442.h.
| #define TIMER_CTL_ICEDEBUG_Pos (31) |
TIMER_T::CTL: ICEDEBUG Position
Definition at line 25116 of file NUC472_442.h.
| #define TIMER_CTL_INTEN_Msk (0x1ul << TIMER_CTL_INTEN_Pos) |
TIMER_T::CTL: INTEN Mask
Definition at line 25111 of file NUC472_442.h.
| #define TIMER_CTL_INTEN_Pos (29) |
TIMER_T::CTL: INTEN Position
Definition at line 25110 of file NUC472_442.h.
| #define TIMER_CTL_OPMODE_Msk (0x3ul << TIMER_CTL_OPMODE_Pos) |
TIMER_T::CTL: OPMODE Mask
Definition at line 25108 of file NUC472_442.h.
| #define TIMER_CTL_OPMODE_Pos (27) |
TIMER_T::CTL: OPMODE Position
Definition at line 25107 of file NUC472_442.h.
| #define TIMER_CTL_PSC_Msk (0xfful << TIMER_CTL_PSC_Pos) |
TIMER_T::CTL: PSC Mask
Definition at line 25084 of file NUC472_442.h.
| #define TIMER_CTL_PSC_Pos (0) |
@addtogroup TIMER_CONST TIMER Bit Field Definition Constant Definitions for TIMER Controller
TIMER_T::CTL: PSC Position
Definition at line 25083 of file NUC472_442.h.
| #define TIMER_CTL_RSTCNT_Msk (0x1ul << TIMER_CTL_RSTCNT_Pos) |
TIMER_T::CTL: RSTCNT Mask
Definition at line 25105 of file NUC472_442.h.
| #define TIMER_CTL_RSTCNT_Pos (26) |
TIMER_T::CTL: RSTCNT Position
Definition at line 25104 of file NUC472_442.h.
| #define TIMER_CTL_TOGDIS1_Msk (0x1ul << TIMER_CTL_TOGDIS1_Pos) |
TIMER_T::CTL: TOGDIS1 Mask
Definition at line 25090 of file NUC472_442.h.
| #define TIMER_CTL_TOGDIS1_Pos (21) |
TIMER_T::CTL: TOGDIS1 Position
Definition at line 25089 of file NUC472_442.h.
| #define TIMER_CTL_TOGDIS2_Msk (0x1ul << TIMER_CTL_TOGDIS2_Pos) |
TIMER_T::CTL: TOGDIS2 Mask
Definition at line 25093 of file NUC472_442.h.
| #define TIMER_CTL_TOGDIS2_Pos (22) |
TIMER_T::CTL: TOGDIS2 Position
Definition at line 25092 of file NUC472_442.h.
| #define TIMER_CTL_WKEN_Msk (0x1ul << TIMER_CTL_WKEN_Pos) |
TIMER_T::CTL: WKEN Mask
Definition at line 25096 of file NUC472_442.h.
| #define TIMER_CTL_WKEN_Pos (23) |
TIMER_T::CTL: WKEN Position
Definition at line 25095 of file NUC472_442.h.
| #define TIMER_EINTSTS_CAPIF_Msk (0x1ul << TIMER_EINTSTS_CAPIF_Pos) |
TIMER_T::EINTSTS: CAPIF Mask
Definition at line 25156 of file NUC472_442.h.
| #define TIMER_EINTSTS_CAPIF_Pos (0) |
TIMER_T::EINTSTS: CAPIF Position
Definition at line 25155 of file NUC472_442.h.
| #define TIMER_EXTCTL_CAPDBEN_Msk (0x1ul << TIMER_EXTCTL_CAPDBEN_Pos) |
TIMER_T::EXTCTL: CAPDBEN Mask
Definition at line 25150 of file NUC472_442.h.
| #define TIMER_EXTCTL_CAPDBEN_Pos (6) |
TIMER_T::EXTCTL: CAPDBEN Position
Definition at line 25149 of file NUC472_442.h.
| #define TIMER_EXTCTL_CAPEDGE_Msk (0x3ul << TIMER_EXTCTL_CAPEDGE_Pos) |
TIMER_T::EXTCTL: CAPEDGE Mask
Definition at line 25138 of file NUC472_442.h.
| #define TIMER_EXTCTL_CAPEDGE_Pos (1) |
TIMER_T::EXTCTL: CAPEDGE Position
Definition at line 25137 of file NUC472_442.h.
| #define TIMER_EXTCTL_CAPEN_Msk (0x1ul << TIMER_EXTCTL_CAPEN_Pos) |
TIMER_T::EXTCTL: CAPEN Mask
Definition at line 25141 of file NUC472_442.h.
| #define TIMER_EXTCTL_CAPEN_Pos (3) |
TIMER_T::EXTCTL: CAPEN Position
Definition at line 25140 of file NUC472_442.h.
| #define TIMER_EXTCTL_CAPFUNCS_Msk (0x1ul << TIMER_EXTCTL_CAPFUNCS_Pos) |
TIMER_T::EXTCTL: CAPFUNCS Mask
Definition at line 25144 of file NUC472_442.h.
| #define TIMER_EXTCTL_CAPFUNCS_Pos (4) |
TIMER_T::EXTCTL: CAPFUNCS Position
Definition at line 25143 of file NUC472_442.h.
| #define TIMER_EXTCTL_CAPIEN_Msk (0x1ul << TIMER_EXTCTL_CAPIEN_Pos) |
TIMER_T::EXTCTL: CAPIEN Mask
Definition at line 25147 of file NUC472_442.h.
| #define TIMER_EXTCTL_CAPIEN_Pos (5) |
TIMER_T::EXTCTL: CAPIEN Position
Definition at line 25146 of file NUC472_442.h.
| #define TIMER_EXTCTL_CNTPHASE_Msk (0x1ul << TIMER_EXTCTL_CNTPHASE_Pos) |
TIMER_T::EXTCTL: CNTPHASE Mask
Definition at line 25135 of file NUC472_442.h.
| #define TIMER_EXTCTL_CNTPHASE_Pos (0) |
TIMER_T::EXTCTL: CNTPHASE Position
Definition at line 25134 of file NUC472_442.h.
| #define TIMER_EXTCTL_ECNTDBEN_Msk (0x1ul << TIMER_EXTCTL_ECNTDBEN_Pos) |
TIMER_T::EXTCTL: ECNTDBEN Mask
Definition at line 25153 of file NUC472_442.h.
| #define TIMER_EXTCTL_ECNTDBEN_Pos (7) |
TIMER_T::EXTCTL: ECNTDBEN Position
Definition at line 25152 of file NUC472_442.h.
| #define TIMER_INTSTS_TIF_Msk (0x1ul << TIMER_INTSTS_TIF_Pos) |
TIMER_T::INTSTS: TIF Mask
Definition at line 25123 of file NUC472_442.h.
| #define TIMER_INTSTS_TIF_Pos (0) |
TIMER_T::INTSTS: TIF Position
Definition at line 25122 of file NUC472_442.h.
| #define TIMER_INTSTS_TWKF_Msk (0x1ul << TIMER_INTSTS_TWKF_Pos) |
TIMER_T::INTSTS: TWKF Mask
Definition at line 25126 of file NUC472_442.h.
| #define TIMER_INTSTS_TWKF_Pos (1) |
TIMER_T::INTSTS: TWKF Position
Definition at line 25125 of file NUC472_442.h.
| #define UART_ALTCTL_ADDRDEN_Msk (0x1ul << UART_ALTCTL_ADDRDEN_Pos) |
UART_T::ALTCTL: ADDRDEN Mask
Definition at line 26057 of file NUC472_442.h.
| #define UART_ALTCTL_ADDRDEN_Pos (15) |
UART_T::ALTCTL: ADDRDEN Position
Definition at line 26056 of file NUC472_442.h.
| #define UART_ALTCTL_ADDRMV_Msk (0xfful << UART_ALTCTL_ADDRMV_Pos) |
UART_T::ALTCTL: ADDRMV Mask
Definition at line 26060 of file NUC472_442.h.
| #define UART_ALTCTL_ADDRMV_Pos (24) |
UART_T::ALTCTL: ADDRMV Position
Definition at line 26059 of file NUC472_442.h.
| #define UART_ALTCTL_BKFL_Msk (0xful << UART_ALTCTL_BKFL_Pos) |
UART_T::ALTCTL: BKFL Mask
Definition at line 26039 of file NUC472_442.h.
| #define UART_ALTCTL_BKFL_Pos (0) |
UART_T::ALTCTL: BKFL Position
Definition at line 26038 of file NUC472_442.h.
| #define UART_ALTCTL_LINRXEN_Msk (0x1ul << UART_ALTCTL_LINRXEN_Pos) |
UART_T::ALTCTL: LINRXEN Mask
Definition at line 26042 of file NUC472_442.h.
| #define UART_ALTCTL_LINRXEN_Pos (6) |
UART_T::ALTCTL: LINRXEN Position
Definition at line 26041 of file NUC472_442.h.
| #define UART_ALTCTL_LINTXEN_Msk (0x1ul << UART_ALTCTL_LINTXEN_Pos) |
UART_T::ALTCTL: LINTXEN Mask
Definition at line 26045 of file NUC472_442.h.
| #define UART_ALTCTL_LINTXEN_Pos (7) |
UART_T::ALTCTL: LINTXEN Position
Definition at line 26044 of file NUC472_442.h.
| #define UART_ALTCTL_RS485AAD_Msk (0x1ul << UART_ALTCTL_RS485AAD_Pos) |
UART_T::ALTCTL: RS485AAD Mask
Definition at line 26051 of file NUC472_442.h.
| #define UART_ALTCTL_RS485AAD_Pos (9) |
UART_T::ALTCTL: RS485AAD Position
Definition at line 26050 of file NUC472_442.h.
| #define UART_ALTCTL_RS485AUD_Msk (0x1ul << UART_ALTCTL_RS485AUD_Pos) |
UART_T::ALTCTL: RS485AUD Mask
Definition at line 26054 of file NUC472_442.h.
| #define UART_ALTCTL_RS485AUD_Pos (10) |
UART_T::ALTCTL: RS485AUD Position
Definition at line 26053 of file NUC472_442.h.
| #define UART_ALTCTL_RS485NMM_Msk (0x1ul << UART_ALTCTL_RS485NMM_Pos) |
UART_T::ALTCTL: RS485NMM Mask
Definition at line 26048 of file NUC472_442.h.
| #define UART_ALTCTL_RS485NMM_Pos (8) |
UART_T::ALTCTL: RS485NMM Position
Definition at line 26047 of file NUC472_442.h.
| #define UART_BAUD_BAUDM0_Msk (0x1ul << UART_BAUD_BAUDM0_Pos) |
UART_T::BAUD: BAUDM0 Mask
Definition at line 26021 of file NUC472_442.h.
| #define UART_BAUD_BAUDM0_Pos (28) |
UART_T::BAUD: BAUDM0 Position
Definition at line 26020 of file NUC472_442.h.
| #define UART_BAUD_BAUDM1_Msk (0x1ul << UART_BAUD_BAUDM1_Pos) |
UART_T::BAUD: BAUDM1 Mask
Definition at line 26024 of file NUC472_442.h.
| #define UART_BAUD_BAUDM1_Pos (29) |
UART_T::BAUD: BAUDM1 Position
Definition at line 26023 of file NUC472_442.h.
| #define UART_BAUD_BRD_Msk (0xfffful << UART_BAUD_BRD_Pos) |
UART_T::BAUD: BRD Mask
Definition at line 26015 of file NUC472_442.h.
| #define UART_BAUD_BRD_Pos (0) |
UART_T::BAUD: BRD Position
Definition at line 26014 of file NUC472_442.h.
| #define UART_BAUD_EDIVM1_Msk (0xful << UART_BAUD_EDIVM1_Pos) |
UART_T::BAUD: EDIVM1 Mask
Definition at line 26018 of file NUC472_442.h.
| #define UART_BAUD_EDIVM1_Pos (24) |
UART_T::BAUD: EDIVM1 Position
Definition at line 26017 of file NUC472_442.h.
| #define UART_DAT_DAT_Msk (0xfful << UART_DAT_DAT_Pos) |
UART_T::DAT: DAT Mask
Definition at line 25808 of file NUC472_442.h.
| #define UART_DAT_DAT_Pos (0) |
@addtogroup UART_CONST UART Bit Field Definition Constant Definitions for UART Controller
UART_T::DAT: DAT Position
Definition at line 25807 of file NUC472_442.h.
| #define UART_FIFO_RFITL_Msk (0xful << UART_FIFO_RFITL_Pos) |
UART_T::FIFO: RFITL Mask
Definition at line 25856 of file NUC472_442.h.
| #define UART_FIFO_RFITL_Pos (4) |
UART_T::FIFO: RFITL Position
Definition at line 25855 of file NUC472_442.h.
| #define UART_FIFO_RTSTRGLV_Msk (0xful << UART_FIFO_RTSTRGLV_Pos) |
UART_T::FIFO: RTSTRGLV Mask
Definition at line 25862 of file NUC472_442.h.
| #define UART_FIFO_RTSTRGLV_Pos (16) |
UART_T::FIFO: RTSTRGLV Position
Definition at line 25861 of file NUC472_442.h.
| #define UART_FIFO_RXOFF_Msk (0x1ul << UART_FIFO_RXOFF_Pos) |
UART_T::FIFO: RXOFF Mask
Definition at line 25859 of file NUC472_442.h.
| #define UART_FIFO_RXOFF_Pos (8) |
UART_T::FIFO: RXOFF Position
Definition at line 25858 of file NUC472_442.h.
| #define UART_FIFO_RXRST_Msk (0x1ul << UART_FIFO_RXRST_Pos) |
UART_T::FIFO: RXRST Mask
Definition at line 25850 of file NUC472_442.h.
| #define UART_FIFO_RXRST_Pos (1) |
UART_T::FIFO: RXRST Position
Definition at line 25849 of file NUC472_442.h.
| #define UART_FIFO_TXRST_Msk (0x1ul << UART_FIFO_TXRST_Pos) |
UART_T::FIFO: TXRST Mask
Definition at line 25853 of file NUC472_442.h.
| #define UART_FIFO_TXRST_Pos (2) |
UART_T::FIFO: TXRST Position
Definition at line 25852 of file NUC472_442.h.
| #define UART_FIFOSTS_ADDRDETF_Msk (0x1ul << UART_FIFOSTS_ADDRDETF_Pos) |
UART_T::FIFOSTS: ADDRDETF Mask
Definition at line 25907 of file NUC472_442.h.
| #define UART_FIFOSTS_ADDRDETF_Pos (3) |
UART_T::FIFOSTS: ADDRDETF Position
Definition at line 25906 of file NUC472_442.h.
| #define UART_FIFOSTS_BIF_Msk (0x1ul << UART_FIFOSTS_BIF_Pos) |
UART_T::FIFOSTS: BIF Mask
Definition at line 25916 of file NUC472_442.h.
| #define UART_FIFOSTS_BIF_Pos (6) |
UART_T::FIFOSTS: BIF Position
Definition at line 25915 of file NUC472_442.h.
| #define UART_FIFOSTS_FEF_Msk (0x1ul << UART_FIFOSTS_FEF_Pos) |
UART_T::FIFOSTS: FEF Mask
Definition at line 25913 of file NUC472_442.h.
| #define UART_FIFOSTS_FEF_Pos (5) |
UART_T::FIFOSTS: FEF Position
Definition at line 25912 of file NUC472_442.h.
| #define UART_FIFOSTS_PEF_Msk (0x1ul << UART_FIFOSTS_PEF_Pos) |
UART_T::FIFOSTS: PEF Mask
Definition at line 25910 of file NUC472_442.h.
| #define UART_FIFOSTS_PEF_Pos (4) |
UART_T::FIFOSTS: PEF Position
Definition at line 25909 of file NUC472_442.h.
| #define UART_FIFOSTS_RXEMPTY_Msk (0x1ul << UART_FIFOSTS_RXEMPTY_Pos) |
UART_T::FIFOSTS: RXEMPTY Mask
Definition at line 25922 of file NUC472_442.h.
| #define UART_FIFOSTS_RXEMPTY_Pos (14) |
UART_T::FIFOSTS: RXEMPTY Position
Definition at line 25921 of file NUC472_442.h.
| #define UART_FIFOSTS_RXFULL_Msk (0x1ul << UART_FIFOSTS_RXFULL_Pos) |
UART_T::FIFOSTS: RXFULL Mask
Definition at line 25925 of file NUC472_442.h.
| #define UART_FIFOSTS_RXFULL_Pos (15) |
UART_T::FIFOSTS: RXFULL Position
Definition at line 25924 of file NUC472_442.h.
| #define UART_FIFOSTS_RXOVIF_Msk (0x1ul << UART_FIFOSTS_RXOVIF_Pos) |
UART_T::FIFOSTS: RXOVIF Mask
Definition at line 25901 of file NUC472_442.h.
| #define UART_FIFOSTS_RXOVIF_Pos (0) |
UART_T::FIFOSTS: RXOVIF Position
Definition at line 25900 of file NUC472_442.h.
| #define UART_FIFOSTS_RXPTR_Msk (0x3ful << UART_FIFOSTS_RXPTR_Pos) |
UART_T::FIFOSTS: RXPTR Mask
Definition at line 25919 of file NUC472_442.h.
| #define UART_FIFOSTS_RXPTR_Pos (8) |
UART_T::FIFOSTS: RXPTR Position
Definition at line 25918 of file NUC472_442.h.
| #define UART_FIFOSTS_SCERR_Msk (0x1ul << UART_FIFOSTS_SCERR_Pos) |
UART_T::FIFOSTS: SCERR Mask
Definition at line 25904 of file NUC472_442.h.
| #define UART_FIFOSTS_SCERR_Pos (2) |
UART_T::FIFOSTS: SCERR Position
Definition at line 25903 of file NUC472_442.h.
| #define UART_FIFOSTS_TXEMPTY_Msk (0x1ul << UART_FIFOSTS_TXEMPTY_Pos) |
UART_T::FIFOSTS: TXEMPTY Mask
Definition at line 25931 of file NUC472_442.h.
| #define UART_FIFOSTS_TXEMPTY_Pos (22) |
UART_T::FIFOSTS: TXEMPTY Position
Definition at line 25930 of file NUC472_442.h.
| #define UART_FIFOSTS_TXEMPTYF_Msk (0x1ul << UART_FIFOSTS_TXEMPTYF_Pos) |
UART_T::FIFOSTS: TXEMPTYF Mask
Definition at line 25940 of file NUC472_442.h.
| #define UART_FIFOSTS_TXEMPTYF_Pos (28) |
UART_T::FIFOSTS: TXEMPTYF Position
Definition at line 25939 of file NUC472_442.h.
| #define UART_FIFOSTS_TXFULL_Msk (0x1ul << UART_FIFOSTS_TXFULL_Pos) |
UART_T::FIFOSTS: TXFULL Mask
Definition at line 25934 of file NUC472_442.h.
| #define UART_FIFOSTS_TXFULL_Pos (23) |
UART_T::FIFOSTS: TXFULL Position
Definition at line 25933 of file NUC472_442.h.
| #define UART_FIFOSTS_TXOVIF_Msk (0x1ul << UART_FIFOSTS_TXOVIF_Pos) |
UART_T::FIFOSTS: TXOVIF Mask
Definition at line 25937 of file NUC472_442.h.
| #define UART_FIFOSTS_TXOVIF_Pos (24) |
UART_T::FIFOSTS: TXOVIF Position
Definition at line 25936 of file NUC472_442.h.
| #define UART_FIFOSTS_TXPTR_Msk (0x3ful << UART_FIFOSTS_TXPTR_Pos) |
UART_T::FIFOSTS: TXPTR Mask
Definition at line 25928 of file NUC472_442.h.
| #define UART_FIFOSTS_TXPTR_Pos (16) |
UART_T::FIFOSTS: TXPTR Position
Definition at line 25927 of file NUC472_442.h.
| #define UART_FUNCSEL_FUNCSEL_Msk (0x7ul << UART_FUNCSEL_FUNCSEL_Pos) |
UART_T::FUNCSEL: FUNCSEL Mask
Definition at line 26063 of file NUC472_442.h.
| #define UART_FUNCSEL_FUNCSEL_Pos (0) |
UART_T::FUNCSEL: FUNCSEL Position
Definition at line 26062 of file NUC472_442.h.
| #define UART_INTEN_ATOCTSEN_Msk (0x1ul << UART_INTEN_ATOCTSEN_Pos) |
UART_T::INTEN: ATOCTSEN Mask
Definition at line 25841 of file NUC472_442.h.
| #define UART_INTEN_ATOCTSEN_Pos (13) |
UART_T::INTEN: ATOCTSEN Position
Definition at line 25840 of file NUC472_442.h.
| #define UART_INTEN_ATORTSEN_Msk (0x1ul << UART_INTEN_ATORTSEN_Pos) |
UART_T::INTEN: ATORTSEN Mask
Definition at line 25838 of file NUC472_442.h.
| #define UART_INTEN_ATORTSEN_Pos (12) |
UART_T::INTEN: ATORTSEN Position
Definition at line 25837 of file NUC472_442.h.
| #define UART_INTEN_BUFERRIEN_Msk (0x1ul << UART_INTEN_BUFERRIEN_Pos) |
UART_T::INTEN: BUFERRIEN Mask
Definition at line 25826 of file NUC472_442.h.
| #define UART_INTEN_BUFERRIEN_Pos (5) |
UART_T::INTEN: BUFERRIEN Position
Definition at line 25825 of file NUC472_442.h.
| #define UART_INTEN_LINIEN_Msk (0x1ul << UART_INTEN_LINIEN_Pos) |
UART_T::INTEN: LINIEN Mask
Definition at line 25832 of file NUC472_442.h.
| #define UART_INTEN_LINIEN_Pos (8) |
UART_T::INTEN: LINIEN Position
Definition at line 25831 of file NUC472_442.h.
| #define UART_INTEN_MODEMIEN_Msk (0x1ul << UART_INTEN_MODEMIEN_Pos) |
UART_T::INTEN: MODEMIEN Mask
Definition at line 25820 of file NUC472_442.h.
| #define UART_INTEN_MODEMIEN_Pos (3) |
UART_T::INTEN: MODEMIEN Position
Definition at line 25819 of file NUC472_442.h.
| #define UART_INTEN_RDAIEN_Msk (0x1ul << UART_INTEN_RDAIEN_Pos) |
UART_T::INTEN: RDAIEN Mask
Definition at line 25811 of file NUC472_442.h.
| #define UART_INTEN_RDAIEN_Pos (0) |
UART_T::INTEN: RDAIEN Position
Definition at line 25810 of file NUC472_442.h.
| #define UART_INTEN_RLSIEN_Msk (0x1ul << UART_INTEN_RLSIEN_Pos) |
UART_T::INTEN: RLSIEN Mask
Definition at line 25817 of file NUC472_442.h.
| #define UART_INTEN_RLSIEN_Pos (2) |
UART_T::INTEN: RLSIEN Position
Definition at line 25816 of file NUC472_442.h.
| #define UART_INTEN_RXPDMAEN_Msk (0x1ul << UART_INTEN_RXPDMAEN_Pos) |
UART_T::INTEN: RXPDMAEN Mask
Definition at line 25847 of file NUC472_442.h.
| #define UART_INTEN_RXPDMAEN_Pos (15) |
UART_T::INTEN: RXPDMAEN Position
Definition at line 25846 of file NUC472_442.h.
| #define UART_INTEN_RXTOIEN_Msk (0x1ul << UART_INTEN_RXTOIEN_Pos) |
UART_T::INTEN: RXTOIEN Mask
Definition at line 25823 of file NUC472_442.h.
| #define UART_INTEN_RXTOIEN_Pos (4) |
UART_T::INTEN: RXTOIEN Position
Definition at line 25822 of file NUC472_442.h.
| #define UART_INTEN_THREIEN_Msk (0x1ul << UART_INTEN_THREIEN_Pos) |
UART_T::INTEN: THREIEN Mask
Definition at line 25814 of file NUC472_442.h.
| #define UART_INTEN_THREIEN_Pos (1) |
UART_T::INTEN: THREIEN Position
Definition at line 25813 of file NUC472_442.h.
| #define UART_INTEN_TOCNTEN_Msk (0x1ul << UART_INTEN_TOCNTEN_Pos) |
UART_T::INTEN: TOCNTEN Mask
Definition at line 25835 of file NUC472_442.h.
| #define UART_INTEN_TOCNTEN_Pos (11) |
UART_T::INTEN: TOCNTEN Position
Definition at line 25834 of file NUC472_442.h.
| #define UART_INTEN_TXPDMAEN_Msk (0x1ul << UART_INTEN_TXPDMAEN_Pos) |
UART_T::INTEN: TXPDMAEN Mask
Definition at line 25844 of file NUC472_442.h.
| #define UART_INTEN_TXPDMAEN_Pos (14) |
UART_T::INTEN: TXPDMAEN Position
Definition at line 25843 of file NUC472_442.h.
| #define UART_INTEN_WKCTSIEN_Msk (0x1ul << UART_INTEN_WKCTSIEN_Pos) |
UART_T::INTEN: WKCTSIEN Mask
Definition at line 25829 of file NUC472_442.h.
| #define UART_INTEN_WKCTSIEN_Pos (6) |
UART_T::INTEN: WKCTSIEN Position
Definition at line 25828 of file NUC472_442.h.
| #define UART_INTSTS_BUFERRIF_Msk (0x1ul << UART_INTSTS_BUFERRIF_Pos) |
UART_T::INTSTS: BUFERRIF Mask
Definition at line 25958 of file NUC472_442.h.
| #define UART_INTSTS_BUFERRIF_Pos (5) |
UART_T::INTSTS: BUFERRIF Position
Definition at line 25957 of file NUC472_442.h.
| #define UART_INTSTS_BUFERRINT_Msk (0x1ul << UART_INTSTS_BUFERRINT_Pos) |
UART_T::INTSTS: BUFERRINT Mask
Definition at line 25979 of file NUC472_442.h.
| #define UART_INTSTS_BUFERRINT_Pos (13) |
UART_T::INTSTS: BUFERRINT Position
Definition at line 25978 of file NUC472_442.h.
| #define UART_INTSTS_HWBUFEIF_Msk (0x1ul << UART_INTSTS_HWBUFEIF_Pos) |
UART_T::INTSTS: HWBUFEIF Mask
Definition at line 25994 of file NUC472_442.h.
| #define UART_INTSTS_HWBUFEIF_Pos (21) |
UART_T::INTSTS: HWBUFEIF Position
Definition at line 25993 of file NUC472_442.h.
| #define UART_INTSTS_HWBUFEINT_Msk (0x1ul << UART_INTSTS_HWBUFEINT_Pos) |
UART_T::INTSTS: HWBUFEINT Mask
Definition at line 26006 of file NUC472_442.h.
| #define UART_INTSTS_HWBUFEINT_Pos (29) |
UART_T::INTSTS: HWBUFEINT Position
Definition at line 26005 of file NUC472_442.h.
| #define UART_INTSTS_HWMODIF_Msk (0x1ul << UART_INTSTS_HWMODIF_Pos) |
UART_T::INTSTS: HWMODIF Mask
Definition at line 25988 of file NUC472_442.h.
| #define UART_INTSTS_HWMODIF_Pos (19) |
UART_T::INTSTS: HWMODIF Position
Definition at line 25987 of file NUC472_442.h.
| #define UART_INTSTS_HWMODINT_Msk (0x1ul << UART_INTSTS_HWMODINT_Pos) |
UART_T::INTSTS: HWMODINT Mask
Definition at line 26000 of file NUC472_442.h.
| #define UART_INTSTS_HWMODINT_Pos (27) |
UART_T::INTSTS: HWMODINT Position
Definition at line 25999 of file NUC472_442.h.
| #define UART_INTSTS_HWRLSIF_Msk (0x1ul << UART_INTSTS_HWRLSIF_Pos) |
UART_T::INTSTS: HWRLSIF Mask
Definition at line 25985 of file NUC472_442.h.
| #define UART_INTSTS_HWRLSIF_Pos (18) |
UART_T::INTSTS: HWRLSIF Position
Definition at line 25984 of file NUC472_442.h.
| #define UART_INTSTS_HWRLSINT_Msk (0x1ul << UART_INTSTS_HWRLSINT_Pos) |
UART_T::INTSTS: HWRLSINT Mask
Definition at line 25997 of file NUC472_442.h.
| #define UART_INTSTS_HWRLSINT_Pos (26) |
UART_T::INTSTS: HWRLSINT Position
Definition at line 25996 of file NUC472_442.h.
| #define UART_INTSTS_HWTOIF_Msk (0x1ul << UART_INTSTS_HWTOIF_Pos) |
UART_T::INTSTS: HWTOIF Mask
Definition at line 25991 of file NUC472_442.h.
| #define UART_INTSTS_HWTOIF_Pos (20) |
UART_T::INTSTS: HWTOIF Position
Definition at line 25990 of file NUC472_442.h.
| #define UART_INTSTS_HWTOINT_Msk (0x1ul << UART_INTSTS_HWTOINT_Pos) |
UART_T::INTSTS: HWTOINT Mask
Definition at line 26003 of file NUC472_442.h.
| #define UART_INTSTS_HWTOINT_Pos (28) |
UART_T::INTSTS: HWTOINT Position
Definition at line 26002 of file NUC472_442.h.
| #define UART_INTSTS_LINIF_Msk (0x1ul << UART_INTSTS_LINIF_Pos) |
UART_T::INTSTS: LINIF Mask
Definition at line 25961 of file NUC472_442.h.
| #define UART_INTSTS_LINIF_Pos (7) |
UART_T::INTSTS: LINIF Position
Definition at line 25960 of file NUC472_442.h.
| #define UART_INTSTS_LININT_Msk (0x1ul << UART_INTSTS_LININT_Pos) |
UART_T::INTSTS: LININT Mask
Definition at line 25982 of file NUC472_442.h.
| #define UART_INTSTS_LININT_Pos (15) |
UART_T::INTSTS: LININT Position
Definition at line 25981 of file NUC472_442.h.
| #define UART_INTSTS_MODEMIF_Msk (0x1ul << UART_INTSTS_MODEMIF_Pos) |
UART_T::INTSTS: MODENIF Mask
Definition at line 25952 of file NUC472_442.h.
| #define UART_INTSTS_MODEMIF_Pos (3) |
UART_T::INTSTS: MODENIF Position
Definition at line 25951 of file NUC472_442.h.
| #define UART_INTSTS_MODEMINT_Msk (0x1ul << UART_INTSTS_MODEMINT_Pos) |
UART_T::INTSTS: MODEMINT Mask
Definition at line 25973 of file NUC472_442.h.
| #define UART_INTSTS_MODEMINT_Pos (11) |
UART_T::INTSTS: MODEMINT Position
Definition at line 25972 of file NUC472_442.h.
| #define UART_INTSTS_RDAIF_Msk (0x1ul << UART_INTSTS_RDAIF_Pos) |
UART_T::INTSTS: RDAIF Mask
Definition at line 25943 of file NUC472_442.h.
| #define UART_INTSTS_RDAIF_Pos (0) |
UART_T::INTSTS: RDAIF Position
Definition at line 25942 of file NUC472_442.h.
| #define UART_INTSTS_RDAINT_Msk (0x1ul << UART_INTSTS_RDAINT_Pos) |
UART_T::INTSTS: RDAINT Mask
Definition at line 25964 of file NUC472_442.h.
| #define UART_INTSTS_RDAINT_Pos (8) |
UART_T::INTSTS: RDAINT Position
Definition at line 25963 of file NUC472_442.h.
| #define UART_INTSTS_RLSIF_Msk (0x1ul << UART_INTSTS_RLSIF_Pos) |
UART_T::INTSTS: RLSIF Mask
Definition at line 25949 of file NUC472_442.h.
| #define UART_INTSTS_RLSIF_Pos (2) |
UART_T::INTSTS: RLSIF Position
Definition at line 25948 of file NUC472_442.h.
| #define UART_INTSTS_RLSINT_Msk (0x1ul << UART_INTSTS_RLSINT_Pos) |
UART_T::INTSTS: RLSINT Mask
Definition at line 25970 of file NUC472_442.h.
| #define UART_INTSTS_RLSINT_Pos (10) |
UART_T::INTSTS: RLSINT Position
Definition at line 25969 of file NUC472_442.h.
| #define UART_INTSTS_RXTOIF_Msk (0x1ul << UART_INTSTS_RXTOIF_Pos) |
UART_T::INTSTS: RXTOIF Mask
Definition at line 25955 of file NUC472_442.h.
| #define UART_INTSTS_RXTOIF_Pos (4) |
UART_T::INTSTS: RXTOIF Position
Definition at line 25954 of file NUC472_442.h.
| #define UART_INTSTS_RXTOINT_Msk (0x1ul << UART_INTSTS_RXTOINT_Pos) |
UART_T::INTSTS: RXTOINT Mask
Definition at line 25976 of file NUC472_442.h.
| #define UART_INTSTS_RXTOINT_Pos (12) |
UART_T::INTSTS: RXTOINT Position
Definition at line 25975 of file NUC472_442.h.
| #define UART_INTSTS_THREIF_Msk (0x1ul << UART_INTSTS_THREIF_Pos) |
UART_T::INTSTS: THREIF Mask
Definition at line 25946 of file NUC472_442.h.
| #define UART_INTSTS_THREIF_Pos (1) |
UART_T::INTSTS: THREIF Position
Definition at line 25945 of file NUC472_442.h.
| #define UART_INTSTS_THREINT_Msk (0x1ul << UART_INTSTS_THREINT_Pos) |
UART_T::INTSTS: THERINT Mask
Definition at line 25967 of file NUC472_442.h.
| #define UART_INTSTS_THREINT_Pos (9) |
UART_T::INTSTS: THERINT Position
Definition at line 25966 of file NUC472_442.h.
| #define UART_IRDA_FIXPULSE_Msk (0x1ul << UART_IRDA_FIXPULSE_Pos) |
UART_T::IRDA: FIXPULSE Mask
Definition at line 26036 of file NUC472_442.h.
| #define UART_IRDA_FIXPULSE_Pos (7) |
UART_T::IRDA: FIXPULSE Position
Definition at line 26035 of file NUC472_442.h.
| #define UART_IRDA_RXINV_Msk (0x1ul << UART_IRDA_RXINV_Pos) |
UART_T::IRDA: RXINV Mask
Definition at line 26033 of file NUC472_442.h.
| #define UART_IRDA_RXINV_Pos (6) |
UART_T::IRDA: RXINV Position
Definition at line 26032 of file NUC472_442.h.
| #define UART_IRDA_TXEN_Msk (0x1ul << UART_IRDA_TXEN_Pos) |
UART_T::IRDA: TXEN Mask
Definition at line 26027 of file NUC472_442.h.
| #define UART_IRDA_TXEN_Pos (1) |
UART_T::IRDA: TXEN Position
Definition at line 26026 of file NUC472_442.h.
| #define UART_IRDA_TXINV_Msk (0x1ul << UART_IRDA_TXINV_Pos) |
UART_T::IRDA: TXINV Mask
Definition at line 26030 of file NUC472_442.h.
| #define UART_IRDA_TXINV_Pos (5) |
UART_T::IRDA: TXINV Position
Definition at line 26029 of file NUC472_442.h.
| #define UART_LINCTL_BITERREN_Msk (0x1ul << UART_LINCTL_BITERREN_Pos) |
UART_T::LINCTL: BITERREN Mask
Definition at line 26093 of file NUC472_442.h.
| #define UART_LINCTL_BITERREN_Pos (12) |
UART_T::LINCTL: BITERREN Position
Definition at line 26092 of file NUC472_442.h.
| #define UART_LINCTL_BRKDETEN_Msk (0x1ul << UART_LINCTL_BRKDETEN_Pos) |
UART_T::LINCTL: BRKDETEN Mask
Definition at line 26087 of file NUC472_442.h.
| #define UART_LINCTL_BRKDETEN_Pos (10) |
UART_T::LINCTL: BRKDETEN Position
Definition at line 26086 of file NUC472_442.h.
| #define UART_LINCTL_BRKFL_Msk (0xful << UART_LINCTL_BRKFL_Pos) |
UART_T::LINCTL: BRKFL Mask
Definition at line 26096 of file NUC472_442.h.
| #define UART_LINCTL_BRKFL_Pos (16) |
UART_T::LINCTL: BRKFL Position
Definition at line 26095 of file NUC472_442.h.
| #define UART_LINCTL_BSL_Msk (0x3ul << UART_LINCTL_BSL_Pos) |
UART_T::LINCTL: BSL Mask
Definition at line 26099 of file NUC472_442.h.
| #define UART_LINCTL_BSL_Pos (20) |
UART_T::LINCTL: BSL Position
Definition at line 26098 of file NUC472_442.h.
| #define UART_LINCTL_HSEL_Msk (0x3ul << UART_LINCTL_HSEL_Pos) |
UART_T::LINCTL: HSEL Mask
Definition at line 26102 of file NUC472_442.h.
| #define UART_LINCTL_HSEL_Pos (22) |
UART_T::LINCTL: HSEL Position
Definition at line 26101 of file NUC472_442.h.
| #define UART_LINCTL_IDPEN_Msk (0x1ul << UART_LINCTL_IDPEN_Pos) |
UART_T::LINCTL: IDPEN Mask
Definition at line 26084 of file NUC472_442.h.
| #define UART_LINCTL_IDPEN_Pos (9) |
UART_T::LINCTL: IDPEN Position
Definition at line 26083 of file NUC472_442.h.
| #define UART_LINCTL_MUTE_Msk (0x1ul << UART_LINCTL_MUTE_Pos) |
UART_T::LINCTL: MUTE Mask
Definition at line 26078 of file NUC472_442.h.
| #define UART_LINCTL_MUTE_Pos (4) |
UART_T::LINCTL: MUTE Position
Definition at line 26077 of file NUC472_442.h.
| #define UART_LINCTL_PID_Msk (0xfful << UART_LINCTL_PID_Pos) |
UART_T::LINCTL: PID Mask
Definition at line 26105 of file NUC472_442.h.
| #define UART_LINCTL_PID_Pos (24) |
UART_T::LINCTL: PID Position
Definition at line 26104 of file NUC472_442.h.
| #define UART_LINCTL_RXOFF_Msk (0x1ul << UART_LINCTL_RXOFF_Pos) |
UART_T::LINCTL: RXOFF Mask
Definition at line 26090 of file NUC472_442.h.
| #define UART_LINCTL_RXOFF_Pos (11) |
UART_T::LINCTL: RXOFF Position
Definition at line 26089 of file NUC472_442.h.
| #define UART_LINCTL_SENDH_Msk (0x1ul << UART_LINCTL_SENDH_Pos) |
UART_T::LINCTL: SENDH Mask
Definition at line 26081 of file NUC472_442.h.
| #define UART_LINCTL_SENDH_Pos (8) |
UART_T::LINCTL: SENDH Position
Definition at line 26080 of file NUC472_442.h.
| #define UART_LINCTL_SLVAREN_Msk (0x1ul << UART_LINCTL_SLVAREN_Pos) |
UART_T::LINCTL: SLVAREN Mask
Definition at line 26072 of file NUC472_442.h.
| #define UART_LINCTL_SLVAREN_Pos (2) |
UART_T::LINCTL: SLVAREN Position
Definition at line 26071 of file NUC472_442.h.
| #define UART_LINCTL_SLVDUEN_Msk (0x1ul << UART_LINCTL_SLVDUEN_Pos) |
UART_T::LINCTL: SLVDUEN Mask
Definition at line 26075 of file NUC472_442.h.
| #define UART_LINCTL_SLVDUEN_Pos (3) |
UART_T::LINCTL: SLVDUEN Position
Definition at line 26074 of file NUC472_442.h.
| #define UART_LINCTL_SLVEN_Msk (0x1ul << UART_LINCTL_SLVEN_Pos) |
UART_T::LINCTL: SLVEN Mask
Definition at line 26066 of file NUC472_442.h.
| #define UART_LINCTL_SLVEN_Pos (0) |
UART_T::LINCTL: SLVEN Position
Definition at line 26065 of file NUC472_442.h.
| #define UART_LINCTL_SLVHDEN_Msk (0x1ul << UART_LINCTL_SLVHDEN_Pos) |
UART_T::LINCTL: SLVHDEN Mask
Definition at line 26069 of file NUC472_442.h.
| #define UART_LINCTL_SLVHDEN_Pos (1) |
UART_T::LINCTL: SLVHDEN Position
Definition at line 26068 of file NUC472_442.h.
| #define UART_LINDEBUG_DEVERRF_Msk (0x1ul << UART_LINDEBUG_DEVERRF_Pos) |
UART_T::LINDEBUG: DEVERRF Mask
Definition at line 26126 of file NUC472_442.h.
| #define UART_LINDEBUG_DEVERRF_Pos (0) |
UART_T::LINDEBUG: DEVERRF Position
Definition at line 26125 of file NUC472_442.h.
| #define UART_LINDEBUG_FRAMEERRF_Msk (0x1ul << UART_LINDEBUG_FRAMEERRF_Pos) |
UART_T::LINDEBUG: FRAMEERRF Mask
Definition at line 26132 of file NUC472_442.h.
| #define UART_LINDEBUG_FRAMEERRF_Pos (2) |
UART_T::LINDEBUG: FRAMEERRF Position
Definition at line 26131 of file NUC472_442.h.
| #define UART_LINDEBUG_SYNCERRF_Msk (0x1ul << UART_LINDEBUG_SYNCERRF_Pos) |
UART_T::LINDEBUG: SYNCERRF Mask
Definition at line 26135 of file NUC472_442.h.
| #define UART_LINDEBUG_SYNCERRF_Pos (3) |
UART_T::LINDEBUG: SYNCERRF Position
Definition at line 26134 of file NUC472_442.h.
| #define UART_LINDEBUG_TOF_Msk (0x1ul << UART_LINDEBUG_TOF_Pos) |
UART_T::LINDEBUG: TOF Mask
Definition at line 26129 of file NUC472_442.h.
| #define UART_LINDEBUG_TOF_Pos (1) |
UART_T::LINDEBUG: TOF Position
Definition at line 26128 of file NUC472_442.h.
| #define UART_LINE_BCB_Msk (0x1ul << UART_LINE_BCB_Pos) |
UART_T::LINE: BCB Mask
Definition at line 25880 of file NUC472_442.h.
| #define UART_LINE_BCB_Pos (6) |
UART_T::LINE: BCB Position
Definition at line 25879 of file NUC472_442.h.
| #define UART_LINE_EPE_Msk (0x1ul << UART_LINE_EPE_Pos) |
UART_T::LINE: EPE Mask
Definition at line 25874 of file NUC472_442.h.
| #define UART_LINE_EPE_Pos (4) |
UART_T::LINE: EPE Position
Definition at line 25873 of file NUC472_442.h.
| #define UART_LINE_NSB_Msk (0x1ul << UART_LINE_NSB_Pos) |
UART_T::LINE: NSB Mask
Definition at line 25868 of file NUC472_442.h.
| #define UART_LINE_NSB_Pos (2) |
UART_T::LINE: NSB Position
Definition at line 25867 of file NUC472_442.h.
| #define UART_LINE_PBE_Msk (0x1ul << UART_LINE_PBE_Pos) |
UART_T::LINE: PBE Mask
Definition at line 25871 of file NUC472_442.h.
| #define UART_LINE_PBE_Pos (3) |
UART_T::LINE: PBE Position
Definition at line 25870 of file NUC472_442.h.
| #define UART_LINE_SPE_Msk (0x1ul << UART_LINE_SPE_Pos) |
UART_T::LINE: SPE Mask
Definition at line 25877 of file NUC472_442.h.
| #define UART_LINE_SPE_Pos (5) |
UART_T::LINE: SPE Position
Definition at line 25876 of file NUC472_442.h.
| #define UART_LINE_WLS_Msk (0x3ul << UART_LINE_WLS_Pos) |
UART_T::LINE: WLS Mask
Definition at line 25865 of file NUC472_442.h.
| #define UART_LINE_WLS_Pos (0) |
UART_T::LINE: WLS Position
Definition at line 25864 of file NUC472_442.h.
| #define UART_LINSTS_BITEF_Msk (0x1ul << UART_LINSTS_BITEF_Pos) |
UART_T::LINSTS: BITEF Mask
Definition at line 26123 of file NUC472_442.h.
| #define UART_LINSTS_BITEF_Pos (9) |
UART_T::LINSTS: BITEF Position
Definition at line 26122 of file NUC472_442.h.
| #define UART_LINSTS_BRKDETF_Msk (0x1ul << UART_LINSTS_BRKDETF_Pos) |
UART_T::LINSTS: BRKDETF Mask
Definition at line 26120 of file NUC472_442.h.
| #define UART_LINSTS_BRKDETF_Pos (8) |
UART_T::LINSTS: BRKDETF Position
Definition at line 26119 of file NUC472_442.h.
| #define UART_LINSTS_SLVHDETF_Msk (0x1ul << UART_LINSTS_SLVHDETF_Pos) |
UART_T::LINSTS: SLVHDETF Mask
Definition at line 26108 of file NUC472_442.h.
| #define UART_LINSTS_SLVHDETF_Pos (0) |
UART_T::LINSTS: SLVHDETF Position
Definition at line 26107 of file NUC472_442.h.
| #define UART_LINSTS_SLVHEF_Msk (0x1ul << UART_LINSTS_SLVHEF_Pos) |
UART_T::LINSTS: SLVHEF Mask
Definition at line 26111 of file NUC472_442.h.
| #define UART_LINSTS_SLVHEF_Pos (1) |
UART_T::LINSTS: SLVHEF Position
Definition at line 26110 of file NUC472_442.h.
| #define UART_LINSTS_SLVIDPEF_Msk (0x1ul << UART_LINSTS_SLVIDPEF_Pos) |
UART_T::LINSTS: SLVIDPEF Mask
Definition at line 26114 of file NUC472_442.h.
| #define UART_LINSTS_SLVIDPEF_Pos (2) |
UART_T::LINSTS: SLVIDPEF Position
Definition at line 26113 of file NUC472_442.h.
| #define UART_LINSTS_SLVSYNCF_Msk (0x1ul << UART_LINSTS_SLVSYNCF_Pos) |
UART_T::LINSTS: SLVSYNCF Mask
Definition at line 26117 of file NUC472_442.h.
| #define UART_LINSTS_SLVSYNCF_Pos (3) |
UART_T::LINSTS: SLVSYNCF Position
Definition at line 26116 of file NUC472_442.h.
| #define UART_MODEM_RTS_Msk (0x1ul << UART_MODEM_RTS_Pos) |
UART_T::MODEM: RTS Mask
Definition at line 25883 of file NUC472_442.h.
| #define UART_MODEM_RTS_Pos (1) |
UART_T::MODEM: RTS Position
Definition at line 25882 of file NUC472_442.h.
| #define UART_MODEM_RTSACTLV_Msk (0x1ul << UART_MODEM_RTSACTLV_Pos) |
UART_T::MODEM: RTSACTLV Mask
Definition at line 25886 of file NUC472_442.h.
| #define UART_MODEM_RTSACTLV_Pos (9) |
UART_T::MODEM: RTSACTLV Position
Definition at line 25885 of file NUC472_442.h.
| #define UART_MODEM_RTSSTS_Msk (0x1ul << UART_MODEM_RTSSTS_Pos) |
UART_T::MODEM: RTSSTS Mask
Definition at line 25889 of file NUC472_442.h.
| #define UART_MODEM_RTSSTS_Pos (13) |
UART_T::MODEM: RTSSTS Position
Definition at line 25888 of file NUC472_442.h.
| #define UART_MODEMSTS_CTSACTLV_Msk (0x1ul << UART_MODEMSTS_CTSACTLV_Pos) |
UART_T::MODEMSTS: CTSACTLV Mask
Definition at line 25898 of file NUC472_442.h.
| #define UART_MODEMSTS_CTSACTLV_Pos (8) |
UART_T::MODEMSTS: CTSACTLV Position
Definition at line 25897 of file NUC472_442.h.
| #define UART_MODEMSTS_CTSDETF_Msk (0x1ul << UART_MODEMSTS_CTSDETF_Pos) |
UART_T::MODEMSTS: CTSDETF Mask
Definition at line 25892 of file NUC472_442.h.
| #define UART_MODEMSTS_CTSDETF_Pos (0) |
UART_T::MODEMSTS: CTSDETF Position
Definition at line 25891 of file NUC472_442.h.
| #define UART_MODEMSTS_CTSSTS_Msk (0x1ul << UART_MODEMSTS_CTSSTS_Pos) |
UART_T::MODEMSTS: CTSSTS Mask
Definition at line 25895 of file NUC472_442.h.
| #define UART_MODEMSTS_CTSSTS_Pos (4) |
UART_T::MODEMSTS: CTSSTS Position
Definition at line 25894 of file NUC472_442.h.
| #define UART_TOUT_DLY_Msk (0xfful << UART_TOUT_DLY_Pos) |
UART_T::TOUT: DLY Mask
Definition at line 26012 of file NUC472_442.h.
| #define UART_TOUT_DLY_Pos (8) |
UART_T::TOUT: DLY Position
Definition at line 26011 of file NUC472_442.h.
| #define UART_TOUT_TOIC_Msk (0xfful << UART_TOUT_TOIC_Pos) |
UART_T::TOUT: TOIC Mask
Definition at line 26009 of file NUC472_442.h.
| #define UART_TOUT_TOIC_Pos (0) |
UART_T::TOUT: TOIC Position
Definition at line 26008 of file NUC472_442.h.
| #define USBD_BUSINTEN_DMADONEIEN_Msk (0x1ul << USBD_BUSINTEN_DMADONEIEN_Pos) |
USBD_T::BUSINTEN: DMADONEIEN Mask
Definition at line 28097 of file NUC472_442.h.
| #define USBD_BUSINTEN_DMADONEIEN_Pos (5) |
USBD_T::BUSINTEN: DMADONEIEN Position
Definition at line 28096 of file NUC472_442.h.
| #define USBD_BUSINTEN_HISPDIEN_Msk (0x1ul << USBD_BUSINTEN_HISPDIEN_Pos) |
USBD_T::BUSINTEN: HISPDIEN Mask
Definition at line 28094 of file NUC472_442.h.
| #define USBD_BUSINTEN_HISPDIEN_Pos (4) |
USBD_T::BUSINTEN: HISPDIEN Position
Definition at line 28093 of file NUC472_442.h.
| #define USBD_BUSINTEN_PHYCLKVLDIEN_Msk (0x1ul << USBD_BUSINTEN_PHYCLKVLDIEN_Pos) |
USBD_T::BUSINTEN: PHYCLKVLDIEN Mask
Definition at line 28100 of file NUC472_442.h.
| #define USBD_BUSINTEN_PHYCLKVLDIEN_Pos (6) |
USBD_T::BUSINTEN: PHYCLKVLDIEN Position
Definition at line 28099 of file NUC472_442.h.
| #define USBD_BUSINTEN_RESUMEIEN_Msk (0x1ul << USBD_BUSINTEN_RESUMEIEN_Pos) |
USBD_T::BUSINTEN: RESUMEIEN Mask
Definition at line 28088 of file NUC472_442.h.
| #define USBD_BUSINTEN_RESUMEIEN_Pos (2) |
USBD_T::BUSINTEN: RESUMEIEN Position
Definition at line 28087 of file NUC472_442.h.
| #define USBD_BUSINTEN_RSTIEN_Msk (0x1ul << USBD_BUSINTEN_RSTIEN_Pos) |
USBD_T::BUSINTEN: RSTIEN Mask
Definition at line 28085 of file NUC472_442.h.
| #define USBD_BUSINTEN_RSTIEN_Pos (1) |
USBD_T::BUSINTEN: RSTIEN Position
Definition at line 28084 of file NUC472_442.h.
| #define USBD_BUSINTEN_SOFIEN_Msk (0x1ul << USBD_BUSINTEN_SOFIEN_Pos) |
USBD_T::BUSINTEN: SOFIEN Mask
Definition at line 28082 of file NUC472_442.h.
| #define USBD_BUSINTEN_SOFIEN_Pos (0) |
USBD_T::BUSINTEN: SOFIEN Position
Definition at line 28081 of file NUC472_442.h.
| #define USBD_BUSINTEN_SUSPENDIEN_Msk (0x1ul << USBD_BUSINTEN_SUSPENDIEN_Pos) |
USBD_T::BUSINTEN: SUSPENDIEN Mask
Definition at line 28091 of file NUC472_442.h.
| #define USBD_BUSINTEN_SUSPENDIEN_Pos (3) |
USBD_T::BUSINTEN: SUSPENDIEN Position
Definition at line 28090 of file NUC472_442.h.
| #define USBD_BUSINTEN_VBUSDETIEN_Msk (0x1ul << USBD_BUSINTEN_VBUSDETIEN_Pos) |
USBD_T::BUSINTEN: VBUSDETIEN Mask
Definition at line 28103 of file NUC472_442.h.
| #define USBD_BUSINTEN_VBUSDETIEN_Pos (8) |
USBD_T::BUSINTEN: VBUSDETIEN Position
Definition at line 28102 of file NUC472_442.h.
| #define USBD_BUSINTSTS_DMADONEIF_Msk (0x1ul << USBD_BUSINTSTS_DMADONEIF_Pos) |
USBD_T::BUSINTSTS: DMADONEIF Mask
Definition at line 28073 of file NUC472_442.h.
| #define USBD_BUSINTSTS_DMADONEIF_Pos (5) |
USBD_T::BUSINTSTS: DMADONEIF Position
Definition at line 28072 of file NUC472_442.h.
| #define USBD_BUSINTSTS_HISPDIF_Msk (0x1ul << USBD_BUSINTSTS_HISPDIF_Pos) |
USBD_T::BUSINTSTS: HISPDIF Mask
Definition at line 28070 of file NUC472_442.h.
| #define USBD_BUSINTSTS_HISPDIF_Pos (4) |
USBD_T::BUSINTSTS: HISPDIF Position
Definition at line 28069 of file NUC472_442.h.
| #define USBD_BUSINTSTS_PHYCLKVLDIF_Msk (0x1ul << USBD_BUSINTSTS_PHYCLKVLDIF_Pos) |
USBD_T::BUSINTSTS: PHYCLKVLDIF Mask
Definition at line 28076 of file NUC472_442.h.
| #define USBD_BUSINTSTS_PHYCLKVLDIF_Pos (6) |
USBD_T::BUSINTSTS: PHYCLKVLDIF Position
Definition at line 28075 of file NUC472_442.h.
| #define USBD_BUSINTSTS_RESUMEIF_Msk (0x1ul << USBD_BUSINTSTS_RESUMEIF_Pos) |
USBD_T::BUSINTSTS: RESUMEIF Mask
Definition at line 28064 of file NUC472_442.h.
| #define USBD_BUSINTSTS_RESUMEIF_Pos (2) |
USBD_T::BUSINTSTS: RESUMEIF Position
Definition at line 28063 of file NUC472_442.h.
| #define USBD_BUSINTSTS_RSTIF_Msk (0x1ul << USBD_BUSINTSTS_RSTIF_Pos) |
USBD_T::BUSINTSTS: RSTIF Mask
Definition at line 28061 of file NUC472_442.h.
| #define USBD_BUSINTSTS_RSTIF_Pos (1) |
USBD_T::BUSINTSTS: RSTIF Position
Definition at line 28060 of file NUC472_442.h.
| #define USBD_BUSINTSTS_SOFIF_Msk (0x1ul << USBD_BUSINTSTS_SOFIF_Pos) |
USBD_T::BUSINTSTS: SOFIF Mask
Definition at line 28058 of file NUC472_442.h.
| #define USBD_BUSINTSTS_SOFIF_Pos (0) |
USBD_T::BUSINTSTS: SOFIF Position
Definition at line 28057 of file NUC472_442.h.
| #define USBD_BUSINTSTS_SUSPENDIF_Msk (0x1ul << USBD_BUSINTSTS_SUSPENDIF_Pos) |
USBD_T::BUSINTSTS: SUSPENDIF Mask
Definition at line 28067 of file NUC472_442.h.
| #define USBD_BUSINTSTS_SUSPENDIF_Pos (3) |
USBD_T::BUSINTSTS: SUSPENDIF Position
Definition at line 28066 of file NUC472_442.h.
| #define USBD_BUSINTSTS_VBUSDETIF_Msk (0x1ul << USBD_BUSINTSTS_VBUSDETIF_Pos) |
USBD_T::BUSINTSTS: VBUSDETIF Mask
Definition at line 28079 of file NUC472_442.h.
| #define USBD_BUSINTSTS_VBUSDETIF_Pos (8) |
USBD_T::BUSINTSTS: VBUSDETIF Position
Definition at line 28078 of file NUC472_442.h.
| #define USBD_CEPBUFEND_EADDR_Msk (0xffful << USBD_CEPBUFEND_EADDR_Pos) |
USBD_T::CEPBUFEND: EADDR Mask
Definition at line 28256 of file NUC472_442.h.
| #define USBD_CEPBUFEND_EADDR_Pos (0) |
USBD_T::CEPBUFEND: EADDR Position
Definition at line 28255 of file NUC472_442.h.
| #define USBD_CEPBUFSTART_SADDR_Msk (0xffful << USBD_CEPBUFSTART_SADDR_Pos) |
USBD_T::CEPBUFSTART: SADDR Mask
Definition at line 28253 of file NUC472_442.h.
| #define USBD_CEPBUFSTART_SADDR_Pos (0) |
USBD_T::CEPBUFSTART: SADDR Position
Definition at line 28252 of file NUC472_442.h.
| #define USBD_CEPCTL_FLUSH_Msk (0x1ul << USBD_CEPCTL_FLUSH_Pos) |
USBD_T::CEPCTL: FLUSH Mask
Definition at line 28139 of file NUC472_442.h.
| #define USBD_CEPCTL_FLUSH_Pos (3) |
USBD_T::CEPCTL: FLUSH Position
Definition at line 28138 of file NUC472_442.h.
| #define USBD_CEPCTL_NAKCLR_Msk (0x1ul << USBD_CEPCTL_NAKCLR_Pos) |
USBD_T::CEPCTL: NAKCLR Mask
Definition at line 28130 of file NUC472_442.h.
| #define USBD_CEPCTL_NAKCLR_Pos (0) |
USBD_T::CEPCTL: NAKCLR Position
Definition at line 28129 of file NUC472_442.h.
| #define USBD_CEPCTL_STALLEN_Msk (0x1ul << USBD_CEPCTL_STALLEN_Pos) |
USBD_T::CEPCTL: STALLEN Mask
Definition at line 28133 of file NUC472_442.h.
| #define USBD_CEPCTL_STALLEN_Pos (1) |
USBD_T::CEPCTL: STALLEN Position
Definition at line 28132 of file NUC472_442.h.
| #define USBD_CEPCTL_ZEROLEN_Msk (0x1ul << USBD_CEPCTL_ZEROLEN_Pos) |
USBD_T::CEPCTL: ZEROLEN Mask
Definition at line 28136 of file NUC472_442.h.
| #define USBD_CEPCTL_ZEROLEN_Pos (2) |
USBD_T::CEPCTL: ZEROLEN Position
Definition at line 28135 of file NUC472_442.h.
| #define USBD_CEPDAT_DAT_Msk (0xfffffffful << USBD_CEPDAT_DAT_Pos) |
USBD_T::CEPDAT: DAT Mask
Definition at line 28127 of file NUC472_442.h.
| #define USBD_CEPDAT_DAT_Pos (0) |
USBD_T::CEPDAT: DAT Position
Definition at line 28126 of file NUC472_442.h.
| #define USBD_CEPDATCNT_DATCNT_Msk (0xfffful << USBD_CEPDATCNT_DATCNT_Pos) |
USBD_T::CEPDATCNT: DATCNT Mask
Definition at line 28226 of file NUC472_442.h.
| #define USBD_CEPDATCNT_DATCNT_Pos (0) |
USBD_T::CEPDATCNT: DATCNT Position
Definition at line 28225 of file NUC472_442.h.
| #define USBD_CEPINTEN_BUFEMPTYIEN_Msk (0x1ul << USBD_CEPINTEN_BUFEMPTYIEN_Pos) |
USBD_T::CEPINTEN: BUFEMPTYIEN Mask
Definition at line 28178 of file NUC472_442.h.
| #define USBD_CEPINTEN_BUFEMPTYIEN_Pos (12) |
USBD_T::CEPINTEN: BUFEMPTYIEN Position
Definition at line 28177 of file NUC472_442.h.
| #define USBD_CEPINTEN_BUFFULLIEN_Msk (0x1ul << USBD_CEPINTEN_BUFFULLIEN_Pos) |
USBD_T::CEPINTEN: BUFFULLIEN Mask
Definition at line 28175 of file NUC472_442.h.
| #define USBD_CEPINTEN_BUFFULLIEN_Pos (11) |
USBD_T::CEPINTEN: BUFFULLIEN Position
Definition at line 28174 of file NUC472_442.h.
| #define USBD_CEPINTEN_ERRIEN_Msk (0x1ul << USBD_CEPINTEN_ERRIEN_Pos) |
USBD_T::CEPINTEN: ERRIEN Mask
Definition at line 28169 of file NUC472_442.h.
| #define USBD_CEPINTEN_ERRIEN_Pos (9) |
USBD_T::CEPINTEN: ERRIEN Position
Definition at line 28168 of file NUC472_442.h.
| #define USBD_CEPINTEN_INTKIEN_Msk (0x1ul << USBD_CEPINTEN_INTKIEN_Pos) |
USBD_T::CEPINTEN: INTKIEN Mask
Definition at line 28151 of file NUC472_442.h.
| #define USBD_CEPINTEN_INTKIEN_Pos (3) |
USBD_T::CEPINTEN: INTKIEN Position
Definition at line 28150 of file NUC472_442.h.
| #define USBD_CEPINTEN_NAKIEN_Msk (0x1ul << USBD_CEPINTEN_NAKIEN_Pos) |
USBD_T::CEPINTEN: NAKIEN Mask
Definition at line 28163 of file NUC472_442.h.
| #define USBD_CEPINTEN_NAKIEN_Pos (7) |
USBD_T::CEPINTEN: NAKIEN Position
Definition at line 28162 of file NUC472_442.h.
| #define USBD_CEPINTEN_OUTTKIEN_Msk (0x1ul << USBD_CEPINTEN_OUTTKIEN_Pos) |
USBD_T::CEPINTEN: OUTTKIEN Mask
Definition at line 28148 of file NUC472_442.h.
| #define USBD_CEPINTEN_OUTTKIEN_Pos (2) |
USBD_T::CEPINTEN: OUTTKIEN Position
Definition at line 28147 of file NUC472_442.h.
| #define USBD_CEPINTEN_PINGIEN_Msk (0x1ul << USBD_CEPINTEN_PINGIEN_Pos) |
USBD_T::CEPINTEN: PINGIEN Mask
Definition at line 28154 of file NUC472_442.h.
| #define USBD_CEPINTEN_PINGIEN_Pos (4) |
USBD_T::CEPINTEN: PINGIEN Position
Definition at line 28153 of file NUC472_442.h.
| #define USBD_CEPINTEN_RXPKIEN_Msk (0x1ul << USBD_CEPINTEN_RXPKIEN_Pos) |
USBD_T::CEPINTEN: RXPKIEN Mask
Definition at line 28160 of file NUC472_442.h.
| #define USBD_CEPINTEN_RXPKIEN_Pos (6) |
USBD_T::CEPINTEN: RXPKIEN Position
Definition at line 28159 of file NUC472_442.h.
| #define USBD_CEPINTEN_SETUPPKIEN_Msk (0x1ul << USBD_CEPINTEN_SETUPPKIEN_Pos) |
USBD_T::CEPINTEN: SETUPPKIEN Mask
Definition at line 28145 of file NUC472_442.h.
| #define USBD_CEPINTEN_SETUPPKIEN_Pos (1) |
USBD_T::CEPINTEN: SETUPPKIEN Position
Definition at line 28144 of file NUC472_442.h.
| #define USBD_CEPINTEN_SETUPTKIEN_Msk (0x1ul << USBD_CEPINTEN_SETUPTKIEN_Pos) |
USBD_T::CEPINTEN: SETUPTKIEN Mask
Definition at line 28142 of file NUC472_442.h.
| #define USBD_CEPINTEN_SETUPTKIEN_Pos (0) |
USBD_T::CEPINTEN: SETUPTKIEN Position
Definition at line 28141 of file NUC472_442.h.
| #define USBD_CEPINTEN_STALLIEN_Msk (0x1ul << USBD_CEPINTEN_STALLIEN_Pos) |
USBD_T::CEPINTEN: STALLIEN Mask
Definition at line 28166 of file NUC472_442.h.
| #define USBD_CEPINTEN_STALLIEN_Pos (8) |
USBD_T::CEPINTEN: STALLIEN Position
Definition at line 28165 of file NUC472_442.h.
| #define USBD_CEPINTEN_STSDONEIEN_Msk (0x1ul << USBD_CEPINTEN_STSDONEIEN_Pos) |
USBD_T::CEPINTEN: STSDONEIEN Mask
Definition at line 28172 of file NUC472_442.h.
| #define USBD_CEPINTEN_STSDONEIEN_Pos (10) |
USBD_T::CEPINTEN: STSDONEIEN Position
Definition at line 28171 of file NUC472_442.h.
| #define USBD_CEPINTEN_TXPKIEN_Msk (0x1ul << USBD_CEPINTEN_TXPKIEN_Pos) |
USBD_T::CEPINTEN: TXPKIEN Mask
Definition at line 28157 of file NUC472_442.h.
| #define USBD_CEPINTEN_TXPKIEN_Pos (5) |
USBD_T::CEPINTEN: TXPKIEN Position
Definition at line 28156 of file NUC472_442.h.
| #define USBD_CEPINTSTS_BUFEMPTYIF_Msk (0x1ul << USBD_CEPINTSTS_BUFEMPTYIF_Pos) |
USBD_T::CEPINTSTS: BUFEMPTYIF Mask
Definition at line 28217 of file NUC472_442.h.
| #define USBD_CEPINTSTS_BUFEMPTYIF_Pos (12) |
USBD_T::CEPINTSTS: BUFEMPTYIF Position
Definition at line 28216 of file NUC472_442.h.
| #define USBD_CEPINTSTS_BUFFULLIF_Msk (0x1ul << USBD_CEPINTSTS_BUFFULLIF_Pos) |
USBD_T::CEPINTSTS: BUFFULLIF Mask
Definition at line 28214 of file NUC472_442.h.
| #define USBD_CEPINTSTS_BUFFULLIF_Pos (11) |
USBD_T::CEPINTSTS: BUFFULLIF Position
Definition at line 28213 of file NUC472_442.h.
| #define USBD_CEPINTSTS_ERRIF_Msk (0x1ul << USBD_CEPINTSTS_ERRIF_Pos) |
USBD_T::CEPINTSTS: ERRIF Mask
Definition at line 28208 of file NUC472_442.h.
| #define USBD_CEPINTSTS_ERRIF_Pos (9) |
USBD_T::CEPINTSTS: ERRIF Position
Definition at line 28207 of file NUC472_442.h.
| #define USBD_CEPINTSTS_INTKIF_Msk (0x1ul << USBD_CEPINTSTS_INTKIF_Pos) |
USBD_T::CEPINTSTS: INTKIF Mask
Definition at line 28190 of file NUC472_442.h.
| #define USBD_CEPINTSTS_INTKIF_Pos (3) |
USBD_T::CEPINTSTS: INTKIF Position
Definition at line 28189 of file NUC472_442.h.
| #define USBD_CEPINTSTS_NAKIF_Msk (0x1ul << USBD_CEPINTSTS_NAKIF_Pos) |
USBD_T::CEPINTSTS: NAKIF Mask
Definition at line 28202 of file NUC472_442.h.
| #define USBD_CEPINTSTS_NAKIF_Pos (7) |
USBD_T::CEPINTSTS: NAKIF Position
Definition at line 28201 of file NUC472_442.h.
| #define USBD_CEPINTSTS_OUTTKIF_Msk (0x1ul << USBD_CEPINTSTS_OUTTKIF_Pos) |
USBD_T::CEPINTSTS: OUTTKIF Mask
Definition at line 28187 of file NUC472_442.h.
| #define USBD_CEPINTSTS_OUTTKIF_Pos (2) |
USBD_T::CEPINTSTS: OUTTKIF Position
Definition at line 28186 of file NUC472_442.h.
| #define USBD_CEPINTSTS_PINGIF_Msk (0x1ul << USBD_CEPINTSTS_PINGIF_Pos) |
USBD_T::CEPINTSTS: PINGIF Mask
Definition at line 28193 of file NUC472_442.h.
| #define USBD_CEPINTSTS_PINGIF_Pos (4) |
USBD_T::CEPINTSTS: PINGIF Position
Definition at line 28192 of file NUC472_442.h.
| #define USBD_CEPINTSTS_RXPKIF_Msk (0x1ul << USBD_CEPINTSTS_RXPKIF_Pos) |
USBD_T::CEPINTSTS: RXPKIF Mask
Definition at line 28199 of file NUC472_442.h.
| #define USBD_CEPINTSTS_RXPKIF_Pos (6) |
USBD_T::CEPINTSTS: RXPKIF Position
Definition at line 28198 of file NUC472_442.h.
| #define USBD_CEPINTSTS_SETUPPKIF_Msk (0x1ul << USBD_CEPINTSTS_SETUPPKIF_Pos) |
USBD_T::CEPINTSTS: SETUPPKIF Mask
Definition at line 28184 of file NUC472_442.h.
| #define USBD_CEPINTSTS_SETUPPKIF_Pos (1) |
USBD_T::CEPINTSTS: SETUPPKIF Position
Definition at line 28183 of file NUC472_442.h.
| #define USBD_CEPINTSTS_SETUPTKIF_Msk (0x1ul << USBD_CEPINTSTS_SETUPTKIF_Pos) |
USBD_T::CEPINTSTS: SETUPTKIF Mask
Definition at line 28181 of file NUC472_442.h.
| #define USBD_CEPINTSTS_SETUPTKIF_Pos (0) |
USBD_T::CEPINTSTS: SETUPTKIF Position
Definition at line 28180 of file NUC472_442.h.
| #define USBD_CEPINTSTS_STALLIF_Msk (0x1ul << USBD_CEPINTSTS_STALLIF_Pos) |
USBD_T::CEPINTSTS: STALLIF Mask
Definition at line 28205 of file NUC472_442.h.
| #define USBD_CEPINTSTS_STALLIF_Pos (8) |
USBD_T::CEPINTSTS: STALLIF Position
Definition at line 28204 of file NUC472_442.h.
| #define USBD_CEPINTSTS_STSDONEIF_Msk (0x1ul << USBD_CEPINTSTS_STSDONEIF_Pos) |
USBD_T::CEPINTSTS: STSDONEIF Mask
Definition at line 28211 of file NUC472_442.h.
| #define USBD_CEPINTSTS_STSDONEIF_Pos (10) |
USBD_T::CEPINTSTS: STSDONEIF Position
Definition at line 28210 of file NUC472_442.h.
| #define USBD_CEPINTSTS_TXPKIF_Msk (0x1ul << USBD_CEPINTSTS_TXPKIF_Pos) |
USBD_T::CEPINTSTS: TXPKIF Mask
Definition at line 28196 of file NUC472_442.h.
| #define USBD_CEPINTSTS_TXPKIF_Pos (5) |
USBD_T::CEPINTSTS: TXPKIF Position
Definition at line 28195 of file NUC472_442.h.
| #define USBD_CEPRXCNT_RXCNT_Msk (0xfful << USBD_CEPRXCNT_RXCNT_Pos) |
USBD_T::CEPRXCNT: RXCNT Mask
Definition at line 28223 of file NUC472_442.h.
| #define USBD_CEPRXCNT_RXCNT_Pos (0) |
USBD_T::CEPRXCNT: RXCNT Position
Definition at line 28222 of file NUC472_442.h.
| #define USBD_CEPTXCNT_TXCNT_Msk (0xfful << USBD_CEPTXCNT_TXCNT_Pos) |
USBD_T::CEPTXCNT: TXCNT Mask
Definition at line 28220 of file NUC472_442.h.
| #define USBD_CEPTXCNT_TXCNT_Pos (0) |
USBD_T::CEPTXCNT: TXCNT Position
Definition at line 28219 of file NUC472_442.h.
| #define USBD_DMAADDR_DMAADDR_Msk (0xfffffffful << USBD_DMAADDR_DMAADDR_Pos) |
USBD_T::DMAADDR: DMAADDR Mask
Definition at line 28409 of file NUC472_442.h.
| #define USBD_DMAADDR_DMAADDR_Pos (0) |
USBD_T::DMAADDR: DMAADDR Position
Definition at line 28408 of file NUC472_442.h.
| #define USBD_DMACNT_DMACNT_Msk (0xffffful << USBD_DMACNT_DMACNT_Pos) |
USBD_T::DMACNT: DMACNT Mask
Definition at line 28274 of file NUC472_442.h.
| #define USBD_DMACNT_DMACNT_Pos (0) |
USBD_T::DMACNT: DMACNT Position
Definition at line 28273 of file NUC472_442.h.
| #define USBD_DMACTL_DMAEN_Msk (0x1ul << USBD_DMACTL_DMAEN_Pos) |
USBD_T::DMACTL: DMAEN Mask
Definition at line 28265 of file NUC472_442.h.
| #define USBD_DMACTL_DMAEN_Pos (5) |
USBD_T::DMACTL: DMAEN Position
Definition at line 28264 of file NUC472_442.h.
| #define USBD_DMACTL_DMARD_Msk (0x1ul << USBD_DMACTL_DMARD_Pos) |
USBD_T::DMACTL: DMARD Mask
Definition at line 28262 of file NUC472_442.h.
| #define USBD_DMACTL_DMARD_Pos (4) |
USBD_T::DMACTL: DMARD Position
Definition at line 28261 of file NUC472_442.h.
| #define USBD_DMACTL_DMARST_Msk (0x1ul << USBD_DMACTL_DMARST_Pos) |
USBD_T::DMACTL: DMARST Mask
Definition at line 28271 of file NUC472_442.h.
| #define USBD_DMACTL_DMARST_Pos (7) |
USBD_T::DMACTL: DMARST Position
Definition at line 28270 of file NUC472_442.h.
| #define USBD_DMACTL_EPNUM_Msk (0xful << USBD_DMACTL_EPNUM_Pos) |
USBD_T::DMACTL: EPNUM Mask
Definition at line 28259 of file NUC472_442.h.
| #define USBD_DMACTL_EPNUM_Pos (0) |
USBD_T::DMACTL: EPNUM Position
Definition at line 28258 of file NUC472_442.h.
| #define USBD_DMACTL_SGEN_Msk (0x1ul << USBD_DMACTL_SGEN_Pos) |
USBD_T::DMACTL: SGEN Mask
Definition at line 28268 of file NUC472_442.h.
| #define USBD_DMACTL_SGEN_Pos (6) |
USBD_T::DMACTL: SGEN Position
Definition at line 28267 of file NUC472_442.h.
| #define USBD_EPBUFEND_EADDR_Msk (0xffful << USBD_EPBUFEND_EADDR_Pos) |
USBD_EP_T::EPBUFEND: EADDR Mask
Definition at line 28406 of file NUC472_442.h.
| #define USBD_EPBUFEND_EADDR_Pos (0) |
USBD_EP_T::EPBUFEND: EADDR Position
Definition at line 28405 of file NUC472_442.h.
| #define USBD_EPBUFSTART_SADDR_Msk (0xffful << USBD_EPBUFSTART_SADDR_Pos) |
USBD_EP_T::EPBUFSTART: SADDR Mask
Definition at line 28403 of file NUC472_442.h.
| #define USBD_EPBUFSTART_SADDR_Pos (0) |
USBD_EP_T::EPBUFSTART: SADDR Position
Definition at line 28402 of file NUC472_442.h.
| #define USBD_EPCFG_EPDIR_Msk (0x1ul << USBD_EPCFG_EPDIR_Pos) |
USBD_EP_T::EPCFG: EPDIR Mask
Definition at line 28397 of file NUC472_442.h.
| #define USBD_EPCFG_EPDIR_Pos (3) |
USBD_EP_T::EPCFG: EPDIR Position
Definition at line 28396 of file NUC472_442.h.
| #define USBD_EPCFG_EPEN_Msk (0x1ul << USBD_EPCFG_EPEN_Pos) |
USBD_EP_T::EPCFG: EPEN Mask
Definition at line 28391 of file NUC472_442.h.
| #define USBD_EPCFG_EPEN_Pos (0) |
USBD_EP_T::EPCFG: EPEN Position
Definition at line 28390 of file NUC472_442.h.
| #define USBD_EPCFG_EPNUM_Msk (0xful << USBD_EPCFG_EPNUM_Pos) |
USBD_EP_T::EPCFG: EPNUM Mask
Definition at line 28400 of file NUC472_442.h.
| #define USBD_EPCFG_EPNUM_Pos (4) |
USBD_EP_T::EPCFG: EPNUM Position
Definition at line 28399 of file NUC472_442.h.
| #define USBD_EPCFG_EPTYPE_Msk (0x3ul << USBD_EPCFG_EPTYPE_Pos) |
USBD_EP_T::EPCFG: EPTYPE Mask
Definition at line 28394 of file NUC472_442.h.
| #define USBD_EPCFG_EPTYPE_Pos (1) |
USBD_EP_T::EPCFG: EPTYPE Position
Definition at line 28393 of file NUC472_442.h.
| #define USBD_EPDAT_EPDAT_Msk (0xfffffffful << USBD_EPDAT_EPDAT_Pos) |
USBD_EP_T::EPDAT: EPDAT Mask
Definition at line 28277 of file NUC472_442.h.
| #define USBD_EPDAT_EPDAT_Pos (0) |
USBD_EP_T::EPDAT: EPDAT Position
Definition at line 28276 of file NUC472_442.h.
| #define USBD_EPDATCNT_DATCNT_Msk (0xfffful << USBD_EPDATCNT_DATCNT_Pos) |
USBD_EP_T::EPDATCNT: DATCNT Mask
Definition at line 28358 of file NUC472_442.h.
| #define USBD_EPDATCNT_DATCNT_Pos (0) |
USBD_EP_T::EPDATCNT: DATCNT Position
Definition at line 28357 of file NUC472_442.h.
| #define USBD_EPDATCNT_DMALOOP_Msk (0x7ffful << USBD_EPDATCNT_DMALOOP_Pos) |
USBD_EP_T::EPDATCNT: DMALOOP Mask
Definition at line 28361 of file NUC472_442.h.
| #define USBD_EPDATCNT_DMALOOP_Pos (16) |
USBD_EP_T::EPDATCNT: DMALOOP Position
Definition at line 28360 of file NUC472_442.h.
| #define USBD_EPINTEN_BUFEMPTYIEN_Msk (0x1ul << USBD_EPINTEN_BUFEMPTYIEN_Pos) |
USBD_EP_T::EPINTEN: BUFEMPTYIEN Mask
Definition at line 28322 of file NUC472_442.h.
| #define USBD_EPINTEN_BUFEMPTYIEN_Pos (1) |
USBD_EP_T::EPINTEN: BUFEMPTYIEN Position
Definition at line 28321 of file NUC472_442.h.
| #define USBD_EPINTEN_BUFFULLIEN_Msk (0x1ul << USBD_EPINTEN_BUFFULLIEN_Pos) |
USBD_EP_T::EPINTEN: BUFFULLIEN Mask
Definition at line 28319 of file NUC472_442.h.
| #define USBD_EPINTEN_BUFFULLIEN_Pos (0) |
USBD_EP_T::EPINTEN: BUFFULLIEN Position
Definition at line 28318 of file NUC472_442.h.
| #define USBD_EPINTEN_ERRIEN_Msk (0x1ul << USBD_EPINTEN_ERRIEN_Pos) |
USBD_EP_T::EPINTEN: ERRIEN Mask
Definition at line 28352 of file NUC472_442.h.
| #define USBD_EPINTEN_ERRIEN_Pos (11) |
USBD_EP_T::EPINTEN: ERRIEN Position
Definition at line 28351 of file NUC472_442.h.
| #define USBD_EPINTEN_INTKIEN_Msk (0x1ul << USBD_EPINTEN_INTKIEN_Pos) |
USBD_EP_T::EPINTEN: INTKIEN Mask
Definition at line 28337 of file NUC472_442.h.
| #define USBD_EPINTEN_INTKIEN_Pos (6) |
USBD_EP_T::EPINTEN: INTKIEN Position
Definition at line 28336 of file NUC472_442.h.
| #define USBD_EPINTEN_NAKIEN_Msk (0x1ul << USBD_EPINTEN_NAKIEN_Pos) |
USBD_EP_T::EPINTEN: NAKIEN Mask
Definition at line 28343 of file NUC472_442.h.
| #define USBD_EPINTEN_NAKIEN_Pos (8) |
USBD_EP_T::EPINTEN: NAKIEN Position
Definition at line 28342 of file NUC472_442.h.
| #define USBD_EPINTEN_NYETIEN_Msk (0x1ul << USBD_EPINTEN_NYETIEN_Pos) |
USBD_EP_T::EPINTEN: NYETIEN Mask
Definition at line 28349 of file NUC472_442.h.
| #define USBD_EPINTEN_NYETIEN_Pos (10) |
USBD_EP_T::EPINTEN: NYETIEN Position
Definition at line 28348 of file NUC472_442.h.
| #define USBD_EPINTEN_OUTTKIEN_Msk (0x1ul << USBD_EPINTEN_OUTTKIEN_Pos) |
USBD_EP_T::EPINTEN: OUTTKIEN Mask
Definition at line 28334 of file NUC472_442.h.
| #define USBD_EPINTEN_OUTTKIEN_Pos (5) |
USBD_EP_T::EPINTEN: OUTTKIEN Position
Definition at line 28333 of file NUC472_442.h.
| #define USBD_EPINTEN_PINGIEN_Msk (0x1ul << USBD_EPINTEN_PINGIEN_Pos) |
USBD_EP_T::EPINTEN: PINGIEN Mask
Definition at line 28340 of file NUC472_442.h.
| #define USBD_EPINTEN_PINGIEN_Pos (7) |
USBD_EP_T::EPINTEN: PINGIEN Position
Definition at line 28339 of file NUC472_442.h.
| #define USBD_EPINTEN_RXPKIEN_Msk (0x1ul << USBD_EPINTEN_RXPKIEN_Pos) |
USBD_EP_T::EPINTEN: RXPKIEN Mask
Definition at line 28331 of file NUC472_442.h.
| #define USBD_EPINTEN_RXPKIEN_Pos (4) |
USBD_EP_T::EPINTEN: RXPKIEN Position
Definition at line 28330 of file NUC472_442.h.
| #define USBD_EPINTEN_SHORTRXIEN_Msk (0x1ul << USBD_EPINTEN_SHORTRXIEN_Pos) |
USBD_EP_T::EPINTEN: SHORTRXIEN Mask
Definition at line 28355 of file NUC472_442.h.
| #define USBD_EPINTEN_SHORTRXIEN_Pos (12) |
USBD_EP_T::EPINTEN: SHORTRXIEN Position
Definition at line 28354 of file NUC472_442.h.
| #define USBD_EPINTEN_SHORTTXIEN_Msk (0x1ul << USBD_EPINTEN_SHORTTXIEN_Pos) |
USBD_EP_T::EPINTEN: SHORTTXIEN Mask
Definition at line 28325 of file NUC472_442.h.
| #define USBD_EPINTEN_SHORTTXIEN_Pos (2) |
USBD_EP_T::EPINTEN: SHORTTXIEN Position
Definition at line 28324 of file NUC472_442.h.
| #define USBD_EPINTEN_STALLIEN_Msk (0x1ul << USBD_EPINTEN_STALLIEN_Pos) |
USBD_EP_T::EPINTEN: STALLIEN Mask
Definition at line 28346 of file NUC472_442.h.
| #define USBD_EPINTEN_STALLIEN_Pos (9) |
USBD_EP_T::EPINTEN: STALLIEN Position
Definition at line 28345 of file NUC472_442.h.
| #define USBD_EPINTEN_TXPKIEN_Msk (0x1ul << USBD_EPINTEN_TXPKIEN_Pos) |
USBD_EP_T::EPINTEN: TXPKIEN Mask
Definition at line 28328 of file NUC472_442.h.
| #define USBD_EPINTEN_TXPKIEN_Pos (3) |
USBD_EP_T::EPINTEN: TXPKIEN Position
Definition at line 28327 of file NUC472_442.h.
| #define USBD_EPINTSTS_BUFEMPTYIF_Msk (0x1ul << USBD_EPINTSTS_BUFEMPTYIF_Pos) |
USBD_EP_T::EPINTSTS: BUFEMPTYIF Mask
Definition at line 28283 of file NUC472_442.h.
| #define USBD_EPINTSTS_BUFEMPTYIF_Pos (1) |
USBD_EP_T::EPINTSTS: BUFEMPTYIF Position
Definition at line 28282 of file NUC472_442.h.
| #define USBD_EPINTSTS_BUFFULLIF_Msk (0x1ul << USBD_EPINTSTS_BUFFULLIF_Pos) |
USBD_EP_T::EPINTSTS: BUFFULLIF Mask
Definition at line 28280 of file NUC472_442.h.
| #define USBD_EPINTSTS_BUFFULLIF_Pos (0) |
USBD_EP_T::EPINTSTS: BUFFULLIF Position
Definition at line 28279 of file NUC472_442.h.
| #define USBD_EPINTSTS_ERRIF_Msk (0x1ul << USBD_EPINTSTS_ERRIF_Pos) |
USBD_EP_T::EPINTSTS: ERRIF Mask
Definition at line 28313 of file NUC472_442.h.
| #define USBD_EPINTSTS_ERRIF_Pos (11) |
USBD_EP_T::EPINTSTS: ERRIF Position
Definition at line 28312 of file NUC472_442.h.
| #define USBD_EPINTSTS_INTKIF_Msk (0x1ul << USBD_EPINTSTS_INTKIF_Pos) |
USBD_EP_T::EPINTSTS: INTKIF Mask
Definition at line 28298 of file NUC472_442.h.
| #define USBD_EPINTSTS_INTKIF_Pos (6) |
USBD_EP_T::EPINTSTS: INTKIF Position
Definition at line 28297 of file NUC472_442.h.
| #define USBD_EPINTSTS_NAKIF_Msk (0x1ul << USBD_EPINTSTS_NAKIF_Pos) |
USBD_EP_T::EPINTSTS: NAKIF Mask
Definition at line 28304 of file NUC472_442.h.
| #define USBD_EPINTSTS_NAKIF_Pos (8) |
USBD_EP_T::EPINTSTS: NAKIF Position
Definition at line 28303 of file NUC472_442.h.
| #define USBD_EPINTSTS_NYETIF_Msk (0x1ul << USBD_EPINTSTS_NYETIF_Pos) |
USBD_EP_T::EPINTSTS: NYETIF Mask
Definition at line 28310 of file NUC472_442.h.
| #define USBD_EPINTSTS_NYETIF_Pos (10) |
USBD_EP_T::EPINTSTS: NYETIF Position
Definition at line 28309 of file NUC472_442.h.
| #define USBD_EPINTSTS_OUTTKIF_Msk (0x1ul << USBD_EPINTSTS_OUTTKIF_Pos) |
USBD_EP_T::EPINTSTS: OUTTKIF Mask
Definition at line 28295 of file NUC472_442.h.
| #define USBD_EPINTSTS_OUTTKIF_Pos (5) |
USBD_EP_T::EPINTSTS: OUTTKIF Position
Definition at line 28294 of file NUC472_442.h.
| #define USBD_EPINTSTS_PINGIF_Msk (0x1ul << USBD_EPINTSTS_PINGIF_Pos) |
USBD_EP_T::EPINTSTS: PINGIF Mask
Definition at line 28301 of file NUC472_442.h.
| #define USBD_EPINTSTS_PINGIF_Pos (7) |
USBD_EP_T::EPINTSTS: PINGIF Position
Definition at line 28300 of file NUC472_442.h.
| #define USBD_EPINTSTS_RXPKIF_Msk (0x1ul << USBD_EPINTSTS_RXPKIF_Pos) |
USBD_EP_T::EPINTSTS: RXPKIF Mask
Definition at line 28292 of file NUC472_442.h.
| #define USBD_EPINTSTS_RXPKIF_Pos (4) |
USBD_EP_T::EPINTSTS: RXPKIF Position
Definition at line 28291 of file NUC472_442.h.
| #define USBD_EPINTSTS_SHORTRXIF_Msk (0x1ul << USBD_EPINTSTS_SHORTRXIF_Pos) |
USBD_EP_T::EPINTSTS: SHORTRXIF Mask
Definition at line 28316 of file NUC472_442.h.
| #define USBD_EPINTSTS_SHORTRXIF_Pos (12) |
USBD_EP_T::EPINTSTS: SHORTRXIF Position
Definition at line 28315 of file NUC472_442.h.
| #define USBD_EPINTSTS_SHORTTXIF_Msk (0x1ul << USBD_EPINTSTS_SHORTTXIF_Pos) |
USBD_EP_T::EPINTSTS: SHORTTXIF Mask
Definition at line 28286 of file NUC472_442.h.
| #define USBD_EPINTSTS_SHORTTXIF_Pos (2) |
USBD_EP_T::EPINTSTS: SHORTTXIF Position
Definition at line 28285 of file NUC472_442.h.
| #define USBD_EPINTSTS_STALLIF_Msk (0x1ul << USBD_EPINTSTS_STALLIF_Pos) |
USBD_EP_T::EPINTSTS: STALLIF Mask
Definition at line 28307 of file NUC472_442.h.
| #define USBD_EPINTSTS_STALLIF_Pos (9) |
USBD_EP_T::EPINTSTS: STALLIF Position
Definition at line 28306 of file NUC472_442.h.
| #define USBD_EPINTSTS_TXPKIF_Msk (0x1ul << USBD_EPINTSTS_TXPKIF_Pos) |
USBD_EP_T::EPINTSTS: TXPKIF Mask
Definition at line 28289 of file NUC472_442.h.
| #define USBD_EPINTSTS_TXPKIF_Pos (3) |
USBD_EP_T::EPINTSTS: TXPKIF Position
Definition at line 28288 of file NUC472_442.h.
| #define USBD_EPMPS_EPMPS_Msk (0x7fful << USBD_EPMPS_EPMPS_Pos) |
USBD_EP_T::EPMPS: EPMPS Mask
Definition at line 28385 of file NUC472_442.h.
| #define USBD_EPMPS_EPMPS_Pos (0) |
USBD_EP_T::EPMPS: EPMPS Position
Definition at line 28384 of file NUC472_442.h.
| #define USBD_EPRSPCTL_DISBUF_Msk (0x1ul << USBD_EPRSPCTL_DISBUF_Pos) |
USBD_EP_T::EPRSPCTL: DISBUF Mask
Definition at line 28382 of file NUC472_442.h.
| #define USBD_EPRSPCTL_DISBUF_Pos (7) |
USBD_EP_T::EPRSPCTL: DISBUF Position
Definition at line 28381 of file NUC472_442.h.
| #define USBD_EPRSPCTL_FLUSH_Msk (0x1ul << USBD_EPRSPCTL_FLUSH_Pos) |
USBD_EP_T::EPRSPCTL: FLUSH Mask
Definition at line 28364 of file NUC472_442.h.
| #define USBD_EPRSPCTL_FLUSH_Pos (0) |
USBD_EP_T::EPRSPCTL: FLUSH Position
Definition at line 28363 of file NUC472_442.h.
| #define USBD_EPRSPCTL_HALT_Msk (0x1ul << USBD_EPRSPCTL_HALT_Pos) |
USBD_EP_T::EPRSPCTL: HALT Mask
Definition at line 28373 of file NUC472_442.h.
| #define USBD_EPRSPCTL_HALT_Pos (4) |
USBD_EP_T::EPRSPCTL: HALT Position
Definition at line 28372 of file NUC472_442.h.
| #define USBD_EPRSPCTL_MODE_Msk (0x3ul << USBD_EPRSPCTL_MODE_Pos) |
USBD_EP_T::EPRSPCTL: MODE Mask
Definition at line 28367 of file NUC472_442.h.
| #define USBD_EPRSPCTL_MODE_Pos (1) |
USBD_EP_T::EPRSPCTL: MODE Position
Definition at line 28366 of file NUC472_442.h.
| #define USBD_EPRSPCTL_SHORTTXEN_Msk (0x1ul << USBD_EPRSPCTL_SHORTTXEN_Pos) |
USBD_EP_T::EPRSPCTL: SHORTTXEN Mask
Definition at line 28379 of file NUC472_442.h.
| #define USBD_EPRSPCTL_SHORTTXEN_Pos (6) |
USBD_EP_T::EPRSPCTL: SHORTTXEN Position
Definition at line 28378 of file NUC472_442.h.
| #define USBD_EPRSPCTL_TOGGLE_Msk (0x1ul << USBD_EPRSPCTL_TOGGLE_Pos) |
USBD_EP_T::EPRSPCTL: TOGGLE Mask
Definition at line 28370 of file NUC472_442.h.
| #define USBD_EPRSPCTL_TOGGLE_Pos (3) |
USBD_EP_T::EPRSPCTL: TOGGLE Position
Definition at line 28369 of file NUC472_442.h.
| #define USBD_EPRSPCTL_ZEROLEN_Msk (0x1ul << USBD_EPRSPCTL_ZEROLEN_Pos) |
USBD_EP_T::EPRSPCTL: ZEROLEN Mask
Definition at line 28376 of file NUC472_442.h.
| #define USBD_EPRSPCTL_ZEROLEN_Pos (5) |
USBD_EP_T::EPRSPCTL: ZEROLEN Position
Definition at line 28375 of file NUC472_442.h.
| #define USBD_EPTXCNT_TXCNT_Msk (0x7fful << USBD_EPTXCNT_TXCNT_Pos) |
USBD_EP_T::EPTXCNT: TXCNT Mask
Definition at line 28388 of file NUC472_442.h.
| #define USBD_EPTXCNT_TXCNT_Pos (0) |
USBD_EP_T::EPTXCNT: TXCNT Position
Definition at line 28387 of file NUC472_442.h.
| #define USBD_FADDR_FADDR_Msk (0x7ful << USBD_FADDR_FADDR_Pos) |
USBD_T::FADDR: FADDR Mask
Definition at line 28121 of file NUC472_442.h.
| #define USBD_FADDR_FADDR_Pos (0) |
USBD_T::FADDR: FADDR Position
Definition at line 28120 of file NUC472_442.h.
| #define USBD_FRAMECNT_FRAMECNT_Msk (0x7fful << USBD_FRAMECNT_FRAMECNT_Pos) |
USBD_T::FRAMECNT: FRAMECNT Mask
Definition at line 28118 of file NUC472_442.h.
| #define USBD_FRAMECNT_FRAMECNT_Pos (3) |
USBD_T::FRAMECNT: FRAMECNT Position
Definition at line 28117 of file NUC472_442.h.
| #define USBD_FRAMECNT_MFRAMECNT_Msk (0x7ul << USBD_FRAMECNT_MFRAMECNT_Pos) |
USBD_T::FRAMECNT: MFRAMECNT Mask
Definition at line 28115 of file NUC472_442.h.
| #define USBD_FRAMECNT_MFRAMECNT_Pos (0) |
USBD_T::FRAMECNT: MFRAMECNT Position
Definition at line 28114 of file NUC472_442.h.
| #define USBD_GINTEN_CEPIE_Msk (0x1ul << USBD_GINTEN_CEPIE_Pos) |
USBD_T::GINTEN: CEPIE Mask
Definition at line 28019 of file NUC472_442.h.
| #define USBD_GINTEN_CEPIE_Pos (1) |
USBD_T::GINTEN: CEPIE Position
Definition at line 28018 of file NUC472_442.h.
| #define USBD_GINTEN_EPAIE_Msk (0x1ul << USBD_GINTEN_EPAIE_Pos) |
USBD_T::GINTEN: EPAIE Mask
Definition at line 28022 of file NUC472_442.h.
| #define USBD_GINTEN_EPAIE_Pos (2) |
USBD_T::GINTEN: EPAIE Position
Definition at line 28021 of file NUC472_442.h.
| #define USBD_GINTEN_EPBIE_Msk (0x1ul << USBD_GINTEN_EPBIE_Pos) |
USBD_T::GINTEN: EPBIE Mask
Definition at line 28025 of file NUC472_442.h.
| #define USBD_GINTEN_EPBIE_Pos (3) |
USBD_T::GINTEN: EPBIE Position
Definition at line 28024 of file NUC472_442.h.
| #define USBD_GINTEN_EPCIE_Msk (0x1ul << USBD_GINTEN_EPCIE_Pos) |
USBD_T::GINTEN: EPCIE Mask
Definition at line 28028 of file NUC472_442.h.
| #define USBD_GINTEN_EPCIE_Pos (4) |
USBD_T::GINTEN: EPCIE Position
Definition at line 28027 of file NUC472_442.h.
| #define USBD_GINTEN_EPDIE_Msk (0x1ul << USBD_GINTEN_EPDIE_Pos) |
USBD_T::GINTEN: EPDIE Mask
Definition at line 28031 of file NUC472_442.h.
| #define USBD_GINTEN_EPDIE_Pos (5) |
USBD_T::GINTEN: EPDIE Position
Definition at line 28030 of file NUC472_442.h.
| #define USBD_GINTEN_EPEIE_Msk (0x1ul << USBD_GINTEN_EPEIE_Pos) |
USBD_T::GINTEN: EPEIE Mask
Definition at line 28034 of file NUC472_442.h.
| #define USBD_GINTEN_EPEIE_Pos (6) |
USBD_T::GINTEN: EPEIE Position
Definition at line 28033 of file NUC472_442.h.
| #define USBD_GINTEN_EPFIE_Msk (0x1ul << USBD_GINTEN_EPFIE_Pos) |
USBD_T::GINTEN: EPFIE Mask
Definition at line 28037 of file NUC472_442.h.
| #define USBD_GINTEN_EPFIE_Pos (7) |
USBD_T::GINTEN: EPFIE Position
Definition at line 28036 of file NUC472_442.h.
| #define USBD_GINTEN_EPGIE_Msk (0x1ul << USBD_GINTEN_EPGIE_Pos) |
USBD_T::GINTEN: EPGIE Mask
Definition at line 28040 of file NUC472_442.h.
| #define USBD_GINTEN_EPGIE_Pos (8) |
USBD_T::GINTEN: EPGIE Position
Definition at line 28039 of file NUC472_442.h.
| #define USBD_GINTEN_EPHIE_Msk (0x1ul << USBD_GINTEN_EPHIE_Pos) |
USBD_T::GINTEN: EPHIE Mask
Definition at line 28043 of file NUC472_442.h.
| #define USBD_GINTEN_EPHIE_Pos (9) |
USBD_T::GINTEN: EPHIE Position
Definition at line 28042 of file NUC472_442.h.
| #define USBD_GINTEN_EPIIE_Msk (0x1ul << USBD_GINTEN_EPIIE_Pos) |
USBD_T::GINTEN: EPIIE Mask
Definition at line 28046 of file NUC472_442.h.
| #define USBD_GINTEN_EPIIE_Pos (10) |
USBD_T::GINTEN: EPIIE Position
Definition at line 28045 of file NUC472_442.h.
| #define USBD_GINTEN_EPJIE_Msk (0x1ul << USBD_GINTEN_EPJIE_Pos) |
USBD_T::GINTEN: EPJIE Mask
Definition at line 28049 of file NUC472_442.h.
| #define USBD_GINTEN_EPJIE_Pos (11) |
USBD_T::GINTEN: EPJIE Position
Definition at line 28048 of file NUC472_442.h.
| #define USBD_GINTEN_EPKIE_Msk (0x1ul << USBD_GINTEN_EPKIE_Pos) |
USBD_T::GINTEN: EPKIE Mask
Definition at line 28052 of file NUC472_442.h.
| #define USBD_GINTEN_EPKIE_Pos (12) |
USBD_T::GINTEN: EPKIE Position
Definition at line 28051 of file NUC472_442.h.
| #define USBD_GINTEN_EPLIE_Msk (0x1ul << USBD_GINTEN_EPLIE_Pos) |
USBD_T::GINTEN: EPLIE Mask
Definition at line 28055 of file NUC472_442.h.
| #define USBD_GINTEN_EPLIE_Pos (13) |
USBD_T::GINTEN: EPLIE Position
Definition at line 28054 of file NUC472_442.h.
| #define USBD_GINTEN_USBIE_Msk (0x1ul << USBD_GINTEN_USBIE_Pos) |
USBD_T::GINTEN: USBIE Mask
Definition at line 28016 of file NUC472_442.h.
| #define USBD_GINTEN_USBIE_Pos (0) |
USBD_T::GINTEN: USBIE Position
Definition at line 28015 of file NUC472_442.h.
| #define USBD_GINTSTS_CEPIF_Msk (0x1ul << USBD_GINTSTS_CEPIF_Pos) |
USBD_T::GINTSTS: CEPIF Mask
Definition at line 27977 of file NUC472_442.h.
| #define USBD_GINTSTS_CEPIF_Pos (1) |
USBD_T::GINTSTS: CEPIF Position
Definition at line 27976 of file NUC472_442.h.
| #define USBD_GINTSTS_EPAIF_Msk (0x1ul << USBD_GINTSTS_EPAIF_Pos) |
USBD_T::GINTSTS: EPAIF Mask
Definition at line 27980 of file NUC472_442.h.
| #define USBD_GINTSTS_EPAIF_Pos (2) |
USBD_T::GINTSTS: EPAIF Position
Definition at line 27979 of file NUC472_442.h.
| #define USBD_GINTSTS_EPBIF_Msk (0x1ul << USBD_GINTSTS_EPBIF_Pos) |
USBD_T::GINTSTS: EPBIF Mask
Definition at line 27983 of file NUC472_442.h.
| #define USBD_GINTSTS_EPBIF_Pos (3) |
USBD_T::GINTSTS: EPBIF Position
Definition at line 27982 of file NUC472_442.h.
| #define USBD_GINTSTS_EPCIF_Msk (0x1ul << USBD_GINTSTS_EPCIF_Pos) |
USBD_T::GINTSTS: EPCIF Mask
Definition at line 27986 of file NUC472_442.h.
| #define USBD_GINTSTS_EPCIF_Pos (4) |
USBD_T::GINTSTS: EPCIF Position
Definition at line 27985 of file NUC472_442.h.
| #define USBD_GINTSTS_EPDIF_Msk (0x1ul << USBD_GINTSTS_EPDIF_Pos) |
USBD_T::GINTSTS: EPDIF Mask
Definition at line 27989 of file NUC472_442.h.
| #define USBD_GINTSTS_EPDIF_Pos (5) |
USBD_T::GINTSTS: EPDIF Position
Definition at line 27988 of file NUC472_442.h.
| #define USBD_GINTSTS_EPEIF_Msk (0x1ul << USBD_GINTSTS_EPEIF_Pos) |
USBD_T::GINTSTS: EPEIF Mask
Definition at line 27992 of file NUC472_442.h.
| #define USBD_GINTSTS_EPEIF_Pos (6) |
USBD_T::GINTSTS: EPEIF Position
Definition at line 27991 of file NUC472_442.h.
| #define USBD_GINTSTS_EPFIF_Msk (0x1ul << USBD_GINTSTS_EPFIF_Pos) |
USBD_T::GINTSTS: EPFIF Mask
Definition at line 27995 of file NUC472_442.h.
| #define USBD_GINTSTS_EPFIF_Pos (7) |
USBD_T::GINTSTS: EPFIF Position
Definition at line 27994 of file NUC472_442.h.
| #define USBD_GINTSTS_EPGIF_Msk (0x1ul << USBD_GINTSTS_EPGIF_Pos) |
USBD_T::GINTSTS: EPGIF Mask
Definition at line 27998 of file NUC472_442.h.
| #define USBD_GINTSTS_EPGIF_Pos (8) |
USBD_T::GINTSTS: EPGIF Position
Definition at line 27997 of file NUC472_442.h.
| #define USBD_GINTSTS_EPHIF_Msk (0x1ul << USBD_GINTSTS_EPHIF_Pos) |
USBD_T::GINTSTS: EPHIF Mask
Definition at line 28001 of file NUC472_442.h.
| #define USBD_GINTSTS_EPHIF_Pos (9) |
USBD_T::GINTSTS: EPHIF Position
Definition at line 28000 of file NUC472_442.h.
| #define USBD_GINTSTS_EPIIF_Msk (0x1ul << USBD_GINTSTS_EPIIF_Pos) |
USBD_T::GINTSTS: EPIIF Mask
Definition at line 28004 of file NUC472_442.h.
| #define USBD_GINTSTS_EPIIF_Pos (10) |
USBD_T::GINTSTS: EPIIF Position
Definition at line 28003 of file NUC472_442.h.
| #define USBD_GINTSTS_EPJIF_Msk (0x1ul << USBD_GINTSTS_EPJIF_Pos) |
USBD_T::GINTSTS: EPJIF Mask
Definition at line 28007 of file NUC472_442.h.
| #define USBD_GINTSTS_EPJIF_Pos (11) |
USBD_T::GINTSTS: EPJIF Position
Definition at line 28006 of file NUC472_442.h.
| #define USBD_GINTSTS_EPKIF_Msk (0x1ul << USBD_GINTSTS_EPKIF_Pos) |
USBD_T::GINTSTS: EPKIF Mask
Definition at line 28010 of file NUC472_442.h.
| #define USBD_GINTSTS_EPKIF_Pos (12) |
USBD_T::GINTSTS: EPKIF Position
Definition at line 28009 of file NUC472_442.h.
| #define USBD_GINTSTS_EPLIF_Msk (0x1ul << USBD_GINTSTS_EPLIF_Pos) |
USBD_T::GINTSTS: EPLIF Mask
Definition at line 28013 of file NUC472_442.h.
| #define USBD_GINTSTS_EPLIF_Pos (13) |
USBD_T::GINTSTS: EPLIF Position
Definition at line 28012 of file NUC472_442.h.
| #define USBD_GINTSTS_USBIF_Msk (0x1ul << USBD_GINTSTS_USBIF_Pos) |
USBD_T::GINTSTS: USBIF Mask
Definition at line 27974 of file NUC472_442.h.
| #define USBD_GINTSTS_USBIF_Pos (0) |
@addtogroup USBD_CONST USBD Bit Field Definition Constant Definitions for USBD Controller
USBD_T::GINTSTS: USBIF Position
Definition at line 27973 of file NUC472_442.h.
| #define USBD_OPER_CURSPD_Msk (0x1ul << USBD_OPER_CURSPD_Pos) |
USBD_T::OPER: CURSPD Mask
Definition at line 28112 of file NUC472_442.h.
| #define USBD_OPER_CURSPD_Pos (2) |
USBD_T::OPER: CURSPD Position
Definition at line 28111 of file NUC472_442.h.
| #define USBD_OPER_HISPDEN_Msk (0x1ul << USBD_OPER_HISPDEN_Pos) |
USBD_T::OPER: HISPDEN Mask
Definition at line 28109 of file NUC472_442.h.
| #define USBD_OPER_HISPDEN_Pos (1) |
USBD_T::OPER: HISPDEN Position
Definition at line 28108 of file NUC472_442.h.
| #define USBD_OPER_RESUMEEN_Msk (0x1ul << USBD_OPER_RESUMEEN_Pos) |
USBD_T::OPER: RESUMEEN Mask
Definition at line 28106 of file NUC472_442.h.
| #define USBD_OPER_RESUMEEN_Pos (0) |
USBD_T::OPER: RESUMEEN Position
Definition at line 28105 of file NUC472_442.h.
| #define USBD_PHYCTL_DPPUEN_Msk (0x1ul << USBD_PHYCTL_DPPUEN_Pos) |
USBD_T::PHYCTL: DPPUEN Mask
Definition at line 28412 of file NUC472_442.h.
| #define USBD_PHYCTL_DPPUEN_Pos (8) |
USBD_T::PHYCTL: DPPUEN Position
Definition at line 28411 of file NUC472_442.h.
| #define USBD_PHYCTL_PHYEN_Msk (0x1ul << USBD_PHYCTL_PHYEN_Pos) |
USBD_T::PHYCTL: PHYEN Mask
Definition at line 28415 of file NUC472_442.h.
| #define USBD_PHYCTL_PHYEN_Pos (9) |
USBD_T::PHYCTL: PHYEN Position
Definition at line 28414 of file NUC472_442.h.
| #define USBD_PHYCTL_VBUSDET_Msk (0x1ul << USBD_PHYCTL_VBUSDET_Pos) |
USBD_T::PHYCTL: VBUSDET Mask
Definition at line 28421 of file NUC472_442.h.
| #define USBD_PHYCTL_VBUSDET_Pos (31) |
USBD_T::PHYCTL: VBUSDET Position
Definition at line 28420 of file NUC472_442.h.
| #define USBD_PHYCTL_WKEN_Msk (0x1ul << USBD_PHYCTL_WKEN_Pos) |
USBD_T::PHYCTL: WKEN Mask
Definition at line 28418 of file NUC472_442.h.
| #define USBD_PHYCTL_WKEN_Pos (24) |
USBD_T::PHYCTL: WKEN Position
Definition at line 28417 of file NUC472_442.h.
| #define USBD_SETUP1_0_SETUP0_Msk (0xfful << USBD_SETUP1_0_SETUP0_Pos) |
USBD_T::SETUP1_0: SETUP0 Mask
Definition at line 28229 of file NUC472_442.h.
| #define USBD_SETUP1_0_SETUP0_Pos (0) |
USBD_T::SETUP1_0: SETUP0 Position
Definition at line 28228 of file NUC472_442.h.
| #define USBD_SETUP1_0_SETUP1_Msk (0xfful << USBD_SETUP1_0_SETUP1_Pos) |
USBD_T::SETUP1_0: SETUP1 Mask
Definition at line 28232 of file NUC472_442.h.
| #define USBD_SETUP1_0_SETUP1_Pos (8) |
USBD_T::SETUP1_0: SETUP1 Position
Definition at line 28231 of file NUC472_442.h.
| #define USBD_SETUP3_2_SETUP2_Msk (0xfful << USBD_SETUP3_2_SETUP2_Pos) |
USBD_T::SETUP3_2: SETUP2 Mask
Definition at line 28235 of file NUC472_442.h.
| #define USBD_SETUP3_2_SETUP2_Pos (0) |
USBD_T::SETUP3_2: SETUP2 Position
Definition at line 28234 of file NUC472_442.h.
| #define USBD_SETUP3_2_SETUP3_Msk (0xfful << USBD_SETUP3_2_SETUP3_Pos) |
USBD_T::SETUP3_2: SETUP3 Mask
Definition at line 28238 of file NUC472_442.h.
| #define USBD_SETUP3_2_SETUP3_Pos (8) |
USBD_T::SETUP3_2: SETUP3 Position
Definition at line 28237 of file NUC472_442.h.
| #define USBD_SETUP5_4_SETUP4_Msk (0xfful << USBD_SETUP5_4_SETUP4_Pos) |
USBD_T::SETUP5_4: SETUP4 Mask
Definition at line 28241 of file NUC472_442.h.
| #define USBD_SETUP5_4_SETUP4_Pos (0) |
USBD_T::SETUP5_4: SETUP4 Position
Definition at line 28240 of file NUC472_442.h.
| #define USBD_SETUP5_4_SETUP5_Msk (0xfful << USBD_SETUP5_4_SETUP5_Pos) |
USBD_T::SETUP5_4: SETUP5 Mask
Definition at line 28244 of file NUC472_442.h.
| #define USBD_SETUP5_4_SETUP5_Pos (8) |
USBD_T::SETUP5_4: SETUP5 Position
Definition at line 28243 of file NUC472_442.h.
| #define USBD_SETUP7_6_SETUP6_Msk (0xfful << USBD_SETUP7_6_SETUP6_Pos) |
USBD_T::SETUP7_6: SETUP6 Mask
Definition at line 28247 of file NUC472_442.h.
| #define USBD_SETUP7_6_SETUP6_Pos (0) |
USBD_T::SETUP7_6: SETUP6 Position
Definition at line 28246 of file NUC472_442.h.
| #define USBD_SETUP7_6_SETUP7_Msk (0xfful << USBD_SETUP7_6_SETUP7_Pos) |
USBD_T::SETUP7_6: SETUP7 Mask
Definition at line 28250 of file NUC472_442.h.
| #define USBD_SETUP7_6_SETUP7_Pos (8) |
USBD_T::SETUP7_6: SETUP7 Position
Definition at line 28249 of file NUC472_442.h.
| #define USBD_TEST_TESTMODE_Msk (0x7ul << USBD_TEST_TESTMODE_Pos) |
USBD_T::TEST: TESTMODE Mask
Definition at line 28124 of file NUC472_442.h.
| #define USBD_TEST_TESTMODE_Pos (0) |
USBD_T::TEST: TESTMODE Position
Definition at line 28123 of file NUC472_442.h.
| #define USBH_HcBulkCurrentED_BCED_Msk (0xffffffful << USBH_HcBulkCurrentED_BCED_Pos) |
USBH_T::HcBulkCurrentED: BCED Mask
Definition at line 26808 of file NUC472_442.h.
| #define USBH_HcBulkCurrentED_BCED_Pos (4) |
USBH_T::HcBulkCurrentED: BCED Position
Definition at line 26807 of file NUC472_442.h.
| #define USBH_HcBulkHeadED_BHED_Msk (0xffffffful << USBH_HcBulkHeadED_BHED_Pos) |
USBH_T::HcBulkHeadED: BHED Mask
Definition at line 26805 of file NUC472_442.h.
| #define USBH_HcBulkHeadED_BHED_Pos (4) |
USBH_T::HcBulkHeadED: BHED Position
Definition at line 26804 of file NUC472_442.h.
| #define USBH_HcCommandStatus_BLF_Msk (0x1ul << USBH_HcCommandStatus_BLF_Pos) |
USBH_T::HcCommandStatus: BLF Mask
Definition at line 26727 of file NUC472_442.h.
| #define USBH_HcCommandStatus_BLF_Pos (2) |
USBH_T::HcCommandStatus: BLF Position
Definition at line 26726 of file NUC472_442.h.
| #define USBH_HcCommandStatus_CLF_Msk (0x1ul << USBH_HcCommandStatus_CLF_Pos) |
USBH_T::HcCommandStatus: CLF Mask
Definition at line 26724 of file NUC472_442.h.
| #define USBH_HcCommandStatus_CLF_Pos (1) |
USBH_T::HcCommandStatus: CLF Position
Definition at line 26723 of file NUC472_442.h.
| #define USBH_HcCommandStatus_HCR_Msk (0x1ul << USBH_HcCommandStatus_HCR_Pos) |
USBH_T::HcCommandStatus: HCR Mask
Definition at line 26721 of file NUC472_442.h.
| #define USBH_HcCommandStatus_HCR_Pos (0) |
USBH_T::HcCommandStatus: HCR Position
Definition at line 26720 of file NUC472_442.h.
| #define USBH_HcCommandStatus_SOC_Msk (0x3ul << USBH_HcCommandStatus_SOC_Pos) |
USBH_T::HcCommandStatus: SOC Mask
Definition at line 26730 of file NUC472_442.h.
| #define USBH_HcCommandStatus_SOC_Pos (16) |
USBH_T::HcCommandStatus: SOC Position
Definition at line 26729 of file NUC472_442.h.
| #define USBH_HcControl_BLE_Msk (0x1ul << USBH_HcControl_BLE_Pos) |
USBH_T::HcControl: BLE Mask
Definition at line 26715 of file NUC472_442.h.
| #define USBH_HcControl_BLE_Pos (5) |
USBH_T::HcControl: BLE Position
Definition at line 26714 of file NUC472_442.h.
| #define USBH_HcControl_CBSR_Msk (0x3ul << USBH_HcControl_CBSR_Pos) |
USBH_T::HcControl: CBSR Mask
Definition at line 26703 of file NUC472_442.h.
| #define USBH_HcControl_CBSR_Pos (0) |
USBH_T::HcControl: CBSR Position
Definition at line 26702 of file NUC472_442.h.
| #define USBH_HcControl_CLE_Msk (0x1ul << USBH_HcControl_CLE_Pos) |
USBH_T::HcControl: CLE Mask
Definition at line 26712 of file NUC472_442.h.
| #define USBH_HcControl_CLE_Pos (4) |
USBH_T::HcControl: CLE Position
Definition at line 26711 of file NUC472_442.h.
| #define USBH_HcControl_HCFS_Msk (0x3ul << USBH_HcControl_HCFS_Pos) |
USBH_T::HcControl: HCFS Mask
Definition at line 26718 of file NUC472_442.h.
| #define USBH_HcControl_HCFS_Pos (6) |
USBH_T::HcControl: HCFS Position
Definition at line 26717 of file NUC472_442.h.
| #define USBH_HcControl_IE_Msk (0x1ul << USBH_HcControl_IE_Pos) |
USBH_T::HcControl: IE Mask
Definition at line 26709 of file NUC472_442.h.
| #define USBH_HcControl_IE_Pos (3) |
USBH_T::HcControl: IE Position
Definition at line 26708 of file NUC472_442.h.
| #define USBH_HcControl_PLE_Msk (0x1ul << USBH_HcControl_PLE_Pos) |
USBH_T::HcControl: CBSR Mask
Definition at line 26706 of file NUC472_442.h.
| #define USBH_HcControl_PLE_Pos (2) |
USBH_T::HcControl: CBSR Position
Definition at line 26705 of file NUC472_442.h.
| #define USBH_HcControlCurrentED_CCED_Msk (0xffffffful << USBH_HcControlCurrentED_CCED_Pos) |
USBH_T::HcControlCurrentED: CCED Mask
Definition at line 26802 of file NUC472_442.h.
| #define USBH_HcControlCurrentED_CCED_Pos (4) |
USBH_T::HcControlCurrentED: CCED Position
Definition at line 26801 of file NUC472_442.h.
| #define USBH_HcControlHeadED_CHED_Msk (0xffffffful << USBH_HcControlHeadED_CHED_Pos) |
USBH_T::HcControlHeadED: CHED Mask
Definition at line 26799 of file NUC472_442.h.
| #define USBH_HcControlHeadED_CHED_Pos (4) |
USBH_T::HcControlHeadED: CHED Position
Definition at line 26798 of file NUC472_442.h.
| #define USBH_HcDoneHead_DH_Msk (0xffffffful << USBH_HcDoneHead_DH_Pos) |
USBH_T::HcDoneHead: DH Mask
Definition at line 26811 of file NUC472_442.h.
| #define USBH_HcDoneHead_DH_Pos (4) |
USBH_T::HcDoneHead: DH Position
Definition at line 26810 of file NUC472_442.h.
| #define USBH_HcFmInterval_FI_Msk (0x3ffful << USBH_HcFmInterval_FI_Pos) |
USBH_T::HcFmInterval: FI Mask
Definition at line 26814 of file NUC472_442.h.
| #define USBH_HcFmInterval_FI_Pos (0) |
USBH_T::HcFmInterval: FI Position
Definition at line 26813 of file NUC472_442.h.
| #define USBH_HcFmInterval_FIT_Msk (0x1ul << USBH_HcFmInterval_FIT_Pos) |
USBH_T::HcFmInterval: FIT Mask
Definition at line 26820 of file NUC472_442.h.
| #define USBH_HcFmInterval_FIT_Pos (31) |
USBH_T::HcFmInterval: FIT Position
Definition at line 26819 of file NUC472_442.h.
| #define USBH_HcFmInterval_FSMPS_Msk (0x7ffful << USBH_HcFmInterval_FSMPS_Pos) |
USBH_T::HcFmInterval: FSMPS Mask
Definition at line 26817 of file NUC472_442.h.
| #define USBH_HcFmInterval_FSMPS_Pos (16) |
USBH_T::HcFmInterval: FSMPS Position
Definition at line 26816 of file NUC472_442.h.
| #define USBH_HcFmNumber_FN_Msk (0xfffful << USBH_HcFmNumber_FN_Pos) |
USBH_T::HcFmNumber: FN Mask
Definition at line 26829 of file NUC472_442.h.
| #define USBH_HcFmNumber_FN_Pos (0) |
USBH_T::HcFmNumber: FN Position
Definition at line 26828 of file NUC472_442.h.
| #define USBH_HcFmRemaining_FR_Msk (0x3ffful << USBH_HcFmRemaining_FR_Pos) |
USBH_T::HcFmRemaining: FR Mask
Definition at line 26823 of file NUC472_442.h.
| #define USBH_HcFmRemaining_FR_Pos (0) |
USBH_T::HcFmRemaining: FR Position
Definition at line 26822 of file NUC472_442.h.
| #define USBH_HcFmRemaining_FRT_Msk (0x1ul << USBH_HcFmRemaining_FRT_Pos) |
USBH_T::HcFmRemaining: FRT Mask
Definition at line 26826 of file NUC472_442.h.
| #define USBH_HcFmRemaining_FRT_Pos (31) |
USBH_T::HcFmRemaining: FRT Position
Definition at line 26825 of file NUC472_442.h.
| #define USBH_HcHCCA_HCCA_Msk (0xfffffful << USBH_HcHCCA_HCCA_Pos) |
USBH_T::HcHCCA: HCCA Mask
Definition at line 26793 of file NUC472_442.h.
| #define USBH_HcHCCA_HCCA_Pos (8) |
USBH_T::HcHCCA: HCCA Position
Definition at line 26792 of file NUC472_442.h.
| #define USBH_HcInterruptDisable_FNO_Msk (0x1ul << USBH_HcInterruptDisable_FNO_Pos) |
USBH_T::HcInterruptDisable: FNO Mask
Definition at line 26784 of file NUC472_442.h.
| #define USBH_HcInterruptDisable_FNO_Pos (5) |
USBH_T::HcInterruptDisable: FNO Position
Definition at line 26783 of file NUC472_442.h.
| #define USBH_HcInterruptDisable_MIE_Msk (0x1ul << USBH_HcInterruptDisable_MIE_Pos) |
USBH_T::HcInterruptDisable: MIE Mask
Definition at line 26790 of file NUC472_442.h.
| #define USBH_HcInterruptDisable_MIE_Pos (31) |
USBH_T::HcInterruptDisable: MIE Position
Definition at line 26789 of file NUC472_442.h.
| #define USBH_HcInterruptDisable_RD_Msk (0x1ul << USBH_HcInterruptDisable_RD_Pos) |
USBH_T::HcInterruptDisable: RD Mask
Definition at line 26781 of file NUC472_442.h.
| #define USBH_HcInterruptDisable_RD_Pos (3) |
USBH_T::HcInterruptDisable: RD Position
Definition at line 26780 of file NUC472_442.h.
| #define USBH_HcInterruptDisable_RHSC_Msk (0x1ul << USBH_HcInterruptDisable_RHSC_Pos) |
USBH_T::HcInterruptDisable: RHSC Mask
Definition at line 26787 of file NUC472_442.h.
| #define USBH_HcInterruptDisable_RHSC_Pos (6) |
USBH_T::HcInterruptDisable: RHSC Position
Definition at line 26786 of file NUC472_442.h.
| #define USBH_HcInterruptDisable_SF_Msk (0x1ul << USBH_HcInterruptDisable_SF_Pos) |
USBH_T::HcInterruptDisable: SF Mask
Definition at line 26778 of file NUC472_442.h.
| #define USBH_HcInterruptDisable_SF_Pos (2) |
USBH_T::HcInterruptDisable: SF Position
Definition at line 26777 of file NUC472_442.h.
| #define USBH_HcInterruptDisable_SO_Msk (0x1ul << USBH_HcInterruptDisable_SO_Pos) |
USBH_T::HcInterruptDisable: SO Mask
Definition at line 26772 of file NUC472_442.h.
| #define USBH_HcInterruptDisable_SO_Pos (0) |
USBH_T::HcInterruptDisable: SO Position
Definition at line 26771 of file NUC472_442.h.
| #define USBH_HcInterruptDisable_WDH_Msk (0x1ul << USBH_HcInterruptDisable_WDH_Pos) |
USBH_T::HcInterruptDisable: WDH Mask
Definition at line 26775 of file NUC472_442.h.
| #define USBH_HcInterruptDisable_WDH_Pos (1) |
USBH_T::HcInterruptDisable: WDH Position
Definition at line 26774 of file NUC472_442.h.
| #define USBH_HcInterruptEnable_FNO_Msk (0x1ul << USBH_HcInterruptEnable_FNO_Pos) |
USBH_T::HcInterruptEnable: FNO Mask
Definition at line 26763 of file NUC472_442.h.
| #define USBH_HcInterruptEnable_FNO_Pos (5) |
USBH_T::HcInterruptEnable: FNO Position
Definition at line 26762 of file NUC472_442.h.
| #define USBH_HcInterruptEnable_MIE_Msk (0x1ul << USBH_HcInterruptEnable_MIE_Pos) |
USBH_T::HcInterruptEnable: MIE Mask
Definition at line 26769 of file NUC472_442.h.
| #define USBH_HcInterruptEnable_MIE_Pos (31) |
USBH_T::HcInterruptEnable: MIE Position
Definition at line 26768 of file NUC472_442.h.
| #define USBH_HcInterruptEnable_RD_Msk (0x1ul << USBH_HcInterruptEnable_RD_Pos) |
USBH_T::HcInterruptEnable: RD Mask
Definition at line 26760 of file NUC472_442.h.
| #define USBH_HcInterruptEnable_RD_Pos (3) |
USBH_T::HcInterruptEnable: RD Position
Definition at line 26759 of file NUC472_442.h.
| #define USBH_HcInterruptEnable_RHSC_Msk (0x1ul << USBH_HcInterruptEnable_RHSC_Pos) |
USBH_T::HcInterruptEnable: RHSC Mask
Definition at line 26766 of file NUC472_442.h.
| #define USBH_HcInterruptEnable_RHSC_Pos (6) |
USBH_T::HcInterruptEnable: RHSC Position
Definition at line 26765 of file NUC472_442.h.
| #define USBH_HcInterruptEnable_SF_Msk (0x1ul << USBH_HcInterruptEnable_SF_Pos) |
USBH_T::HcInterruptEnable: SF Mask
Definition at line 26757 of file NUC472_442.h.
| #define USBH_HcInterruptEnable_SF_Pos (2) |
USBH_T::HcInterruptEnable: SF Position
Definition at line 26756 of file NUC472_442.h.
| #define USBH_HcInterruptEnable_SO_Msk (0x1ul << USBH_HcInterruptEnable_SO_Pos) |
USBH_T::HcInterruptEnable: SO Mask
Definition at line 26751 of file NUC472_442.h.
| #define USBH_HcInterruptEnable_SO_Pos (0) |
USBH_T::HcInterruptEnable: SO Position
Definition at line 26750 of file NUC472_442.h.
| #define USBH_HcInterruptEnable_WDH_Msk (0x1ul << USBH_HcInterruptEnable_WDH_Pos) |
USBH_T::HcInterruptEnable: WDH Mask
Definition at line 26754 of file NUC472_442.h.
| #define USBH_HcInterruptEnable_WDH_Pos (1) |
USBH_T::HcInterruptEnable: WDH Position
Definition at line 26753 of file NUC472_442.h.
| #define USBH_HcInterruptStatus_FNO_Msk (0x1ul << USBH_HcInterruptStatus_FNO_Pos) |
USBH_T::HcInterruptStatus: FNO Mask
Definition at line 26745 of file NUC472_442.h.
| #define USBH_HcInterruptStatus_FNO_Pos (5) |
USBH_T::HcInterruptStatus: FNO Position
Definition at line 26744 of file NUC472_442.h.
| #define USBH_HcInterruptStatus_RD_Msk (0x1ul << USBH_HcInterruptStatus_RD_Pos) |
USBH_T::HcInterruptStatus: RD Mask
Definition at line 26742 of file NUC472_442.h.
| #define USBH_HcInterruptStatus_RD_Pos (3) |
USBH_T::HcInterruptStatus: RD Position
Definition at line 26741 of file NUC472_442.h.
| #define USBH_HcInterruptStatus_RHSC_Msk (0x1ul << USBH_HcInterruptStatus_RHSC_Pos) |
USBH_T::HcInterruptStatus: RHSC Mask
Definition at line 26748 of file NUC472_442.h.
| #define USBH_HcInterruptStatus_RHSC_Pos (6) |
USBH_T::HcInterruptStatus: RHSC Position
Definition at line 26747 of file NUC472_442.h.
| #define USBH_HcInterruptStatus_SF_Msk (0x1ul << USBH_HcInterruptStatus_SF_Pos) |
USBH_T::HcInterruptStatus: SF Mask
Definition at line 26739 of file NUC472_442.h.
| #define USBH_HcInterruptStatus_SF_Pos (2) |
USBH_T::HcInterruptStatus: SF Position
Definition at line 26738 of file NUC472_442.h.
| #define USBH_HcInterruptStatus_SO_Msk (0x1ul << USBH_HcInterruptStatus_SO_Pos) |
USBH_T::HcInterruptStatus: SO Mask
Definition at line 26733 of file NUC472_442.h.
| #define USBH_HcInterruptStatus_SO_Pos (0) |
USBH_T::HcInterruptStatus: SO Position
Definition at line 26732 of file NUC472_442.h.
| #define USBH_HcInterruptStatus_WDH_Msk (0x1ul << USBH_HcInterruptStatus_WDH_Pos) |
USBH_T::HcInterruptStatus: WDH Mask
Definition at line 26736 of file NUC472_442.h.
| #define USBH_HcInterruptStatus_WDH_Pos (1) |
USBH_T::HcInterruptStatus: WDH Position
Definition at line 26735 of file NUC472_442.h.
| #define USBH_HcLSThreshold_LST_Msk (0xffful << USBH_HcLSThreshold_LST_Pos) |
USBH_T::HcLSThreshold: LST Mask
Definition at line 26835 of file NUC472_442.h.
| #define USBH_HcLSThreshold_LST_Pos (0) |
USBH_T::HcLSThreshold: LST Position
Definition at line 26834 of file NUC472_442.h.
| #define USBH_HcMiscControl_ABORT_Msk (0x1ul << USBH_HcMiscControl_ABORT_Pos) |
USBH_T::HcMiscControl: ABORT Mask
Definition at line 26922 of file NUC472_442.h.
| #define USBH_HcMiscControl_ABORT_Pos (1) |
USBH_T::HcMiscControl: ABORT Position
Definition at line 26921 of file NUC472_442.h.
| #define USBH_HcMiscControl_DBR16_Msk (0x1ul << USBH_HcMiscControl_DBR16_Pos) |
USBH_T::HcMiscControl: DBR16 Mask
Definition at line 26919 of file NUC472_442.h.
| #define USBH_HcMiscControl_DBR16_Pos (0) |
USBH_T::HcMiscControl: DBR16 Position
Definition at line 26918 of file NUC472_442.h.
| #define USBH_HcMiscControl_DPRT1_Msk (0x1ul << USBH_HcMiscControl_DPRT1_Pos) |
USBH_T::HcMiscControl: DPRT1 Mask
Definition at line 26934 of file NUC472_442.h.
| #define USBH_HcMiscControl_DPRT1_Pos (16) |
USBH_T::HcMiscControl: DPRT1 Position
Definition at line 26933 of file NUC472_442.h.
| #define USBH_HcMiscControl_DPRT2_Msk (0x1ul << USBH_HcMiscControl_DPRT2_Pos) |
USBH_T::HcMiscControl: DPRT2 Mask
Definition at line 26937 of file NUC472_442.h.
| #define USBH_HcMiscControl_DPRT2_Pos (17) |
USBH_T::HcMiscControl: DPRT2 Position
Definition at line 26936 of file NUC472_442.h.
| #define USBH_HcMiscControl_OCAL_Msk (0x1ul << USBH_HcMiscControl_OCAL_Pos) |
USBH_T::HcMiscControl: OCAL Mask
Definition at line 26925 of file NUC472_442.h.
| #define USBH_HcMiscControl_OCAL_Pos (3) |
USBH_T::HcMiscControl: OCAL Position
Definition at line 26924 of file NUC472_442.h.
| #define USBH_HcMiscControl_PCAL_Msk (0x1ul << USBH_HcMiscControl_PCAL_Pos) |
USBH_T::HcMiscControl: PCAL Mask
Definition at line 26928 of file NUC472_442.h.
| #define USBH_HcMiscControl_PCAL_Pos (4) |
USBH_T::HcMiscControl: PCAL Position
Definition at line 26927 of file NUC472_442.h.
| #define USBH_HcMiscControl_SIEPD_Msk (0x1ul << USBH_HcMiscControl_SIEPD_Pos) |
USBH_T::HcMiscControl: SIEPD Mask
Definition at line 26931 of file NUC472_442.h.
| #define USBH_HcMiscControl_SIEPD_Pos (8) |
USBH_T::HcMiscControl: SIEPD Position
Definition at line 26930 of file NUC472_442.h.
| #define USBH_HcPeriodCurrentED_PCED_Msk (0xffffffful << USBH_HcPeriodCurrentED_PCED_Pos) |
USBH_T::HcPeriodCurrentED: PCED Mask
Definition at line 26796 of file NUC472_442.h.
| #define USBH_HcPeriodCurrentED_PCED_Pos (4) |
USBH_T::HcPeriodCurrentED: PCED Position
Definition at line 26795 of file NUC472_442.h.
| #define USBH_HcPeriodicStart_PS_Msk (0x3ffful << USBH_HcPeriodicStart_PS_Pos) |
USBH_T::HcPeriodicStart: PS Mask
Definition at line 26832 of file NUC472_442.h.
| #define USBH_HcPeriodicStart_PS_Pos (0) |
USBH_T::HcPeriodicStart: PS Position
Definition at line 26831 of file NUC472_442.h.
| #define USBH_HcPhyControl_STBYEN_Msk (0x1ul << USBH_HcPhyControl_STBYEN_Pos) |
USBH_T::HcPhyControl: STBYEN Mask
Definition at line 26916 of file NUC472_442.h.
| #define USBH_HcPhyControl_STBYEN_Pos (27) |
USBH_T::HcPhyControl: STBYEN Position
Definition at line 26915 of file NUC472_442.h.
| #define USBH_HcRevision_REV_Msk (0xfful << USBH_HcRevision_REV_Pos) |
USBH_T::HcRevision: REV Mask
Definition at line 26700 of file NUC472_442.h.
| #define USBH_HcRevision_REV_Pos (0) |
@addtogroup USBH_CONST USBH Bit Field Definition Constant Definitions for USBH Controller
USBH_T::HcRevision: REV Position
Definition at line 26699 of file NUC472_442.h.
| #define USBH_HcRhDescriptorA_DT_Msk (0x1ul << USBH_HcRhDescriptorA_DT_Pos) |
USBH_T::HcRhDescriptorA: DT Mask
Definition at line 26847 of file NUC472_442.h.
| #define USBH_HcRhDescriptorA_DT_Pos (10) |
USBH_T::HcRhDescriptorA: DT Position
Definition at line 26846 of file NUC472_442.h.
| #define USBH_HcRhDescriptorA_NDP_Msk (0xfful << USBH_HcRhDescriptorA_NDP_Pos) |
USBH_T::HcRhDescriptorA: NDP Mask
Definition at line 26838 of file NUC472_442.h.
| #define USBH_HcRhDescriptorA_NDP_Pos (0) |
USBH_T::HcRhDescriptorA: NDP Position
Definition at line 26837 of file NUC472_442.h.
| #define USBH_HcRhDescriptorA_NOCP_Msk (0x1ul << USBH_HcRhDescriptorA_NOCP_Pos) |
USBH_T::HcRhDescriptorA: NOCP Mask
Definition at line 26853 of file NUC472_442.h.
| #define USBH_HcRhDescriptorA_NOCP_Pos (12) |
USBH_T::HcRhDescriptorA: NOCP Position
Definition at line 26852 of file NUC472_442.h.
| #define USBH_HcRhDescriptorA_NPS_Msk (0x1ul << USBH_HcRhDescriptorA_NPS_Pos) |
USBH_T::HcRhDescriptorA: NPS Mask
Definition at line 26844 of file NUC472_442.h.
| #define USBH_HcRhDescriptorA_NPS_Pos (9) |
USBH_T::HcRhDescriptorA: NPS Position
Definition at line 26843 of file NUC472_442.h.
| #define USBH_HcRhDescriptorA_OCPM_Msk (0x1ul << USBH_HcRhDescriptorA_OCPM_Pos) |
USBH_T::HcRhDescriptorA: OCPM Mask
Definition at line 26850 of file NUC472_442.h.
| #define USBH_HcRhDescriptorA_OCPM_Pos (11) |
USBH_T::HcRhDescriptorA: OCPM Position
Definition at line 26849 of file NUC472_442.h.
| #define USBH_HcRhDescriptorA_POTPGT_Msk (0xfful << USBH_HcRhDescriptorA_POTPGT_Pos) |
USBH_T::HcRhDescriptorA: POTPGT Mask
Definition at line 26856 of file NUC472_442.h.
| #define USBH_HcRhDescriptorA_POTPGT_Pos (24) |
USBH_T::HcRhDescriptorA: POTPGT Position
Definition at line 26855 of file NUC472_442.h.
| #define USBH_HcRhDescriptorA_PSM_Msk (0x1ul << USBH_HcRhDescriptorA_PSM_Pos) |
USBH_T::HcRhDescriptorA: PSM Mask
Definition at line 26841 of file NUC472_442.h.
| #define USBH_HcRhDescriptorA_PSM_Pos (8) |
USBH_T::HcRhDescriptorA: PSM Position
Definition at line 26840 of file NUC472_442.h.
| #define USBH_HcRhDescriptorB_PPCM_Msk (0xfffful << USBH_HcRhDescriptorB_PPCM_Pos) |
USBH_T::HcRhDescriptorB: PPCM Mask
Definition at line 26859 of file NUC472_442.h.
| #define USBH_HcRhDescriptorB_PPCM_Pos (16) |
USBH_T::HcRhDescriptorB: PPCM Position
Definition at line 26858 of file NUC472_442.h.
| #define USBH_HcRhPortStatus_CCS_Msk (0x1ul << USBH_HcRhPortStatus_CCS_Pos) |
USBH_T::HcRhPortStatus: CCS Mask
Definition at line 26880 of file NUC472_442.h.
| #define USBH_HcRhPortStatus_CCS_Pos (0) |
USBH_T::HcRhPortStatus: CCS Position
Definition at line 26879 of file NUC472_442.h.
| #define USBH_HcRhPortStatus_CSC_Msk (0x1ul << USBH_HcRhPortStatus_CSC_Pos) |
USBH_T::HcRhPortStatus: CSC Mask
Definition at line 26901 of file NUC472_442.h.
| #define USBH_HcRhPortStatus_CSC_Pos (16) |
USBH_T::HcRhPortStatus: CSC Position
Definition at line 26900 of file NUC472_442.h.
| #define USBH_HcRhPortStatus_LSDA_Msk (0x1ul << USBH_HcRhPortStatus_LSDA_Pos) |
USBH_T::HcRhPortStatus: LSDA Mask
Definition at line 26898 of file NUC472_442.h.
| #define USBH_HcRhPortStatus_LSDA_Pos (9) |
USBH_T::HcRhPortStatus: LSDA Position
Definition at line 26897 of file NUC472_442.h.
| #define USBH_HcRhPortStatus_OCIC_Msk (0x1ul << USBH_HcRhPortStatus_OCIC_Pos) |
USBH_T::HcRhPortStatus: OCIC Mask
Definition at line 26910 of file NUC472_442.h.
| #define USBH_HcRhPortStatus_OCIC_Pos (19) |
USBH_T::HcRhPortStatus: OCIC Position
Definition at line 26909 of file NUC472_442.h.
| #define USBH_HcRhPortStatus_PES_Msk (0x1ul << USBH_HcRhPortStatus_PES_Pos) |
USBH_T::HcRhPortStatus: PES Mask
Definition at line 26883 of file NUC472_442.h.
| #define USBH_HcRhPortStatus_PES_Pos (1) |
USBH_T::HcRhPortStatus: PES Position
Definition at line 26882 of file NUC472_442.h.
| #define USBH_HcRhPortStatus_PESC_Msk (0x1ul << USBH_HcRhPortStatus_PESC_Pos) |
USBH_T::HcRhPortStatus: PESC Mask
Definition at line 26904 of file NUC472_442.h.
| #define USBH_HcRhPortStatus_PESC_Pos (17) |
USBH_T::HcRhPortStatus: PESC Position
Definition at line 26903 of file NUC472_442.h.
| #define USBH_HcRhPortStatus_POCI_Msk (0x1ul << USBH_HcRhPortStatus_POCI_Pos) |
USBH_T::HcRhPortStatus: POCI Mask
Definition at line 26889 of file NUC472_442.h.
| #define USBH_HcRhPortStatus_POCI_Pos (3) |
USBH_T::HcRhPortStatus: POCI Position
Definition at line 26888 of file NUC472_442.h.
| #define USBH_HcRhPortStatus_PPS_Msk (0x1ul << USBH_HcRhPortStatus_PPS_Pos) |
USBH_T::HcRhPortStatus: PPS Mask
Definition at line 26895 of file NUC472_442.h.
| #define USBH_HcRhPortStatus_PPS_Pos (8) |
USBH_T::HcRhPortStatus: PPS Position
Definition at line 26894 of file NUC472_442.h.
| #define USBH_HcRhPortStatus_PRS_Msk (0x1ul << USBH_HcRhPortStatus_PRS_Pos) |
USBH_T::HcRhPortStatus: PRS Mask
Definition at line 26892 of file NUC472_442.h.
| #define USBH_HcRhPortStatus_PRS_Pos (4) |
USBH_T::HcRhPortStatus: PRS Position
Definition at line 26891 of file NUC472_442.h.
| #define USBH_HcRhPortStatus_PRSC_Msk (0x1ul << USBH_HcRhPortStatus_PRSC_Pos) |
USBH_T::HcRhPortStatus: PRSC Mask
Definition at line 26913 of file NUC472_442.h.
| #define USBH_HcRhPortStatus_PRSC_Pos (20) |
USBH_T::HcRhPortStatus: PRSC Position
Definition at line 26912 of file NUC472_442.h.
| #define USBH_HcRhPortStatus_PSS_Msk (0x1ul << USBH_HcRhPortStatus_PSS_Pos) |
USBH_T::HcRhPortStatus: PSS Mask
Definition at line 26886 of file NUC472_442.h.
| #define USBH_HcRhPortStatus_PSS_Pos (2) |
USBH_T::HcRhPortStatus: PSS Position
Definition at line 26885 of file NUC472_442.h.
| #define USBH_HcRhPortStatus_PSSC_Msk (0x1ul << USBH_HcRhPortStatus_PSSC_Pos) |
USBH_T::HcRhPortStatus: PSSC Mask
Definition at line 26907 of file NUC472_442.h.
| #define USBH_HcRhPortStatus_PSSC_Pos (18) |
USBH_T::HcRhPortStatus: PSSC Position
Definition at line 26906 of file NUC472_442.h.
| #define USBH_HcRhStatus_CRWE_Msk (0x1ul << USBH_HcRhStatus_CRWE_Pos) |
USBH_T::HcRhStatus: CRWE Mask
Definition at line 26877 of file NUC472_442.h.
| #define USBH_HcRhStatus_CRWE_Pos (31) |
USBH_T::HcRhStatus: CRWE Position
Definition at line 26876 of file NUC472_442.h.
| #define USBH_HcRhStatus_DRWE_Msk (0x1ul << USBH_HcRhStatus_DRWE_Pos) |
USBH_T::HcRhStatus: DRWE Mask
Definition at line 26868 of file NUC472_442.h.
| #define USBH_HcRhStatus_DRWE_Pos (15) |
USBH_T::HcRhStatus: DRWE Position
Definition at line 26867 of file NUC472_442.h.
| #define USBH_HcRhStatus_LPS_Msk (0x1ul << USBH_HcRhStatus_LPS_Pos) |
USBH_T::HcRhStatus: LPS Mask
Definition at line 26862 of file NUC472_442.h.
| #define USBH_HcRhStatus_LPS_Pos (0) |
USBH_T::HcRhStatus: LPS Position
Definition at line 26861 of file NUC472_442.h.
| #define USBH_HcRhStatus_LPSC_Msk (0x1ul << USBH_HcRhStatus_LPSC_Pos) |
USBH_T::HcRhStatus: LPSC Mask
Definition at line 26871 of file NUC472_442.h.
| #define USBH_HcRhStatus_LPSC_Pos (16) |
USBH_T::HcRhStatus: LPSC Position
Definition at line 26870 of file NUC472_442.h.
| #define USBH_HcRhStatus_OCI_Msk (0x1ul << USBH_HcRhStatus_OCI_Pos) |
USBH_T::HcRhStatus: OCI Mask
Definition at line 26865 of file NUC472_442.h.
| #define USBH_HcRhStatus_OCI_Pos (1) |
USBH_T::HcRhStatus: OCI Position
Definition at line 26864 of file NUC472_442.h.
| #define USBH_HcRhStatus_OCIC_Msk (0x1ul << USBH_HcRhStatus_OCIC_Pos) |
USBH_T::HcRhStatus: OCIC Mask
Definition at line 26874 of file NUC472_442.h.
| #define USBH_HcRhStatus_OCIC_Pos (17) |
USBH_T::HcRhStatus: OCIC Position
Definition at line 26873 of file NUC472_442.h.
| #define WDT_ALTCTL_RSTDSEL_Msk (0x3ul << WDT_ALTCTL_RSTDSEL_Pos) |
WDT_T::ALTCTL: RSTDSEL Mask
Definition at line 28553 of file NUC472_442.h.
| #define WDT_ALTCTL_RSTDSEL_Pos (0) |
WDT_T::ALTCTL: RSTDSEL Position
Definition at line 28552 of file NUC472_442.h.
| #define WDT_CTL_ICEDEBUG_Msk (0x1ul << WDT_CTL_ICEDEBUG_Pos) |
WDT_T::CTL: ICEDEBUG Mask
Definition at line 28550 of file NUC472_442.h.
| #define WDT_CTL_ICEDEBUG_Pos (31) |
WDT_T::CTL: ICEDEBUG Position
Definition at line 28549 of file NUC472_442.h.
| #define WDT_CTL_IF_Msk (0x1ul << WDT_CTL_IF_Pos) |
WDT_T::CTL: IF Mask
Definition at line 28532 of file NUC472_442.h.
| #define WDT_CTL_IF_Pos (3) |
WDT_T::CTL: IF Position
Definition at line 28531 of file NUC472_442.h.
| #define WDT_CTL_INTEN_Msk (0x1ul << WDT_CTL_INTEN_Pos) |
WDT_T::CTL: INTEN Mask
Definition at line 28541 of file NUC472_442.h.
| #define WDT_CTL_INTEN_Pos (6) |
WDT_T::CTL: INTEN Position
Definition at line 28540 of file NUC472_442.h.
| #define WDT_CTL_RSTCNT_Msk (0x1ul << WDT_CTL_RSTCNT_Pos) |
WDT_T::CTL: RSTCNT Mask
Definition at line 28523 of file NUC472_442.h.
| #define WDT_CTL_RSTCNT_Pos (0) |
@addtogroup WDT_CONST WDT Bit Field Definition Constant Definitions for WDT Controller
WDT_T::CTL: RSTCNT Position
Definition at line 28522 of file NUC472_442.h.
| #define WDT_CTL_RSTEN_Msk (0x1ul << WDT_CTL_RSTEN_Pos) |
WDT_T::CTL: RSTEN Mask
Definition at line 28526 of file NUC472_442.h.
| #define WDT_CTL_RSTEN_Pos (1) |
WDT_T::CTL: RSTEN Position
Definition at line 28525 of file NUC472_442.h.
| #define WDT_CTL_RSTF_Msk (0x1ul << WDT_CTL_RSTF_Pos) |
WDT_T::CTL: RSTF Mask
Definition at line 28529 of file NUC472_442.h.
| #define WDT_CTL_RSTF_Pos (2) |
WDT_T::CTL: RSTF Position
Definition at line 28528 of file NUC472_442.h.
| #define WDT_CTL_TOUTSEL_Msk (0x7ul << WDT_CTL_TOUTSEL_Pos) |
WDT_T::CTL: TOUTSEL Mask
Definition at line 28547 of file NUC472_442.h.
| #define WDT_CTL_TOUTSEL_Pos (8) |
WDT_T::CTL: TOUTSEL Position
Definition at line 28546 of file NUC472_442.h.
| #define WDT_CTL_WDTEN_Msk (0x1ul << WDT_CTL_WDTEN_Pos) |
WDT_T::CTL: WDTEN Mask
Definition at line 28544 of file NUC472_442.h.
| #define WDT_CTL_WDTEN_Pos (7) |
WDT_T::CTL: WDTEN Position
Definition at line 28543 of file NUC472_442.h.
| #define WDT_CTL_WKEN_Msk (0x1ul << WDT_CTL_WKEN_Pos) |
WDT_T::CTL: WKEN Mask
Definition at line 28535 of file NUC472_442.h.
| #define WDT_CTL_WKEN_Pos (4) |
WDT_T::CTL: WKEN Position
Definition at line 28534 of file NUC472_442.h.
| #define WDT_CTL_WKF_Msk (0x1ul << WDT_CTL_WKF_Pos) |
WDT_T::CTL: WKF Mask
Definition at line 28538 of file NUC472_442.h.
| #define WDT_CTL_WKF_Pos (5) |
WDT_T::CTL: WKF Position
Definition at line 28537 of file NUC472_442.h.
| #define WWDT_CNT_CNTDAT_Msk (0x3ful << WWDT_CNT_CNTDAT_Pos) |
WWDT_T::CNT: CNTDAT Mask
Definition at line 28690 of file NUC472_442.h.
| #define WWDT_CNT_CNTDAT_Pos (0) |
WWDT_T::CNT: CNTDAT Position
Definition at line 28689 of file NUC472_442.h.
| #define WWDT_CTL_CMPDAT_Msk (0x3ful << WWDT_CTL_CMPDAT_Pos) |
WWDT_T::CTL: CMPDAT Mask
Definition at line 28678 of file NUC472_442.h.
| #define WWDT_CTL_CMPDAT_Pos (16) |
WWDT_T::CTL: CMPDAT Position
Definition at line 28677 of file NUC472_442.h.
| #define WWDT_CTL_ICEDEBUG_Msk (0x1ul << WWDT_CTL_ICEDEBUG_Pos) |
WWDT_T::CTL: ICEDEBUG Mask
Definition at line 28681 of file NUC472_442.h.
| #define WWDT_CTL_ICEDEBUG_Pos (31) |
WWDT_T::CTL: ICEDEBUG Position
Definition at line 28680 of file NUC472_442.h.
| #define WWDT_CTL_INTEN_Msk (0x1ul << WWDT_CTL_INTEN_Pos) |
WWDT_T::CTL: INTEN Mask
Definition at line 28672 of file NUC472_442.h.
| #define WWDT_CTL_INTEN_Pos (1) |
WWDT_T::CTL: INTEN Position
Definition at line 28671 of file NUC472_442.h.
| #define WWDT_CTL_PSCSEL_Msk (0xful << WWDT_CTL_PSCSEL_Pos) |
WWDT_T::CTL: PSCSEL Mask
Definition at line 28675 of file NUC472_442.h.
| #define WWDT_CTL_PSCSEL_Pos (8) |
WWDT_T::CTL: PSCSEL Position
Definition at line 28674 of file NUC472_442.h.
| #define WWDT_CTL_WWDTEN_Msk (0x1ul << WWDT_CTL_WWDTEN_Pos) |
WWDT_T::CTL: WWDTEN Mask
Definition at line 28669 of file NUC472_442.h.
| #define WWDT_CTL_WWDTEN_Pos (0) |
WWDT_T::CTL: WWDTEN Position
Definition at line 28668 of file NUC472_442.h.
| #define WWDT_RLDCNT_RLDCNT_Msk (0xfffffffful << WWDT_RLDCNT_RLDCNT_Pos) |
WWDT_T::RLDCNT: RLDCNT Mask
Definition at line 28666 of file NUC472_442.h.
| #define WWDT_RLDCNT_RLDCNT_Pos (0) |
@addtogroup WWDT_CONST WWDT Bit Field Definition Constant Definitions for WWDT Controller
WWDT_T::RLDCNT: RLDCNT Position
Definition at line 28665 of file NUC472_442.h.
| #define WWDT_STATUS_WWDTIF_Msk (0x1ul << WWDT_STATUS_WWDTIF_Pos) |
WWDT_T::STATUS: WWDTIF Mask
Definition at line 28684 of file NUC472_442.h.
| #define WWDT_STATUS_WWDTIF_Pos (0) |
WWDT_T::STATUS: WWDTIF Position
Definition at line 28683 of file NUC472_442.h.
| #define WWDT_STATUS_WWDTRF_Msk (0x1ul << WWDT_STATUS_WWDTRF_Pos) |
WWDT_T::STATUS: WWDTRF Mask
Definition at line 28687 of file NUC472_442.h.
| #define WWDT_STATUS_WWDTRF_Pos (1) |
WWDT_T::STATUS: WWDTRF Position
Definition at line 28686 of file NUC472_442.h.
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